1*4882a593Smuzhiyun // SPDX-License-Identifier: ISC
2*4882a593Smuzhiyun /* Copyright (C) 2020 MediaTek Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Author: Felix Fietkau <nbd@nbd.name>
5*4882a593Smuzhiyun * Lorenzo Bianconi <lorenzo@kernel.org>
6*4882a593Smuzhiyun * Sean Wang <sean.wang@mediatek.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/iopoll.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/mmc/host.h>
14*4882a593Smuzhiyun #include <linux/mmc/sdio_ids.h>
15*4882a593Smuzhiyun #include <linux/mmc/sdio_func.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include "mt7615.h"
18*4882a593Smuzhiyun #include "sdio.h"
19*4882a593Smuzhiyun #include "mac.h"
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun static const struct sdio_device_id mt7663s_table[] = {
22*4882a593Smuzhiyun { SDIO_DEVICE(SDIO_VENDOR_ID_MEDIATEK, 0x7603) },
23*4882a593Smuzhiyun { } /* Terminating entry */
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun
mt7663s_read_whisr(struct mt76_dev * dev)26*4882a593Smuzhiyun static u32 mt7663s_read_whisr(struct mt76_dev *dev)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun return sdio_readl(dev->sdio.func, MCR_WHISR, NULL);
29*4882a593Smuzhiyun }
30*4882a593Smuzhiyun
mt7663s_read_pcr(struct mt7615_dev * dev)31*4882a593Smuzhiyun u32 mt7663s_read_pcr(struct mt7615_dev *dev)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun struct mt76_sdio *sdio = &dev->mt76.sdio;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun return sdio_readl(sdio->func, MCR_WHLPCR, NULL);
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
mt7663s_read_mailbox(struct mt76_dev * dev,u32 offset)38*4882a593Smuzhiyun static u32 mt7663s_read_mailbox(struct mt76_dev *dev, u32 offset)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun struct sdio_func *func = dev->sdio.func;
41*4882a593Smuzhiyun u32 val = ~0, status;
42*4882a593Smuzhiyun int err;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun sdio_claim_host(func);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun sdio_writel(func, offset, MCR_H2DSM0R, &err);
47*4882a593Smuzhiyun if (err < 0) {
48*4882a593Smuzhiyun dev_err(dev->dev, "failed setting address [err=%d]\n", err);
49*4882a593Smuzhiyun goto out;
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun sdio_writel(func, H2D_SW_INT_READ, MCR_WSICR, &err);
53*4882a593Smuzhiyun if (err < 0) {
54*4882a593Smuzhiyun dev_err(dev->dev, "failed setting read mode [err=%d]\n", err);
55*4882a593Smuzhiyun goto out;
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun err = readx_poll_timeout(mt7663s_read_whisr, dev, status,
59*4882a593Smuzhiyun status & H2D_SW_INT_READ, 0, 1000000);
60*4882a593Smuzhiyun if (err < 0) {
61*4882a593Smuzhiyun dev_err(dev->dev, "query whisr timeout\n");
62*4882a593Smuzhiyun goto out;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun sdio_writel(func, H2D_SW_INT_READ, MCR_WHISR, &err);
66*4882a593Smuzhiyun if (err < 0) {
67*4882a593Smuzhiyun dev_err(dev->dev, "failed setting read mode [err=%d]\n", err);
68*4882a593Smuzhiyun goto out;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun val = sdio_readl(func, MCR_H2DSM0R, &err);
72*4882a593Smuzhiyun if (err < 0) {
73*4882a593Smuzhiyun dev_err(dev->dev, "failed reading h2dsm0r [err=%d]\n", err);
74*4882a593Smuzhiyun goto out;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun if (val != offset) {
78*4882a593Smuzhiyun dev_err(dev->dev, "register mismatch\n");
79*4882a593Smuzhiyun val = ~0;
80*4882a593Smuzhiyun goto out;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun val = sdio_readl(func, MCR_D2HRM1R, &err);
84*4882a593Smuzhiyun if (err < 0)
85*4882a593Smuzhiyun dev_err(dev->dev, "failed reading d2hrm1r [err=%d]\n", err);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun out:
88*4882a593Smuzhiyun sdio_release_host(func);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun return val;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
mt7663s_write_mailbox(struct mt76_dev * dev,u32 offset,u32 val)93*4882a593Smuzhiyun static void mt7663s_write_mailbox(struct mt76_dev *dev, u32 offset, u32 val)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun struct sdio_func *func = dev->sdio.func;
96*4882a593Smuzhiyun u32 status;
97*4882a593Smuzhiyun int err;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun sdio_claim_host(func);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun sdio_writel(func, offset, MCR_H2DSM0R, &err);
102*4882a593Smuzhiyun if (err < 0) {
103*4882a593Smuzhiyun dev_err(dev->dev, "failed setting address [err=%d]\n", err);
104*4882a593Smuzhiyun goto out;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun sdio_writel(func, val, MCR_H2DSM1R, &err);
108*4882a593Smuzhiyun if (err < 0) {
109*4882a593Smuzhiyun dev_err(dev->dev,
110*4882a593Smuzhiyun "failed setting write value [err=%d]\n", err);
111*4882a593Smuzhiyun goto out;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun sdio_writel(func, H2D_SW_INT_WRITE, MCR_WSICR, &err);
115*4882a593Smuzhiyun if (err < 0) {
116*4882a593Smuzhiyun dev_err(dev->dev, "failed setting write mode [err=%d]\n", err);
117*4882a593Smuzhiyun goto out;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun err = readx_poll_timeout(mt7663s_read_whisr, dev, status,
121*4882a593Smuzhiyun status & H2D_SW_INT_WRITE, 0, 1000000);
122*4882a593Smuzhiyun if (err < 0) {
123*4882a593Smuzhiyun dev_err(dev->dev, "query whisr timeout\n");
124*4882a593Smuzhiyun goto out;
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun sdio_writel(func, H2D_SW_INT_WRITE, MCR_WHISR, &err);
128*4882a593Smuzhiyun if (err < 0) {
129*4882a593Smuzhiyun dev_err(dev->dev, "failed setting write mode [err=%d]\n", err);
130*4882a593Smuzhiyun goto out;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun val = sdio_readl(func, MCR_H2DSM0R, &err);
134*4882a593Smuzhiyun if (err < 0) {
135*4882a593Smuzhiyun dev_err(dev->dev, "failed reading h2dsm0r [err=%d]\n", err);
136*4882a593Smuzhiyun goto out;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun if (val != offset)
140*4882a593Smuzhiyun dev_err(dev->dev, "register mismatch\n");
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun out:
143*4882a593Smuzhiyun sdio_release_host(func);
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun
mt7663s_rr(struct mt76_dev * dev,u32 offset)146*4882a593Smuzhiyun static u32 mt7663s_rr(struct mt76_dev *dev, u32 offset)
147*4882a593Smuzhiyun {
148*4882a593Smuzhiyun if (test_bit(MT76_STATE_MCU_RUNNING, &dev->phy.state))
149*4882a593Smuzhiyun return dev->mcu_ops->mcu_rr(dev, offset);
150*4882a593Smuzhiyun else
151*4882a593Smuzhiyun return mt7663s_read_mailbox(dev, offset);
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun
mt7663s_wr(struct mt76_dev * dev,u32 offset,u32 val)154*4882a593Smuzhiyun static void mt7663s_wr(struct mt76_dev *dev, u32 offset, u32 val)
155*4882a593Smuzhiyun {
156*4882a593Smuzhiyun if (test_bit(MT76_STATE_MCU_RUNNING, &dev->phy.state))
157*4882a593Smuzhiyun dev->mcu_ops->mcu_wr(dev, offset, val);
158*4882a593Smuzhiyun else
159*4882a593Smuzhiyun mt7663s_write_mailbox(dev, offset, val);
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
mt7663s_rmw(struct mt76_dev * dev,u32 offset,u32 mask,u32 val)162*4882a593Smuzhiyun static u32 mt7663s_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val)
163*4882a593Smuzhiyun {
164*4882a593Smuzhiyun val |= mt7663s_rr(dev, offset) & ~mask;
165*4882a593Smuzhiyun mt7663s_wr(dev, offset, val);
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun return val;
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
mt7663s_write_copy(struct mt76_dev * dev,u32 offset,const void * data,int len)170*4882a593Smuzhiyun static void mt7663s_write_copy(struct mt76_dev *dev, u32 offset,
171*4882a593Smuzhiyun const void *data, int len)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun const u32 *val = data;
174*4882a593Smuzhiyun int i;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun for (i = 0; i < len / sizeof(u32); i++) {
177*4882a593Smuzhiyun mt7663s_wr(dev, offset, val[i]);
178*4882a593Smuzhiyun offset += sizeof(u32);
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun
mt7663s_read_copy(struct mt76_dev * dev,u32 offset,void * data,int len)182*4882a593Smuzhiyun static void mt7663s_read_copy(struct mt76_dev *dev, u32 offset,
183*4882a593Smuzhiyun void *data, int len)
184*4882a593Smuzhiyun {
185*4882a593Smuzhiyun u32 *val = data;
186*4882a593Smuzhiyun int i;
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun for (i = 0; i < len / sizeof(u32); i++) {
189*4882a593Smuzhiyun val[i] = mt7663s_rr(dev, offset);
190*4882a593Smuzhiyun offset += sizeof(u32);
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun
mt7663s_wr_rp(struct mt76_dev * dev,u32 base,const struct mt76_reg_pair * data,int len)194*4882a593Smuzhiyun static int mt7663s_wr_rp(struct mt76_dev *dev, u32 base,
195*4882a593Smuzhiyun const struct mt76_reg_pair *data,
196*4882a593Smuzhiyun int len)
197*4882a593Smuzhiyun {
198*4882a593Smuzhiyun int i;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun for (i = 0; i < len; i++) {
201*4882a593Smuzhiyun mt7663s_wr(dev, data->reg, data->value);
202*4882a593Smuzhiyun data++;
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun return 0;
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun
mt7663s_rd_rp(struct mt76_dev * dev,u32 base,struct mt76_reg_pair * data,int len)208*4882a593Smuzhiyun static int mt7663s_rd_rp(struct mt76_dev *dev, u32 base,
209*4882a593Smuzhiyun struct mt76_reg_pair *data,
210*4882a593Smuzhiyun int len)
211*4882a593Smuzhiyun {
212*4882a593Smuzhiyun int i;
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun for (i = 0; i < len; i++) {
215*4882a593Smuzhiyun data->value = mt7663s_rr(dev, data->reg);
216*4882a593Smuzhiyun data++;
217*4882a593Smuzhiyun }
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun return 0;
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun
mt7663s_init_work(struct work_struct * work)222*4882a593Smuzhiyun static void mt7663s_init_work(struct work_struct *work)
223*4882a593Smuzhiyun {
224*4882a593Smuzhiyun struct mt7615_dev *dev;
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun dev = container_of(work, struct mt7615_dev, mcu_work);
227*4882a593Smuzhiyun if (mt7663s_mcu_init(dev))
228*4882a593Smuzhiyun return;
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun mt7615_mcu_set_eeprom(dev);
231*4882a593Smuzhiyun mt7615_mac_init(dev);
232*4882a593Smuzhiyun mt7615_phy_init(dev);
233*4882a593Smuzhiyun mt7615_mcu_del_wtbl_all(dev);
234*4882a593Smuzhiyun mt7615_check_offload_capability(dev);
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun
mt7663s_hw_init(struct mt7615_dev * dev,struct sdio_func * func)237*4882a593Smuzhiyun static int mt7663s_hw_init(struct mt7615_dev *dev, struct sdio_func *func)
238*4882a593Smuzhiyun {
239*4882a593Smuzhiyun u32 status, ctrl;
240*4882a593Smuzhiyun int ret;
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun sdio_claim_host(func);
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun ret = sdio_enable_func(func);
245*4882a593Smuzhiyun if (ret < 0)
246*4882a593Smuzhiyun goto release;
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun /* Get ownership from the device */
249*4882a593Smuzhiyun sdio_writel(func, WHLPCR_INT_EN_CLR | WHLPCR_FW_OWN_REQ_CLR,
250*4882a593Smuzhiyun MCR_WHLPCR, &ret);
251*4882a593Smuzhiyun if (ret < 0)
252*4882a593Smuzhiyun goto disable_func;
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun ret = readx_poll_timeout(mt7663s_read_pcr, dev, status,
255*4882a593Smuzhiyun status & WHLPCR_IS_DRIVER_OWN, 2000, 1000000);
256*4882a593Smuzhiyun if (ret < 0) {
257*4882a593Smuzhiyun dev_err(dev->mt76.dev, "Cannot get ownership from device");
258*4882a593Smuzhiyun goto disable_func;
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun ret = sdio_set_block_size(func, 512);
262*4882a593Smuzhiyun if (ret < 0)
263*4882a593Smuzhiyun goto disable_func;
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun /* Enable interrupt */
266*4882a593Smuzhiyun sdio_writel(func, WHLPCR_INT_EN_SET, MCR_WHLPCR, &ret);
267*4882a593Smuzhiyun if (ret < 0)
268*4882a593Smuzhiyun goto disable_func;
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun ctrl = WHIER_RX0_DONE_INT_EN | WHIER_TX_DONE_INT_EN;
271*4882a593Smuzhiyun sdio_writel(func, ctrl, MCR_WHIER, &ret);
272*4882a593Smuzhiyun if (ret < 0)
273*4882a593Smuzhiyun goto disable_func;
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun /* set WHISR as read clear and Rx aggregation number as 16 */
276*4882a593Smuzhiyun ctrl = FIELD_PREP(MAX_HIF_RX_LEN_NUM, 16);
277*4882a593Smuzhiyun sdio_writel(func, ctrl, MCR_WHCR, &ret);
278*4882a593Smuzhiyun if (ret < 0)
279*4882a593Smuzhiyun goto disable_func;
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun ret = sdio_claim_irq(func, mt7663s_sdio_irq);
282*4882a593Smuzhiyun if (ret < 0)
283*4882a593Smuzhiyun goto disable_func;
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun sdio_release_host(func);
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun return 0;
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun disable_func:
290*4882a593Smuzhiyun sdio_disable_func(func);
291*4882a593Smuzhiyun release:
292*4882a593Smuzhiyun sdio_release_host(func);
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun return ret;
295*4882a593Smuzhiyun }
296*4882a593Smuzhiyun
mt7663s_sta_add(struct mt76_dev * mdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)297*4882a593Smuzhiyun static int mt7663s_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
298*4882a593Smuzhiyun struct ieee80211_sta *sta)
299*4882a593Smuzhiyun {
300*4882a593Smuzhiyun struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
301*4882a593Smuzhiyun struct mt76_sdio *sdio = &mdev->sdio;
302*4882a593Smuzhiyun u32 pse, ple;
303*4882a593Smuzhiyun int err;
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun err = mt7615_mac_sta_add(mdev, vif, sta);
306*4882a593Smuzhiyun if (err < 0)
307*4882a593Smuzhiyun return err;
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun /* init sched data quota */
310*4882a593Smuzhiyun pse = mt76_get_field(dev, MT_PSE_PG_HIF0_GROUP, MT_HIF0_MIN_QUOTA);
311*4882a593Smuzhiyun ple = mt76_get_field(dev, MT_PLE_PG_HIF0_GROUP, MT_HIF0_MIN_QUOTA);
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun mutex_lock(&sdio->sched.lock);
314*4882a593Smuzhiyun sdio->sched.pse_data_quota = pse;
315*4882a593Smuzhiyun sdio->sched.ple_data_quota = ple;
316*4882a593Smuzhiyun mutex_unlock(&sdio->sched.lock);
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun return 0;
319*4882a593Smuzhiyun }
320*4882a593Smuzhiyun
mt7663s_probe(struct sdio_func * func,const struct sdio_device_id * id)321*4882a593Smuzhiyun static int mt7663s_probe(struct sdio_func *func,
322*4882a593Smuzhiyun const struct sdio_device_id *id)
323*4882a593Smuzhiyun {
324*4882a593Smuzhiyun static const struct mt76_driver_ops drv_ops = {
325*4882a593Smuzhiyun .txwi_size = MT_USB_TXD_SIZE,
326*4882a593Smuzhiyun .drv_flags = MT_DRV_RX_DMA_HDR,
327*4882a593Smuzhiyun .tx_prepare_skb = mt7663_usb_sdio_tx_prepare_skb,
328*4882a593Smuzhiyun .tx_complete_skb = mt7663_usb_sdio_tx_complete_skb,
329*4882a593Smuzhiyun .tx_status_data = mt7663_usb_sdio_tx_status_data,
330*4882a593Smuzhiyun .rx_skb = mt7615_queue_rx_skb,
331*4882a593Smuzhiyun .sta_ps = mt7615_sta_ps,
332*4882a593Smuzhiyun .sta_add = mt7663s_sta_add,
333*4882a593Smuzhiyun .sta_remove = mt7615_mac_sta_remove,
334*4882a593Smuzhiyun .update_survey = mt7615_update_channel,
335*4882a593Smuzhiyun };
336*4882a593Smuzhiyun static const struct mt76_bus_ops mt7663s_ops = {
337*4882a593Smuzhiyun .rr = mt7663s_rr,
338*4882a593Smuzhiyun .rmw = mt7663s_rmw,
339*4882a593Smuzhiyun .wr = mt7663s_wr,
340*4882a593Smuzhiyun .write_copy = mt7663s_write_copy,
341*4882a593Smuzhiyun .read_copy = mt7663s_read_copy,
342*4882a593Smuzhiyun .wr_rp = mt7663s_wr_rp,
343*4882a593Smuzhiyun .rd_rp = mt7663s_rd_rp,
344*4882a593Smuzhiyun .type = MT76_BUS_SDIO,
345*4882a593Smuzhiyun };
346*4882a593Smuzhiyun struct ieee80211_ops *ops;
347*4882a593Smuzhiyun struct mt7615_dev *dev;
348*4882a593Smuzhiyun struct mt76_dev *mdev;
349*4882a593Smuzhiyun int i, ret;
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun ops = devm_kmemdup(&func->dev, &mt7615_ops, sizeof(mt7615_ops),
352*4882a593Smuzhiyun GFP_KERNEL);
353*4882a593Smuzhiyun if (!ops)
354*4882a593Smuzhiyun return -ENOMEM;
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun mdev = mt76_alloc_device(&func->dev, sizeof(*dev), ops, &drv_ops);
357*4882a593Smuzhiyun if (!mdev)
358*4882a593Smuzhiyun return -ENOMEM;
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun dev = container_of(mdev, struct mt7615_dev, mt76);
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun INIT_WORK(&dev->mcu_work, mt7663s_init_work);
363*4882a593Smuzhiyun dev->reg_map = mt7663_usb_sdio_reg_map;
364*4882a593Smuzhiyun dev->ops = ops;
365*4882a593Smuzhiyun sdio_set_drvdata(func, dev);
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun ret = mt76s_init(mdev, func, &mt7663s_ops);
368*4882a593Smuzhiyun if (ret < 0)
369*4882a593Smuzhiyun goto err_free;
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun INIT_WORK(&mdev->sdio.tx.xmit_work, mt7663s_tx_work);
372*4882a593Smuzhiyun INIT_WORK(&mdev->sdio.rx.recv_work, mt7663s_rx_work);
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun ret = mt7663s_hw_init(dev, func);
375*4882a593Smuzhiyun if (ret)
376*4882a593Smuzhiyun goto err_deinit;
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun mdev->rev = (mt76_rr(dev, MT_HW_CHIPID) << 16) |
379*4882a593Smuzhiyun (mt76_rr(dev, MT_HW_REV) & 0xff);
380*4882a593Smuzhiyun dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun mdev->sdio.intr_data = devm_kmalloc(mdev->dev,
383*4882a593Smuzhiyun sizeof(struct mt76s_intr),
384*4882a593Smuzhiyun GFP_KERNEL);
385*4882a593Smuzhiyun if (!mdev->sdio.intr_data) {
386*4882a593Smuzhiyun ret = -ENOMEM;
387*4882a593Smuzhiyun goto err_deinit;
388*4882a593Smuzhiyun }
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(mdev->sdio.xmit_buf); i++) {
391*4882a593Smuzhiyun mdev->sdio.xmit_buf[i] = devm_kmalloc(mdev->dev,
392*4882a593Smuzhiyun MT76S_XMIT_BUF_SZ,
393*4882a593Smuzhiyun GFP_KERNEL);
394*4882a593Smuzhiyun if (!mdev->sdio.xmit_buf[i]) {
395*4882a593Smuzhiyun ret = -ENOMEM;
396*4882a593Smuzhiyun goto err_deinit;
397*4882a593Smuzhiyun }
398*4882a593Smuzhiyun }
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun ret = mt76s_alloc_queues(&dev->mt76);
401*4882a593Smuzhiyun if (ret)
402*4882a593Smuzhiyun goto err_deinit;
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun ret = mt7663_usb_sdio_register_device(dev);
405*4882a593Smuzhiyun if (ret)
406*4882a593Smuzhiyun goto err_deinit;
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun return 0;
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun err_deinit:
411*4882a593Smuzhiyun mt76s_deinit(&dev->mt76);
412*4882a593Smuzhiyun err_free:
413*4882a593Smuzhiyun mt76_free_device(&dev->mt76);
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun return ret;
416*4882a593Smuzhiyun }
417*4882a593Smuzhiyun
mt7663s_remove(struct sdio_func * func)418*4882a593Smuzhiyun static void mt7663s_remove(struct sdio_func *func)
419*4882a593Smuzhiyun {
420*4882a593Smuzhiyun struct mt7615_dev *dev = sdio_get_drvdata(func);
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun if (!test_and_clear_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
423*4882a593Smuzhiyun return;
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun ieee80211_unregister_hw(dev->mt76.hw);
426*4882a593Smuzhiyun mt76s_deinit(&dev->mt76);
427*4882a593Smuzhiyun mt76_free_device(&dev->mt76);
428*4882a593Smuzhiyun }
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun #ifdef CONFIG_PM
mt7663s_suspend(struct device * dev)431*4882a593Smuzhiyun static int mt7663s_suspend(struct device *dev)
432*4882a593Smuzhiyun {
433*4882a593Smuzhiyun struct sdio_func *func = dev_to_sdio_func(dev);
434*4882a593Smuzhiyun struct mt7615_dev *mdev = sdio_get_drvdata(func);
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun if (!test_bit(MT76_STATE_SUSPEND, &mdev->mphy.state) &&
437*4882a593Smuzhiyun mt7615_firmware_offload(mdev)) {
438*4882a593Smuzhiyun int err;
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun err = mt7615_mcu_set_hif_suspend(mdev, true);
441*4882a593Smuzhiyun if (err < 0)
442*4882a593Smuzhiyun return err;
443*4882a593Smuzhiyun }
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER);
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun mt76s_stop_txrx(&mdev->mt76);
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun return mt7615_mcu_set_fw_ctrl(mdev);
450*4882a593Smuzhiyun }
451*4882a593Smuzhiyun
mt7663s_resume(struct device * dev)452*4882a593Smuzhiyun static int mt7663s_resume(struct device *dev)
453*4882a593Smuzhiyun {
454*4882a593Smuzhiyun struct sdio_func *func = dev_to_sdio_func(dev);
455*4882a593Smuzhiyun struct mt7615_dev *mdev = sdio_get_drvdata(func);
456*4882a593Smuzhiyun int err;
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun err = mt7615_mcu_set_drv_ctrl(mdev);
459*4882a593Smuzhiyun if (err)
460*4882a593Smuzhiyun return err;
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun if (!test_bit(MT76_STATE_SUSPEND, &mdev->mphy.state) &&
463*4882a593Smuzhiyun mt7615_firmware_offload(mdev))
464*4882a593Smuzhiyun err = mt7615_mcu_set_hif_suspend(mdev, false);
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun return err;
467*4882a593Smuzhiyun }
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun static const struct dev_pm_ops mt7663s_pm_ops = {
470*4882a593Smuzhiyun .suspend = mt7663s_suspend,
471*4882a593Smuzhiyun .resume = mt7663s_resume,
472*4882a593Smuzhiyun };
473*4882a593Smuzhiyun #endif
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun MODULE_DEVICE_TABLE(sdio, mt7663s_table);
476*4882a593Smuzhiyun MODULE_FIRMWARE(MT7663_OFFLOAD_FIRMWARE_N9);
477*4882a593Smuzhiyun MODULE_FIRMWARE(MT7663_OFFLOAD_ROM_PATCH);
478*4882a593Smuzhiyun MODULE_FIRMWARE(MT7663_FIRMWARE_N9);
479*4882a593Smuzhiyun MODULE_FIRMWARE(MT7663_ROM_PATCH);
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun static struct sdio_driver mt7663s_driver = {
482*4882a593Smuzhiyun .name = KBUILD_MODNAME,
483*4882a593Smuzhiyun .probe = mt7663s_probe,
484*4882a593Smuzhiyun .remove = mt7663s_remove,
485*4882a593Smuzhiyun .id_table = mt7663s_table,
486*4882a593Smuzhiyun #ifdef CONFIG_PM
487*4882a593Smuzhiyun .drv = {
488*4882a593Smuzhiyun .pm = &mt7663s_pm_ops,
489*4882a593Smuzhiyun }
490*4882a593Smuzhiyun #endif
491*4882a593Smuzhiyun };
492*4882a593Smuzhiyun module_sdio_driver(mt7663s_driver);
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
495*4882a593Smuzhiyun MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
496*4882a593Smuzhiyun MODULE_LICENSE("Dual BSD/GPL");
497