1*4882a593Smuzhiyun // SPDX-License-Identifier: ISC
2*4882a593Smuzhiyun /* Copyright (C) 2019 MediaTek Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Author: Ryder Lee <ryder.lee@mediatek.com>
5*4882a593Smuzhiyun * Felix Fietkau <nbd@nbd.name>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/pci.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include "mt7615.h"
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun static const struct pci_device_id mt7615_pci_device_table[] = {
15*4882a593Smuzhiyun { PCI_DEVICE(0x14c3, 0x7615) },
16*4882a593Smuzhiyun { PCI_DEVICE(0x14c3, 0x7663) },
17*4882a593Smuzhiyun { PCI_DEVICE(0x14c3, 0x7611) },
18*4882a593Smuzhiyun { },
19*4882a593Smuzhiyun };
20*4882a593Smuzhiyun
mt7615_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)21*4882a593Smuzhiyun static int mt7615_pci_probe(struct pci_dev *pdev,
22*4882a593Smuzhiyun const struct pci_device_id *id)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun const u32 *map;
25*4882a593Smuzhiyun int ret;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun ret = pcim_enable_device(pdev);
28*4882a593Smuzhiyun if (ret)
29*4882a593Smuzhiyun return ret;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
32*4882a593Smuzhiyun if (ret)
33*4882a593Smuzhiyun return ret;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun pci_set_master(pdev);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
38*4882a593Smuzhiyun if (ret < 0)
39*4882a593Smuzhiyun return ret;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
42*4882a593Smuzhiyun if (ret)
43*4882a593Smuzhiyun goto error;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun mt76_pci_disable_aspm(pdev);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun map = id->device == 0x7663 ? mt7663e_reg_map : mt7615e_reg_map;
48*4882a593Smuzhiyun ret = mt7615_mmio_probe(&pdev->dev, pcim_iomap_table(pdev)[0],
49*4882a593Smuzhiyun pdev->irq, map);
50*4882a593Smuzhiyun if (ret)
51*4882a593Smuzhiyun goto error;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun return 0;
54*4882a593Smuzhiyun error:
55*4882a593Smuzhiyun pci_free_irq_vectors(pdev);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun return ret;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
mt7615_pci_remove(struct pci_dev * pdev)60*4882a593Smuzhiyun static void mt7615_pci_remove(struct pci_dev *pdev)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun struct mt76_dev *mdev = pci_get_drvdata(pdev);
63*4882a593Smuzhiyun struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun mt7615_unregister_device(dev);
66*4882a593Smuzhiyun devm_free_irq(&pdev->dev, pdev->irq, dev);
67*4882a593Smuzhiyun pci_free_irq_vectors(pdev);
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun #ifdef CONFIG_PM
mt7615_pci_suspend(struct pci_dev * pdev,pm_message_t state)71*4882a593Smuzhiyun static int mt7615_pci_suspend(struct pci_dev *pdev, pm_message_t state)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun struct mt76_dev *mdev = pci_get_drvdata(pdev);
74*4882a593Smuzhiyun struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
75*4882a593Smuzhiyun bool hif_suspend;
76*4882a593Smuzhiyun int i, err;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun err = mt7615_pm_wake(dev);
79*4882a593Smuzhiyun if (err < 0)
80*4882a593Smuzhiyun return err;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun hif_suspend = !test_bit(MT76_STATE_SUSPEND, &dev->mphy.state) &&
83*4882a593Smuzhiyun mt7615_firmware_offload(dev);
84*4882a593Smuzhiyun if (hif_suspend) {
85*4882a593Smuzhiyun err = mt7615_mcu_set_hif_suspend(dev, true);
86*4882a593Smuzhiyun if (err)
87*4882a593Smuzhiyun return err;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun napi_disable(&mdev->tx_napi);
91*4882a593Smuzhiyun mt76_worker_disable(&mdev->tx_worker);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun mt76_for_each_q_rx(mdev, i) {
94*4882a593Smuzhiyun napi_disable(&mdev->napi[i]);
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun tasklet_kill(&dev->irq_tasklet);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun mt7615_dma_reset(dev);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun err = mt7615_wait_pdma_busy(dev);
101*4882a593Smuzhiyun if (err)
102*4882a593Smuzhiyun goto restore;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun if (is_mt7663(mdev)) {
105*4882a593Smuzhiyun mt76_set(dev, MT_PDMA_SLP_PROT, MT_PDMA_AXI_SLPPROT_ENABLE);
106*4882a593Smuzhiyun if (!mt76_poll_msec(dev, MT_PDMA_SLP_PROT,
107*4882a593Smuzhiyun MT_PDMA_AXI_SLPPROT_RDY,
108*4882a593Smuzhiyun MT_PDMA_AXI_SLPPROT_RDY, 1000)) {
109*4882a593Smuzhiyun dev_err(mdev->dev, "PDMA sleep protection failed\n");
110*4882a593Smuzhiyun err = -EIO;
111*4882a593Smuzhiyun goto restore;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun pci_enable_wake(pdev, pci_choose_state(pdev, state), true);
116*4882a593Smuzhiyun pci_save_state(pdev);
117*4882a593Smuzhiyun err = pci_set_power_state(pdev, pci_choose_state(pdev, state));
118*4882a593Smuzhiyun if (err)
119*4882a593Smuzhiyun goto restore;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun err = mt7615_mcu_set_fw_ctrl(dev);
122*4882a593Smuzhiyun if (err)
123*4882a593Smuzhiyun goto restore;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun return 0;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun restore:
128*4882a593Smuzhiyun mt76_for_each_q_rx(mdev, i) {
129*4882a593Smuzhiyun napi_enable(&mdev->napi[i]);
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun napi_enable(&mdev->tx_napi);
132*4882a593Smuzhiyun if (hif_suspend)
133*4882a593Smuzhiyun mt7615_mcu_set_hif_suspend(dev, false);
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun return err;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
mt7615_pci_resume(struct pci_dev * pdev)138*4882a593Smuzhiyun static int mt7615_pci_resume(struct pci_dev *pdev)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun struct mt76_dev *mdev = pci_get_drvdata(pdev);
141*4882a593Smuzhiyun struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
142*4882a593Smuzhiyun bool pdma_reset;
143*4882a593Smuzhiyun int i, err;
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun err = mt7615_mcu_set_drv_ctrl(dev);
146*4882a593Smuzhiyun if (err < 0)
147*4882a593Smuzhiyun return err;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun err = pci_set_power_state(pdev, PCI_D0);
150*4882a593Smuzhiyun if (err)
151*4882a593Smuzhiyun return err;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun pci_restore_state(pdev);
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun if (is_mt7663(&dev->mt76)) {
156*4882a593Smuzhiyun mt76_clear(dev, MT_PDMA_SLP_PROT, MT_PDMA_AXI_SLPPROT_ENABLE);
157*4882a593Smuzhiyun mt76_wr(dev, MT_PCIE_IRQ_ENABLE, 1);
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun pdma_reset = !mt76_rr(dev, MT_WPDMA_TX_RING0_CTRL0) &&
161*4882a593Smuzhiyun !mt76_rr(dev, MT_WPDMA_TX_RING0_CTRL1);
162*4882a593Smuzhiyun if (pdma_reset)
163*4882a593Smuzhiyun dev_err(mdev->dev, "PDMA engine must be reinitialized\n");
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun mt76_worker_enable(&mdev->tx_worker);
166*4882a593Smuzhiyun mt76_for_each_q_rx(mdev, i) {
167*4882a593Smuzhiyun napi_enable(&mdev->napi[i]);
168*4882a593Smuzhiyun napi_schedule(&mdev->napi[i]);
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun napi_enable(&mdev->tx_napi);
171*4882a593Smuzhiyun napi_schedule(&mdev->tx_napi);
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun if (!test_bit(MT76_STATE_SUSPEND, &dev->mphy.state) &&
174*4882a593Smuzhiyun mt7615_firmware_offload(dev))
175*4882a593Smuzhiyun err = mt7615_mcu_set_hif_suspend(dev, false);
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun return err;
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun #endif /* CONFIG_PM */
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun struct pci_driver mt7615_pci_driver = {
182*4882a593Smuzhiyun .name = KBUILD_MODNAME,
183*4882a593Smuzhiyun .id_table = mt7615_pci_device_table,
184*4882a593Smuzhiyun .probe = mt7615_pci_probe,
185*4882a593Smuzhiyun .remove = mt7615_pci_remove,
186*4882a593Smuzhiyun #ifdef CONFIG_PM
187*4882a593Smuzhiyun .suspend = mt7615_pci_suspend,
188*4882a593Smuzhiyun .resume = mt7615_pci_resume,
189*4882a593Smuzhiyun #endif /* CONFIG_PM */
190*4882a593Smuzhiyun };
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, mt7615_pci_device_table);
193*4882a593Smuzhiyun MODULE_FIRMWARE(MT7615_FIRMWARE_CR4);
194*4882a593Smuzhiyun MODULE_FIRMWARE(MT7615_FIRMWARE_N9);
195*4882a593Smuzhiyun MODULE_FIRMWARE(MT7615_ROM_PATCH);
196*4882a593Smuzhiyun MODULE_FIRMWARE(MT7663_OFFLOAD_FIRMWARE_N9);
197*4882a593Smuzhiyun MODULE_FIRMWARE(MT7663_OFFLOAD_ROM_PATCH);
198*4882a593Smuzhiyun MODULE_FIRMWARE(MT7663_FIRMWARE_N9);
199*4882a593Smuzhiyun MODULE_FIRMWARE(MT7663_ROM_PATCH);
200