1*4882a593Smuzhiyun /* SPDX-License-Identifier: ISC */ 2*4882a593Smuzhiyun /* Copyright (C) 2019 MediaTek Inc. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef __MT7615_MCU_H 5*4882a593Smuzhiyun #define __MT7615_MCU_H 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun struct mt7615_mcu_txd { 8*4882a593Smuzhiyun __le32 txd[8]; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun __le16 len; 11*4882a593Smuzhiyun __le16 pq_id; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun u8 cid; 14*4882a593Smuzhiyun u8 pkt_type; 15*4882a593Smuzhiyun u8 set_query; /* FW don't care */ 16*4882a593Smuzhiyun u8 seq; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun u8 uc_d2b0_rev; 19*4882a593Smuzhiyun u8 ext_cid; 20*4882a593Smuzhiyun u8 s2d_index; 21*4882a593Smuzhiyun u8 ext_cid_ack; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun u32 reserved[5]; 24*4882a593Smuzhiyun } __packed __aligned(4); 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /** 27*4882a593Smuzhiyun * struct mt7615_uni_txd - mcu command descriptor for firmware v3 28*4882a593Smuzhiyun * @txd: hardware descriptor 29*4882a593Smuzhiyun * @len: total length not including txd 30*4882a593Smuzhiyun * @cid: command identifier 31*4882a593Smuzhiyun * @pkt_type: must be 0xa0 (cmd packet by long format) 32*4882a593Smuzhiyun * @frag_n: fragment number 33*4882a593Smuzhiyun * @seq: sequence number 34*4882a593Smuzhiyun * @checksum: 0 mean there is no checksum 35*4882a593Smuzhiyun * @s2d_index: index for command source and destination 36*4882a593Smuzhiyun * Definition | value | note 37*4882a593Smuzhiyun * CMD_S2D_IDX_H2N | 0x00 | command from HOST to WM 38*4882a593Smuzhiyun * CMD_S2D_IDX_C2N | 0x01 | command from WA to WM 39*4882a593Smuzhiyun * CMD_S2D_IDX_H2C | 0x02 | command from HOST to WA 40*4882a593Smuzhiyun * CMD_S2D_IDX_H2N_AND_H2C | 0x03 | command from HOST to WA and WM 41*4882a593Smuzhiyun * 42*4882a593Smuzhiyun * @option: command option 43*4882a593Smuzhiyun * BIT[0]: UNI_CMD_OPT_BIT_ACK 44*4882a593Smuzhiyun * set to 1 to request a fw reply 45*4882a593Smuzhiyun * if UNI_CMD_OPT_BIT_0_ACK is set and UNI_CMD_OPT_BIT_2_SET_QUERY 46*4882a593Smuzhiyun * is set, mcu firmware will send response event EID = 0x01 47*4882a593Smuzhiyun * (UNI_EVENT_ID_CMD_RESULT) to the host. 48*4882a593Smuzhiyun * BIT[1]: UNI_CMD_OPT_BIT_UNI_CMD 49*4882a593Smuzhiyun * 0: original command 50*4882a593Smuzhiyun * 1: unified command 51*4882a593Smuzhiyun * BIT[2]: UNI_CMD_OPT_BIT_SET_QUERY 52*4882a593Smuzhiyun * 0: QUERY command 53*4882a593Smuzhiyun * 1: SET command 54*4882a593Smuzhiyun */ 55*4882a593Smuzhiyun struct mt7615_uni_txd { 56*4882a593Smuzhiyun __le32 txd[8]; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* DW1 */ 59*4882a593Smuzhiyun __le16 len; 60*4882a593Smuzhiyun __le16 cid; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* DW2 */ 63*4882a593Smuzhiyun u8 reserved; 64*4882a593Smuzhiyun u8 pkt_type; 65*4882a593Smuzhiyun u8 frag_n; 66*4882a593Smuzhiyun u8 seq; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* DW3 */ 69*4882a593Smuzhiyun __le16 checksum; 70*4882a593Smuzhiyun u8 s2d_index; 71*4882a593Smuzhiyun u8 option; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* DW4 */ 74*4882a593Smuzhiyun u8 reserved2[4]; 75*4882a593Smuzhiyun } __packed __aligned(4); 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* event table */ 78*4882a593Smuzhiyun enum { 79*4882a593Smuzhiyun MCU_EVENT_TARGET_ADDRESS_LEN = 0x01, 80*4882a593Smuzhiyun MCU_EVENT_FW_START = 0x01, 81*4882a593Smuzhiyun MCU_EVENT_GENERIC = 0x01, 82*4882a593Smuzhiyun MCU_EVENT_ACCESS_REG = 0x02, 83*4882a593Smuzhiyun MCU_EVENT_MT_PATCH_SEM = 0x04, 84*4882a593Smuzhiyun MCU_EVENT_REG_ACCESS = 0x05, 85*4882a593Smuzhiyun MCU_EVENT_SCAN_DONE = 0x0d, 86*4882a593Smuzhiyun MCU_EVENT_ROC = 0x10, 87*4882a593Smuzhiyun MCU_EVENT_BSS_ABSENCE = 0x11, 88*4882a593Smuzhiyun MCU_EVENT_BSS_BEACON_LOSS = 0x13, 89*4882a593Smuzhiyun MCU_EVENT_CH_PRIVILEGE = 0x18, 90*4882a593Smuzhiyun MCU_EVENT_SCHED_SCAN_DONE = 0x23, 91*4882a593Smuzhiyun MCU_EVENT_EXT = 0xed, 92*4882a593Smuzhiyun MCU_EVENT_RESTART_DL = 0xef, 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* ext event table */ 96*4882a593Smuzhiyun enum { 97*4882a593Smuzhiyun MCU_EXT_EVENT_PS_SYNC = 0x5, 98*4882a593Smuzhiyun MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13, 99*4882a593Smuzhiyun MCU_EXT_EVENT_THERMAL_PROTECT = 0x22, 100*4882a593Smuzhiyun MCU_EXT_EVENT_ASSERT_DUMP = 0x23, 101*4882a593Smuzhiyun MCU_EXT_EVENT_RDD_REPORT = 0x3a, 102*4882a593Smuzhiyun MCU_EXT_EVENT_CSA_NOTIFY = 0x4f, 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun enum { 106*4882a593Smuzhiyun MT_SKU_CCK_1_2 = 0, 107*4882a593Smuzhiyun MT_SKU_CCK_55_11, 108*4882a593Smuzhiyun MT_SKU_OFDM_6_9, 109*4882a593Smuzhiyun MT_SKU_OFDM_12_18, 110*4882a593Smuzhiyun MT_SKU_OFDM_24_36, 111*4882a593Smuzhiyun MT_SKU_OFDM_48, 112*4882a593Smuzhiyun MT_SKU_OFDM_54, 113*4882a593Smuzhiyun MT_SKU_HT20_0_8, 114*4882a593Smuzhiyun MT_SKU_HT20_32, 115*4882a593Smuzhiyun MT_SKU_HT20_1_2_9_10, 116*4882a593Smuzhiyun MT_SKU_HT20_3_4_11_12, 117*4882a593Smuzhiyun MT_SKU_HT20_5_13, 118*4882a593Smuzhiyun MT_SKU_HT20_6_14, 119*4882a593Smuzhiyun MT_SKU_HT20_7_15, 120*4882a593Smuzhiyun MT_SKU_HT40_0_8, 121*4882a593Smuzhiyun MT_SKU_HT40_32, 122*4882a593Smuzhiyun MT_SKU_HT40_1_2_9_10, 123*4882a593Smuzhiyun MT_SKU_HT40_3_4_11_12, 124*4882a593Smuzhiyun MT_SKU_HT40_5_13, 125*4882a593Smuzhiyun MT_SKU_HT40_6_14, 126*4882a593Smuzhiyun MT_SKU_HT40_7_15, 127*4882a593Smuzhiyun MT_SKU_VHT20_0, 128*4882a593Smuzhiyun MT_SKU_VHT20_1_2, 129*4882a593Smuzhiyun MT_SKU_VHT20_3_4, 130*4882a593Smuzhiyun MT_SKU_VHT20_5_6, 131*4882a593Smuzhiyun MT_SKU_VHT20_7, 132*4882a593Smuzhiyun MT_SKU_VHT20_8, 133*4882a593Smuzhiyun MT_SKU_VHT20_9, 134*4882a593Smuzhiyun MT_SKU_VHT40_0, 135*4882a593Smuzhiyun MT_SKU_VHT40_1_2, 136*4882a593Smuzhiyun MT_SKU_VHT40_3_4, 137*4882a593Smuzhiyun MT_SKU_VHT40_5_6, 138*4882a593Smuzhiyun MT_SKU_VHT40_7, 139*4882a593Smuzhiyun MT_SKU_VHT40_8, 140*4882a593Smuzhiyun MT_SKU_VHT40_9, 141*4882a593Smuzhiyun MT_SKU_VHT80_0, 142*4882a593Smuzhiyun MT_SKU_VHT80_1_2, 143*4882a593Smuzhiyun MT_SKU_VHT80_3_4, 144*4882a593Smuzhiyun MT_SKU_VHT80_5_6, 145*4882a593Smuzhiyun MT_SKU_VHT80_7, 146*4882a593Smuzhiyun MT_SKU_VHT80_8, 147*4882a593Smuzhiyun MT_SKU_VHT80_9, 148*4882a593Smuzhiyun MT_SKU_VHT160_0, 149*4882a593Smuzhiyun MT_SKU_VHT160_1_2, 150*4882a593Smuzhiyun MT_SKU_VHT160_3_4, 151*4882a593Smuzhiyun MT_SKU_VHT160_5_6, 152*4882a593Smuzhiyun MT_SKU_VHT160_7, 153*4882a593Smuzhiyun MT_SKU_VHT160_8, 154*4882a593Smuzhiyun MT_SKU_VHT160_9, 155*4882a593Smuzhiyun MT_SKU_1SS_DELTA, 156*4882a593Smuzhiyun MT_SKU_2SS_DELTA, 157*4882a593Smuzhiyun MT_SKU_3SS_DELTA, 158*4882a593Smuzhiyun MT_SKU_4SS_DELTA, 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun struct mt7615_mcu_rxd { 162*4882a593Smuzhiyun __le32 rxd[4]; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun __le16 len; 165*4882a593Smuzhiyun __le16 pkt_type_id; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun u8 eid; 168*4882a593Smuzhiyun u8 seq; 169*4882a593Smuzhiyun __le16 __rsv; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun u8 ext_eid; 172*4882a593Smuzhiyun u8 __rsv1[2]; 173*4882a593Smuzhiyun u8 s2d_index; 174*4882a593Smuzhiyun }; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun struct mt7615_mcu_rdd_report { 177*4882a593Smuzhiyun struct mt7615_mcu_rxd rxd; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun u8 idx; 180*4882a593Smuzhiyun u8 long_detected; 181*4882a593Smuzhiyun u8 constant_prf_detected; 182*4882a593Smuzhiyun u8 staggered_prf_detected; 183*4882a593Smuzhiyun u8 radar_type_idx; 184*4882a593Smuzhiyun u8 periodic_pulse_num; 185*4882a593Smuzhiyun u8 long_pulse_num; 186*4882a593Smuzhiyun u8 hw_pulse_num; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun u8 out_lpn; 189*4882a593Smuzhiyun u8 out_spn; 190*4882a593Smuzhiyun u8 out_crpn; 191*4882a593Smuzhiyun u8 out_crpw; 192*4882a593Smuzhiyun u8 out_crbn; 193*4882a593Smuzhiyun u8 out_stgpn; 194*4882a593Smuzhiyun u8 out_stgpw; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun u8 _rsv[2]; 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun __le32 out_pri_const; 199*4882a593Smuzhiyun __le32 out_pri_stg[3]; 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun struct { 202*4882a593Smuzhiyun __le32 start; 203*4882a593Smuzhiyun __le16 pulse_width; 204*4882a593Smuzhiyun __le16 pulse_power; 205*4882a593Smuzhiyun } long_pulse[32]; 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun struct { 208*4882a593Smuzhiyun __le32 start; 209*4882a593Smuzhiyun __le16 pulse_width; 210*4882a593Smuzhiyun __le16 pulse_power; 211*4882a593Smuzhiyun } periodic_pulse[32]; 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun struct { 214*4882a593Smuzhiyun __le32 start; 215*4882a593Smuzhiyun __le16 pulse_width; 216*4882a593Smuzhiyun __le16 pulse_power; 217*4882a593Smuzhiyun u8 sc_pass; 218*4882a593Smuzhiyun u8 sw_reset; 219*4882a593Smuzhiyun } hw_pulse[32]; 220*4882a593Smuzhiyun }; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10)) 223*4882a593Smuzhiyun #define MCU_PKT_ID 0xa0 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun enum { 226*4882a593Smuzhiyun MCU_Q_QUERY, 227*4882a593Smuzhiyun MCU_Q_SET, 228*4882a593Smuzhiyun MCU_Q_RESERVED, 229*4882a593Smuzhiyun MCU_Q_NA 230*4882a593Smuzhiyun }; 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun enum { 233*4882a593Smuzhiyun MCU_S2D_H2N, 234*4882a593Smuzhiyun MCU_S2D_C2N, 235*4882a593Smuzhiyun MCU_S2D_H2C, 236*4882a593Smuzhiyun MCU_S2D_H2CN 237*4882a593Smuzhiyun }; 238*4882a593Smuzhiyun 239*4882a593Smuzhiyun #define MCU_FW_PREFIX BIT(31) 240*4882a593Smuzhiyun #define MCU_UNI_PREFIX BIT(30) 241*4882a593Smuzhiyun #define MCU_CE_PREFIX BIT(29) 242*4882a593Smuzhiyun #define MCU_QUERY_PREFIX BIT(28) 243*4882a593Smuzhiyun #define MCU_CMD_MASK ~(MCU_FW_PREFIX | MCU_UNI_PREFIX | \ 244*4882a593Smuzhiyun MCU_CE_PREFIX | MCU_QUERY_PREFIX) 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun #define MCU_QUERY_MASK BIT(16) 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun enum { 249*4882a593Smuzhiyun MCU_CMD_TARGET_ADDRESS_LEN_REQ = MCU_FW_PREFIX | 0x01, 250*4882a593Smuzhiyun MCU_CMD_FW_START_REQ = MCU_FW_PREFIX | 0x02, 251*4882a593Smuzhiyun MCU_CMD_INIT_ACCESS_REG = 0x3, 252*4882a593Smuzhiyun MCU_CMD_PATCH_START_REQ = 0x05, 253*4882a593Smuzhiyun MCU_CMD_PATCH_FINISH_REQ = MCU_FW_PREFIX | 0x07, 254*4882a593Smuzhiyun MCU_CMD_PATCH_SEM_CONTROL = MCU_FW_PREFIX | 0x10, 255*4882a593Smuzhiyun MCU_CMD_EXT_CID = 0xED, 256*4882a593Smuzhiyun MCU_CMD_FW_SCATTER = MCU_FW_PREFIX | 0xEE, 257*4882a593Smuzhiyun MCU_CMD_RESTART_DL_REQ = MCU_FW_PREFIX | 0xEF, 258*4882a593Smuzhiyun }; 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun enum { 261*4882a593Smuzhiyun MCU_EXT_CMD_RF_REG_ACCESS = 0x02, 262*4882a593Smuzhiyun MCU_EXT_CMD_PM_STATE_CTRL = 0x07, 263*4882a593Smuzhiyun MCU_EXT_CMD_CHANNEL_SWITCH = 0x08, 264*4882a593Smuzhiyun MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11, 265*4882a593Smuzhiyun MCU_EXT_CMD_FW_LOG_2_HOST = 0x13, 266*4882a593Smuzhiyun MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21, 267*4882a593Smuzhiyun MCU_EXT_CMD_STA_REC_UPDATE = 0x25, 268*4882a593Smuzhiyun MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26, 269*4882a593Smuzhiyun MCU_EXT_CMD_EDCA_UPDATE = 0x27, 270*4882a593Smuzhiyun MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A, 271*4882a593Smuzhiyun MCU_EXT_CMD_GET_TEMP = 0x2c, 272*4882a593Smuzhiyun MCU_EXT_CMD_WTBL_UPDATE = 0x32, 273*4882a593Smuzhiyun MCU_EXT_CMD_SET_RDD_CTRL = 0x3a, 274*4882a593Smuzhiyun MCU_EXT_CMD_ATE_CTRL = 0x3d, 275*4882a593Smuzhiyun MCU_EXT_CMD_PROTECT_CTRL = 0x3e, 276*4882a593Smuzhiyun MCU_EXT_CMD_DBDC_CTRL = 0x45, 277*4882a593Smuzhiyun MCU_EXT_CMD_MAC_INIT_CTRL = 0x46, 278*4882a593Smuzhiyun MCU_EXT_CMD_BCN_OFFLOAD = 0x49, 279*4882a593Smuzhiyun MCU_EXT_CMD_SET_RX_PATH = 0x4e, 280*4882a593Smuzhiyun MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58, 281*4882a593Smuzhiyun MCU_EXT_CMD_RXDCOC_CAL = 0x59, 282*4882a593Smuzhiyun MCU_EXT_CMD_TXDPD_CAL = 0x60, 283*4882a593Smuzhiyun MCU_EXT_CMD_SET_RDD_TH = 0x7c, 284*4882a593Smuzhiyun MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d, 285*4882a593Smuzhiyun }; 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun enum { 288*4882a593Smuzhiyun MCU_UNI_CMD_DEV_INFO_UPDATE = MCU_UNI_PREFIX | 0x01, 289*4882a593Smuzhiyun MCU_UNI_CMD_BSS_INFO_UPDATE = MCU_UNI_PREFIX | 0x02, 290*4882a593Smuzhiyun MCU_UNI_CMD_STA_REC_UPDATE = MCU_UNI_PREFIX | 0x03, 291*4882a593Smuzhiyun MCU_UNI_CMD_SUSPEND = MCU_UNI_PREFIX | 0x05, 292*4882a593Smuzhiyun MCU_UNI_CMD_OFFLOAD = MCU_UNI_PREFIX | 0x06, 293*4882a593Smuzhiyun MCU_UNI_CMD_HIF_CTRL = MCU_UNI_PREFIX | 0x07, 294*4882a593Smuzhiyun }; 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun enum { 297*4882a593Smuzhiyun MCU_ATE_SET_FREQ_OFFSET = 0xa, 298*4882a593Smuzhiyun MCU_ATE_SET_TX_POWER_CONTROL = 0x15, 299*4882a593Smuzhiyun }; 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun struct mt7615_mcu_uni_event { 302*4882a593Smuzhiyun u8 cid; 303*4882a593Smuzhiyun u8 pad[3]; 304*4882a593Smuzhiyun __le32 status; /* 0: success, others: fail */ 305*4882a593Smuzhiyun } __packed; 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun struct mt7615_beacon_loss_event { 308*4882a593Smuzhiyun u8 bss_idx; 309*4882a593Smuzhiyun u8 reason; 310*4882a593Smuzhiyun u8 pad[2]; 311*4882a593Smuzhiyun } __packed; 312*4882a593Smuzhiyun 313*4882a593Smuzhiyun struct mt7615_mcu_scan_ssid { 314*4882a593Smuzhiyun __le32 ssid_len; 315*4882a593Smuzhiyun u8 ssid[IEEE80211_MAX_SSID_LEN]; 316*4882a593Smuzhiyun } __packed; 317*4882a593Smuzhiyun 318*4882a593Smuzhiyun struct mt7615_mcu_scan_channel { 319*4882a593Smuzhiyun u8 band; /* 1: 2.4GHz 320*4882a593Smuzhiyun * 2: 5.0GHz 321*4882a593Smuzhiyun * Others: Reserved 322*4882a593Smuzhiyun */ 323*4882a593Smuzhiyun u8 channel_num; 324*4882a593Smuzhiyun } __packed; 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun struct mt7615_mcu_scan_match { 327*4882a593Smuzhiyun __le32 rssi_th; 328*4882a593Smuzhiyun u8 ssid[IEEE80211_MAX_SSID_LEN]; 329*4882a593Smuzhiyun u8 ssid_len; 330*4882a593Smuzhiyun u8 rsv[3]; 331*4882a593Smuzhiyun } __packed; 332*4882a593Smuzhiyun 333*4882a593Smuzhiyun struct mt7615_hw_scan_req { 334*4882a593Smuzhiyun u8 seq_num; 335*4882a593Smuzhiyun u8 bss_idx; 336*4882a593Smuzhiyun u8 scan_type; /* 0: PASSIVE SCAN 337*4882a593Smuzhiyun * 1: ACTIVE SCAN 338*4882a593Smuzhiyun */ 339*4882a593Smuzhiyun u8 ssid_type; /* BIT(0) wildcard SSID 340*4882a593Smuzhiyun * BIT(1) P2P wildcard SSID 341*4882a593Smuzhiyun * BIT(2) specified SSID + wildcard SSID 342*4882a593Smuzhiyun * BIT(2) + ssid_type_ext BIT(0) specified SSID only 343*4882a593Smuzhiyun */ 344*4882a593Smuzhiyun u8 ssids_num; 345*4882a593Smuzhiyun u8 probe_req_num; /* Number of probe request for each SSID */ 346*4882a593Smuzhiyun u8 scan_func; /* BIT(0) Enable random MAC scan 347*4882a593Smuzhiyun * BIT(1) Disable DBDC scan type 1~3. 348*4882a593Smuzhiyun * BIT(2) Use DBDC scan type 3 (dedicated one RF to scan). 349*4882a593Smuzhiyun */ 350*4882a593Smuzhiyun u8 version; /* 0: Not support fields after ies. 351*4882a593Smuzhiyun * 1: Support fields after ies. 352*4882a593Smuzhiyun */ 353*4882a593Smuzhiyun struct mt7615_mcu_scan_ssid ssids[4]; 354*4882a593Smuzhiyun __le16 probe_delay_time; 355*4882a593Smuzhiyun __le16 channel_dwell_time; /* channel Dwell interval */ 356*4882a593Smuzhiyun __le16 timeout_value; 357*4882a593Smuzhiyun u8 channel_type; /* 0: Full channels 358*4882a593Smuzhiyun * 1: Only 2.4GHz channels 359*4882a593Smuzhiyun * 2: Only 5GHz channels 360*4882a593Smuzhiyun * 3: P2P social channel only (channel #1, #6 and #11) 361*4882a593Smuzhiyun * 4: Specified channels 362*4882a593Smuzhiyun * Others: Reserved 363*4882a593Smuzhiyun */ 364*4882a593Smuzhiyun u8 channels_num; /* valid when channel_type is 4 */ 365*4882a593Smuzhiyun /* valid when channels_num is set */ 366*4882a593Smuzhiyun struct mt7615_mcu_scan_channel channels[32]; 367*4882a593Smuzhiyun __le16 ies_len; 368*4882a593Smuzhiyun u8 ies[MT7615_SCAN_IE_LEN]; 369*4882a593Smuzhiyun /* following fields are valid if version > 0 */ 370*4882a593Smuzhiyun u8 ext_channels_num; 371*4882a593Smuzhiyun u8 ext_ssids_num; 372*4882a593Smuzhiyun __le16 channel_min_dwell_time; 373*4882a593Smuzhiyun struct mt7615_mcu_scan_channel ext_channels[32]; 374*4882a593Smuzhiyun struct mt7615_mcu_scan_ssid ext_ssids[6]; 375*4882a593Smuzhiyun u8 bssid[ETH_ALEN]; 376*4882a593Smuzhiyun u8 random_mac[ETH_ALEN]; /* valid when BIT(1) in scan_func is set. */ 377*4882a593Smuzhiyun u8 pad[63]; 378*4882a593Smuzhiyun u8 ssid_type_ext; 379*4882a593Smuzhiyun } __packed; 380*4882a593Smuzhiyun 381*4882a593Smuzhiyun #define SCAN_DONE_EVENT_MAX_CHANNEL_NUM 64 382*4882a593Smuzhiyun struct mt7615_hw_scan_done { 383*4882a593Smuzhiyun u8 seq_num; 384*4882a593Smuzhiyun u8 sparse_channel_num; 385*4882a593Smuzhiyun struct mt7615_mcu_scan_channel sparse_channel; 386*4882a593Smuzhiyun u8 complete_channel_num; 387*4882a593Smuzhiyun u8 current_state; 388*4882a593Smuzhiyun u8 version; 389*4882a593Smuzhiyun u8 pad; 390*4882a593Smuzhiyun __le32 beacon_scan_num; 391*4882a593Smuzhiyun u8 pno_enabled; 392*4882a593Smuzhiyun u8 pad2[3]; 393*4882a593Smuzhiyun u8 sparse_channel_valid_num; 394*4882a593Smuzhiyun u8 pad3[3]; 395*4882a593Smuzhiyun u8 channel_num[SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 396*4882a593Smuzhiyun /* idle format for channel_idle_time 397*4882a593Smuzhiyun * 0: first bytes: idle time(ms) 2nd byte: dwell time(ms) 398*4882a593Smuzhiyun * 1: first bytes: idle time(8ms) 2nd byte: dwell time(8ms) 399*4882a593Smuzhiyun * 2: dwell time (16us) 400*4882a593Smuzhiyun */ 401*4882a593Smuzhiyun __le16 channel_idle_time[SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 402*4882a593Smuzhiyun /* beacon and probe response count */ 403*4882a593Smuzhiyun u8 beacon_probe_num[SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 404*4882a593Smuzhiyun u8 mdrdy_count[SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 405*4882a593Smuzhiyun __le32 beacon_2g_num; 406*4882a593Smuzhiyun __le32 beacon_5g_num; 407*4882a593Smuzhiyun } __packed; 408*4882a593Smuzhiyun 409*4882a593Smuzhiyun struct mt7615_sched_scan_req { 410*4882a593Smuzhiyun u8 version; 411*4882a593Smuzhiyun u8 seq_num; 412*4882a593Smuzhiyun u8 stop_on_match; 413*4882a593Smuzhiyun u8 ssids_num; 414*4882a593Smuzhiyun u8 match_num; 415*4882a593Smuzhiyun u8 pad; 416*4882a593Smuzhiyun __le16 ie_len; 417*4882a593Smuzhiyun struct mt7615_mcu_scan_ssid ssids[MT7615_MAX_SCHED_SCAN_SSID]; 418*4882a593Smuzhiyun struct mt7615_mcu_scan_match match[MT7615_MAX_SCAN_MATCH]; 419*4882a593Smuzhiyun u8 channel_type; 420*4882a593Smuzhiyun u8 channels_num; 421*4882a593Smuzhiyun u8 intervals_num; 422*4882a593Smuzhiyun u8 scan_func; /* BIT(0) eable random mac address */ 423*4882a593Smuzhiyun struct mt7615_mcu_scan_channel channels[64]; 424*4882a593Smuzhiyun __le16 intervals[MT7615_MAX_SCHED_SCAN_INTERVAL]; 425*4882a593Smuzhiyun u8 random_mac[ETH_ALEN]; /* valid when BIT(0) in scan_func is set */ 426*4882a593Smuzhiyun u8 pad2[58]; 427*4882a593Smuzhiyun } __packed; 428*4882a593Smuzhiyun 429*4882a593Smuzhiyun struct nt7615_sched_scan_done { 430*4882a593Smuzhiyun u8 seq_num; 431*4882a593Smuzhiyun u8 status; /* 0: ssid found */ 432*4882a593Smuzhiyun __le16 pad; 433*4882a593Smuzhiyun } __packed; 434*4882a593Smuzhiyun 435*4882a593Smuzhiyun struct mt7615_mcu_reg_event { 436*4882a593Smuzhiyun __le32 reg; 437*4882a593Smuzhiyun __le32 val; 438*4882a593Smuzhiyun } __packed; 439*4882a593Smuzhiyun 440*4882a593Smuzhiyun struct mt7615_mcu_bss_event { 441*4882a593Smuzhiyun u8 bss_idx; 442*4882a593Smuzhiyun u8 is_absent; 443*4882a593Smuzhiyun u8 free_quota; 444*4882a593Smuzhiyun u8 pad; 445*4882a593Smuzhiyun } __packed; 446*4882a593Smuzhiyun 447*4882a593Smuzhiyun struct mt7615_bss_basic_tlv { 448*4882a593Smuzhiyun __le16 tag; 449*4882a593Smuzhiyun __le16 len; 450*4882a593Smuzhiyun u8 active; 451*4882a593Smuzhiyun u8 omac_idx; 452*4882a593Smuzhiyun u8 hw_bss_idx; 453*4882a593Smuzhiyun u8 band_idx; 454*4882a593Smuzhiyun __le32 conn_type; 455*4882a593Smuzhiyun u8 conn_state; 456*4882a593Smuzhiyun u8 wmm_idx; 457*4882a593Smuzhiyun u8 bssid[ETH_ALEN]; 458*4882a593Smuzhiyun __le16 bmc_tx_wlan_idx; 459*4882a593Smuzhiyun __le16 bcn_interval; 460*4882a593Smuzhiyun u8 dtim_period; 461*4882a593Smuzhiyun u8 phymode; /* bit(0): A 462*4882a593Smuzhiyun * bit(1): B 463*4882a593Smuzhiyun * bit(2): G 464*4882a593Smuzhiyun * bit(3): GN 465*4882a593Smuzhiyun * bit(4): AN 466*4882a593Smuzhiyun * bit(5): AC 467*4882a593Smuzhiyun */ 468*4882a593Smuzhiyun __le16 sta_idx; 469*4882a593Smuzhiyun u8 nonht_basic_phy; 470*4882a593Smuzhiyun u8 pad[3]; 471*4882a593Smuzhiyun } __packed; 472*4882a593Smuzhiyun 473*4882a593Smuzhiyun struct mt7615_bss_qos_tlv { 474*4882a593Smuzhiyun __le16 tag; 475*4882a593Smuzhiyun __le16 len; 476*4882a593Smuzhiyun u8 qos; 477*4882a593Smuzhiyun u8 pad[3]; 478*4882a593Smuzhiyun } __packed; 479*4882a593Smuzhiyun 480*4882a593Smuzhiyun struct mt7615_wow_ctrl_tlv { 481*4882a593Smuzhiyun __le16 tag; 482*4882a593Smuzhiyun __le16 len; 483*4882a593Smuzhiyun u8 cmd; /* 0x1: PM_WOWLAN_REQ_START 484*4882a593Smuzhiyun * 0x2: PM_WOWLAN_REQ_STOP 485*4882a593Smuzhiyun * 0x3: PM_WOWLAN_PARAM_CLEAR 486*4882a593Smuzhiyun */ 487*4882a593Smuzhiyun u8 trigger; /* 0: NONE 488*4882a593Smuzhiyun * BIT(0): NL80211_WOWLAN_TRIG_MAGIC_PKT 489*4882a593Smuzhiyun * BIT(1): NL80211_WOWLAN_TRIG_ANY 490*4882a593Smuzhiyun * BIT(2): NL80211_WOWLAN_TRIG_DISCONNECT 491*4882a593Smuzhiyun * BIT(3): NL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE 492*4882a593Smuzhiyun * BIT(4): BEACON_LOST 493*4882a593Smuzhiyun * BIT(5): NL80211_WOWLAN_TRIG_NET_DETECT 494*4882a593Smuzhiyun */ 495*4882a593Smuzhiyun u8 wakeup_hif; /* 0x0: HIF_SDIO 496*4882a593Smuzhiyun * 0x1: HIF_USB 497*4882a593Smuzhiyun * 0x2: HIF_PCIE 498*4882a593Smuzhiyun * 0x3: HIF_GPIO 499*4882a593Smuzhiyun */ 500*4882a593Smuzhiyun u8 pad; 501*4882a593Smuzhiyun u8 rsv[4]; 502*4882a593Smuzhiyun } __packed; 503*4882a593Smuzhiyun 504*4882a593Smuzhiyun #define MT7615_WOW_MASK_MAX_LEN 16 505*4882a593Smuzhiyun #define MT7615_WOW_PATTEN_MAX_LEN 128 506*4882a593Smuzhiyun struct mt7615_wow_pattern_tlv { 507*4882a593Smuzhiyun __le16 tag; 508*4882a593Smuzhiyun __le16 len; 509*4882a593Smuzhiyun u8 index; /* pattern index */ 510*4882a593Smuzhiyun u8 enable; /* 0: disable 511*4882a593Smuzhiyun * 1: enable 512*4882a593Smuzhiyun */ 513*4882a593Smuzhiyun u8 data_len; /* pattern length */ 514*4882a593Smuzhiyun u8 pad; 515*4882a593Smuzhiyun u8 mask[MT7615_WOW_MASK_MAX_LEN]; 516*4882a593Smuzhiyun u8 pattern[MT7615_WOW_PATTEN_MAX_LEN]; 517*4882a593Smuzhiyun u8 rsv[4]; 518*4882a593Smuzhiyun } __packed; 519*4882a593Smuzhiyun 520*4882a593Smuzhiyun struct mt7615_suspend_tlv { 521*4882a593Smuzhiyun __le16 tag; 522*4882a593Smuzhiyun __le16 len; 523*4882a593Smuzhiyun u8 enable; /* 0: suspend mode disabled 524*4882a593Smuzhiyun * 1: suspend mode enabled 525*4882a593Smuzhiyun */ 526*4882a593Smuzhiyun u8 mdtim; /* LP parameter */ 527*4882a593Smuzhiyun u8 wow_suspend; /* 0: update by origin policy 528*4882a593Smuzhiyun * 1: update by wow dtim 529*4882a593Smuzhiyun */ 530*4882a593Smuzhiyun u8 pad[5]; 531*4882a593Smuzhiyun } __packed; 532*4882a593Smuzhiyun 533*4882a593Smuzhiyun struct mt7615_gtk_rekey_tlv { 534*4882a593Smuzhiyun __le16 tag; 535*4882a593Smuzhiyun __le16 len; 536*4882a593Smuzhiyun u8 kek[NL80211_KEK_LEN]; 537*4882a593Smuzhiyun u8 kck[NL80211_KCK_LEN]; 538*4882a593Smuzhiyun u8 replay_ctr[NL80211_REPLAY_CTR_LEN]; 539*4882a593Smuzhiyun u8 rekey_mode; /* 0: rekey offload enable 540*4882a593Smuzhiyun * 1: rekey offload disable 541*4882a593Smuzhiyun * 2: rekey update 542*4882a593Smuzhiyun */ 543*4882a593Smuzhiyun u8 keyid; 544*4882a593Smuzhiyun u8 pad[2]; 545*4882a593Smuzhiyun __le32 proto; /* WPA-RSN-WAPI-OPSN */ 546*4882a593Smuzhiyun __le32 pairwise_cipher; 547*4882a593Smuzhiyun __le32 group_cipher; 548*4882a593Smuzhiyun __le32 key_mgmt; /* NONE-PSK-IEEE802.1X */ 549*4882a593Smuzhiyun __le32 mgmt_group_cipher; 550*4882a593Smuzhiyun u8 option; /* 1: rekey data update without enabling offload */ 551*4882a593Smuzhiyun u8 reserverd[3]; 552*4882a593Smuzhiyun } __packed; 553*4882a593Smuzhiyun 554*4882a593Smuzhiyun struct mt7615_roc_tlv { 555*4882a593Smuzhiyun u8 bss_idx; 556*4882a593Smuzhiyun u8 token; 557*4882a593Smuzhiyun u8 active; 558*4882a593Smuzhiyun u8 primary_chan; 559*4882a593Smuzhiyun u8 sco; 560*4882a593Smuzhiyun u8 band; 561*4882a593Smuzhiyun u8 width; /* To support 80/160MHz bandwidth */ 562*4882a593Smuzhiyun u8 freq_seg1; /* To support 80/160MHz bandwidth */ 563*4882a593Smuzhiyun u8 freq_seg2; /* To support 80/160MHz bandwidth */ 564*4882a593Smuzhiyun u8 req_type; 565*4882a593Smuzhiyun u8 dbdc_band; 566*4882a593Smuzhiyun u8 rsv0; 567*4882a593Smuzhiyun __le32 max_interval; /* ms */ 568*4882a593Smuzhiyun u8 rsv1[8]; 569*4882a593Smuzhiyun } __packed; 570*4882a593Smuzhiyun 571*4882a593Smuzhiyun struct mt7615_arpns_tlv { 572*4882a593Smuzhiyun __le16 tag; 573*4882a593Smuzhiyun __le16 len; 574*4882a593Smuzhiyun u8 mode; 575*4882a593Smuzhiyun u8 ips_num; 576*4882a593Smuzhiyun u8 option; 577*4882a593Smuzhiyun u8 pad[1]; 578*4882a593Smuzhiyun } __packed; 579*4882a593Smuzhiyun 580*4882a593Smuzhiyun /* offload mcu commands */ 581*4882a593Smuzhiyun enum { 582*4882a593Smuzhiyun MCU_CMD_START_HW_SCAN = MCU_CE_PREFIX | 0x03, 583*4882a593Smuzhiyun MCU_CMD_SET_PS_PROFILE = MCU_CE_PREFIX | 0x05, 584*4882a593Smuzhiyun MCU_CMD_SET_CHAN_DOMAIN = MCU_CE_PREFIX | 0x0f, 585*4882a593Smuzhiyun MCU_CMD_SET_BSS_CONNECTED = MCU_CE_PREFIX | 0x16, 586*4882a593Smuzhiyun MCU_CMD_SET_BSS_ABORT = MCU_CE_PREFIX | 0x17, 587*4882a593Smuzhiyun MCU_CMD_CANCEL_HW_SCAN = MCU_CE_PREFIX | 0x1b, 588*4882a593Smuzhiyun MCU_CMD_SET_ROC = MCU_CE_PREFIX | 0x1c, 589*4882a593Smuzhiyun MCU_CMD_SET_P2P_OPPPS = MCU_CE_PREFIX | 0x33, 590*4882a593Smuzhiyun MCU_CMD_SCHED_SCAN_ENABLE = MCU_CE_PREFIX | 0x61, 591*4882a593Smuzhiyun MCU_CMD_SCHED_SCAN_REQ = MCU_CE_PREFIX | 0x62, 592*4882a593Smuzhiyun MCU_CMD_REG_WRITE = MCU_CE_PREFIX | 0xc0, 593*4882a593Smuzhiyun MCU_CMD_REG_READ = MCU_CE_PREFIX | MCU_QUERY_MASK | 0xc0, 594*4882a593Smuzhiyun }; 595*4882a593Smuzhiyun 596*4882a593Smuzhiyun #define MCU_CMD_ACK BIT(0) 597*4882a593Smuzhiyun #define MCU_CMD_UNI BIT(1) 598*4882a593Smuzhiyun #define MCU_CMD_QUERY BIT(2) 599*4882a593Smuzhiyun 600*4882a593Smuzhiyun #define MCU_CMD_UNI_EXT_ACK (MCU_CMD_ACK | MCU_CMD_UNI | MCU_CMD_QUERY) 601*4882a593Smuzhiyun 602*4882a593Smuzhiyun enum { 603*4882a593Smuzhiyun UNI_BSS_INFO_BASIC = 0, 604*4882a593Smuzhiyun UNI_BSS_INFO_RLM = 2, 605*4882a593Smuzhiyun UNI_BSS_INFO_BCN_CONTENT = 7, 606*4882a593Smuzhiyun UNI_BSS_INFO_QBSS = 15, 607*4882a593Smuzhiyun UNI_BSS_INFO_UAPSD = 19, 608*4882a593Smuzhiyun }; 609*4882a593Smuzhiyun 610*4882a593Smuzhiyun enum { 611*4882a593Smuzhiyun UNI_SUSPEND_MODE_SETTING, 612*4882a593Smuzhiyun UNI_SUSPEND_WOW_CTRL, 613*4882a593Smuzhiyun UNI_SUSPEND_WOW_GPIO_PARAM, 614*4882a593Smuzhiyun UNI_SUSPEND_WOW_WAKEUP_PORT, 615*4882a593Smuzhiyun UNI_SUSPEND_WOW_PATTERN, 616*4882a593Smuzhiyun }; 617*4882a593Smuzhiyun 618*4882a593Smuzhiyun enum { 619*4882a593Smuzhiyun UNI_OFFLOAD_OFFLOAD_ARP, 620*4882a593Smuzhiyun UNI_OFFLOAD_OFFLOAD_ND, 621*4882a593Smuzhiyun UNI_OFFLOAD_OFFLOAD_GTK_REKEY, 622*4882a593Smuzhiyun UNI_OFFLOAD_OFFLOAD_BMC_RPY_DETECT, 623*4882a593Smuzhiyun }; 624*4882a593Smuzhiyun 625*4882a593Smuzhiyun enum { 626*4882a593Smuzhiyun PATCH_SEM_RELEASE = 0x0, 627*4882a593Smuzhiyun PATCH_SEM_GET = 0x1 628*4882a593Smuzhiyun }; 629*4882a593Smuzhiyun 630*4882a593Smuzhiyun enum { 631*4882a593Smuzhiyun PATCH_NOT_DL_SEM_FAIL = 0x0, 632*4882a593Smuzhiyun PATCH_IS_DL = 0x1, 633*4882a593Smuzhiyun PATCH_NOT_DL_SEM_SUCCESS = 0x2, 634*4882a593Smuzhiyun PATCH_REL_SEM_SUCCESS = 0x3 635*4882a593Smuzhiyun }; 636*4882a593Smuzhiyun 637*4882a593Smuzhiyun enum { 638*4882a593Smuzhiyun FW_STATE_INITIAL = 0, 639*4882a593Smuzhiyun FW_STATE_FW_DOWNLOAD = 1, 640*4882a593Smuzhiyun FW_STATE_NORMAL_OPERATION = 2, 641*4882a593Smuzhiyun FW_STATE_NORMAL_TRX = 3, 642*4882a593Smuzhiyun FW_STATE_CR4_RDY = 7 643*4882a593Smuzhiyun }; 644*4882a593Smuzhiyun 645*4882a593Smuzhiyun enum { 646*4882a593Smuzhiyun FW_STATE_PWR_ON = 1, 647*4882a593Smuzhiyun FW_STATE_N9_RDY = 2, 648*4882a593Smuzhiyun }; 649*4882a593Smuzhiyun 650*4882a593Smuzhiyun #define STA_TYPE_STA BIT(0) 651*4882a593Smuzhiyun #define STA_TYPE_AP BIT(1) 652*4882a593Smuzhiyun #define STA_TYPE_ADHOC BIT(2) 653*4882a593Smuzhiyun #define STA_TYPE_WDS BIT(4) 654*4882a593Smuzhiyun #define STA_TYPE_BC BIT(5) 655*4882a593Smuzhiyun 656*4882a593Smuzhiyun #define NETWORK_INFRA BIT(16) 657*4882a593Smuzhiyun #define NETWORK_P2P BIT(17) 658*4882a593Smuzhiyun #define NETWORK_IBSS BIT(18) 659*4882a593Smuzhiyun #define NETWORK_WDS BIT(21) 660*4882a593Smuzhiyun 661*4882a593Smuzhiyun #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA) 662*4882a593Smuzhiyun #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA) 663*4882a593Smuzhiyun #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P) 664*4882a593Smuzhiyun #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P) 665*4882a593Smuzhiyun #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS) 666*4882a593Smuzhiyun #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS) 667*4882a593Smuzhiyun #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA) 668*4882a593Smuzhiyun 669*4882a593Smuzhiyun #define CONN_STATE_DISCONNECT 0 670*4882a593Smuzhiyun #define CONN_STATE_CONNECT 1 671*4882a593Smuzhiyun #define CONN_STATE_PORT_SECURE 2 672*4882a593Smuzhiyun 673*4882a593Smuzhiyun enum { 674*4882a593Smuzhiyun DEV_INFO_ACTIVE, 675*4882a593Smuzhiyun DEV_INFO_MAX_NUM 676*4882a593Smuzhiyun }; 677*4882a593Smuzhiyun 678*4882a593Smuzhiyun enum { 679*4882a593Smuzhiyun DBDC_TYPE_WMM, 680*4882a593Smuzhiyun DBDC_TYPE_MGMT, 681*4882a593Smuzhiyun DBDC_TYPE_BSS, 682*4882a593Smuzhiyun DBDC_TYPE_MBSS, 683*4882a593Smuzhiyun DBDC_TYPE_REPEATER, 684*4882a593Smuzhiyun DBDC_TYPE_MU, 685*4882a593Smuzhiyun DBDC_TYPE_BF, 686*4882a593Smuzhiyun DBDC_TYPE_PTA, 687*4882a593Smuzhiyun __DBDC_TYPE_MAX, 688*4882a593Smuzhiyun }; 689*4882a593Smuzhiyun 690*4882a593Smuzhiyun struct tlv { 691*4882a593Smuzhiyun __le16 tag; 692*4882a593Smuzhiyun __le16 len; 693*4882a593Smuzhiyun } __packed; 694*4882a593Smuzhiyun 695*4882a593Smuzhiyun struct bss_info_omac { 696*4882a593Smuzhiyun __le16 tag; 697*4882a593Smuzhiyun __le16 len; 698*4882a593Smuzhiyun u8 hw_bss_idx; 699*4882a593Smuzhiyun u8 omac_idx; 700*4882a593Smuzhiyun u8 band_idx; 701*4882a593Smuzhiyun u8 rsv0; 702*4882a593Smuzhiyun __le32 conn_type; 703*4882a593Smuzhiyun u32 rsv1; 704*4882a593Smuzhiyun } __packed; 705*4882a593Smuzhiyun 706*4882a593Smuzhiyun struct bss_info_basic { 707*4882a593Smuzhiyun __le16 tag; 708*4882a593Smuzhiyun __le16 len; 709*4882a593Smuzhiyun __le32 network_type; 710*4882a593Smuzhiyun u8 active; 711*4882a593Smuzhiyun u8 rsv0; 712*4882a593Smuzhiyun __le16 bcn_interval; 713*4882a593Smuzhiyun u8 bssid[ETH_ALEN]; 714*4882a593Smuzhiyun u8 wmm_idx; 715*4882a593Smuzhiyun u8 dtim_period; 716*4882a593Smuzhiyun u8 bmc_tx_wlan_idx; 717*4882a593Smuzhiyun u8 cipher; /* not used */ 718*4882a593Smuzhiyun u8 phymode; /* not used */ 719*4882a593Smuzhiyun u8 rsv1[5]; 720*4882a593Smuzhiyun } __packed; 721*4882a593Smuzhiyun 722*4882a593Smuzhiyun struct bss_info_rf_ch { 723*4882a593Smuzhiyun __le16 tag; 724*4882a593Smuzhiyun __le16 len; 725*4882a593Smuzhiyun u8 pri_ch; 726*4882a593Smuzhiyun u8 central_ch0; 727*4882a593Smuzhiyun u8 central_ch1; 728*4882a593Smuzhiyun u8 bw; 729*4882a593Smuzhiyun } __packed; 730*4882a593Smuzhiyun 731*4882a593Smuzhiyun struct bss_info_ext_bss { 732*4882a593Smuzhiyun __le16 tag; 733*4882a593Smuzhiyun __le16 len; 734*4882a593Smuzhiyun __le32 mbss_tsf_offset; /* in unit of us */ 735*4882a593Smuzhiyun u8 rsv[8]; 736*4882a593Smuzhiyun } __packed; 737*4882a593Smuzhiyun 738*4882a593Smuzhiyun enum { 739*4882a593Smuzhiyun BSS_INFO_OMAC, 740*4882a593Smuzhiyun BSS_INFO_BASIC, 741*4882a593Smuzhiyun BSS_INFO_RF_CH, /* optional, for BT/LTE coex */ 742*4882a593Smuzhiyun BSS_INFO_PM, /* sta only */ 743*4882a593Smuzhiyun BSS_INFO_UAPSD, /* sta only */ 744*4882a593Smuzhiyun BSS_INFO_ROAM_DETECTION, /* obsoleted */ 745*4882a593Smuzhiyun BSS_INFO_LQ_RM, /* obsoleted */ 746*4882a593Smuzhiyun BSS_INFO_EXT_BSS, 747*4882a593Smuzhiyun BSS_INFO_BMC_INFO, /* for bmc rate control in CR4 */ 748*4882a593Smuzhiyun BSS_INFO_SYNC_MODE, /* obsoleted */ 749*4882a593Smuzhiyun BSS_INFO_RA, 750*4882a593Smuzhiyun BSS_INFO_MAX_NUM 751*4882a593Smuzhiyun }; 752*4882a593Smuzhiyun 753*4882a593Smuzhiyun enum { 754*4882a593Smuzhiyun WTBL_RESET_AND_SET = 1, 755*4882a593Smuzhiyun WTBL_SET, 756*4882a593Smuzhiyun WTBL_QUERY, 757*4882a593Smuzhiyun WTBL_RESET_ALL 758*4882a593Smuzhiyun }; 759*4882a593Smuzhiyun 760*4882a593Smuzhiyun struct wtbl_req_hdr { 761*4882a593Smuzhiyun u8 wlan_idx; 762*4882a593Smuzhiyun u8 operation; 763*4882a593Smuzhiyun __le16 tlv_num; 764*4882a593Smuzhiyun u8 rsv[4]; 765*4882a593Smuzhiyun } __packed; 766*4882a593Smuzhiyun 767*4882a593Smuzhiyun struct wtbl_generic { 768*4882a593Smuzhiyun __le16 tag; 769*4882a593Smuzhiyun __le16 len; 770*4882a593Smuzhiyun u8 peer_addr[ETH_ALEN]; 771*4882a593Smuzhiyun u8 muar_idx; 772*4882a593Smuzhiyun u8 skip_tx; 773*4882a593Smuzhiyun u8 cf_ack; 774*4882a593Smuzhiyun u8 qos; 775*4882a593Smuzhiyun u8 mesh; 776*4882a593Smuzhiyun u8 adm; 777*4882a593Smuzhiyun __le16 partial_aid; 778*4882a593Smuzhiyun u8 baf_en; 779*4882a593Smuzhiyun u8 aad_om; 780*4882a593Smuzhiyun } __packed; 781*4882a593Smuzhiyun 782*4882a593Smuzhiyun struct wtbl_rx { 783*4882a593Smuzhiyun __le16 tag; 784*4882a593Smuzhiyun __le16 len; 785*4882a593Smuzhiyun u8 rcid; 786*4882a593Smuzhiyun u8 rca1; 787*4882a593Smuzhiyun u8 rca2; 788*4882a593Smuzhiyun u8 rv; 789*4882a593Smuzhiyun u8 rsv[4]; 790*4882a593Smuzhiyun } __packed; 791*4882a593Smuzhiyun 792*4882a593Smuzhiyun struct wtbl_ht { 793*4882a593Smuzhiyun __le16 tag; 794*4882a593Smuzhiyun __le16 len; 795*4882a593Smuzhiyun u8 ht; 796*4882a593Smuzhiyun u8 ldpc; 797*4882a593Smuzhiyun u8 af; 798*4882a593Smuzhiyun u8 mm; 799*4882a593Smuzhiyun u8 rsv[4]; 800*4882a593Smuzhiyun } __packed; 801*4882a593Smuzhiyun 802*4882a593Smuzhiyun struct wtbl_vht { 803*4882a593Smuzhiyun __le16 tag; 804*4882a593Smuzhiyun __le16 len; 805*4882a593Smuzhiyun u8 ldpc; 806*4882a593Smuzhiyun u8 dyn_bw; 807*4882a593Smuzhiyun u8 vht; 808*4882a593Smuzhiyun u8 txop_ps; 809*4882a593Smuzhiyun u8 rsv[4]; 810*4882a593Smuzhiyun } __packed; 811*4882a593Smuzhiyun 812*4882a593Smuzhiyun struct wtbl_tx_ps { 813*4882a593Smuzhiyun __le16 tag; 814*4882a593Smuzhiyun __le16 len; 815*4882a593Smuzhiyun u8 txps; 816*4882a593Smuzhiyun u8 rsv[3]; 817*4882a593Smuzhiyun } __packed; 818*4882a593Smuzhiyun 819*4882a593Smuzhiyun struct wtbl_hdr_trans { 820*4882a593Smuzhiyun __le16 tag; 821*4882a593Smuzhiyun __le16 len; 822*4882a593Smuzhiyun u8 to_ds; 823*4882a593Smuzhiyun u8 from_ds; 824*4882a593Smuzhiyun u8 disable_rx_trans; 825*4882a593Smuzhiyun u8 rsv; 826*4882a593Smuzhiyun } __packed; 827*4882a593Smuzhiyun 828*4882a593Smuzhiyun enum { 829*4882a593Smuzhiyun MT_BA_TYPE_INVALID, 830*4882a593Smuzhiyun MT_BA_TYPE_ORIGINATOR, 831*4882a593Smuzhiyun MT_BA_TYPE_RECIPIENT 832*4882a593Smuzhiyun }; 833*4882a593Smuzhiyun 834*4882a593Smuzhiyun enum { 835*4882a593Smuzhiyun RST_BA_MAC_TID_MATCH, 836*4882a593Smuzhiyun RST_BA_MAC_MATCH, 837*4882a593Smuzhiyun RST_BA_NO_MATCH 838*4882a593Smuzhiyun }; 839*4882a593Smuzhiyun 840*4882a593Smuzhiyun struct wtbl_ba { 841*4882a593Smuzhiyun __le16 tag; 842*4882a593Smuzhiyun __le16 len; 843*4882a593Smuzhiyun /* common */ 844*4882a593Smuzhiyun u8 tid; 845*4882a593Smuzhiyun u8 ba_type; 846*4882a593Smuzhiyun u8 rsv0[2]; 847*4882a593Smuzhiyun /* originator only */ 848*4882a593Smuzhiyun __le16 sn; 849*4882a593Smuzhiyun u8 ba_en; 850*4882a593Smuzhiyun u8 ba_winsize_idx; 851*4882a593Smuzhiyun __le16 ba_winsize; 852*4882a593Smuzhiyun /* recipient only */ 853*4882a593Smuzhiyun u8 peer_addr[ETH_ALEN]; 854*4882a593Smuzhiyun u8 rst_ba_tid; 855*4882a593Smuzhiyun u8 rst_ba_sel; 856*4882a593Smuzhiyun u8 rst_ba_sb; 857*4882a593Smuzhiyun u8 band_idx; 858*4882a593Smuzhiyun u8 rsv1[4]; 859*4882a593Smuzhiyun } __packed; 860*4882a593Smuzhiyun 861*4882a593Smuzhiyun struct wtbl_bf { 862*4882a593Smuzhiyun __le16 tag; 863*4882a593Smuzhiyun __le16 len; 864*4882a593Smuzhiyun u8 ibf; 865*4882a593Smuzhiyun u8 ebf; 866*4882a593Smuzhiyun u8 ibf_vht; 867*4882a593Smuzhiyun u8 ebf_vht; 868*4882a593Smuzhiyun u8 gid; 869*4882a593Smuzhiyun u8 pfmu_idx; 870*4882a593Smuzhiyun u8 rsv[2]; 871*4882a593Smuzhiyun } __packed; 872*4882a593Smuzhiyun 873*4882a593Smuzhiyun struct wtbl_smps { 874*4882a593Smuzhiyun __le16 tag; 875*4882a593Smuzhiyun __le16 len; 876*4882a593Smuzhiyun u8 smps; 877*4882a593Smuzhiyun u8 rsv[3]; 878*4882a593Smuzhiyun } __packed; 879*4882a593Smuzhiyun 880*4882a593Smuzhiyun struct wtbl_pn { 881*4882a593Smuzhiyun __le16 tag; 882*4882a593Smuzhiyun __le16 len; 883*4882a593Smuzhiyun u8 pn[6]; 884*4882a593Smuzhiyun u8 rsv[2]; 885*4882a593Smuzhiyun } __packed; 886*4882a593Smuzhiyun 887*4882a593Smuzhiyun struct wtbl_spe { 888*4882a593Smuzhiyun __le16 tag; 889*4882a593Smuzhiyun __le16 len; 890*4882a593Smuzhiyun u8 spe_idx; 891*4882a593Smuzhiyun u8 rsv[3]; 892*4882a593Smuzhiyun } __packed; 893*4882a593Smuzhiyun 894*4882a593Smuzhiyun struct wtbl_raw { 895*4882a593Smuzhiyun __le16 tag; 896*4882a593Smuzhiyun __le16 len; 897*4882a593Smuzhiyun u8 wtbl_idx; 898*4882a593Smuzhiyun u8 dw; 899*4882a593Smuzhiyun u8 rsv[2]; 900*4882a593Smuzhiyun __le32 msk; 901*4882a593Smuzhiyun __le32 val; 902*4882a593Smuzhiyun } __packed; 903*4882a593Smuzhiyun 904*4882a593Smuzhiyun #define MT7615_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \ 905*4882a593Smuzhiyun sizeof(struct wtbl_generic) + \ 906*4882a593Smuzhiyun sizeof(struct wtbl_rx) + \ 907*4882a593Smuzhiyun sizeof(struct wtbl_ht) + \ 908*4882a593Smuzhiyun sizeof(struct wtbl_vht) + \ 909*4882a593Smuzhiyun sizeof(struct wtbl_tx_ps) + \ 910*4882a593Smuzhiyun sizeof(struct wtbl_hdr_trans) +\ 911*4882a593Smuzhiyun sizeof(struct wtbl_ba) + \ 912*4882a593Smuzhiyun sizeof(struct wtbl_bf) + \ 913*4882a593Smuzhiyun sizeof(struct wtbl_smps) + \ 914*4882a593Smuzhiyun sizeof(struct wtbl_pn) + \ 915*4882a593Smuzhiyun sizeof(struct wtbl_spe)) 916*4882a593Smuzhiyun 917*4882a593Smuzhiyun #define MT7615_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ 918*4882a593Smuzhiyun sizeof(struct sta_rec_basic) + \ 919*4882a593Smuzhiyun sizeof(struct sta_rec_ht) + \ 920*4882a593Smuzhiyun sizeof(struct sta_rec_vht) + \ 921*4882a593Smuzhiyun sizeof(struct sta_rec_uapsd) + \ 922*4882a593Smuzhiyun sizeof(struct tlv) + \ 923*4882a593Smuzhiyun MT7615_WTBL_UPDATE_MAX_SIZE) 924*4882a593Smuzhiyun 925*4882a593Smuzhiyun #define MT7615_WTBL_UPDATE_BA_SIZE (sizeof(struct wtbl_req_hdr) + \ 926*4882a593Smuzhiyun sizeof(struct wtbl_ba)) 927*4882a593Smuzhiyun 928*4882a593Smuzhiyun enum { 929*4882a593Smuzhiyun WTBL_GENERIC, 930*4882a593Smuzhiyun WTBL_RX, 931*4882a593Smuzhiyun WTBL_HT, 932*4882a593Smuzhiyun WTBL_VHT, 933*4882a593Smuzhiyun WTBL_PEER_PS, /* not used */ 934*4882a593Smuzhiyun WTBL_TX_PS, 935*4882a593Smuzhiyun WTBL_HDR_TRANS, 936*4882a593Smuzhiyun WTBL_SEC_KEY, 937*4882a593Smuzhiyun WTBL_BA, 938*4882a593Smuzhiyun WTBL_RDG, /* obsoleted */ 939*4882a593Smuzhiyun WTBL_PROTECT, /* not used */ 940*4882a593Smuzhiyun WTBL_CLEAR, /* not used */ 941*4882a593Smuzhiyun WTBL_BF, 942*4882a593Smuzhiyun WTBL_SMPS, 943*4882a593Smuzhiyun WTBL_RAW_DATA, /* debug only */ 944*4882a593Smuzhiyun WTBL_PN, 945*4882a593Smuzhiyun WTBL_SPE, 946*4882a593Smuzhiyun WTBL_MAX_NUM 947*4882a593Smuzhiyun }; 948*4882a593Smuzhiyun 949*4882a593Smuzhiyun struct sta_ntlv_hdr { 950*4882a593Smuzhiyun u8 rsv[2]; 951*4882a593Smuzhiyun __le16 tlv_num; 952*4882a593Smuzhiyun } __packed; 953*4882a593Smuzhiyun 954*4882a593Smuzhiyun struct sta_req_hdr { 955*4882a593Smuzhiyun u8 bss_idx; 956*4882a593Smuzhiyun u8 wlan_idx; 957*4882a593Smuzhiyun __le16 tlv_num; 958*4882a593Smuzhiyun u8 is_tlv_append; 959*4882a593Smuzhiyun u8 muar_idx; 960*4882a593Smuzhiyun u8 rsv[2]; 961*4882a593Smuzhiyun } __packed; 962*4882a593Smuzhiyun 963*4882a593Smuzhiyun struct sta_rec_state { 964*4882a593Smuzhiyun __le16 tag; 965*4882a593Smuzhiyun __le16 len; 966*4882a593Smuzhiyun u8 state; 967*4882a593Smuzhiyun __le32 flags; 968*4882a593Smuzhiyun u8 vhtop; 969*4882a593Smuzhiyun u8 pad[2]; 970*4882a593Smuzhiyun } __packed; 971*4882a593Smuzhiyun 972*4882a593Smuzhiyun struct sta_rec_basic { 973*4882a593Smuzhiyun __le16 tag; 974*4882a593Smuzhiyun __le16 len; 975*4882a593Smuzhiyun __le32 conn_type; 976*4882a593Smuzhiyun u8 conn_state; 977*4882a593Smuzhiyun u8 qos; 978*4882a593Smuzhiyun __le16 aid; 979*4882a593Smuzhiyun u8 peer_addr[ETH_ALEN]; 980*4882a593Smuzhiyun #define EXTRA_INFO_VER BIT(0) 981*4882a593Smuzhiyun #define EXTRA_INFO_NEW BIT(1) 982*4882a593Smuzhiyun __le16 extra_info; 983*4882a593Smuzhiyun } __packed; 984*4882a593Smuzhiyun 985*4882a593Smuzhiyun struct sta_rec_ht { 986*4882a593Smuzhiyun __le16 tag; 987*4882a593Smuzhiyun __le16 len; 988*4882a593Smuzhiyun __le16 ht_cap; 989*4882a593Smuzhiyun u16 rsv; 990*4882a593Smuzhiyun } __packed; 991*4882a593Smuzhiyun 992*4882a593Smuzhiyun struct sta_rec_vht { 993*4882a593Smuzhiyun __le16 tag; 994*4882a593Smuzhiyun __le16 len; 995*4882a593Smuzhiyun __le32 vht_cap; 996*4882a593Smuzhiyun __le16 vht_rx_mcs_map; 997*4882a593Smuzhiyun __le16 vht_tx_mcs_map; 998*4882a593Smuzhiyun } __packed; 999*4882a593Smuzhiyun 1000*4882a593Smuzhiyun struct sta_rec_ba { 1001*4882a593Smuzhiyun __le16 tag; 1002*4882a593Smuzhiyun __le16 len; 1003*4882a593Smuzhiyun u8 tid; 1004*4882a593Smuzhiyun u8 ba_type; 1005*4882a593Smuzhiyun u8 amsdu; 1006*4882a593Smuzhiyun u8 ba_en; 1007*4882a593Smuzhiyun __le16 ssn; 1008*4882a593Smuzhiyun __le16 winsize; 1009*4882a593Smuzhiyun } __packed; 1010*4882a593Smuzhiyun 1011*4882a593Smuzhiyun struct sta_rec_uapsd { 1012*4882a593Smuzhiyun __le16 tag; 1013*4882a593Smuzhiyun __le16 len; 1014*4882a593Smuzhiyun u8 dac_map; 1015*4882a593Smuzhiyun u8 tac_map; 1016*4882a593Smuzhiyun u8 max_sp; 1017*4882a593Smuzhiyun u8 rsv0; 1018*4882a593Smuzhiyun __le16 listen_interval; 1019*4882a593Smuzhiyun u8 rsv1[2]; 1020*4882a593Smuzhiyun } __packed; 1021*4882a593Smuzhiyun 1022*4882a593Smuzhiyun enum { 1023*4882a593Smuzhiyun STA_REC_BASIC, 1024*4882a593Smuzhiyun STA_REC_RA, 1025*4882a593Smuzhiyun STA_REC_RA_CMM_INFO, 1026*4882a593Smuzhiyun STA_REC_RA_UPDATE, 1027*4882a593Smuzhiyun STA_REC_BF, 1028*4882a593Smuzhiyun STA_REC_AMSDU, /* for CR4 */ 1029*4882a593Smuzhiyun STA_REC_BA, 1030*4882a593Smuzhiyun STA_REC_STATE, 1031*4882a593Smuzhiyun STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */ 1032*4882a593Smuzhiyun STA_REC_HT, 1033*4882a593Smuzhiyun STA_REC_VHT, 1034*4882a593Smuzhiyun STA_REC_APPS, 1035*4882a593Smuzhiyun STA_REC_WTBL = 13, 1036*4882a593Smuzhiyun STA_REC_MAX_NUM 1037*4882a593Smuzhiyun }; 1038*4882a593Smuzhiyun 1039*4882a593Smuzhiyun enum { 1040*4882a593Smuzhiyun CMD_CBW_20MHZ, 1041*4882a593Smuzhiyun CMD_CBW_40MHZ, 1042*4882a593Smuzhiyun CMD_CBW_80MHZ, 1043*4882a593Smuzhiyun CMD_CBW_160MHZ, 1044*4882a593Smuzhiyun CMD_CBW_10MHZ, 1045*4882a593Smuzhiyun CMD_CBW_5MHZ, 1046*4882a593Smuzhiyun CMD_CBW_8080MHZ 1047*4882a593Smuzhiyun }; 1048*4882a593Smuzhiyun 1049*4882a593Smuzhiyun enum { 1050*4882a593Smuzhiyun CH_SWITCH_NORMAL = 0, 1051*4882a593Smuzhiyun CH_SWITCH_SCAN = 3, 1052*4882a593Smuzhiyun CH_SWITCH_MCC = 4, 1053*4882a593Smuzhiyun CH_SWITCH_DFS = 5, 1054*4882a593Smuzhiyun CH_SWITCH_BACKGROUND_SCAN_START = 6, 1055*4882a593Smuzhiyun CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7, 1056*4882a593Smuzhiyun CH_SWITCH_BACKGROUND_SCAN_STOP = 8, 1057*4882a593Smuzhiyun CH_SWITCH_SCAN_BYPASS_DPD = 9 1058*4882a593Smuzhiyun }; 1059*4882a593Smuzhiyun 1060*4882a593Smuzhiyun #endif 1061