xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/mediatek/mt76/mt7615/init.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: ISC
2*4882a593Smuzhiyun /* Copyright (C) 2019 MediaTek Inc.
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Author: Roy Luo <royluo@google.com>
5*4882a593Smuzhiyun  *         Ryder Lee <ryder.lee@mediatek.com>
6*4882a593Smuzhiyun  *         Felix Fietkau <nbd@nbd.name>
7*4882a593Smuzhiyun  *         Lorenzo Bianconi <lorenzo@kernel.org>
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/etherdevice.h>
11*4882a593Smuzhiyun #include "mt7615.h"
12*4882a593Smuzhiyun #include "mac.h"
13*4882a593Smuzhiyun #include "eeprom.h"
14*4882a593Smuzhiyun 
mt7615_phy_init(struct mt7615_dev * dev)15*4882a593Smuzhiyun void mt7615_phy_init(struct mt7615_dev *dev)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun 	/* disable rf low power beacon mode */
18*4882a593Smuzhiyun 	mt76_set(dev, MT_WF_PHY_WF2_RFCTRL0(0), MT_WF_PHY_WF2_RFCTRL0_LPBCN_EN);
19*4882a593Smuzhiyun 	mt76_set(dev, MT_WF_PHY_WF2_RFCTRL0(1), MT_WF_PHY_WF2_RFCTRL0_LPBCN_EN);
20*4882a593Smuzhiyun }
21*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt7615_phy_init);
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun static void
mt7615_init_mac_chain(struct mt7615_dev * dev,int chain)24*4882a593Smuzhiyun mt7615_init_mac_chain(struct mt7615_dev *dev, int chain)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun 	u32 val;
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun 	if (!chain)
29*4882a593Smuzhiyun 		val = MT_CFG_CCR_MAC_D0_1X_GC_EN | MT_CFG_CCR_MAC_D0_2X_GC_EN;
30*4882a593Smuzhiyun 	else
31*4882a593Smuzhiyun 		val = MT_CFG_CCR_MAC_D1_1X_GC_EN | MT_CFG_CCR_MAC_D1_2X_GC_EN;
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun 	/* enable band 0/1 clk */
34*4882a593Smuzhiyun 	mt76_set(dev, MT_CFG_CCR, val);
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun 	mt76_rmw(dev, MT_TMAC_TRCR(chain),
37*4882a593Smuzhiyun 		 MT_TMAC_TRCR_CCA_SEL | MT_TMAC_TRCR_SEC_CCA_SEL,
38*4882a593Smuzhiyun 		 FIELD_PREP(MT_TMAC_TRCR_CCA_SEL, 2) |
39*4882a593Smuzhiyun 		 FIELD_PREP(MT_TMAC_TRCR_SEC_CCA_SEL, 0));
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun 	mt76_wr(dev, MT_AGG_ACR(chain),
42*4882a593Smuzhiyun 		MT_AGG_ACR_PKT_TIME_EN | MT_AGG_ACR_NO_BA_AR_RULE |
43*4882a593Smuzhiyun 		FIELD_PREP(MT_AGG_ACR_CFEND_RATE, MT7615_CFEND_RATE_DEFAULT) |
44*4882a593Smuzhiyun 		FIELD_PREP(MT_AGG_ACR_BAR_RATE, MT7615_BAR_RATE_DEFAULT));
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 	mt76_wr(dev, MT_AGG_ARUCR(chain),
47*4882a593Smuzhiyun 		FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), 7) |
48*4882a593Smuzhiyun 		FIELD_PREP(MT_AGG_ARxCR_LIMIT(1), 2) |
49*4882a593Smuzhiyun 		FIELD_PREP(MT_AGG_ARxCR_LIMIT(2), 2) |
50*4882a593Smuzhiyun 		FIELD_PREP(MT_AGG_ARxCR_LIMIT(3), 2) |
51*4882a593Smuzhiyun 		FIELD_PREP(MT_AGG_ARxCR_LIMIT(4), 1) |
52*4882a593Smuzhiyun 		FIELD_PREP(MT_AGG_ARxCR_LIMIT(5), 1) |
53*4882a593Smuzhiyun 		FIELD_PREP(MT_AGG_ARxCR_LIMIT(6), 1) |
54*4882a593Smuzhiyun 		FIELD_PREP(MT_AGG_ARxCR_LIMIT(7), 1));
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun 	mt76_wr(dev, MT_AGG_ARDCR(chain),
57*4882a593Smuzhiyun 		FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), MT7615_RATE_RETRY - 1) |
58*4882a593Smuzhiyun 		FIELD_PREP(MT_AGG_ARxCR_LIMIT(1), MT7615_RATE_RETRY - 1) |
59*4882a593Smuzhiyun 		FIELD_PREP(MT_AGG_ARxCR_LIMIT(2), MT7615_RATE_RETRY - 1) |
60*4882a593Smuzhiyun 		FIELD_PREP(MT_AGG_ARxCR_LIMIT(3), MT7615_RATE_RETRY - 1) |
61*4882a593Smuzhiyun 		FIELD_PREP(MT_AGG_ARxCR_LIMIT(4), MT7615_RATE_RETRY - 1) |
62*4882a593Smuzhiyun 		FIELD_PREP(MT_AGG_ARxCR_LIMIT(5), MT7615_RATE_RETRY - 1) |
63*4882a593Smuzhiyun 		FIELD_PREP(MT_AGG_ARxCR_LIMIT(6), MT7615_RATE_RETRY - 1) |
64*4882a593Smuzhiyun 		FIELD_PREP(MT_AGG_ARxCR_LIMIT(7), MT7615_RATE_RETRY - 1));
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 	mt76_clear(dev, MT_DMA_RCFR0(chain), MT_DMA_RCFR0_MCU_RX_TDLS);
67*4882a593Smuzhiyun 	if (!mt7615_firmware_offload(dev)) {
68*4882a593Smuzhiyun 		u32 mask, set;
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun 		mask = MT_DMA_RCFR0_MCU_RX_MGMT |
71*4882a593Smuzhiyun 		       MT_DMA_RCFR0_MCU_RX_CTL_NON_BAR |
72*4882a593Smuzhiyun 		       MT_DMA_RCFR0_MCU_RX_CTL_BAR |
73*4882a593Smuzhiyun 		       MT_DMA_RCFR0_MCU_RX_BYPASS |
74*4882a593Smuzhiyun 		       MT_DMA_RCFR0_RX_DROPPED_UCAST |
75*4882a593Smuzhiyun 		       MT_DMA_RCFR0_RX_DROPPED_MCAST;
76*4882a593Smuzhiyun 		set = FIELD_PREP(MT_DMA_RCFR0_RX_DROPPED_UCAST, 2) |
77*4882a593Smuzhiyun 		      FIELD_PREP(MT_DMA_RCFR0_RX_DROPPED_MCAST, 2);
78*4882a593Smuzhiyun 		mt76_rmw(dev, MT_DMA_RCFR0(chain), mask, set);
79*4882a593Smuzhiyun 	}
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun 
mt7615_mac_init(struct mt7615_dev * dev)82*4882a593Smuzhiyun void mt7615_mac_init(struct mt7615_dev *dev)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun 	int i;
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 	mt7615_init_mac_chain(dev, 0);
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	mt76_rmw_field(dev, MT_TMAC_CTCR0,
89*4882a593Smuzhiyun 		       MT_TMAC_CTCR0_INS_DDLMT_REFTIME, 0x3f);
90*4882a593Smuzhiyun 	mt76_rmw_field(dev, MT_TMAC_CTCR0,
91*4882a593Smuzhiyun 		       MT_TMAC_CTCR0_INS_DDLMT_DENSITY, 0x3);
92*4882a593Smuzhiyun 	mt76_rmw(dev, MT_TMAC_CTCR0,
93*4882a593Smuzhiyun 		 MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN |
94*4882a593Smuzhiyun 		 MT_TMAC_CTCR0_INS_DDLMT_EN,
95*4882a593Smuzhiyun 		 MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN |
96*4882a593Smuzhiyun 		 MT_TMAC_CTCR0_INS_DDLMT_EN);
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	mt7615_mcu_set_rts_thresh(&dev->phy, 0x92b);
99*4882a593Smuzhiyun 	mt7615_mac_set_scs(&dev->phy, true);
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	mt76_rmw(dev, MT_AGG_SCR, MT_AGG_SCR_NLNAV_MID_PTEC_DIS,
102*4882a593Smuzhiyun 		 MT_AGG_SCR_NLNAV_MID_PTEC_DIS);
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	mt76_wr(dev, MT_AGG_ARCR,
105*4882a593Smuzhiyun 		FIELD_PREP(MT_AGG_ARCR_RTS_RATE_THR, 2) |
106*4882a593Smuzhiyun 		MT_AGG_ARCR_RATE_DOWN_RATIO_EN |
107*4882a593Smuzhiyun 		FIELD_PREP(MT_AGG_ARCR_RATE_DOWN_RATIO, 1) |
108*4882a593Smuzhiyun 		FIELD_PREP(MT_AGG_ARCR_RATE_UP_EXTRA_TH, 4));
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	for (i = 0; i < MT7615_WTBL_SIZE; i++)
111*4882a593Smuzhiyun 		mt7615_mac_wtbl_update(dev, i,
112*4882a593Smuzhiyun 				       MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_EN);
115*4882a593Smuzhiyun 	mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0, MT_WF_RMAC_MIB_RXTIME_EN);
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	/* disable hdr translation and hw AMSDU */
118*4882a593Smuzhiyun 	mt76_wr(dev, MT_DMA_DCR0,
119*4882a593Smuzhiyun 		FIELD_PREP(MT_DMA_DCR0_MAX_RX_LEN, 3072) |
120*4882a593Smuzhiyun 		MT_DMA_DCR0_RX_VEC_DROP);
121*4882a593Smuzhiyun 	/* disable TDLS filtering */
122*4882a593Smuzhiyun 	mt76_clear(dev, MT_WF_PFCR, MT_WF_PFCR_TDLS_EN);
123*4882a593Smuzhiyun 	mt76_set(dev, MT_WF_MIB_SCR0, MT_MIB_SCR0_AGG_CNT_RANGE_EN);
124*4882a593Smuzhiyun 	if (is_mt7663(&dev->mt76)) {
125*4882a593Smuzhiyun 		mt76_wr(dev, MT_WF_AGG(0x160), 0x5c341c02);
126*4882a593Smuzhiyun 		mt76_wr(dev, MT_WF_AGG(0x164), 0x70708040);
127*4882a593Smuzhiyun 	} else {
128*4882a593Smuzhiyun 		mt7615_init_mac_chain(dev, 1);
129*4882a593Smuzhiyun 	}
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt7615_mac_init);
132*4882a593Smuzhiyun 
mt7615_check_offload_capability(struct mt7615_dev * dev)133*4882a593Smuzhiyun void mt7615_check_offload_capability(struct mt7615_dev *dev)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun 	struct ieee80211_hw *hw = mt76_hw(dev);
136*4882a593Smuzhiyun 	struct wiphy *wiphy = hw->wiphy;
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 	if (mt7615_firmware_offload(dev)) {
139*4882a593Smuzhiyun 		ieee80211_hw_set(hw, SUPPORTS_PS);
140*4882a593Smuzhiyun 		ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 		wiphy->max_remain_on_channel_duration = 5000;
143*4882a593Smuzhiyun 		wiphy->features |= NL80211_FEATURE_SCHED_SCAN_RANDOM_MAC_ADDR |
144*4882a593Smuzhiyun 				   NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR |
145*4882a593Smuzhiyun 				   WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL |
146*4882a593Smuzhiyun 				   NL80211_FEATURE_P2P_GO_CTWIN |
147*4882a593Smuzhiyun 				   NL80211_FEATURE_P2P_GO_OPPPS;
148*4882a593Smuzhiyun 	} else {
149*4882a593Smuzhiyun 		dev->ops->hw_scan = NULL;
150*4882a593Smuzhiyun 		dev->ops->cancel_hw_scan = NULL;
151*4882a593Smuzhiyun 		dev->ops->sched_scan_start = NULL;
152*4882a593Smuzhiyun 		dev->ops->sched_scan_stop = NULL;
153*4882a593Smuzhiyun 		dev->ops->set_rekey_data = NULL;
154*4882a593Smuzhiyun 		dev->ops->remain_on_channel = NULL;
155*4882a593Smuzhiyun 		dev->ops->cancel_remain_on_channel = NULL;
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 		wiphy->max_sched_scan_plan_interval = 0;
158*4882a593Smuzhiyun 		wiphy->max_sched_scan_ie_len = 0;
159*4882a593Smuzhiyun 		wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
160*4882a593Smuzhiyun 		wiphy->max_sched_scan_ssids = 0;
161*4882a593Smuzhiyun 		wiphy->max_match_sets = 0;
162*4882a593Smuzhiyun 		wiphy->max_sched_scan_reqs = 0;
163*4882a593Smuzhiyun 	}
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt7615_check_offload_capability);
166*4882a593Smuzhiyun 
mt7615_wait_for_mcu_init(struct mt7615_dev * dev)167*4882a593Smuzhiyun bool mt7615_wait_for_mcu_init(struct mt7615_dev *dev)
168*4882a593Smuzhiyun {
169*4882a593Smuzhiyun 	flush_work(&dev->mcu_work);
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 	return test_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state);
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt7615_wait_for_mcu_init);
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun #define CCK_RATE(_idx, _rate) {						\
176*4882a593Smuzhiyun 	.bitrate = _rate,						\
177*4882a593Smuzhiyun 	.flags = IEEE80211_RATE_SHORT_PREAMBLE,				\
178*4882a593Smuzhiyun 	.hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx),			\
179*4882a593Smuzhiyun 	.hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + (_idx)),	\
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun #define OFDM_RATE(_idx, _rate) {					\
183*4882a593Smuzhiyun 	.bitrate = _rate,						\
184*4882a593Smuzhiyun 	.hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx),			\
185*4882a593Smuzhiyun 	.hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx),		\
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun struct ieee80211_rate mt7615_rates[] = {
189*4882a593Smuzhiyun 	CCK_RATE(0, 10),
190*4882a593Smuzhiyun 	CCK_RATE(1, 20),
191*4882a593Smuzhiyun 	CCK_RATE(2, 55),
192*4882a593Smuzhiyun 	CCK_RATE(3, 110),
193*4882a593Smuzhiyun 	OFDM_RATE(11, 60),
194*4882a593Smuzhiyun 	OFDM_RATE(15, 90),
195*4882a593Smuzhiyun 	OFDM_RATE(10, 120),
196*4882a593Smuzhiyun 	OFDM_RATE(14, 180),
197*4882a593Smuzhiyun 	OFDM_RATE(9,  240),
198*4882a593Smuzhiyun 	OFDM_RATE(13, 360),
199*4882a593Smuzhiyun 	OFDM_RATE(8,  480),
200*4882a593Smuzhiyun 	OFDM_RATE(12, 540),
201*4882a593Smuzhiyun };
202*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt7615_rates);
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun static const struct ieee80211_iface_limit if_limits[] = {
205*4882a593Smuzhiyun 	{
206*4882a593Smuzhiyun 		.max = 1,
207*4882a593Smuzhiyun 		.types = BIT(NL80211_IFTYPE_ADHOC)
208*4882a593Smuzhiyun 	}, {
209*4882a593Smuzhiyun 		.max = MT7615_MAX_INTERFACES,
210*4882a593Smuzhiyun 		.types = BIT(NL80211_IFTYPE_AP) |
211*4882a593Smuzhiyun #ifdef CONFIG_MAC80211_MESH
212*4882a593Smuzhiyun 			 BIT(NL80211_IFTYPE_MESH_POINT) |
213*4882a593Smuzhiyun #endif
214*4882a593Smuzhiyun 			 BIT(NL80211_IFTYPE_P2P_CLIENT) |
215*4882a593Smuzhiyun 			 BIT(NL80211_IFTYPE_P2P_GO) |
216*4882a593Smuzhiyun 			 BIT(NL80211_IFTYPE_STATION)
217*4882a593Smuzhiyun 	}
218*4882a593Smuzhiyun };
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun static const struct ieee80211_iface_combination if_comb_radar[] = {
221*4882a593Smuzhiyun 	{
222*4882a593Smuzhiyun 		.limits = if_limits,
223*4882a593Smuzhiyun 		.n_limits = ARRAY_SIZE(if_limits),
224*4882a593Smuzhiyun 		.max_interfaces = 4,
225*4882a593Smuzhiyun 		.num_different_channels = 1,
226*4882a593Smuzhiyun 		.beacon_int_infra_match = true,
227*4882a593Smuzhiyun 		.radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
228*4882a593Smuzhiyun 				       BIT(NL80211_CHAN_WIDTH_20) |
229*4882a593Smuzhiyun 				       BIT(NL80211_CHAN_WIDTH_40) |
230*4882a593Smuzhiyun 				       BIT(NL80211_CHAN_WIDTH_80) |
231*4882a593Smuzhiyun 				       BIT(NL80211_CHAN_WIDTH_160) |
232*4882a593Smuzhiyun 				       BIT(NL80211_CHAN_WIDTH_80P80),
233*4882a593Smuzhiyun 	}
234*4882a593Smuzhiyun };
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun static const struct ieee80211_iface_combination if_comb[] = {
237*4882a593Smuzhiyun 	{
238*4882a593Smuzhiyun 		.limits = if_limits,
239*4882a593Smuzhiyun 		.n_limits = ARRAY_SIZE(if_limits),
240*4882a593Smuzhiyun 		.max_interfaces = 4,
241*4882a593Smuzhiyun 		.num_different_channels = 1,
242*4882a593Smuzhiyun 		.beacon_int_infra_match = true,
243*4882a593Smuzhiyun 	}
244*4882a593Smuzhiyun };
245*4882a593Smuzhiyun 
mt7615_init_txpower(struct mt7615_dev * dev,struct ieee80211_supported_band * sband)246*4882a593Smuzhiyun void mt7615_init_txpower(struct mt7615_dev *dev,
247*4882a593Smuzhiyun 			 struct ieee80211_supported_band *sband)
248*4882a593Smuzhiyun {
249*4882a593Smuzhiyun 	int i, n_chains = hweight8(dev->mphy.antenna_mask), target_chains;
250*4882a593Smuzhiyun 	int delta_idx, delta = mt76_tx_power_nss_delta(n_chains);
251*4882a593Smuzhiyun 	u8 *eep = (u8 *)dev->mt76.eeprom.data;
252*4882a593Smuzhiyun 	enum nl80211_band band = sband->band;
253*4882a593Smuzhiyun 	u8 rate_val;
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun 	delta_idx = mt7615_eeprom_get_power_delta_index(dev, band);
256*4882a593Smuzhiyun 	rate_val = eep[delta_idx];
257*4882a593Smuzhiyun 	if ((rate_val & ~MT_EE_RATE_POWER_MASK) ==
258*4882a593Smuzhiyun 	    (MT_EE_RATE_POWER_EN | MT_EE_RATE_POWER_SIGN))
259*4882a593Smuzhiyun 		delta += rate_val & MT_EE_RATE_POWER_MASK;
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun 	if (!is_mt7663(&dev->mt76) && mt7615_ext_pa_enabled(dev, band))
262*4882a593Smuzhiyun 		target_chains = 1;
263*4882a593Smuzhiyun 	else
264*4882a593Smuzhiyun 		target_chains = n_chains;
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	for (i = 0; i < sband->n_channels; i++) {
267*4882a593Smuzhiyun 		struct ieee80211_channel *chan = &sband->channels[i];
268*4882a593Smuzhiyun 		u8 target_power = 0;
269*4882a593Smuzhiyun 		int j;
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 		for (j = 0; j < target_chains; j++) {
272*4882a593Smuzhiyun 			int index;
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun 			index = mt7615_eeprom_get_target_power_index(dev, chan, j);
275*4882a593Smuzhiyun 			if (index < 0)
276*4882a593Smuzhiyun 				continue;
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun 			target_power = max(target_power, eep[index]);
279*4882a593Smuzhiyun 		}
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun 		target_power = DIV_ROUND_UP(target_power + delta, 2);
282*4882a593Smuzhiyun 		chan->max_power = min_t(int, chan->max_reg_power,
283*4882a593Smuzhiyun 					target_power);
284*4882a593Smuzhiyun 		chan->orig_mpwr = target_power;
285*4882a593Smuzhiyun 	}
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt7615_init_txpower);
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun static void
mt7615_regd_notifier(struct wiphy * wiphy,struct regulatory_request * request)290*4882a593Smuzhiyun mt7615_regd_notifier(struct wiphy *wiphy,
291*4882a593Smuzhiyun 		     struct regulatory_request *request)
292*4882a593Smuzhiyun {
293*4882a593Smuzhiyun 	struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
294*4882a593Smuzhiyun 	struct mt7615_dev *dev = mt7615_hw_dev(hw);
295*4882a593Smuzhiyun 	struct mt76_phy *mphy = hw->priv;
296*4882a593Smuzhiyun 	struct mt7615_phy *phy = mphy->priv;
297*4882a593Smuzhiyun 	struct cfg80211_chan_def *chandef = &mphy->chandef;
298*4882a593Smuzhiyun 
299*4882a593Smuzhiyun 	dev->mt76.region = request->dfs_region;
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun 	if (!(chandef->chan->flags & IEEE80211_CHAN_RADAR))
302*4882a593Smuzhiyun 		return;
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun 	mt7615_mutex_acquire(dev);
305*4882a593Smuzhiyun 	mt7615_dfs_init_radar_detector(phy);
306*4882a593Smuzhiyun 	mt7615_mutex_release(dev);
307*4882a593Smuzhiyun }
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun static void
mt7615_init_wiphy(struct ieee80211_hw * hw)310*4882a593Smuzhiyun mt7615_init_wiphy(struct ieee80211_hw *hw)
311*4882a593Smuzhiyun {
312*4882a593Smuzhiyun 	struct mt7615_phy *phy = mt7615_hw_phy(hw);
313*4882a593Smuzhiyun 	struct wiphy *wiphy = hw->wiphy;
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun 	hw->queues = 4;
316*4882a593Smuzhiyun 	hw->max_rates = 3;
317*4882a593Smuzhiyun 	hw->max_report_rates = 7;
318*4882a593Smuzhiyun 	hw->max_rate_tries = 11;
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun 	phy->slottime = 9;
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun 	hw->sta_data_size = sizeof(struct mt7615_sta);
323*4882a593Smuzhiyun 	hw->vif_data_size = sizeof(struct mt7615_vif);
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun 	if (is_mt7663(&phy->dev->mt76)) {
326*4882a593Smuzhiyun 		wiphy->iface_combinations = if_comb;
327*4882a593Smuzhiyun 		wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
328*4882a593Smuzhiyun 	} else {
329*4882a593Smuzhiyun 		wiphy->iface_combinations = if_comb_radar;
330*4882a593Smuzhiyun 		wiphy->n_iface_combinations = ARRAY_SIZE(if_comb_radar);
331*4882a593Smuzhiyun 	}
332*4882a593Smuzhiyun 	wiphy->reg_notifier = mt7615_regd_notifier;
333*4882a593Smuzhiyun 
334*4882a593Smuzhiyun 	wiphy->max_sched_scan_plan_interval = MT7615_MAX_SCHED_SCAN_INTERVAL;
335*4882a593Smuzhiyun 	wiphy->max_sched_scan_ie_len = IEEE80211_MAX_DATA_LEN;
336*4882a593Smuzhiyun 	wiphy->max_scan_ie_len = MT7615_SCAN_IE_LEN;
337*4882a593Smuzhiyun 	wiphy->max_sched_scan_ssids = MT7615_MAX_SCHED_SCAN_SSID;
338*4882a593Smuzhiyun 	wiphy->max_match_sets = MT7615_MAX_SCAN_MATCH;
339*4882a593Smuzhiyun 	wiphy->max_sched_scan_reqs = 1;
340*4882a593Smuzhiyun 	wiphy->max_scan_ssids = 4;
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun 	wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL);
343*4882a593Smuzhiyun 	wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS);
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun 	ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS);
346*4882a593Smuzhiyun 	ieee80211_hw_set(hw, TX_STATUS_NO_AMPDU_LEN);
347*4882a593Smuzhiyun 	ieee80211_hw_set(hw, WANT_MONITOR_VIF);
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun 	if (is_mt7615(&phy->dev->mt76))
350*4882a593Smuzhiyun 		hw->max_tx_fragments = MT_TXP_MAX_BUF_NUM;
351*4882a593Smuzhiyun 	else
352*4882a593Smuzhiyun 		hw->max_tx_fragments = MT_HW_TXP_MAX_BUF_NUM;
353*4882a593Smuzhiyun }
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun static void
mt7615_cap_dbdc_enable(struct mt7615_dev * dev)356*4882a593Smuzhiyun mt7615_cap_dbdc_enable(struct mt7615_dev *dev)
357*4882a593Smuzhiyun {
358*4882a593Smuzhiyun 	dev->mphy.sband_5g.sband.vht_cap.cap &=
359*4882a593Smuzhiyun 			~(IEEE80211_VHT_CAP_SHORT_GI_160 |
360*4882a593Smuzhiyun 			  IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ);
361*4882a593Smuzhiyun 	if (dev->chainmask == 0xf)
362*4882a593Smuzhiyun 		dev->mphy.antenna_mask = dev->chainmask >> 2;
363*4882a593Smuzhiyun 	else
364*4882a593Smuzhiyun 		dev->mphy.antenna_mask = dev->chainmask >> 1;
365*4882a593Smuzhiyun 	dev->phy.chainmask = dev->mphy.antenna_mask;
366*4882a593Smuzhiyun 	dev->mphy.hw->wiphy->available_antennas_rx = dev->phy.chainmask;
367*4882a593Smuzhiyun 	dev->mphy.hw->wiphy->available_antennas_tx = dev->phy.chainmask;
368*4882a593Smuzhiyun 	mt76_set_stream_caps(&dev->mphy, true);
369*4882a593Smuzhiyun }
370*4882a593Smuzhiyun 
371*4882a593Smuzhiyun static void
mt7615_cap_dbdc_disable(struct mt7615_dev * dev)372*4882a593Smuzhiyun mt7615_cap_dbdc_disable(struct mt7615_dev *dev)
373*4882a593Smuzhiyun {
374*4882a593Smuzhiyun 	dev->mphy.sband_5g.sband.vht_cap.cap |=
375*4882a593Smuzhiyun 			IEEE80211_VHT_CAP_SHORT_GI_160 |
376*4882a593Smuzhiyun 			IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ;
377*4882a593Smuzhiyun 	dev->mphy.antenna_mask = dev->chainmask;
378*4882a593Smuzhiyun 	dev->phy.chainmask = dev->chainmask;
379*4882a593Smuzhiyun 	dev->mphy.hw->wiphy->available_antennas_rx = dev->chainmask;
380*4882a593Smuzhiyun 	dev->mphy.hw->wiphy->available_antennas_tx = dev->chainmask;
381*4882a593Smuzhiyun 	mt76_set_stream_caps(&dev->mphy, true);
382*4882a593Smuzhiyun }
383*4882a593Smuzhiyun 
mt7615_register_ext_phy(struct mt7615_dev * dev)384*4882a593Smuzhiyun int mt7615_register_ext_phy(struct mt7615_dev *dev)
385*4882a593Smuzhiyun {
386*4882a593Smuzhiyun 	struct mt7615_phy *phy = mt7615_ext_phy(dev);
387*4882a593Smuzhiyun 	struct mt76_phy *mphy;
388*4882a593Smuzhiyun 	int ret;
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun 	if (!is_mt7615(&dev->mt76))
391*4882a593Smuzhiyun 		return -EOPNOTSUPP;
392*4882a593Smuzhiyun 
393*4882a593Smuzhiyun 	if (test_bit(MT76_STATE_RUNNING, &dev->mphy.state))
394*4882a593Smuzhiyun 		return -EINVAL;
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun 	if (phy)
397*4882a593Smuzhiyun 		return 0;
398*4882a593Smuzhiyun 
399*4882a593Smuzhiyun 	mt7615_cap_dbdc_enable(dev);
400*4882a593Smuzhiyun 	mphy = mt76_alloc_phy(&dev->mt76, sizeof(*phy), &mt7615_ops);
401*4882a593Smuzhiyun 	if (!mphy)
402*4882a593Smuzhiyun 		return -ENOMEM;
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun 	phy = mphy->priv;
405*4882a593Smuzhiyun 	phy->dev = dev;
406*4882a593Smuzhiyun 	phy->mt76 = mphy;
407*4882a593Smuzhiyun 	phy->chainmask = dev->chainmask & ~dev->phy.chainmask;
408*4882a593Smuzhiyun 	mphy->antenna_mask = BIT(hweight8(phy->chainmask)) - 1;
409*4882a593Smuzhiyun 	mt7615_init_wiphy(mphy->hw);
410*4882a593Smuzhiyun 
411*4882a593Smuzhiyun 	INIT_DELAYED_WORK(&phy->mac_work, mt7615_mac_work);
412*4882a593Smuzhiyun 	INIT_DELAYED_WORK(&phy->scan_work, mt7615_scan_work);
413*4882a593Smuzhiyun 	skb_queue_head_init(&phy->scan_event_list);
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun 	INIT_WORK(&phy->roc_work, mt7615_roc_work);
416*4882a593Smuzhiyun 	timer_setup(&phy->roc_timer, mt7615_roc_timer, 0);
417*4882a593Smuzhiyun 	init_waitqueue_head(&phy->roc_wait);
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun 	mt7615_mac_set_scs(phy, true);
420*4882a593Smuzhiyun 
421*4882a593Smuzhiyun 	/*
422*4882a593Smuzhiyun 	 * Make the secondary PHY MAC address local without overlapping with
423*4882a593Smuzhiyun 	 * the usual MAC address allocation scheme on multiple virtual interfaces
424*4882a593Smuzhiyun 	 */
425*4882a593Smuzhiyun 	mphy->hw->wiphy->perm_addr[0] |= 2;
426*4882a593Smuzhiyun 	mphy->hw->wiphy->perm_addr[0] ^= BIT(7);
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun 	/* second phy can only handle 5 GHz */
429*4882a593Smuzhiyun 	mphy->sband_2g.sband.n_channels = 0;
430*4882a593Smuzhiyun 	mphy->hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL;
431*4882a593Smuzhiyun 
432*4882a593Smuzhiyun 	ret = mt76_register_phy(mphy);
433*4882a593Smuzhiyun 	if (ret)
434*4882a593Smuzhiyun 		ieee80211_free_hw(mphy->hw);
435*4882a593Smuzhiyun 
436*4882a593Smuzhiyun 	return ret;
437*4882a593Smuzhiyun }
438*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt7615_register_ext_phy);
439*4882a593Smuzhiyun 
mt7615_unregister_ext_phy(struct mt7615_dev * dev)440*4882a593Smuzhiyun void mt7615_unregister_ext_phy(struct mt7615_dev *dev)
441*4882a593Smuzhiyun {
442*4882a593Smuzhiyun 	struct mt7615_phy *phy = mt7615_ext_phy(dev);
443*4882a593Smuzhiyun 	struct mt76_phy *mphy = dev->mt76.phy2;
444*4882a593Smuzhiyun 
445*4882a593Smuzhiyun 	if (!phy)
446*4882a593Smuzhiyun 		return;
447*4882a593Smuzhiyun 
448*4882a593Smuzhiyun 	mt7615_cap_dbdc_disable(dev);
449*4882a593Smuzhiyun 	mt76_unregister_phy(mphy);
450*4882a593Smuzhiyun 	ieee80211_free_hw(mphy->hw);
451*4882a593Smuzhiyun }
452*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt7615_unregister_ext_phy);
453*4882a593Smuzhiyun 
mt7615_init_device(struct mt7615_dev * dev)454*4882a593Smuzhiyun void mt7615_init_device(struct mt7615_dev *dev)
455*4882a593Smuzhiyun {
456*4882a593Smuzhiyun 	struct ieee80211_hw *hw = mt76_hw(dev);
457*4882a593Smuzhiyun 
458*4882a593Smuzhiyun 	dev->phy.dev = dev;
459*4882a593Smuzhiyun 	dev->phy.mt76 = &dev->mt76.phy;
460*4882a593Smuzhiyun 	dev->mt76.phy.priv = &dev->phy;
461*4882a593Smuzhiyun 
462*4882a593Smuzhiyun 	INIT_DELAYED_WORK(&dev->pm.ps_work, mt7615_pm_power_save_work);
463*4882a593Smuzhiyun 	INIT_WORK(&dev->pm.wake_work, mt7615_pm_wake_work);
464*4882a593Smuzhiyun 	init_completion(&dev->pm.wake_cmpl);
465*4882a593Smuzhiyun 	spin_lock_init(&dev->pm.txq_lock);
466*4882a593Smuzhiyun 	set_bit(MT76_STATE_PM, &dev->mphy.state);
467*4882a593Smuzhiyun 	INIT_DELAYED_WORK(&dev->phy.mac_work, mt7615_mac_work);
468*4882a593Smuzhiyun 	INIT_DELAYED_WORK(&dev->phy.scan_work, mt7615_scan_work);
469*4882a593Smuzhiyun 	skb_queue_head_init(&dev->phy.scan_event_list);
470*4882a593Smuzhiyun 	INIT_LIST_HEAD(&dev->sta_poll_list);
471*4882a593Smuzhiyun 	spin_lock_init(&dev->sta_poll_lock);
472*4882a593Smuzhiyun 	init_waitqueue_head(&dev->reset_wait);
473*4882a593Smuzhiyun 	init_waitqueue_head(&dev->phy.roc_wait);
474*4882a593Smuzhiyun 
475*4882a593Smuzhiyun 	INIT_WORK(&dev->reset_work, mt7615_mac_reset_work);
476*4882a593Smuzhiyun 	INIT_WORK(&dev->phy.roc_work, mt7615_roc_work);
477*4882a593Smuzhiyun 	timer_setup(&dev->phy.roc_timer, mt7615_roc_timer, 0);
478*4882a593Smuzhiyun 
479*4882a593Smuzhiyun 	mt7615_init_wiphy(hw);
480*4882a593Smuzhiyun 	dev->pm.idle_timeout = MT7615_PM_TIMEOUT;
481*4882a593Smuzhiyun 	dev->mphy.sband_2g.sband.ht_cap.cap |= IEEE80211_HT_CAP_LDPC_CODING;
482*4882a593Smuzhiyun 	dev->mphy.sband_5g.sband.ht_cap.cap |= IEEE80211_HT_CAP_LDPC_CODING;
483*4882a593Smuzhiyun 	dev->mphy.sband_5g.sband.vht_cap.cap |=
484*4882a593Smuzhiyun 			IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991 |
485*4882a593Smuzhiyun 			IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK;
486*4882a593Smuzhiyun 	mt7615_cap_dbdc_disable(dev);
487*4882a593Smuzhiyun 	dev->phy.dfs_state = -1;
488*4882a593Smuzhiyun 
489*4882a593Smuzhiyun #ifdef CONFIG_NL80211_TESTMODE
490*4882a593Smuzhiyun 	dev->mt76.test_ops = &mt7615_testmode_ops;
491*4882a593Smuzhiyun #endif
492*4882a593Smuzhiyun }
493*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt7615_init_device);
494