xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/mediatek/mt76/mt7603/mcu.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: ISC
2*4882a593Smuzhiyun 
3*4882a593Smuzhiyun #include <linux/firmware.h>
4*4882a593Smuzhiyun #include "mt7603.h"
5*4882a593Smuzhiyun #include "mcu.h"
6*4882a593Smuzhiyun #include "eeprom.h"
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #define MCU_SKB_RESERVE	8
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun struct mt7603_fw_trailer {
11*4882a593Smuzhiyun 	char fw_ver[10];
12*4882a593Smuzhiyun 	char build_date[15];
13*4882a593Smuzhiyun 	__le32 dl_len;
14*4882a593Smuzhiyun } __packed;
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun static int
__mt7603_mcu_msg_send(struct mt7603_dev * dev,struct sk_buff * skb,int cmd,int * wait_seq)17*4882a593Smuzhiyun __mt7603_mcu_msg_send(struct mt7603_dev *dev, struct sk_buff *skb,
18*4882a593Smuzhiyun 		      int cmd, int *wait_seq)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun 	int hdrlen = dev->mcu_running ? sizeof(struct mt7603_mcu_txd) : 12;
21*4882a593Smuzhiyun 	struct mt76_dev *mdev = &dev->mt76;
22*4882a593Smuzhiyun 	struct mt7603_mcu_txd *txd;
23*4882a593Smuzhiyun 	u8 seq;
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun 	seq = ++mdev->mcu.msg_seq & 0xf;
26*4882a593Smuzhiyun 	if (!seq)
27*4882a593Smuzhiyun 		seq = ++mdev->mcu.msg_seq & 0xf;
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun 	txd = (struct mt7603_mcu_txd *)skb_push(skb, hdrlen);
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun 	txd->len = cpu_to_le16(skb->len);
32*4882a593Smuzhiyun 	if (cmd == -MCU_CMD_FW_SCATTER)
33*4882a593Smuzhiyun 		txd->pq_id = cpu_to_le16(MCU_PORT_QUEUE_FW);
34*4882a593Smuzhiyun 	else
35*4882a593Smuzhiyun 		txd->pq_id = cpu_to_le16(MCU_PORT_QUEUE);
36*4882a593Smuzhiyun 	txd->pkt_type = MCU_PKT_ID;
37*4882a593Smuzhiyun 	txd->seq = seq;
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun 	if (cmd < 0) {
40*4882a593Smuzhiyun 		txd->cid = -cmd;
41*4882a593Smuzhiyun 		txd->set_query = MCU_Q_NA;
42*4882a593Smuzhiyun 	} else {
43*4882a593Smuzhiyun 		txd->cid = MCU_CMD_EXT_CID;
44*4882a593Smuzhiyun 		txd->ext_cid = cmd;
45*4882a593Smuzhiyun 		txd->set_query = MCU_Q_SET;
46*4882a593Smuzhiyun 		txd->ext_cid_ack = 1;
47*4882a593Smuzhiyun 	}
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun 	if (wait_seq)
50*4882a593Smuzhiyun 		*wait_seq = seq;
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun 	return mt76_tx_queue_skb_raw(dev, MT_TXQ_MCU, skb, 0);
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun static int
mt7603_mcu_msg_send(struct mt76_dev * mdev,int cmd,const void * data,int len,bool wait_resp)56*4882a593Smuzhiyun mt7603_mcu_msg_send(struct mt76_dev *mdev, int cmd, const void *data,
57*4882a593Smuzhiyun 		    int len, bool wait_resp)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun 	struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
60*4882a593Smuzhiyun 	unsigned long expires = jiffies + 3 * HZ;
61*4882a593Smuzhiyun 	struct mt7603_mcu_rxd *rxd;
62*4882a593Smuzhiyun 	struct sk_buff *skb;
63*4882a593Smuzhiyun 	int ret, seq;
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun 	skb = mt76_mcu_msg_alloc(mdev, data, len);
66*4882a593Smuzhiyun 	if (!skb)
67*4882a593Smuzhiyun 		return -ENOMEM;
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	mutex_lock(&mdev->mcu.mutex);
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun 	ret = __mt7603_mcu_msg_send(dev, skb, cmd, &seq);
72*4882a593Smuzhiyun 	if (ret)
73*4882a593Smuzhiyun 		goto out;
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun 	while (wait_resp) {
76*4882a593Smuzhiyun 		bool check_seq = false;
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 		skb = mt76_mcu_get_response(&dev->mt76, expires);
79*4882a593Smuzhiyun 		if (!skb) {
80*4882a593Smuzhiyun 			dev_err(mdev->dev,
81*4882a593Smuzhiyun 				"MCU message %d (seq %d) timed out\n",
82*4882a593Smuzhiyun 				cmd, seq);
83*4882a593Smuzhiyun 			dev->mcu_hang = MT7603_WATCHDOG_TIMEOUT;
84*4882a593Smuzhiyun 			ret = -ETIMEDOUT;
85*4882a593Smuzhiyun 			break;
86*4882a593Smuzhiyun 		}
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 		rxd = (struct mt7603_mcu_rxd *)skb->data;
89*4882a593Smuzhiyun 		if (seq == rxd->seq)
90*4882a593Smuzhiyun 			check_seq = true;
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 		dev_kfree_skb(skb);
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 		if (check_seq)
95*4882a593Smuzhiyun 			break;
96*4882a593Smuzhiyun 	}
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun out:
99*4882a593Smuzhiyun 	mutex_unlock(&mdev->mcu.mutex);
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	return ret;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun static int
mt7603_mcu_init_download(struct mt7603_dev * dev,u32 addr,u32 len)105*4882a593Smuzhiyun mt7603_mcu_init_download(struct mt7603_dev *dev, u32 addr, u32 len)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun 	struct {
108*4882a593Smuzhiyun 		__le32 addr;
109*4882a593Smuzhiyun 		__le32 len;
110*4882a593Smuzhiyun 		__le32 mode;
111*4882a593Smuzhiyun 	} req = {
112*4882a593Smuzhiyun 		.addr = cpu_to_le32(addr),
113*4882a593Smuzhiyun 		.len = cpu_to_le32(len),
114*4882a593Smuzhiyun 		.mode = cpu_to_le32(BIT(31)),
115*4882a593Smuzhiyun 	};
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	return __mt76_mcu_send_msg(&dev->mt76, -MCU_CMD_TARGET_ADDRESS_LEN_REQ,
118*4882a593Smuzhiyun 				   &req, sizeof(req), true);
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun static int
mt7603_mcu_send_firmware(struct mt7603_dev * dev,const void * data,int len)122*4882a593Smuzhiyun mt7603_mcu_send_firmware(struct mt7603_dev *dev, const void *data, int len)
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun 	int cur_len, ret = 0;
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	while (len > 0) {
127*4882a593Smuzhiyun 		cur_len = min_t(int, 4096 - sizeof(struct mt7603_mcu_txd),
128*4882a593Smuzhiyun 				len);
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 		ret = __mt76_mcu_send_msg(&dev->mt76, -MCU_CMD_FW_SCATTER,
131*4882a593Smuzhiyun 					  data, cur_len, false);
132*4882a593Smuzhiyun 		if (ret)
133*4882a593Smuzhiyun 			break;
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 		data += cur_len;
136*4882a593Smuzhiyun 		len -= cur_len;
137*4882a593Smuzhiyun 	}
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	return ret;
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun static int
mt7603_mcu_start_firmware(struct mt7603_dev * dev,u32 addr)143*4882a593Smuzhiyun mt7603_mcu_start_firmware(struct mt7603_dev *dev, u32 addr)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun 	struct {
146*4882a593Smuzhiyun 		__le32 override;
147*4882a593Smuzhiyun 		__le32 addr;
148*4882a593Smuzhiyun 	} req = {
149*4882a593Smuzhiyun 		.override = cpu_to_le32(addr ? 1 : 0),
150*4882a593Smuzhiyun 		.addr = cpu_to_le32(addr),
151*4882a593Smuzhiyun 	};
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun 	return __mt76_mcu_send_msg(&dev->mt76, -MCU_CMD_FW_START_REQ,
154*4882a593Smuzhiyun 				   &req, sizeof(req), true);
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun static int
mt7603_mcu_restart(struct mt76_dev * dev)158*4882a593Smuzhiyun mt7603_mcu_restart(struct mt76_dev *dev)
159*4882a593Smuzhiyun {
160*4882a593Smuzhiyun 	return __mt76_mcu_send_msg(dev, -MCU_CMD_RESTART_DL_REQ,
161*4882a593Smuzhiyun 				   NULL, 0, true);
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun 
mt7603_load_firmware(struct mt7603_dev * dev)164*4882a593Smuzhiyun static int mt7603_load_firmware(struct mt7603_dev *dev)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun 	const struct firmware *fw;
167*4882a593Smuzhiyun 	const struct mt7603_fw_trailer *hdr;
168*4882a593Smuzhiyun 	const char *firmware;
169*4882a593Smuzhiyun 	int dl_len;
170*4882a593Smuzhiyun 	u32 addr, val;
171*4882a593Smuzhiyun 	int ret;
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	if (is_mt7628(dev)) {
174*4882a593Smuzhiyun 		if (mt76xx_rev(dev) == MT7628_REV_E1)
175*4882a593Smuzhiyun 			firmware = MT7628_FIRMWARE_E1;
176*4882a593Smuzhiyun 		else
177*4882a593Smuzhiyun 			firmware = MT7628_FIRMWARE_E2;
178*4882a593Smuzhiyun 	} else {
179*4882a593Smuzhiyun 		if (mt76xx_rev(dev) < MT7603_REV_E2)
180*4882a593Smuzhiyun 			firmware = MT7603_FIRMWARE_E1;
181*4882a593Smuzhiyun 		else
182*4882a593Smuzhiyun 			firmware = MT7603_FIRMWARE_E2;
183*4882a593Smuzhiyun 	}
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	ret = request_firmware(&fw, firmware, dev->mt76.dev);
186*4882a593Smuzhiyun 	if (ret)
187*4882a593Smuzhiyun 		return ret;
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 	if (!fw || !fw->data || fw->size < sizeof(*hdr)) {
190*4882a593Smuzhiyun 		dev_err(dev->mt76.dev, "Invalid firmware\n");
191*4882a593Smuzhiyun 		ret = -EINVAL;
192*4882a593Smuzhiyun 		goto out;
193*4882a593Smuzhiyun 	}
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	hdr = (const struct mt7603_fw_trailer *)(fw->data + fw->size -
196*4882a593Smuzhiyun 						 sizeof(*hdr));
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	dev_info(dev->mt76.dev, "Firmware Version: %.10s\n", hdr->fw_ver);
199*4882a593Smuzhiyun 	dev_info(dev->mt76.dev, "Build Time: %.15s\n", hdr->build_date);
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun 	addr = mt7603_reg_map(dev, 0x50012498);
202*4882a593Smuzhiyun 	mt76_wr(dev, addr, 0x5);
203*4882a593Smuzhiyun 	mt76_wr(dev, addr, 0x5);
204*4882a593Smuzhiyun 	udelay(1);
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun 	/* switch to bypass mode */
207*4882a593Smuzhiyun 	mt76_rmw(dev, MT_SCH_4, MT_SCH_4_FORCE_QID,
208*4882a593Smuzhiyun 		 MT_SCH_4_BYPASS | FIELD_PREP(MT_SCH_4_FORCE_QID, 5));
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 	val = mt76_rr(dev, MT_TOP_MISC2);
211*4882a593Smuzhiyun 	if (val & BIT(1)) {
212*4882a593Smuzhiyun 		dev_info(dev->mt76.dev, "Firmware already running...\n");
213*4882a593Smuzhiyun 		goto running;
214*4882a593Smuzhiyun 	}
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	if (!mt76_poll_msec(dev, MT_TOP_MISC2, BIT(0) | BIT(1), BIT(0), 500)) {
217*4882a593Smuzhiyun 		dev_err(dev->mt76.dev, "Timeout waiting for ROM code to become ready\n");
218*4882a593Smuzhiyun 		ret = -EIO;
219*4882a593Smuzhiyun 		goto out;
220*4882a593Smuzhiyun 	}
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	dl_len = le32_to_cpu(hdr->dl_len) + 4;
223*4882a593Smuzhiyun 	ret = mt7603_mcu_init_download(dev, MCU_FIRMWARE_ADDRESS, dl_len);
224*4882a593Smuzhiyun 	if (ret) {
225*4882a593Smuzhiyun 		dev_err(dev->mt76.dev, "Download request failed\n");
226*4882a593Smuzhiyun 		goto out;
227*4882a593Smuzhiyun 	}
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 	ret = mt7603_mcu_send_firmware(dev, fw->data, dl_len);
230*4882a593Smuzhiyun 	if (ret) {
231*4882a593Smuzhiyun 		dev_err(dev->mt76.dev, "Failed to send firmware to device\n");
232*4882a593Smuzhiyun 		goto out;
233*4882a593Smuzhiyun 	}
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun 	ret = mt7603_mcu_start_firmware(dev, MCU_FIRMWARE_ADDRESS);
236*4882a593Smuzhiyun 	if (ret) {
237*4882a593Smuzhiyun 		dev_err(dev->mt76.dev, "Failed to start firmware\n");
238*4882a593Smuzhiyun 		goto out;
239*4882a593Smuzhiyun 	}
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun 	if (!mt76_poll_msec(dev, MT_TOP_MISC2, BIT(1), BIT(1), 500)) {
242*4882a593Smuzhiyun 		dev_err(dev->mt76.dev, "Timeout waiting for firmware to initialize\n");
243*4882a593Smuzhiyun 		ret = -EIO;
244*4882a593Smuzhiyun 		goto out;
245*4882a593Smuzhiyun 	}
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun running:
248*4882a593Smuzhiyun 	mt76_clear(dev, MT_SCH_4, MT_SCH_4_FORCE_QID | MT_SCH_4_BYPASS);
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun 	mt76_set(dev, MT_SCH_4, BIT(8));
251*4882a593Smuzhiyun 	mt76_clear(dev, MT_SCH_4, BIT(8));
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun 	dev->mcu_running = true;
254*4882a593Smuzhiyun 	snprintf(dev->mt76.hw->wiphy->fw_version,
255*4882a593Smuzhiyun 		 sizeof(dev->mt76.hw->wiphy->fw_version),
256*4882a593Smuzhiyun 		 "%.10s-%.15s", hdr->fw_ver, hdr->build_date);
257*4882a593Smuzhiyun 	dev_info(dev->mt76.dev, "firmware init done\n");
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun out:
260*4882a593Smuzhiyun 	release_firmware(fw);
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 	return ret;
263*4882a593Smuzhiyun }
264*4882a593Smuzhiyun 
mt7603_mcu_init(struct mt7603_dev * dev)265*4882a593Smuzhiyun int mt7603_mcu_init(struct mt7603_dev *dev)
266*4882a593Smuzhiyun {
267*4882a593Smuzhiyun 	static const struct mt76_mcu_ops mt7603_mcu_ops = {
268*4882a593Smuzhiyun 		.headroom = sizeof(struct mt7603_mcu_txd),
269*4882a593Smuzhiyun 		.mcu_send_msg = mt7603_mcu_msg_send,
270*4882a593Smuzhiyun 		.mcu_restart = mt7603_mcu_restart,
271*4882a593Smuzhiyun 	};
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	dev->mt76.mcu_ops = &mt7603_mcu_ops;
274*4882a593Smuzhiyun 	return mt7603_load_firmware(dev);
275*4882a593Smuzhiyun }
276*4882a593Smuzhiyun 
mt7603_mcu_exit(struct mt7603_dev * dev)277*4882a593Smuzhiyun void mt7603_mcu_exit(struct mt7603_dev *dev)
278*4882a593Smuzhiyun {
279*4882a593Smuzhiyun 	__mt76_mcu_restart(&dev->mt76);
280*4882a593Smuzhiyun 	skb_queue_purge(&dev->mt76.mcu.res_q);
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun 
mt7603_mcu_set_eeprom(struct mt7603_dev * dev)283*4882a593Smuzhiyun int mt7603_mcu_set_eeprom(struct mt7603_dev *dev)
284*4882a593Smuzhiyun {
285*4882a593Smuzhiyun 	static const u16 req_fields[] = {
286*4882a593Smuzhiyun #define WORD(_start)			\
287*4882a593Smuzhiyun 		_start,			\
288*4882a593Smuzhiyun 		_start + 1
289*4882a593Smuzhiyun #define GROUP_2G(_start)		\
290*4882a593Smuzhiyun 		WORD(_start),		\
291*4882a593Smuzhiyun 		WORD(_start + 2),	\
292*4882a593Smuzhiyun 		WORD(_start + 4)
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun 		MT_EE_NIC_CONF_0 + 1,
295*4882a593Smuzhiyun 		WORD(MT_EE_NIC_CONF_1),
296*4882a593Smuzhiyun 		MT_EE_WIFI_RF_SETTING,
297*4882a593Smuzhiyun 		MT_EE_TX_POWER_DELTA_BW40,
298*4882a593Smuzhiyun 		MT_EE_TX_POWER_DELTA_BW80 + 1,
299*4882a593Smuzhiyun 		MT_EE_TX_POWER_EXT_PA_5G,
300*4882a593Smuzhiyun 		MT_EE_TEMP_SENSOR_CAL,
301*4882a593Smuzhiyun 		GROUP_2G(MT_EE_TX_POWER_0_START_2G),
302*4882a593Smuzhiyun 		GROUP_2G(MT_EE_TX_POWER_1_START_2G),
303*4882a593Smuzhiyun 		WORD(MT_EE_TX_POWER_CCK),
304*4882a593Smuzhiyun 		WORD(MT_EE_TX_POWER_OFDM_2G_6M),
305*4882a593Smuzhiyun 		WORD(MT_EE_TX_POWER_OFDM_2G_24M),
306*4882a593Smuzhiyun 		WORD(MT_EE_TX_POWER_OFDM_2G_54M),
307*4882a593Smuzhiyun 		WORD(MT_EE_TX_POWER_HT_BPSK_QPSK),
308*4882a593Smuzhiyun 		WORD(MT_EE_TX_POWER_HT_16_64_QAM),
309*4882a593Smuzhiyun 		WORD(MT_EE_TX_POWER_HT_64_QAM),
310*4882a593Smuzhiyun 		MT_EE_ELAN_RX_MODE_GAIN,
311*4882a593Smuzhiyun 		MT_EE_ELAN_RX_MODE_NF,
312*4882a593Smuzhiyun 		MT_EE_ELAN_RX_MODE_P1DB,
313*4882a593Smuzhiyun 		MT_EE_ELAN_BYPASS_MODE_GAIN,
314*4882a593Smuzhiyun 		MT_EE_ELAN_BYPASS_MODE_NF,
315*4882a593Smuzhiyun 		MT_EE_ELAN_BYPASS_MODE_P1DB,
316*4882a593Smuzhiyun 		WORD(MT_EE_STEP_NUM_NEG_6_7),
317*4882a593Smuzhiyun 		WORD(MT_EE_STEP_NUM_NEG_4_5),
318*4882a593Smuzhiyun 		WORD(MT_EE_STEP_NUM_NEG_2_3),
319*4882a593Smuzhiyun 		WORD(MT_EE_STEP_NUM_NEG_0_1),
320*4882a593Smuzhiyun 		WORD(MT_EE_REF_STEP_24G),
321*4882a593Smuzhiyun 		WORD(MT_EE_STEP_NUM_PLUS_1_2),
322*4882a593Smuzhiyun 		WORD(MT_EE_STEP_NUM_PLUS_3_4),
323*4882a593Smuzhiyun 		WORD(MT_EE_STEP_NUM_PLUS_5_6),
324*4882a593Smuzhiyun 		MT_EE_STEP_NUM_PLUS_7,
325*4882a593Smuzhiyun 		MT_EE_XTAL_FREQ_OFFSET,
326*4882a593Smuzhiyun 		MT_EE_XTAL_TRIM_2_COMP,
327*4882a593Smuzhiyun 		MT_EE_XTAL_TRIM_3_COMP,
328*4882a593Smuzhiyun 		MT_EE_XTAL_WF_RFCAL,
329*4882a593Smuzhiyun 
330*4882a593Smuzhiyun 		/* unknown fields below */
331*4882a593Smuzhiyun 		WORD(0x24),
332*4882a593Smuzhiyun 		0x34,
333*4882a593Smuzhiyun 		0x39,
334*4882a593Smuzhiyun 		0x3b,
335*4882a593Smuzhiyun 		WORD(0x42),
336*4882a593Smuzhiyun 		WORD(0x9e),
337*4882a593Smuzhiyun 		0xf2,
338*4882a593Smuzhiyun 		WORD(0xf8),
339*4882a593Smuzhiyun 		0xfa,
340*4882a593Smuzhiyun 		0x12e,
341*4882a593Smuzhiyun 		WORD(0x130), WORD(0x132), WORD(0x134), WORD(0x136),
342*4882a593Smuzhiyun 		WORD(0x138), WORD(0x13a), WORD(0x13c), WORD(0x13e),
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun #undef GROUP_2G
345*4882a593Smuzhiyun #undef WORD
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun 	};
348*4882a593Smuzhiyun 	struct req_data {
349*4882a593Smuzhiyun 		__le16 addr;
350*4882a593Smuzhiyun 		u8 val;
351*4882a593Smuzhiyun 		u8 pad;
352*4882a593Smuzhiyun 	} __packed;
353*4882a593Smuzhiyun 	struct {
354*4882a593Smuzhiyun 		u8 buffer_mode;
355*4882a593Smuzhiyun 		u8 len;
356*4882a593Smuzhiyun 		u8 pad[2];
357*4882a593Smuzhiyun 	} req_hdr = {
358*4882a593Smuzhiyun 		.buffer_mode = 1,
359*4882a593Smuzhiyun 		.len = ARRAY_SIZE(req_fields) - 1,
360*4882a593Smuzhiyun 	};
361*4882a593Smuzhiyun 	const int size = 0xff * sizeof(struct req_data);
362*4882a593Smuzhiyun 	u8 *req, *eep = (u8 *)dev->mt76.eeprom.data;
363*4882a593Smuzhiyun 	int i, ret, len = sizeof(req_hdr) + size;
364*4882a593Smuzhiyun 	struct req_data *data;
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun 	BUILD_BUG_ON(ARRAY_SIZE(req_fields) * sizeof(*data) > size);
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun 	req = kmalloc(len, GFP_KERNEL);
369*4882a593Smuzhiyun 	if (!req)
370*4882a593Smuzhiyun 		return -ENOMEM;
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun 	memcpy(req, &req_hdr, sizeof(req_hdr));
373*4882a593Smuzhiyun 	data = (struct req_data *)(req + sizeof(req_hdr));
374*4882a593Smuzhiyun 	memset(data, 0, size);
375*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(req_fields); i++) {
376*4882a593Smuzhiyun 		data[i].addr = cpu_to_le16(req_fields[i]);
377*4882a593Smuzhiyun 		data[i].val = eep[req_fields[i]];
378*4882a593Smuzhiyun 	}
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun 	ret = __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_EFUSE_BUFFER_MODE,
381*4882a593Smuzhiyun 				  req, len, true);
382*4882a593Smuzhiyun 	kfree(req);
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun 	return ret;
385*4882a593Smuzhiyun }
386*4882a593Smuzhiyun 
mt7603_mcu_set_tx_power(struct mt7603_dev * dev)387*4882a593Smuzhiyun static int mt7603_mcu_set_tx_power(struct mt7603_dev *dev)
388*4882a593Smuzhiyun {
389*4882a593Smuzhiyun 	struct {
390*4882a593Smuzhiyun 		u8 center_channel;
391*4882a593Smuzhiyun 		u8 tssi;
392*4882a593Smuzhiyun 		u8 temp_comp;
393*4882a593Smuzhiyun 		u8 target_power[2];
394*4882a593Smuzhiyun 		u8 rate_power_delta[14];
395*4882a593Smuzhiyun 		u8 bw_power_delta;
396*4882a593Smuzhiyun 		u8 ch_power_delta[6];
397*4882a593Smuzhiyun 		u8 temp_comp_power[17];
398*4882a593Smuzhiyun 		u8 reserved;
399*4882a593Smuzhiyun 	} req = {
400*4882a593Smuzhiyun 		.center_channel = dev->mphy.chandef.chan->hw_value,
401*4882a593Smuzhiyun #define EEP_VAL(n) ((u8 *)dev->mt76.eeprom.data)[n]
402*4882a593Smuzhiyun 		.tssi = EEP_VAL(MT_EE_NIC_CONF_1 + 1),
403*4882a593Smuzhiyun 		.temp_comp = EEP_VAL(MT_EE_NIC_CONF_1),
404*4882a593Smuzhiyun 		.target_power = {
405*4882a593Smuzhiyun 			EEP_VAL(MT_EE_TX_POWER_0_START_2G + 2),
406*4882a593Smuzhiyun 			EEP_VAL(MT_EE_TX_POWER_1_START_2G + 2)
407*4882a593Smuzhiyun 		},
408*4882a593Smuzhiyun 		.bw_power_delta = EEP_VAL(MT_EE_TX_POWER_DELTA_BW40),
409*4882a593Smuzhiyun 		.ch_power_delta = {
410*4882a593Smuzhiyun 			EEP_VAL(MT_EE_TX_POWER_0_START_2G + 3),
411*4882a593Smuzhiyun 			EEP_VAL(MT_EE_TX_POWER_0_START_2G + 4),
412*4882a593Smuzhiyun 			EEP_VAL(MT_EE_TX_POWER_0_START_2G + 5),
413*4882a593Smuzhiyun 			EEP_VAL(MT_EE_TX_POWER_1_START_2G + 3),
414*4882a593Smuzhiyun 			EEP_VAL(MT_EE_TX_POWER_1_START_2G + 4),
415*4882a593Smuzhiyun 			EEP_VAL(MT_EE_TX_POWER_1_START_2G + 5)
416*4882a593Smuzhiyun 		},
417*4882a593Smuzhiyun #undef EEP_VAL
418*4882a593Smuzhiyun 	};
419*4882a593Smuzhiyun 	u8 *eep = (u8 *)dev->mt76.eeprom.data;
420*4882a593Smuzhiyun 
421*4882a593Smuzhiyun 	memcpy(req.rate_power_delta, eep + MT_EE_TX_POWER_CCK,
422*4882a593Smuzhiyun 	       sizeof(req.rate_power_delta));
423*4882a593Smuzhiyun 
424*4882a593Smuzhiyun 	memcpy(req.temp_comp_power, eep + MT_EE_STEP_NUM_NEG_6_7,
425*4882a593Smuzhiyun 	       sizeof(req.temp_comp_power));
426*4882a593Smuzhiyun 
427*4882a593Smuzhiyun 	return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_SET_TX_POWER_CTRL,
428*4882a593Smuzhiyun 				   &req, sizeof(req), true);
429*4882a593Smuzhiyun }
430*4882a593Smuzhiyun 
mt7603_mcu_set_channel(struct mt7603_dev * dev)431*4882a593Smuzhiyun int mt7603_mcu_set_channel(struct mt7603_dev *dev)
432*4882a593Smuzhiyun {
433*4882a593Smuzhiyun 	struct cfg80211_chan_def *chandef = &dev->mphy.chandef;
434*4882a593Smuzhiyun 	struct ieee80211_hw *hw = mt76_hw(dev);
435*4882a593Smuzhiyun 	int n_chains = hweight8(dev->mphy.antenna_mask);
436*4882a593Smuzhiyun 	struct {
437*4882a593Smuzhiyun 		u8 control_chan;
438*4882a593Smuzhiyun 		u8 center_chan;
439*4882a593Smuzhiyun 		u8 bw;
440*4882a593Smuzhiyun 		u8 tx_streams;
441*4882a593Smuzhiyun 		u8 rx_streams;
442*4882a593Smuzhiyun 		u8 _res0[7];
443*4882a593Smuzhiyun 		u8 txpower[21];
444*4882a593Smuzhiyun 		u8 _res1[3];
445*4882a593Smuzhiyun 	} req = {
446*4882a593Smuzhiyun 		.control_chan = chandef->chan->hw_value,
447*4882a593Smuzhiyun 		.center_chan = chandef->chan->hw_value,
448*4882a593Smuzhiyun 		.bw = MT_BW_20,
449*4882a593Smuzhiyun 		.tx_streams = n_chains,
450*4882a593Smuzhiyun 		.rx_streams = n_chains,
451*4882a593Smuzhiyun 	};
452*4882a593Smuzhiyun 	s8 tx_power;
453*4882a593Smuzhiyun 	int i, ret;
454*4882a593Smuzhiyun 
455*4882a593Smuzhiyun 	if (dev->mphy.chandef.width == NL80211_CHAN_WIDTH_40) {
456*4882a593Smuzhiyun 		req.bw = MT_BW_40;
457*4882a593Smuzhiyun 		if (chandef->center_freq1 > chandef->chan->center_freq)
458*4882a593Smuzhiyun 			req.center_chan += 2;
459*4882a593Smuzhiyun 		else
460*4882a593Smuzhiyun 			req.center_chan -= 2;
461*4882a593Smuzhiyun 	}
462*4882a593Smuzhiyun 
463*4882a593Smuzhiyun 	tx_power = hw->conf.power_level * 2;
464*4882a593Smuzhiyun 	if (dev->mphy.antenna_mask == 3)
465*4882a593Smuzhiyun 		tx_power -= 6;
466*4882a593Smuzhiyun 	tx_power = min(tx_power, dev->tx_power_limit);
467*4882a593Smuzhiyun 
468*4882a593Smuzhiyun 	dev->mphy.txpower_cur = tx_power;
469*4882a593Smuzhiyun 
470*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(req.txpower); i++)
471*4882a593Smuzhiyun 		req.txpower[i] = tx_power;
472*4882a593Smuzhiyun 
473*4882a593Smuzhiyun 	ret = __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_CHANNEL_SWITCH,
474*4882a593Smuzhiyun 				  &req, sizeof(req), true);
475*4882a593Smuzhiyun 	if (ret)
476*4882a593Smuzhiyun 		return ret;
477*4882a593Smuzhiyun 
478*4882a593Smuzhiyun 	return mt7603_mcu_set_tx_power(dev);
479*4882a593Smuzhiyun }
480