xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/mediatek/mt76/mt7603/main.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: ISC
2*4882a593Smuzhiyun 
3*4882a593Smuzhiyun #include <linux/etherdevice.h>
4*4882a593Smuzhiyun #include <linux/platform_device.h>
5*4882a593Smuzhiyun #include <linux/pci.h>
6*4882a593Smuzhiyun #include <linux/module.h>
7*4882a593Smuzhiyun #include "mt7603.h"
8*4882a593Smuzhiyun #include "mac.h"
9*4882a593Smuzhiyun #include "eeprom.h"
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun static int
mt7603_start(struct ieee80211_hw * hw)12*4882a593Smuzhiyun mt7603_start(struct ieee80211_hw *hw)
13*4882a593Smuzhiyun {
14*4882a593Smuzhiyun 	struct mt7603_dev *dev = hw->priv;
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun 	mt7603_mac_reset_counters(dev);
17*4882a593Smuzhiyun 	mt7603_mac_start(dev);
18*4882a593Smuzhiyun 	dev->mphy.survey_time = ktime_get_boottime();
19*4882a593Smuzhiyun 	set_bit(MT76_STATE_RUNNING, &dev->mphy.state);
20*4882a593Smuzhiyun 	mt7603_mac_work(&dev->mt76.mac_work.work);
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun 	return 0;
23*4882a593Smuzhiyun }
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun static void
mt7603_stop(struct ieee80211_hw * hw)26*4882a593Smuzhiyun mt7603_stop(struct ieee80211_hw *hw)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun 	struct mt7603_dev *dev = hw->priv;
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun 	clear_bit(MT76_STATE_RUNNING, &dev->mphy.state);
31*4882a593Smuzhiyun 	cancel_delayed_work_sync(&dev->mt76.mac_work);
32*4882a593Smuzhiyun 	mt7603_mac_stop(dev);
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun static int
mt7603_add_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif)36*4882a593Smuzhiyun mt7603_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun 	struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv;
39*4882a593Smuzhiyun 	struct mt7603_dev *dev = hw->priv;
40*4882a593Smuzhiyun 	struct mt76_txq *mtxq;
41*4882a593Smuzhiyun 	u8 bc_addr[ETH_ALEN];
42*4882a593Smuzhiyun 	int idx;
43*4882a593Smuzhiyun 	int ret = 0;
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun 	mutex_lock(&dev->mt76.mutex);
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun 	mvif->idx = ffs(~dev->mphy.vif_mask) - 1;
48*4882a593Smuzhiyun 	if (mvif->idx >= MT7603_MAX_INTERFACES) {
49*4882a593Smuzhiyun 		ret = -ENOSPC;
50*4882a593Smuzhiyun 		goto out;
51*4882a593Smuzhiyun 	}
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun 	mt76_wr(dev, MT_MAC_ADDR0(mvif->idx),
54*4882a593Smuzhiyun 		get_unaligned_le32(vif->addr));
55*4882a593Smuzhiyun 	mt76_wr(dev, MT_MAC_ADDR1(mvif->idx),
56*4882a593Smuzhiyun 		(get_unaligned_le16(vif->addr + 4) |
57*4882a593Smuzhiyun 		 MT_MAC_ADDR1_VALID));
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun 	if (vif->type == NL80211_IFTYPE_AP) {
60*4882a593Smuzhiyun 		mt76_wr(dev, MT_BSSID0(mvif->idx),
61*4882a593Smuzhiyun 			get_unaligned_le32(vif->addr));
62*4882a593Smuzhiyun 		mt76_wr(dev, MT_BSSID1(mvif->idx),
63*4882a593Smuzhiyun 			(get_unaligned_le16(vif->addr + 4) |
64*4882a593Smuzhiyun 			 MT_BSSID1_VALID));
65*4882a593Smuzhiyun 	}
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun 	idx = MT7603_WTBL_RESERVED - 1 - mvif->idx;
68*4882a593Smuzhiyun 	dev->mphy.vif_mask |= BIT(mvif->idx);
69*4882a593Smuzhiyun 	INIT_LIST_HEAD(&mvif->sta.poll_list);
70*4882a593Smuzhiyun 	mvif->sta.wcid.idx = idx;
71*4882a593Smuzhiyun 	mvif->sta.wcid.hw_key_idx = -1;
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	eth_broadcast_addr(bc_addr);
74*4882a593Smuzhiyun 	mt7603_wtbl_init(dev, idx, mvif->idx, bc_addr);
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	mtxq = (struct mt76_txq *)vif->txq->drv_priv;
77*4882a593Smuzhiyun 	mtxq->wcid = &mvif->sta.wcid;
78*4882a593Smuzhiyun 	rcu_assign_pointer(dev->mt76.wcid[idx], &mvif->sta.wcid);
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun out:
81*4882a593Smuzhiyun 	mutex_unlock(&dev->mt76.mutex);
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	return ret;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun static void
mt7603_remove_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif)87*4882a593Smuzhiyun mt7603_remove_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun 	struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv;
90*4882a593Smuzhiyun 	struct mt7603_sta *msta = &mvif->sta;
91*4882a593Smuzhiyun 	struct mt7603_dev *dev = hw->priv;
92*4882a593Smuzhiyun 	int idx = msta->wcid.idx;
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	mt76_wr(dev, MT_MAC_ADDR0(mvif->idx), 0);
95*4882a593Smuzhiyun 	mt76_wr(dev, MT_MAC_ADDR1(mvif->idx), 0);
96*4882a593Smuzhiyun 	mt76_wr(dev, MT_BSSID0(mvif->idx), 0);
97*4882a593Smuzhiyun 	mt76_wr(dev, MT_BSSID1(mvif->idx), 0);
98*4882a593Smuzhiyun 	mt7603_beacon_set_timer(dev, mvif->idx, 0);
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	rcu_assign_pointer(dev->mt76.wcid[idx], NULL);
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	spin_lock_bh(&dev->sta_poll_lock);
103*4882a593Smuzhiyun 	if (!list_empty(&msta->poll_list))
104*4882a593Smuzhiyun 		list_del_init(&msta->poll_list);
105*4882a593Smuzhiyun 	spin_unlock_bh(&dev->sta_poll_lock);
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	mutex_lock(&dev->mt76.mutex);
108*4882a593Smuzhiyun 	dev->mphy.vif_mask &= ~BIT(mvif->idx);
109*4882a593Smuzhiyun 	mutex_unlock(&dev->mt76.mutex);
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun 
mt7603_init_edcca(struct mt7603_dev * dev)112*4882a593Smuzhiyun void mt7603_init_edcca(struct mt7603_dev *dev)
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun 	/* Set lower signal level to -65dBm */
115*4882a593Smuzhiyun 	mt76_rmw_field(dev, MT_RXTD(8), MT_RXTD_8_LOWER_SIGNAL, 0x23);
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	/* clear previous energy detect monitor results */
118*4882a593Smuzhiyun 	mt76_rr(dev, MT_MIB_STAT_ED);
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	if (dev->ed_monitor)
121*4882a593Smuzhiyun 		mt76_set(dev, MT_MIB_CTL, MT_MIB_CTL_ED_TIME);
122*4882a593Smuzhiyun 	else
123*4882a593Smuzhiyun 		mt76_clear(dev, MT_MIB_CTL, MT_MIB_CTL_ED_TIME);
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	dev->ed_strict_mode = 0xff;
126*4882a593Smuzhiyun 	dev->ed_strong_signal = 0;
127*4882a593Smuzhiyun 	dev->ed_time = ktime_get_boottime();
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	mt7603_edcca_set_strict(dev, false);
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun static int
mt7603_set_channel(struct mt7603_dev * dev,struct cfg80211_chan_def * def)133*4882a593Smuzhiyun mt7603_set_channel(struct mt7603_dev *dev, struct cfg80211_chan_def *def)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun 	u8 *rssi_data = (u8 *)dev->mt76.eeprom.data;
136*4882a593Smuzhiyun 	int idx, ret;
137*4882a593Smuzhiyun 	u8 bw = MT_BW_20;
138*4882a593Smuzhiyun 	bool failed = false;
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	cancel_delayed_work_sync(&dev->mt76.mac_work);
141*4882a593Smuzhiyun 	tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	mutex_lock(&dev->mt76.mutex);
144*4882a593Smuzhiyun 	set_bit(MT76_RESET, &dev->mphy.state);
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	mt7603_beacon_set_timer(dev, -1, 0);
147*4882a593Smuzhiyun 	mt76_set_channel(&dev->mphy);
148*4882a593Smuzhiyun 	mt7603_mac_stop(dev);
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	if (def->width == NL80211_CHAN_WIDTH_40)
151*4882a593Smuzhiyun 		bw = MT_BW_40;
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun 	dev->mphy.chandef = *def;
154*4882a593Smuzhiyun 	mt76_rmw_field(dev, MT_AGG_BWCR, MT_AGG_BWCR_BW, bw);
155*4882a593Smuzhiyun 	ret = mt7603_mcu_set_channel(dev);
156*4882a593Smuzhiyun 	if (ret) {
157*4882a593Smuzhiyun 		failed = true;
158*4882a593Smuzhiyun 		goto out;
159*4882a593Smuzhiyun 	}
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	if (def->chan->band == NL80211_BAND_5GHZ) {
162*4882a593Smuzhiyun 		idx = 1;
163*4882a593Smuzhiyun 		rssi_data += MT_EE_RSSI_OFFSET_5G;
164*4882a593Smuzhiyun 	} else {
165*4882a593Smuzhiyun 		idx = 0;
166*4882a593Smuzhiyun 		rssi_data += MT_EE_RSSI_OFFSET_2G;
167*4882a593Smuzhiyun 	}
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 	memcpy(dev->rssi_offset, rssi_data, sizeof(dev->rssi_offset));
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 	idx |= (def->chan -
172*4882a593Smuzhiyun 		mt76_hw(dev)->wiphy->bands[def->chan->band]->channels) << 1;
173*4882a593Smuzhiyun 	mt76_wr(dev, MT_WF_RMAC_CH_FREQ, idx);
174*4882a593Smuzhiyun 	mt7603_mac_set_timing(dev);
175*4882a593Smuzhiyun 	mt7603_mac_start(dev);
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	clear_bit(MT76_RESET, &dev->mphy.state);
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 	mt76_txq_schedule_all(&dev->mphy);
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun 	ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mt76.mac_work,
182*4882a593Smuzhiyun 				     msecs_to_jiffies(MT7603_WATCHDOG_TIME));
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	/* reset channel stats */
185*4882a593Smuzhiyun 	mt76_clear(dev, MT_MIB_CTL, MT_MIB_CTL_READ_CLR_DIS);
186*4882a593Smuzhiyun 	mt76_set(dev, MT_MIB_CTL,
187*4882a593Smuzhiyun 		 MT_MIB_CTL_CCA_NAV_TX | MT_MIB_CTL_PSCCA_TIME);
188*4882a593Smuzhiyun 	mt76_rr(dev, MT_MIB_STAT_CCA);
189*4882a593Smuzhiyun 	mt7603_cca_stats_reset(dev);
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	dev->mphy.survey_time = ktime_get_boottime();
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	mt7603_init_edcca(dev);
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun out:
196*4882a593Smuzhiyun 	if (!(mt76_hw(dev)->conf.flags & IEEE80211_CONF_OFFCHANNEL))
197*4882a593Smuzhiyun 		mt7603_beacon_set_timer(dev, -1, dev->mt76.beacon_int);
198*4882a593Smuzhiyun 	mutex_unlock(&dev->mt76.mutex);
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	tasklet_enable(&dev->mt76.pre_tbtt_tasklet);
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	if (failed)
203*4882a593Smuzhiyun 		mt7603_mac_work(&dev->mt76.mac_work.work);
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 	return ret;
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun static int
mt7603_config(struct ieee80211_hw * hw,u32 changed)209*4882a593Smuzhiyun mt7603_config(struct ieee80211_hw *hw, u32 changed)
210*4882a593Smuzhiyun {
211*4882a593Smuzhiyun 	struct mt7603_dev *dev = hw->priv;
212*4882a593Smuzhiyun 	int ret = 0;
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 	if (changed & (IEEE80211_CONF_CHANGE_CHANNEL |
215*4882a593Smuzhiyun 		       IEEE80211_CONF_CHANGE_POWER)) {
216*4882a593Smuzhiyun 		ieee80211_stop_queues(hw);
217*4882a593Smuzhiyun 		ret = mt7603_set_channel(dev, &hw->conf.chandef);
218*4882a593Smuzhiyun 		ieee80211_wake_queues(hw);
219*4882a593Smuzhiyun 	}
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun 	if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
222*4882a593Smuzhiyun 		mutex_lock(&dev->mt76.mutex);
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun 		if (!(hw->conf.flags & IEEE80211_CONF_MONITOR))
225*4882a593Smuzhiyun 			dev->rxfilter |= MT_WF_RFCR_DROP_OTHER_UC;
226*4882a593Smuzhiyun 		else
227*4882a593Smuzhiyun 			dev->rxfilter &= ~MT_WF_RFCR_DROP_OTHER_UC;
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 		mt76_wr(dev, MT_WF_RFCR, dev->rxfilter);
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun 		mutex_unlock(&dev->mt76.mutex);
232*4882a593Smuzhiyun 	}
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 	return ret;
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun static void
mt7603_configure_filter(struct ieee80211_hw * hw,unsigned int changed_flags,unsigned int * total_flags,u64 multicast)238*4882a593Smuzhiyun mt7603_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
239*4882a593Smuzhiyun 			unsigned int *total_flags, u64 multicast)
240*4882a593Smuzhiyun {
241*4882a593Smuzhiyun 	struct mt7603_dev *dev = hw->priv;
242*4882a593Smuzhiyun 	u32 flags = 0;
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun #define MT76_FILTER(_flag, _hw) do { \
245*4882a593Smuzhiyun 		flags |= *total_flags & FIF_##_flag;			\
246*4882a593Smuzhiyun 		dev->rxfilter &= ~(_hw);				\
247*4882a593Smuzhiyun 		dev->rxfilter |= !(flags & FIF_##_flag) * (_hw);	\
248*4882a593Smuzhiyun 	} while (0)
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun 	dev->rxfilter &= ~(MT_WF_RFCR_DROP_OTHER_BSS |
251*4882a593Smuzhiyun 			   MT_WF_RFCR_DROP_OTHER_BEACON |
252*4882a593Smuzhiyun 			   MT_WF_RFCR_DROP_FRAME_REPORT |
253*4882a593Smuzhiyun 			   MT_WF_RFCR_DROP_PROBEREQ |
254*4882a593Smuzhiyun 			   MT_WF_RFCR_DROP_MCAST_FILTERED |
255*4882a593Smuzhiyun 			   MT_WF_RFCR_DROP_MCAST |
256*4882a593Smuzhiyun 			   MT_WF_RFCR_DROP_BCAST |
257*4882a593Smuzhiyun 			   MT_WF_RFCR_DROP_DUPLICATE |
258*4882a593Smuzhiyun 			   MT_WF_RFCR_DROP_A2_BSSID |
259*4882a593Smuzhiyun 			   MT_WF_RFCR_DROP_UNWANTED_CTL |
260*4882a593Smuzhiyun 			   MT_WF_RFCR_DROP_STBC_MULTI);
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 	MT76_FILTER(OTHER_BSS, MT_WF_RFCR_DROP_OTHER_TIM |
263*4882a593Smuzhiyun 			       MT_WF_RFCR_DROP_A3_MAC |
264*4882a593Smuzhiyun 			       MT_WF_RFCR_DROP_A3_BSSID);
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	MT76_FILTER(FCSFAIL, MT_WF_RFCR_DROP_FCSFAIL);
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun 	MT76_FILTER(CONTROL, MT_WF_RFCR_DROP_CTS |
269*4882a593Smuzhiyun 			     MT_WF_RFCR_DROP_RTS |
270*4882a593Smuzhiyun 			     MT_WF_RFCR_DROP_CTL_RSV |
271*4882a593Smuzhiyun 			     MT_WF_RFCR_DROP_NDPA);
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	*total_flags = flags;
274*4882a593Smuzhiyun 	mt76_wr(dev, MT_WF_RFCR, dev->rxfilter);
275*4882a593Smuzhiyun }
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun static void
mt7603_bss_info_changed(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_bss_conf * info,u32 changed)278*4882a593Smuzhiyun mt7603_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
279*4882a593Smuzhiyun 			struct ieee80211_bss_conf *info, u32 changed)
280*4882a593Smuzhiyun {
281*4882a593Smuzhiyun 	struct mt7603_dev *dev = hw->priv;
282*4882a593Smuzhiyun 	struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv;
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun 	mutex_lock(&dev->mt76.mutex);
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun 	if (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BSSID)) {
287*4882a593Smuzhiyun 		if (info->assoc || info->ibss_joined) {
288*4882a593Smuzhiyun 			mt76_wr(dev, MT_BSSID0(mvif->idx),
289*4882a593Smuzhiyun 				get_unaligned_le32(info->bssid));
290*4882a593Smuzhiyun 			mt76_wr(dev, MT_BSSID1(mvif->idx),
291*4882a593Smuzhiyun 				(get_unaligned_le16(info->bssid + 4) |
292*4882a593Smuzhiyun 				 MT_BSSID1_VALID));
293*4882a593Smuzhiyun 		} else {
294*4882a593Smuzhiyun 			mt76_wr(dev, MT_BSSID0(mvif->idx), 0);
295*4882a593Smuzhiyun 			mt76_wr(dev, MT_BSSID1(mvif->idx), 0);
296*4882a593Smuzhiyun 		}
297*4882a593Smuzhiyun 	}
298*4882a593Smuzhiyun 
299*4882a593Smuzhiyun 	if (changed & BSS_CHANGED_ERP_SLOT) {
300*4882a593Smuzhiyun 		int slottime = info->use_short_slot ? 9 : 20;
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun 		if (slottime != dev->slottime) {
303*4882a593Smuzhiyun 			dev->slottime = slottime;
304*4882a593Smuzhiyun 			mt7603_mac_set_timing(dev);
305*4882a593Smuzhiyun 		}
306*4882a593Smuzhiyun 	}
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun 	if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON_INT)) {
309*4882a593Smuzhiyun 		int beacon_int = !!info->enable_beacon * info->beacon_int;
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun 		tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
312*4882a593Smuzhiyun 		mt7603_beacon_set_timer(dev, mvif->idx, beacon_int);
313*4882a593Smuzhiyun 		tasklet_enable(&dev->mt76.pre_tbtt_tasklet);
314*4882a593Smuzhiyun 	}
315*4882a593Smuzhiyun 
316*4882a593Smuzhiyun 	mutex_unlock(&dev->mt76.mutex);
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun int
mt7603_sta_add(struct mt76_dev * mdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)320*4882a593Smuzhiyun mt7603_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
321*4882a593Smuzhiyun 	       struct ieee80211_sta *sta)
322*4882a593Smuzhiyun {
323*4882a593Smuzhiyun 	struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
324*4882a593Smuzhiyun 	struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv;
325*4882a593Smuzhiyun 	struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv;
326*4882a593Smuzhiyun 	int idx;
327*4882a593Smuzhiyun 	int ret = 0;
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun 	idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7603_WTBL_STA - 1);
330*4882a593Smuzhiyun 	if (idx < 0)
331*4882a593Smuzhiyun 		return -ENOSPC;
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun 	INIT_LIST_HEAD(&msta->poll_list);
334*4882a593Smuzhiyun 	__skb_queue_head_init(&msta->psq);
335*4882a593Smuzhiyun 	msta->ps = ~0;
336*4882a593Smuzhiyun 	msta->smps = ~0;
337*4882a593Smuzhiyun 	msta->wcid.sta = 1;
338*4882a593Smuzhiyun 	msta->wcid.idx = idx;
339*4882a593Smuzhiyun 	mt7603_wtbl_init(dev, idx, mvif->idx, sta->addr);
340*4882a593Smuzhiyun 	mt7603_wtbl_set_ps(dev, msta, false);
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun 	if (vif->type == NL80211_IFTYPE_AP)
343*4882a593Smuzhiyun 		set_bit(MT_WCID_FLAG_CHECK_PS, &msta->wcid.flags);
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun 	return ret;
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun void
mt7603_sta_assoc(struct mt76_dev * mdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)349*4882a593Smuzhiyun mt7603_sta_assoc(struct mt76_dev *mdev, struct ieee80211_vif *vif,
350*4882a593Smuzhiyun 		 struct ieee80211_sta *sta)
351*4882a593Smuzhiyun {
352*4882a593Smuzhiyun 	struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
353*4882a593Smuzhiyun 
354*4882a593Smuzhiyun 	mt7603_wtbl_update_cap(dev, sta);
355*4882a593Smuzhiyun }
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun void
mt7603_sta_remove(struct mt76_dev * mdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)358*4882a593Smuzhiyun mt7603_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif,
359*4882a593Smuzhiyun 		  struct ieee80211_sta *sta)
360*4882a593Smuzhiyun {
361*4882a593Smuzhiyun 	struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
362*4882a593Smuzhiyun 	struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv;
363*4882a593Smuzhiyun 	struct mt76_wcid *wcid = (struct mt76_wcid *)sta->drv_priv;
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun 	spin_lock_bh(&dev->ps_lock);
366*4882a593Smuzhiyun 	__skb_queue_purge(&msta->psq);
367*4882a593Smuzhiyun 	mt7603_filter_tx(dev, wcid->idx, true);
368*4882a593Smuzhiyun 	spin_unlock_bh(&dev->ps_lock);
369*4882a593Smuzhiyun 
370*4882a593Smuzhiyun 	spin_lock_bh(&dev->sta_poll_lock);
371*4882a593Smuzhiyun 	if (!list_empty(&msta->poll_list))
372*4882a593Smuzhiyun 		list_del_init(&msta->poll_list);
373*4882a593Smuzhiyun 	spin_unlock_bh(&dev->sta_poll_lock);
374*4882a593Smuzhiyun 
375*4882a593Smuzhiyun 	mt7603_wtbl_clear(dev, wcid->idx);
376*4882a593Smuzhiyun }
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun static void
mt7603_ps_tx_list(struct mt7603_dev * dev,struct sk_buff_head * list)379*4882a593Smuzhiyun mt7603_ps_tx_list(struct mt7603_dev *dev, struct sk_buff_head *list)
380*4882a593Smuzhiyun {
381*4882a593Smuzhiyun 	struct sk_buff *skb;
382*4882a593Smuzhiyun 
383*4882a593Smuzhiyun 	while ((skb = __skb_dequeue(list)) != NULL)
384*4882a593Smuzhiyun 		mt76_tx_queue_skb_raw(dev, skb_get_queue_mapping(skb),
385*4882a593Smuzhiyun 				      skb, 0);
386*4882a593Smuzhiyun }
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun void
mt7603_sta_ps(struct mt76_dev * mdev,struct ieee80211_sta * sta,bool ps)389*4882a593Smuzhiyun mt7603_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps)
390*4882a593Smuzhiyun {
391*4882a593Smuzhiyun 	struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
392*4882a593Smuzhiyun 	struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv;
393*4882a593Smuzhiyun 	struct sk_buff_head list;
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun 	mt76_stop_tx_queues(&dev->mt76, sta, true);
396*4882a593Smuzhiyun 	mt7603_wtbl_set_ps(dev, msta, ps);
397*4882a593Smuzhiyun 	if (ps)
398*4882a593Smuzhiyun 		return;
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 	__skb_queue_head_init(&list);
401*4882a593Smuzhiyun 
402*4882a593Smuzhiyun 	spin_lock_bh(&dev->ps_lock);
403*4882a593Smuzhiyun 	skb_queue_splice_tail_init(&msta->psq, &list);
404*4882a593Smuzhiyun 	spin_unlock_bh(&dev->ps_lock);
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun 	mt7603_ps_tx_list(dev, &list);
407*4882a593Smuzhiyun }
408*4882a593Smuzhiyun 
409*4882a593Smuzhiyun static void
mt7603_ps_set_more_data(struct sk_buff * skb)410*4882a593Smuzhiyun mt7603_ps_set_more_data(struct sk_buff *skb)
411*4882a593Smuzhiyun {
412*4882a593Smuzhiyun 	struct ieee80211_hdr *hdr;
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun 	hdr = (struct ieee80211_hdr *)&skb->data[MT_TXD_SIZE];
415*4882a593Smuzhiyun 	hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA);
416*4882a593Smuzhiyun }
417*4882a593Smuzhiyun 
418*4882a593Smuzhiyun static void
mt7603_release_buffered_frames(struct ieee80211_hw * hw,struct ieee80211_sta * sta,u16 tids,int nframes,enum ieee80211_frame_release_type reason,bool more_data)419*4882a593Smuzhiyun mt7603_release_buffered_frames(struct ieee80211_hw *hw,
420*4882a593Smuzhiyun 			       struct ieee80211_sta *sta,
421*4882a593Smuzhiyun 			       u16 tids, int nframes,
422*4882a593Smuzhiyun 			       enum ieee80211_frame_release_type reason,
423*4882a593Smuzhiyun 			       bool more_data)
424*4882a593Smuzhiyun {
425*4882a593Smuzhiyun 	struct mt7603_dev *dev = hw->priv;
426*4882a593Smuzhiyun 	struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv;
427*4882a593Smuzhiyun 	struct sk_buff_head list;
428*4882a593Smuzhiyun 	struct sk_buff *skb, *tmp;
429*4882a593Smuzhiyun 
430*4882a593Smuzhiyun 	__skb_queue_head_init(&list);
431*4882a593Smuzhiyun 
432*4882a593Smuzhiyun 	mt7603_wtbl_set_ps(dev, msta, false);
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun 	spin_lock_bh(&dev->ps_lock);
435*4882a593Smuzhiyun 	skb_queue_walk_safe(&msta->psq, skb, tmp) {
436*4882a593Smuzhiyun 		if (!nframes)
437*4882a593Smuzhiyun 			break;
438*4882a593Smuzhiyun 
439*4882a593Smuzhiyun 		if (!(tids & BIT(skb->priority)))
440*4882a593Smuzhiyun 			continue;
441*4882a593Smuzhiyun 
442*4882a593Smuzhiyun 		skb_set_queue_mapping(skb, MT_TXQ_PSD);
443*4882a593Smuzhiyun 		__skb_unlink(skb, &msta->psq);
444*4882a593Smuzhiyun 		mt7603_ps_set_more_data(skb);
445*4882a593Smuzhiyun 		__skb_queue_tail(&list, skb);
446*4882a593Smuzhiyun 		nframes--;
447*4882a593Smuzhiyun 	}
448*4882a593Smuzhiyun 	spin_unlock_bh(&dev->ps_lock);
449*4882a593Smuzhiyun 
450*4882a593Smuzhiyun 	if (!skb_queue_empty(&list))
451*4882a593Smuzhiyun 		ieee80211_sta_eosp(sta);
452*4882a593Smuzhiyun 
453*4882a593Smuzhiyun 	mt7603_ps_tx_list(dev, &list);
454*4882a593Smuzhiyun 
455*4882a593Smuzhiyun 	if (nframes)
456*4882a593Smuzhiyun 		mt76_release_buffered_frames(hw, sta, tids, nframes, reason,
457*4882a593Smuzhiyun 					     more_data);
458*4882a593Smuzhiyun }
459*4882a593Smuzhiyun 
460*4882a593Smuzhiyun static int
mt7603_set_key(struct ieee80211_hw * hw,enum set_key_cmd cmd,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct ieee80211_key_conf * key)461*4882a593Smuzhiyun mt7603_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
462*4882a593Smuzhiyun 	       struct ieee80211_vif *vif, struct ieee80211_sta *sta,
463*4882a593Smuzhiyun 	       struct ieee80211_key_conf *key)
464*4882a593Smuzhiyun {
465*4882a593Smuzhiyun 	struct mt7603_dev *dev = hw->priv;
466*4882a593Smuzhiyun 	struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv;
467*4882a593Smuzhiyun 	struct mt7603_sta *msta = sta ? (struct mt7603_sta *)sta->drv_priv :
468*4882a593Smuzhiyun 				  &mvif->sta;
469*4882a593Smuzhiyun 	struct mt76_wcid *wcid = &msta->wcid;
470*4882a593Smuzhiyun 	int idx = key->keyidx;
471*4882a593Smuzhiyun 
472*4882a593Smuzhiyun 	/* fall back to sw encryption for unsupported ciphers */
473*4882a593Smuzhiyun 	switch (key->cipher) {
474*4882a593Smuzhiyun 	case WLAN_CIPHER_SUITE_TKIP:
475*4882a593Smuzhiyun 	case WLAN_CIPHER_SUITE_CCMP:
476*4882a593Smuzhiyun 		break;
477*4882a593Smuzhiyun 	default:
478*4882a593Smuzhiyun 		return -EOPNOTSUPP;
479*4882a593Smuzhiyun 	}
480*4882a593Smuzhiyun 
481*4882a593Smuzhiyun 	/*
482*4882a593Smuzhiyun 	 * The hardware does not support per-STA RX GTK, fall back
483*4882a593Smuzhiyun 	 * to software mode for these.
484*4882a593Smuzhiyun 	 */
485*4882a593Smuzhiyun 	if ((vif->type == NL80211_IFTYPE_ADHOC ||
486*4882a593Smuzhiyun 	     vif->type == NL80211_IFTYPE_MESH_POINT) &&
487*4882a593Smuzhiyun 	    (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
488*4882a593Smuzhiyun 	     key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
489*4882a593Smuzhiyun 	    !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
490*4882a593Smuzhiyun 		return -EOPNOTSUPP;
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun 	if (cmd == SET_KEY) {
493*4882a593Smuzhiyun 		key->hw_key_idx = wcid->idx;
494*4882a593Smuzhiyun 		wcid->hw_key_idx = idx;
495*4882a593Smuzhiyun 	} else {
496*4882a593Smuzhiyun 		if (idx == wcid->hw_key_idx)
497*4882a593Smuzhiyun 			wcid->hw_key_idx = -1;
498*4882a593Smuzhiyun 
499*4882a593Smuzhiyun 		key = NULL;
500*4882a593Smuzhiyun 	}
501*4882a593Smuzhiyun 	mt76_wcid_key_setup(&dev->mt76, wcid, key);
502*4882a593Smuzhiyun 
503*4882a593Smuzhiyun 	return mt7603_wtbl_set_key(dev, wcid->idx, key);
504*4882a593Smuzhiyun }
505*4882a593Smuzhiyun 
506*4882a593Smuzhiyun static int
mt7603_conf_tx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u16 queue,const struct ieee80211_tx_queue_params * params)507*4882a593Smuzhiyun mt7603_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u16 queue,
508*4882a593Smuzhiyun 	       const struct ieee80211_tx_queue_params *params)
509*4882a593Smuzhiyun {
510*4882a593Smuzhiyun 	struct mt7603_dev *dev = hw->priv;
511*4882a593Smuzhiyun 	u16 cw_min = (1 << 5) - 1;
512*4882a593Smuzhiyun 	u16 cw_max = (1 << 10) - 1;
513*4882a593Smuzhiyun 	u32 val;
514*4882a593Smuzhiyun 
515*4882a593Smuzhiyun 	queue = dev->mt76.q_tx[queue]->hw_idx;
516*4882a593Smuzhiyun 
517*4882a593Smuzhiyun 	if (params->cw_min)
518*4882a593Smuzhiyun 		cw_min = params->cw_min;
519*4882a593Smuzhiyun 	if (params->cw_max)
520*4882a593Smuzhiyun 		cw_max = params->cw_max;
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun 	mutex_lock(&dev->mt76.mutex);
523*4882a593Smuzhiyun 	mt7603_mac_stop(dev);
524*4882a593Smuzhiyun 
525*4882a593Smuzhiyun 	val = mt76_rr(dev, MT_WMM_TXOP(queue));
526*4882a593Smuzhiyun 	val &= ~(MT_WMM_TXOP_MASK << MT_WMM_TXOP_SHIFT(queue));
527*4882a593Smuzhiyun 	val |= params->txop << MT_WMM_TXOP_SHIFT(queue);
528*4882a593Smuzhiyun 	mt76_wr(dev, MT_WMM_TXOP(queue), val);
529*4882a593Smuzhiyun 
530*4882a593Smuzhiyun 	val = mt76_rr(dev, MT_WMM_AIFSN);
531*4882a593Smuzhiyun 	val &= ~(MT_WMM_AIFSN_MASK << MT_WMM_AIFSN_SHIFT(queue));
532*4882a593Smuzhiyun 	val |= params->aifs << MT_WMM_AIFSN_SHIFT(queue);
533*4882a593Smuzhiyun 	mt76_wr(dev, MT_WMM_AIFSN, val);
534*4882a593Smuzhiyun 
535*4882a593Smuzhiyun 	val = mt76_rr(dev, MT_WMM_CWMIN);
536*4882a593Smuzhiyun 	val &= ~(MT_WMM_CWMIN_MASK << MT_WMM_CWMIN_SHIFT(queue));
537*4882a593Smuzhiyun 	val |= cw_min << MT_WMM_CWMIN_SHIFT(queue);
538*4882a593Smuzhiyun 	mt76_wr(dev, MT_WMM_CWMIN, val);
539*4882a593Smuzhiyun 
540*4882a593Smuzhiyun 	val = mt76_rr(dev, MT_WMM_CWMAX(queue));
541*4882a593Smuzhiyun 	val &= ~(MT_WMM_CWMAX_MASK << MT_WMM_CWMAX_SHIFT(queue));
542*4882a593Smuzhiyun 	val |= cw_max << MT_WMM_CWMAX_SHIFT(queue);
543*4882a593Smuzhiyun 	mt76_wr(dev, MT_WMM_CWMAX(queue), val);
544*4882a593Smuzhiyun 
545*4882a593Smuzhiyun 	mt7603_mac_start(dev);
546*4882a593Smuzhiyun 	mutex_unlock(&dev->mt76.mutex);
547*4882a593Smuzhiyun 
548*4882a593Smuzhiyun 	return 0;
549*4882a593Smuzhiyun }
550*4882a593Smuzhiyun 
551*4882a593Smuzhiyun static void
mt7603_flush(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u32 queues,bool drop)552*4882a593Smuzhiyun mt7603_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
553*4882a593Smuzhiyun 	     u32 queues, bool drop)
554*4882a593Smuzhiyun {
555*4882a593Smuzhiyun }
556*4882a593Smuzhiyun 
557*4882a593Smuzhiyun static int
mt7603_ampdu_action(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_ampdu_params * params)558*4882a593Smuzhiyun mt7603_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
559*4882a593Smuzhiyun 		    struct ieee80211_ampdu_params *params)
560*4882a593Smuzhiyun {
561*4882a593Smuzhiyun 	enum ieee80211_ampdu_mlme_action action = params->action;
562*4882a593Smuzhiyun 	struct mt7603_dev *dev = hw->priv;
563*4882a593Smuzhiyun 	struct ieee80211_sta *sta = params->sta;
564*4882a593Smuzhiyun 	struct ieee80211_txq *txq = sta->txq[params->tid];
565*4882a593Smuzhiyun 	struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv;
566*4882a593Smuzhiyun 	u16 tid = params->tid;
567*4882a593Smuzhiyun 	u16 ssn = params->ssn;
568*4882a593Smuzhiyun 	u8 ba_size = params->buf_size;
569*4882a593Smuzhiyun 	struct mt76_txq *mtxq;
570*4882a593Smuzhiyun 	int ret = 0;
571*4882a593Smuzhiyun 
572*4882a593Smuzhiyun 	if (!txq)
573*4882a593Smuzhiyun 		return -EINVAL;
574*4882a593Smuzhiyun 
575*4882a593Smuzhiyun 	mtxq = (struct mt76_txq *)txq->drv_priv;
576*4882a593Smuzhiyun 
577*4882a593Smuzhiyun 	mutex_lock(&dev->mt76.mutex);
578*4882a593Smuzhiyun 	switch (action) {
579*4882a593Smuzhiyun 	case IEEE80211_AMPDU_RX_START:
580*4882a593Smuzhiyun 		mt76_rx_aggr_start(&dev->mt76, &msta->wcid, tid, ssn,
581*4882a593Smuzhiyun 				   params->buf_size);
582*4882a593Smuzhiyun 		mt7603_mac_rx_ba_reset(dev, sta->addr, tid);
583*4882a593Smuzhiyun 		break;
584*4882a593Smuzhiyun 	case IEEE80211_AMPDU_RX_STOP:
585*4882a593Smuzhiyun 		mt76_rx_aggr_stop(&dev->mt76, &msta->wcid, tid);
586*4882a593Smuzhiyun 		break;
587*4882a593Smuzhiyun 	case IEEE80211_AMPDU_TX_OPERATIONAL:
588*4882a593Smuzhiyun 		mtxq->aggr = true;
589*4882a593Smuzhiyun 		mtxq->send_bar = false;
590*4882a593Smuzhiyun 		mt7603_mac_tx_ba_reset(dev, msta->wcid.idx, tid, ba_size);
591*4882a593Smuzhiyun 		break;
592*4882a593Smuzhiyun 	case IEEE80211_AMPDU_TX_STOP_FLUSH:
593*4882a593Smuzhiyun 	case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
594*4882a593Smuzhiyun 		mtxq->aggr = false;
595*4882a593Smuzhiyun 		mt7603_mac_tx_ba_reset(dev, msta->wcid.idx, tid, -1);
596*4882a593Smuzhiyun 		break;
597*4882a593Smuzhiyun 	case IEEE80211_AMPDU_TX_START:
598*4882a593Smuzhiyun 		mtxq->agg_ssn = IEEE80211_SN_TO_SEQ(ssn);
599*4882a593Smuzhiyun 		ret = IEEE80211_AMPDU_TX_START_IMMEDIATE;
600*4882a593Smuzhiyun 		break;
601*4882a593Smuzhiyun 	case IEEE80211_AMPDU_TX_STOP_CONT:
602*4882a593Smuzhiyun 		mtxq->aggr = false;
603*4882a593Smuzhiyun 		mt7603_mac_tx_ba_reset(dev, msta->wcid.idx, tid, -1);
604*4882a593Smuzhiyun 		ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
605*4882a593Smuzhiyun 		break;
606*4882a593Smuzhiyun 	}
607*4882a593Smuzhiyun 	mutex_unlock(&dev->mt76.mutex);
608*4882a593Smuzhiyun 
609*4882a593Smuzhiyun 	return ret;
610*4882a593Smuzhiyun }
611*4882a593Smuzhiyun 
612*4882a593Smuzhiyun static void
mt7603_sta_rate_tbl_update(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta)613*4882a593Smuzhiyun mt7603_sta_rate_tbl_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
614*4882a593Smuzhiyun 			   struct ieee80211_sta *sta)
615*4882a593Smuzhiyun {
616*4882a593Smuzhiyun 	struct mt7603_dev *dev = hw->priv;
617*4882a593Smuzhiyun 	struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv;
618*4882a593Smuzhiyun 	struct ieee80211_sta_rates *sta_rates = rcu_dereference(sta->rates);
619*4882a593Smuzhiyun 	int i;
620*4882a593Smuzhiyun 
621*4882a593Smuzhiyun 	if (!sta_rates)
622*4882a593Smuzhiyun 		return;
623*4882a593Smuzhiyun 
624*4882a593Smuzhiyun 	spin_lock_bh(&dev->mt76.lock);
625*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(msta->rates); i++) {
626*4882a593Smuzhiyun 		msta->rates[i].idx = sta_rates->rate[i].idx;
627*4882a593Smuzhiyun 		msta->rates[i].count = sta_rates->rate[i].count;
628*4882a593Smuzhiyun 		msta->rates[i].flags = sta_rates->rate[i].flags;
629*4882a593Smuzhiyun 
630*4882a593Smuzhiyun 		if (msta->rates[i].idx < 0 || !msta->rates[i].count)
631*4882a593Smuzhiyun 			break;
632*4882a593Smuzhiyun 	}
633*4882a593Smuzhiyun 	msta->n_rates = i;
634*4882a593Smuzhiyun 	mt7603_wtbl_set_rates(dev, msta, NULL, msta->rates);
635*4882a593Smuzhiyun 	msta->rate_probe = false;
636*4882a593Smuzhiyun 	mt7603_wtbl_set_smps(dev, msta,
637*4882a593Smuzhiyun 			     sta->smps_mode == IEEE80211_SMPS_DYNAMIC);
638*4882a593Smuzhiyun 	spin_unlock_bh(&dev->mt76.lock);
639*4882a593Smuzhiyun }
640*4882a593Smuzhiyun 
641*4882a593Smuzhiyun static void
mt7603_set_coverage_class(struct ieee80211_hw * hw,s16 coverage_class)642*4882a593Smuzhiyun mt7603_set_coverage_class(struct ieee80211_hw *hw, s16 coverage_class)
643*4882a593Smuzhiyun {
644*4882a593Smuzhiyun 	struct mt7603_dev *dev = hw->priv;
645*4882a593Smuzhiyun 
646*4882a593Smuzhiyun 	mutex_lock(&dev->mt76.mutex);
647*4882a593Smuzhiyun 	dev->coverage_class = max_t(s16, coverage_class, 0);
648*4882a593Smuzhiyun 	mt7603_mac_set_timing(dev);
649*4882a593Smuzhiyun 	mutex_unlock(&dev->mt76.mutex);
650*4882a593Smuzhiyun }
651*4882a593Smuzhiyun 
mt7603_tx(struct ieee80211_hw * hw,struct ieee80211_tx_control * control,struct sk_buff * skb)652*4882a593Smuzhiyun static void mt7603_tx(struct ieee80211_hw *hw,
653*4882a593Smuzhiyun 		      struct ieee80211_tx_control *control,
654*4882a593Smuzhiyun 		      struct sk_buff *skb)
655*4882a593Smuzhiyun {
656*4882a593Smuzhiyun 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
657*4882a593Smuzhiyun 	struct ieee80211_vif *vif = info->control.vif;
658*4882a593Smuzhiyun 	struct mt7603_dev *dev = hw->priv;
659*4882a593Smuzhiyun 	struct mt76_wcid *wcid = &dev->global_sta.wcid;
660*4882a593Smuzhiyun 
661*4882a593Smuzhiyun 	if (control->sta) {
662*4882a593Smuzhiyun 		struct mt7603_sta *msta;
663*4882a593Smuzhiyun 
664*4882a593Smuzhiyun 		msta = (struct mt7603_sta *)control->sta->drv_priv;
665*4882a593Smuzhiyun 		wcid = &msta->wcid;
666*4882a593Smuzhiyun 	} else if (vif) {
667*4882a593Smuzhiyun 		struct mt7603_vif *mvif;
668*4882a593Smuzhiyun 
669*4882a593Smuzhiyun 		mvif = (struct mt7603_vif *)vif->drv_priv;
670*4882a593Smuzhiyun 		wcid = &mvif->sta.wcid;
671*4882a593Smuzhiyun 	}
672*4882a593Smuzhiyun 
673*4882a593Smuzhiyun 	mt76_tx(&dev->mphy, control->sta, wcid, skb);
674*4882a593Smuzhiyun }
675*4882a593Smuzhiyun 
676*4882a593Smuzhiyun const struct ieee80211_ops mt7603_ops = {
677*4882a593Smuzhiyun 	.tx = mt7603_tx,
678*4882a593Smuzhiyun 	.start = mt7603_start,
679*4882a593Smuzhiyun 	.stop = mt7603_stop,
680*4882a593Smuzhiyun 	.add_interface = mt7603_add_interface,
681*4882a593Smuzhiyun 	.remove_interface = mt7603_remove_interface,
682*4882a593Smuzhiyun 	.config = mt7603_config,
683*4882a593Smuzhiyun 	.configure_filter = mt7603_configure_filter,
684*4882a593Smuzhiyun 	.bss_info_changed = mt7603_bss_info_changed,
685*4882a593Smuzhiyun 	.sta_state = mt76_sta_state,
686*4882a593Smuzhiyun 	.sta_pre_rcu_remove = mt76_sta_pre_rcu_remove,
687*4882a593Smuzhiyun 	.set_key = mt7603_set_key,
688*4882a593Smuzhiyun 	.conf_tx = mt7603_conf_tx,
689*4882a593Smuzhiyun 	.sw_scan_start = mt76_sw_scan,
690*4882a593Smuzhiyun 	.sw_scan_complete = mt76_sw_scan_complete,
691*4882a593Smuzhiyun 	.flush = mt7603_flush,
692*4882a593Smuzhiyun 	.ampdu_action = mt7603_ampdu_action,
693*4882a593Smuzhiyun 	.get_txpower = mt76_get_txpower,
694*4882a593Smuzhiyun 	.wake_tx_queue = mt76_wake_tx_queue,
695*4882a593Smuzhiyun 	.sta_rate_tbl_update = mt7603_sta_rate_tbl_update,
696*4882a593Smuzhiyun 	.release_buffered_frames = mt7603_release_buffered_frames,
697*4882a593Smuzhiyun 	.set_coverage_class = mt7603_set_coverage_class,
698*4882a593Smuzhiyun 	.set_tim = mt76_set_tim,
699*4882a593Smuzhiyun 	.get_survey = mt76_get_survey,
700*4882a593Smuzhiyun 	.get_antenna = mt76_get_antenna,
701*4882a593Smuzhiyun };
702*4882a593Smuzhiyun 
703*4882a593Smuzhiyun MODULE_LICENSE("Dual BSD/GPL");
704*4882a593Smuzhiyun 
mt7603_init(void)705*4882a593Smuzhiyun static int __init mt7603_init(void)
706*4882a593Smuzhiyun {
707*4882a593Smuzhiyun 	int ret;
708*4882a593Smuzhiyun 
709*4882a593Smuzhiyun 	ret = platform_driver_register(&mt76_wmac_driver);
710*4882a593Smuzhiyun 	if (ret)
711*4882a593Smuzhiyun 		return ret;
712*4882a593Smuzhiyun 
713*4882a593Smuzhiyun #ifdef CONFIG_PCI
714*4882a593Smuzhiyun 	ret = pci_register_driver(&mt7603_pci_driver);
715*4882a593Smuzhiyun 	if (ret)
716*4882a593Smuzhiyun 		platform_driver_unregister(&mt76_wmac_driver);
717*4882a593Smuzhiyun #endif
718*4882a593Smuzhiyun 	return ret;
719*4882a593Smuzhiyun }
720*4882a593Smuzhiyun 
mt7603_exit(void)721*4882a593Smuzhiyun static void __exit mt7603_exit(void)
722*4882a593Smuzhiyun {
723*4882a593Smuzhiyun #ifdef CONFIG_PCI
724*4882a593Smuzhiyun 	pci_unregister_driver(&mt7603_pci_driver);
725*4882a593Smuzhiyun #endif
726*4882a593Smuzhiyun 	platform_driver_unregister(&mt76_wmac_driver);
727*4882a593Smuzhiyun }
728*4882a593Smuzhiyun 
729*4882a593Smuzhiyun module_init(mt7603_init);
730*4882a593Smuzhiyun module_exit(mt7603_exit);
731