1*4882a593Smuzhiyun /* SPDX-License-Identifier: ISC */ 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun #ifndef __MT7603_EEPROM_H 4*4882a593Smuzhiyun #define __MT7603_EEPROM_H 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #include "mt7603.h" 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun enum mt7603_eeprom_field { 9*4882a593Smuzhiyun MT_EE_CHIP_ID = 0x000, 10*4882a593Smuzhiyun MT_EE_VERSION = 0x002, 11*4882a593Smuzhiyun MT_EE_MAC_ADDR = 0x004, 12*4882a593Smuzhiyun MT_EE_NIC_CONF_0 = 0x034, 13*4882a593Smuzhiyun MT_EE_NIC_CONF_1 = 0x036, 14*4882a593Smuzhiyun MT_EE_NIC_CONF_2 = 0x042, 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun MT_EE_XTAL_TRIM_1 = 0x03a, 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun MT_EE_RSSI_OFFSET_2G = 0x046, 19*4882a593Smuzhiyun MT_EE_WIFI_RF_SETTING = 0x048, 20*4882a593Smuzhiyun MT_EE_RSSI_OFFSET_5G = 0x04a, 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun MT_EE_TX_POWER_DELTA_BW40 = 0x050, 23*4882a593Smuzhiyun MT_EE_TX_POWER_DELTA_BW80 = 0x052, 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun MT_EE_TX_POWER_EXT_PA_5G = 0x054, 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun MT_EE_TEMP_SENSOR_CAL = 0x055, 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun MT_EE_TX_POWER_0_START_2G = 0x056, 30*4882a593Smuzhiyun MT_EE_TX_POWER_1_START_2G = 0x05c, 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* used as byte arrays */ 33*4882a593Smuzhiyun #define MT_TX_POWER_GROUP_SIZE_5G 5 34*4882a593Smuzhiyun #define MT_TX_POWER_GROUPS_5G 6 35*4882a593Smuzhiyun MT_EE_TX_POWER_0_START_5G = 0x062, 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun MT_EE_TX_POWER_0_GRP3_TX_POWER_DELTA = 0x074, 38*4882a593Smuzhiyun MT_EE_TX_POWER_0_GRP4_TSSI_SLOPE = 0x076, 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun MT_EE_TX_POWER_1_START_5G = 0x080, 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun MT_EE_TX_POWER_CCK = 0x0a0, 43*4882a593Smuzhiyun MT_EE_TX_POWER_OFDM_2G_6M = 0x0a2, 44*4882a593Smuzhiyun MT_EE_TX_POWER_OFDM_2G_24M = 0x0a4, 45*4882a593Smuzhiyun MT_EE_TX_POWER_OFDM_2G_54M = 0x0a6, 46*4882a593Smuzhiyun MT_EE_TX_POWER_HT_BPSK_QPSK = 0x0a8, 47*4882a593Smuzhiyun MT_EE_TX_POWER_HT_16_64_QAM = 0x0aa, 48*4882a593Smuzhiyun MT_EE_TX_POWER_HT_64_QAM = 0x0ac, 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun MT_EE_ELAN_RX_MODE_GAIN = 0x0c0, 51*4882a593Smuzhiyun MT_EE_ELAN_RX_MODE_NF = 0x0c1, 52*4882a593Smuzhiyun MT_EE_ELAN_RX_MODE_P1DB = 0x0c2, 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun MT_EE_ELAN_BYPASS_MODE_GAIN = 0x0c3, 55*4882a593Smuzhiyun MT_EE_ELAN_BYPASS_MODE_NF = 0x0c4, 56*4882a593Smuzhiyun MT_EE_ELAN_BYPASS_MODE_P1DB = 0x0c5, 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun MT_EE_STEP_NUM_NEG_6_7 = 0x0c6, 59*4882a593Smuzhiyun MT_EE_STEP_NUM_NEG_4_5 = 0x0c8, 60*4882a593Smuzhiyun MT_EE_STEP_NUM_NEG_2_3 = 0x0ca, 61*4882a593Smuzhiyun MT_EE_STEP_NUM_NEG_0_1 = 0x0cc, 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun MT_EE_REF_STEP_24G = 0x0ce, 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun MT_EE_STEP_NUM_PLUS_1_2 = 0x0d0, 66*4882a593Smuzhiyun MT_EE_STEP_NUM_PLUS_3_4 = 0x0d2, 67*4882a593Smuzhiyun MT_EE_STEP_NUM_PLUS_5_6 = 0x0d4, 68*4882a593Smuzhiyun MT_EE_STEP_NUM_PLUS_7 = 0x0d6, 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun MT_EE_CP_FT_VERSION = 0x0f0, 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun MT_EE_TX_POWER_TSSI_OFF = 0x0f2, 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun MT_EE_XTAL_FREQ_OFFSET = 0x0f4, 75*4882a593Smuzhiyun MT_EE_XTAL_TRIM_2_COMP = 0x0f5, 76*4882a593Smuzhiyun MT_EE_XTAL_TRIM_3_COMP = 0x0f6, 77*4882a593Smuzhiyun MT_EE_XTAL_WF_RFCAL = 0x0f7, 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun __MT_EE_MAX 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun enum mt7603_eeprom_source { 83*4882a593Smuzhiyun MT_EE_SRC_PROM, 84*4882a593Smuzhiyun MT_EE_SRC_EFUSE, 85*4882a593Smuzhiyun MT_EE_SRC_FLASH, 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #define MT_EE_NIC_CONF_0_RX_PATH GENMASK(3, 0) 89*4882a593Smuzhiyun #define MT_EE_NIC_CONF_0_TX_PATH GENMASK(7, 4) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #endif 92