1*4882a593Smuzhiyun // SPDX-License-Identifier: ISC
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include "mt76.h"
7*4882a593Smuzhiyun #include "trace.h"
8*4882a593Smuzhiyun
mt76_mmio_rr(struct mt76_dev * dev,u32 offset)9*4882a593Smuzhiyun static u32 mt76_mmio_rr(struct mt76_dev *dev, u32 offset)
10*4882a593Smuzhiyun {
11*4882a593Smuzhiyun u32 val;
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun val = readl(dev->mmio.regs + offset);
14*4882a593Smuzhiyun trace_reg_rr(dev, offset, val);
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun return val;
17*4882a593Smuzhiyun }
18*4882a593Smuzhiyun
mt76_mmio_wr(struct mt76_dev * dev,u32 offset,u32 val)19*4882a593Smuzhiyun static void mt76_mmio_wr(struct mt76_dev *dev, u32 offset, u32 val)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun trace_reg_wr(dev, offset, val);
22*4882a593Smuzhiyun writel(val, dev->mmio.regs + offset);
23*4882a593Smuzhiyun }
24*4882a593Smuzhiyun
mt76_mmio_rmw(struct mt76_dev * dev,u32 offset,u32 mask,u32 val)25*4882a593Smuzhiyun static u32 mt76_mmio_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun val |= mt76_mmio_rr(dev, offset) & ~mask;
28*4882a593Smuzhiyun mt76_mmio_wr(dev, offset, val);
29*4882a593Smuzhiyun return val;
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun
mt76_mmio_write_copy(struct mt76_dev * dev,u32 offset,const void * data,int len)32*4882a593Smuzhiyun static void mt76_mmio_write_copy(struct mt76_dev *dev, u32 offset,
33*4882a593Smuzhiyun const void *data, int len)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun __iowrite32_copy(dev->mmio.regs + offset, data, DIV_ROUND_UP(len, 4));
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
mt76_mmio_read_copy(struct mt76_dev * dev,u32 offset,void * data,int len)38*4882a593Smuzhiyun static void mt76_mmio_read_copy(struct mt76_dev *dev, u32 offset,
39*4882a593Smuzhiyun void *data, int len)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun __ioread32_copy(data, dev->mmio.regs + offset, DIV_ROUND_UP(len, 4));
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
mt76_mmio_wr_rp(struct mt76_dev * dev,u32 base,const struct mt76_reg_pair * data,int len)44*4882a593Smuzhiyun static int mt76_mmio_wr_rp(struct mt76_dev *dev, u32 base,
45*4882a593Smuzhiyun const struct mt76_reg_pair *data, int len)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun while (len > 0) {
48*4882a593Smuzhiyun mt76_mmio_wr(dev, data->reg, data->value);
49*4882a593Smuzhiyun data++;
50*4882a593Smuzhiyun len--;
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun return 0;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
mt76_mmio_rd_rp(struct mt76_dev * dev,u32 base,struct mt76_reg_pair * data,int len)56*4882a593Smuzhiyun static int mt76_mmio_rd_rp(struct mt76_dev *dev, u32 base,
57*4882a593Smuzhiyun struct mt76_reg_pair *data, int len)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun while (len > 0) {
60*4882a593Smuzhiyun data->value = mt76_mmio_rr(dev, data->reg);
61*4882a593Smuzhiyun data++;
62*4882a593Smuzhiyun len--;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun return 0;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
mt76_set_irq_mask(struct mt76_dev * dev,u32 addr,u32 clear,u32 set)68*4882a593Smuzhiyun void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr,
69*4882a593Smuzhiyun u32 clear, u32 set)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun unsigned long flags;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun spin_lock_irqsave(&dev->mmio.irq_lock, flags);
74*4882a593Smuzhiyun dev->mmio.irqmask &= ~clear;
75*4882a593Smuzhiyun dev->mmio.irqmask |= set;
76*4882a593Smuzhiyun if (addr)
77*4882a593Smuzhiyun mt76_mmio_wr(dev, addr, dev->mmio.irqmask);
78*4882a593Smuzhiyun spin_unlock_irqrestore(&dev->mmio.irq_lock, flags);
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76_set_irq_mask);
81*4882a593Smuzhiyun
mt76_mmio_init(struct mt76_dev * dev,void __iomem * regs)82*4882a593Smuzhiyun void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun static const struct mt76_bus_ops mt76_mmio_ops = {
85*4882a593Smuzhiyun .rr = mt76_mmio_rr,
86*4882a593Smuzhiyun .rmw = mt76_mmio_rmw,
87*4882a593Smuzhiyun .wr = mt76_mmio_wr,
88*4882a593Smuzhiyun .write_copy = mt76_mmio_write_copy,
89*4882a593Smuzhiyun .read_copy = mt76_mmio_read_copy,
90*4882a593Smuzhiyun .wr_rp = mt76_mmio_wr_rp,
91*4882a593Smuzhiyun .rd_rp = mt76_mmio_rd_rp,
92*4882a593Smuzhiyun .type = MT76_BUS_MMIO,
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun dev->bus = &mt76_mmio_ops;
96*4882a593Smuzhiyun dev->mmio.regs = regs;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun spin_lock_init(&dev->mmio.irq_lock);
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mt76_mmio_init);
101