1*4882a593Smuzhiyun /* SPDX-License-Identifier: ISC */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef __MT76_DMA_H 6*4882a593Smuzhiyun #define __MT76_DMA_H 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define DMA_DUMMY_DATA ((void *)~0) 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define MT_RING_SIZE 0x10 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define MT_DMA_CTL_SD_LEN1 GENMASK(13, 0) 13*4882a593Smuzhiyun #define MT_DMA_CTL_LAST_SEC1 BIT(14) 14*4882a593Smuzhiyun #define MT_DMA_CTL_BURST BIT(15) 15*4882a593Smuzhiyun #define MT_DMA_CTL_SD_LEN0 GENMASK(29, 16) 16*4882a593Smuzhiyun #define MT_DMA_CTL_LAST_SEC0 BIT(30) 17*4882a593Smuzhiyun #define MT_DMA_CTL_DMA_DONE BIT(31) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define MT_DMA_HDR_LEN 4 20*4882a593Smuzhiyun #define MT_RX_INFO_LEN 4 21*4882a593Smuzhiyun #define MT_FCE_INFO_LEN 4 22*4882a593Smuzhiyun #define MT_RX_RXWI_LEN 32 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun struct mt76_desc { 25*4882a593Smuzhiyun __le32 buf0; 26*4882a593Smuzhiyun __le32 ctrl; 27*4882a593Smuzhiyun __le32 buf1; 28*4882a593Smuzhiyun __le32 info; 29*4882a593Smuzhiyun } __packed __aligned(4); 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun enum mt76_qsel { 32*4882a593Smuzhiyun MT_QSEL_MGMT, 33*4882a593Smuzhiyun MT_QSEL_HCCA, 34*4882a593Smuzhiyun MT_QSEL_EDCA, 35*4882a593Smuzhiyun MT_QSEL_EDCA_2, 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun enum mt76_mcu_evt_type { 39*4882a593Smuzhiyun EVT_CMD_DONE, 40*4882a593Smuzhiyun EVT_CMD_ERROR, 41*4882a593Smuzhiyun EVT_CMD_RETRY, 42*4882a593Smuzhiyun EVT_EVENT_PWR_RSP, 43*4882a593Smuzhiyun EVT_EVENT_WOW_RSP, 44*4882a593Smuzhiyun EVT_EVENT_CARRIER_DETECT_RSP, 45*4882a593Smuzhiyun EVT_EVENT_DFS_DETECT_RSP, 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun void mt76_dma_attach(struct mt76_dev *dev); 49*4882a593Smuzhiyun void mt76_dma_cleanup(struct mt76_dev *dev); 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #endif 52