1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * drivers/net/wireless/mwl8k.c
3*4882a593Smuzhiyun * Driver for Marvell TOPDOG 802.11 Wireless cards
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2008, 2009, 2010 Marvell Semiconductor Inc.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public
8*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any
9*4882a593Smuzhiyun * warranty of any kind, whether express or implied.
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/interrupt.h>
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/kernel.h>
15*4882a593Smuzhiyun #include <linux/sched.h>
16*4882a593Smuzhiyun #include <linux/spinlock.h>
17*4882a593Smuzhiyun #include <linux/list.h>
18*4882a593Smuzhiyun #include <linux/pci.h>
19*4882a593Smuzhiyun #include <linux/delay.h>
20*4882a593Smuzhiyun #include <linux/completion.h>
21*4882a593Smuzhiyun #include <linux/etherdevice.h>
22*4882a593Smuzhiyun #include <linux/slab.h>
23*4882a593Smuzhiyun #include <net/mac80211.h>
24*4882a593Smuzhiyun #include <linux/moduleparam.h>
25*4882a593Smuzhiyun #include <linux/firmware.h>
26*4882a593Smuzhiyun #include <linux/workqueue.h>
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
29*4882a593Smuzhiyun #define MWL8K_NAME KBUILD_MODNAME
30*4882a593Smuzhiyun #define MWL8K_VERSION "0.13"
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /* Module parameters */
33*4882a593Smuzhiyun static bool ap_mode_default;
34*4882a593Smuzhiyun module_param(ap_mode_default, bool, 0);
35*4882a593Smuzhiyun MODULE_PARM_DESC(ap_mode_default,
36*4882a593Smuzhiyun "Set to 1 to make ap mode the default instead of sta mode");
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /* Register definitions */
39*4882a593Smuzhiyun #define MWL8K_HIU_GEN_PTR 0x00000c10
40*4882a593Smuzhiyun #define MWL8K_MODE_STA 0x0000005a
41*4882a593Smuzhiyun #define MWL8K_MODE_AP 0x000000a5
42*4882a593Smuzhiyun #define MWL8K_HIU_INT_CODE 0x00000c14
43*4882a593Smuzhiyun #define MWL8K_FWSTA_READY 0xf0f1f2f4
44*4882a593Smuzhiyun #define MWL8K_FWAP_READY 0xf1f2f4a5
45*4882a593Smuzhiyun #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
46*4882a593Smuzhiyun #define MWL8K_HIU_SCRATCH 0x00000c40
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /* Host->device communications */
49*4882a593Smuzhiyun #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
50*4882a593Smuzhiyun #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
51*4882a593Smuzhiyun #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
52*4882a593Smuzhiyun #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
53*4882a593Smuzhiyun #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
54*4882a593Smuzhiyun #define MWL8K_H2A_INT_DUMMY (1 << 20)
55*4882a593Smuzhiyun #define MWL8K_H2A_INT_RESET (1 << 15)
56*4882a593Smuzhiyun #define MWL8K_H2A_INT_DOORBELL (1 << 1)
57*4882a593Smuzhiyun #define MWL8K_H2A_INT_PPA_READY (1 << 0)
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* Device->host communications */
60*4882a593Smuzhiyun #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
61*4882a593Smuzhiyun #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
62*4882a593Smuzhiyun #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
63*4882a593Smuzhiyun #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
64*4882a593Smuzhiyun #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
65*4882a593Smuzhiyun #define MWL8K_A2H_INT_DUMMY (1 << 20)
66*4882a593Smuzhiyun #define MWL8K_A2H_INT_BA_WATCHDOG (1 << 14)
67*4882a593Smuzhiyun #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
68*4882a593Smuzhiyun #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
69*4882a593Smuzhiyun #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
70*4882a593Smuzhiyun #define MWL8K_A2H_INT_RADIO_ON (1 << 6)
71*4882a593Smuzhiyun #define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
72*4882a593Smuzhiyun #define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
73*4882a593Smuzhiyun #define MWL8K_A2H_INT_OPC_DONE (1 << 2)
74*4882a593Smuzhiyun #define MWL8K_A2H_INT_RX_READY (1 << 1)
75*4882a593Smuzhiyun #define MWL8K_A2H_INT_TX_DONE (1 << 0)
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /* HW micro second timer register
78*4882a593Smuzhiyun * located at offset 0xA600. This
79*4882a593Smuzhiyun * will be used to timestamp tx
80*4882a593Smuzhiyun * packets.
81*4882a593Smuzhiyun */
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun #define MWL8K_HW_TIMER_REGISTER 0x0000a600
84*4882a593Smuzhiyun #define BBU_RXRDY_CNT_REG 0x0000a860
85*4882a593Smuzhiyun #define NOK_CCA_CNT_REG 0x0000a6a0
86*4882a593Smuzhiyun #define BBU_AVG_NOISE_VAL 0x67
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
89*4882a593Smuzhiyun MWL8K_A2H_INT_CHNL_SWITCHED | \
90*4882a593Smuzhiyun MWL8K_A2H_INT_QUEUE_EMPTY | \
91*4882a593Smuzhiyun MWL8K_A2H_INT_RADAR_DETECT | \
92*4882a593Smuzhiyun MWL8K_A2H_INT_RADIO_ON | \
93*4882a593Smuzhiyun MWL8K_A2H_INT_RADIO_OFF | \
94*4882a593Smuzhiyun MWL8K_A2H_INT_MAC_EVENT | \
95*4882a593Smuzhiyun MWL8K_A2H_INT_OPC_DONE | \
96*4882a593Smuzhiyun MWL8K_A2H_INT_RX_READY | \
97*4882a593Smuzhiyun MWL8K_A2H_INT_TX_DONE | \
98*4882a593Smuzhiyun MWL8K_A2H_INT_BA_WATCHDOG)
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun #define MWL8K_RX_QUEUES 1
101*4882a593Smuzhiyun #define MWL8K_TX_WMM_QUEUES 4
102*4882a593Smuzhiyun #define MWL8K_MAX_AMPDU_QUEUES 8
103*4882a593Smuzhiyun #define MWL8K_MAX_TX_QUEUES (MWL8K_TX_WMM_QUEUES + MWL8K_MAX_AMPDU_QUEUES)
104*4882a593Smuzhiyun #define mwl8k_tx_queues(priv) (MWL8K_TX_WMM_QUEUES + (priv)->num_ampdu_queues)
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun /* txpriorities are mapped with hw queues.
107*4882a593Smuzhiyun * Each hw queue has a txpriority.
108*4882a593Smuzhiyun */
109*4882a593Smuzhiyun #define TOTAL_HW_TX_QUEUES 8
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /* Each HW queue can have one AMPDU stream.
112*4882a593Smuzhiyun * But, because one of the hw queue is reserved,
113*4882a593Smuzhiyun * maximum AMPDU queues that can be created are
114*4882a593Smuzhiyun * one short of total tx queues.
115*4882a593Smuzhiyun */
116*4882a593Smuzhiyun #define MWL8K_NUM_AMPDU_STREAMS (TOTAL_HW_TX_QUEUES - 1)
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun #define MWL8K_NUM_CHANS 18
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun struct rxd_ops {
121*4882a593Smuzhiyun int rxd_size;
122*4882a593Smuzhiyun void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
123*4882a593Smuzhiyun void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
124*4882a593Smuzhiyun int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
125*4882a593Smuzhiyun __le16 *qos, s8 *noise);
126*4882a593Smuzhiyun };
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun struct mwl8k_device_info {
129*4882a593Smuzhiyun char *part_name;
130*4882a593Smuzhiyun char *helper_image;
131*4882a593Smuzhiyun char *fw_image_sta;
132*4882a593Smuzhiyun char *fw_image_ap;
133*4882a593Smuzhiyun struct rxd_ops *ap_rxd_ops;
134*4882a593Smuzhiyun u32 fw_api_ap;
135*4882a593Smuzhiyun };
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun struct mwl8k_rx_queue {
138*4882a593Smuzhiyun int rxd_count;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun /* hw receives here */
141*4882a593Smuzhiyun int head;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun /* refill descs here */
144*4882a593Smuzhiyun int tail;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun void *rxd;
147*4882a593Smuzhiyun dma_addr_t rxd_dma;
148*4882a593Smuzhiyun struct {
149*4882a593Smuzhiyun struct sk_buff *skb;
150*4882a593Smuzhiyun DEFINE_DMA_UNMAP_ADDR(dma);
151*4882a593Smuzhiyun } *buf;
152*4882a593Smuzhiyun };
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun struct mwl8k_tx_queue {
155*4882a593Smuzhiyun /* hw transmits here */
156*4882a593Smuzhiyun int head;
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun /* sw appends here */
159*4882a593Smuzhiyun int tail;
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun unsigned int len;
162*4882a593Smuzhiyun struct mwl8k_tx_desc *txd;
163*4882a593Smuzhiyun dma_addr_t txd_dma;
164*4882a593Smuzhiyun struct sk_buff **skb;
165*4882a593Smuzhiyun };
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun enum {
168*4882a593Smuzhiyun AMPDU_NO_STREAM,
169*4882a593Smuzhiyun AMPDU_STREAM_NEW,
170*4882a593Smuzhiyun AMPDU_STREAM_IN_PROGRESS,
171*4882a593Smuzhiyun AMPDU_STREAM_ACTIVE,
172*4882a593Smuzhiyun };
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun struct mwl8k_ampdu_stream {
175*4882a593Smuzhiyun struct ieee80211_sta *sta;
176*4882a593Smuzhiyun u8 tid;
177*4882a593Smuzhiyun u8 state;
178*4882a593Smuzhiyun u8 idx;
179*4882a593Smuzhiyun };
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun struct mwl8k_priv {
182*4882a593Smuzhiyun struct ieee80211_hw *hw;
183*4882a593Smuzhiyun struct pci_dev *pdev;
184*4882a593Smuzhiyun int irq;
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun struct mwl8k_device_info *device_info;
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun void __iomem *sram;
189*4882a593Smuzhiyun void __iomem *regs;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun /* firmware */
192*4882a593Smuzhiyun const struct firmware *fw_helper;
193*4882a593Smuzhiyun const struct firmware *fw_ucode;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun /* hardware/firmware parameters */
196*4882a593Smuzhiyun bool ap_fw;
197*4882a593Smuzhiyun struct rxd_ops *rxd_ops;
198*4882a593Smuzhiyun struct ieee80211_supported_band band_24;
199*4882a593Smuzhiyun struct ieee80211_channel channels_24[14];
200*4882a593Smuzhiyun struct ieee80211_rate rates_24[13];
201*4882a593Smuzhiyun struct ieee80211_supported_band band_50;
202*4882a593Smuzhiyun struct ieee80211_channel channels_50[9];
203*4882a593Smuzhiyun struct ieee80211_rate rates_50[8];
204*4882a593Smuzhiyun u32 ap_macids_supported;
205*4882a593Smuzhiyun u32 sta_macids_supported;
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun /* Ampdu stream information */
208*4882a593Smuzhiyun u8 num_ampdu_queues;
209*4882a593Smuzhiyun spinlock_t stream_lock;
210*4882a593Smuzhiyun struct mwl8k_ampdu_stream ampdu[MWL8K_MAX_AMPDU_QUEUES];
211*4882a593Smuzhiyun struct work_struct watchdog_ba_handle;
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun /* firmware access */
214*4882a593Smuzhiyun struct mutex fw_mutex;
215*4882a593Smuzhiyun struct task_struct *fw_mutex_owner;
216*4882a593Smuzhiyun struct task_struct *hw_restart_owner;
217*4882a593Smuzhiyun int fw_mutex_depth;
218*4882a593Smuzhiyun struct completion *hostcmd_wait;
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun atomic_t watchdog_event_pending;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun /* lock held over TX and TX reap */
223*4882a593Smuzhiyun spinlock_t tx_lock;
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun /* TX quiesce completion, protected by fw_mutex and tx_lock */
226*4882a593Smuzhiyun struct completion *tx_wait;
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun /* List of interfaces. */
229*4882a593Smuzhiyun u32 macids_used;
230*4882a593Smuzhiyun struct list_head vif_list;
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun /* power management status cookie from firmware */
233*4882a593Smuzhiyun u32 *cookie;
234*4882a593Smuzhiyun dma_addr_t cookie_dma;
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun u16 num_mcaddrs;
237*4882a593Smuzhiyun u8 hw_rev;
238*4882a593Smuzhiyun u32 fw_rev;
239*4882a593Smuzhiyun u32 caps;
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun /*
242*4882a593Smuzhiyun * Running count of TX packets in flight, to avoid
243*4882a593Smuzhiyun * iterating over the transmit rings each time.
244*4882a593Smuzhiyun */
245*4882a593Smuzhiyun int pending_tx_pkts;
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
248*4882a593Smuzhiyun struct mwl8k_tx_queue txq[MWL8K_MAX_TX_QUEUES];
249*4882a593Smuzhiyun u32 txq_offset[MWL8K_MAX_TX_QUEUES];
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun bool radio_on;
252*4882a593Smuzhiyun bool radio_short_preamble;
253*4882a593Smuzhiyun bool sniffer_enabled;
254*4882a593Smuzhiyun bool wmm_enabled;
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun /* XXX need to convert this to handle multiple interfaces */
257*4882a593Smuzhiyun bool capture_beacon;
258*4882a593Smuzhiyun u8 capture_bssid[ETH_ALEN];
259*4882a593Smuzhiyun struct sk_buff *beacon_skb;
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun /*
262*4882a593Smuzhiyun * This FJ worker has to be global as it is scheduled from the
263*4882a593Smuzhiyun * RX handler. At this point we don't know which interface it
264*4882a593Smuzhiyun * belongs to until the list of bssids waiting to complete join
265*4882a593Smuzhiyun * is checked.
266*4882a593Smuzhiyun */
267*4882a593Smuzhiyun struct work_struct finalize_join_worker;
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun /* Tasklet to perform TX reclaim. */
270*4882a593Smuzhiyun struct tasklet_struct poll_tx_task;
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun /* Tasklet to perform RX. */
273*4882a593Smuzhiyun struct tasklet_struct poll_rx_task;
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun /* Most recently reported noise in dBm */
276*4882a593Smuzhiyun s8 noise;
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun /*
279*4882a593Smuzhiyun * preserve the queue configurations so they can be restored if/when
280*4882a593Smuzhiyun * the firmware image is swapped.
281*4882a593Smuzhiyun */
282*4882a593Smuzhiyun struct ieee80211_tx_queue_params wmm_params[MWL8K_TX_WMM_QUEUES];
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun /* To perform the task of reloading the firmware */
285*4882a593Smuzhiyun struct work_struct fw_reload;
286*4882a593Smuzhiyun bool hw_restart_in_progress;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun /* async firmware loading state */
289*4882a593Smuzhiyun unsigned fw_state;
290*4882a593Smuzhiyun char *fw_pref;
291*4882a593Smuzhiyun char *fw_alt;
292*4882a593Smuzhiyun bool is_8764;
293*4882a593Smuzhiyun struct completion firmware_loading_complete;
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun /* bitmap of running BSSes */
296*4882a593Smuzhiyun u32 running_bsses;
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun /* ACS related */
299*4882a593Smuzhiyun bool sw_scan_start;
300*4882a593Smuzhiyun struct ieee80211_channel *acs_chan;
301*4882a593Smuzhiyun unsigned long channel_time;
302*4882a593Smuzhiyun struct survey_info survey[MWL8K_NUM_CHANS];
303*4882a593Smuzhiyun };
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun #define MAX_WEP_KEY_LEN 13
306*4882a593Smuzhiyun #define NUM_WEP_KEYS 4
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun /* Per interface specific private data */
309*4882a593Smuzhiyun struct mwl8k_vif {
310*4882a593Smuzhiyun struct list_head list;
311*4882a593Smuzhiyun struct ieee80211_vif *vif;
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun /* Firmware macid for this vif. */
314*4882a593Smuzhiyun int macid;
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun /* Non AMPDU sequence number assigned by driver. */
317*4882a593Smuzhiyun u16 seqno;
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun /* Saved WEP keys */
320*4882a593Smuzhiyun struct {
321*4882a593Smuzhiyun u8 enabled;
322*4882a593Smuzhiyun u8 key[sizeof(struct ieee80211_key_conf) + MAX_WEP_KEY_LEN];
323*4882a593Smuzhiyun } wep_key_conf[NUM_WEP_KEYS];
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun /* BSSID */
326*4882a593Smuzhiyun u8 bssid[ETH_ALEN];
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun /* A flag to indicate is HW crypto is enabled for this bssid */
329*4882a593Smuzhiyun bool is_hw_crypto_enabled;
330*4882a593Smuzhiyun };
331*4882a593Smuzhiyun #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
332*4882a593Smuzhiyun #define IEEE80211_KEY_CONF(_u8) ((struct ieee80211_key_conf *)(_u8))
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun struct tx_traffic_info {
335*4882a593Smuzhiyun u32 start_time;
336*4882a593Smuzhiyun u32 pkts;
337*4882a593Smuzhiyun };
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun #define MWL8K_MAX_TID 8
340*4882a593Smuzhiyun struct mwl8k_sta {
341*4882a593Smuzhiyun /* Index into station database. Returned by UPDATE_STADB. */
342*4882a593Smuzhiyun u8 peer_id;
343*4882a593Smuzhiyun u8 is_ampdu_allowed;
344*4882a593Smuzhiyun struct tx_traffic_info tx_stats[MWL8K_MAX_TID];
345*4882a593Smuzhiyun };
346*4882a593Smuzhiyun #define MWL8K_STA(_sta) ((struct mwl8k_sta *)&((_sta)->drv_priv))
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun static const struct ieee80211_channel mwl8k_channels_24[] = {
349*4882a593Smuzhiyun { .band = NL80211_BAND_2GHZ, .center_freq = 2412, .hw_value = 1, },
350*4882a593Smuzhiyun { .band = NL80211_BAND_2GHZ, .center_freq = 2417, .hw_value = 2, },
351*4882a593Smuzhiyun { .band = NL80211_BAND_2GHZ, .center_freq = 2422, .hw_value = 3, },
352*4882a593Smuzhiyun { .band = NL80211_BAND_2GHZ, .center_freq = 2427, .hw_value = 4, },
353*4882a593Smuzhiyun { .band = NL80211_BAND_2GHZ, .center_freq = 2432, .hw_value = 5, },
354*4882a593Smuzhiyun { .band = NL80211_BAND_2GHZ, .center_freq = 2437, .hw_value = 6, },
355*4882a593Smuzhiyun { .band = NL80211_BAND_2GHZ, .center_freq = 2442, .hw_value = 7, },
356*4882a593Smuzhiyun { .band = NL80211_BAND_2GHZ, .center_freq = 2447, .hw_value = 8, },
357*4882a593Smuzhiyun { .band = NL80211_BAND_2GHZ, .center_freq = 2452, .hw_value = 9, },
358*4882a593Smuzhiyun { .band = NL80211_BAND_2GHZ, .center_freq = 2457, .hw_value = 10, },
359*4882a593Smuzhiyun { .band = NL80211_BAND_2GHZ, .center_freq = 2462, .hw_value = 11, },
360*4882a593Smuzhiyun { .band = NL80211_BAND_2GHZ, .center_freq = 2467, .hw_value = 12, },
361*4882a593Smuzhiyun { .band = NL80211_BAND_2GHZ, .center_freq = 2472, .hw_value = 13, },
362*4882a593Smuzhiyun { .band = NL80211_BAND_2GHZ, .center_freq = 2484, .hw_value = 14, },
363*4882a593Smuzhiyun };
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun static const struct ieee80211_rate mwl8k_rates_24[] = {
366*4882a593Smuzhiyun { .bitrate = 10, .hw_value = 2, },
367*4882a593Smuzhiyun { .bitrate = 20, .hw_value = 4, },
368*4882a593Smuzhiyun { .bitrate = 55, .hw_value = 11, },
369*4882a593Smuzhiyun { .bitrate = 110, .hw_value = 22, },
370*4882a593Smuzhiyun { .bitrate = 220, .hw_value = 44, },
371*4882a593Smuzhiyun { .bitrate = 60, .hw_value = 12, },
372*4882a593Smuzhiyun { .bitrate = 90, .hw_value = 18, },
373*4882a593Smuzhiyun { .bitrate = 120, .hw_value = 24, },
374*4882a593Smuzhiyun { .bitrate = 180, .hw_value = 36, },
375*4882a593Smuzhiyun { .bitrate = 240, .hw_value = 48, },
376*4882a593Smuzhiyun { .bitrate = 360, .hw_value = 72, },
377*4882a593Smuzhiyun { .bitrate = 480, .hw_value = 96, },
378*4882a593Smuzhiyun { .bitrate = 540, .hw_value = 108, },
379*4882a593Smuzhiyun };
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun static const struct ieee80211_channel mwl8k_channels_50[] = {
382*4882a593Smuzhiyun { .band = NL80211_BAND_5GHZ, .center_freq = 5180, .hw_value = 36, },
383*4882a593Smuzhiyun { .band = NL80211_BAND_5GHZ, .center_freq = 5200, .hw_value = 40, },
384*4882a593Smuzhiyun { .band = NL80211_BAND_5GHZ, .center_freq = 5220, .hw_value = 44, },
385*4882a593Smuzhiyun { .band = NL80211_BAND_5GHZ, .center_freq = 5240, .hw_value = 48, },
386*4882a593Smuzhiyun { .band = NL80211_BAND_5GHZ, .center_freq = 5745, .hw_value = 149, },
387*4882a593Smuzhiyun { .band = NL80211_BAND_5GHZ, .center_freq = 5765, .hw_value = 153, },
388*4882a593Smuzhiyun { .band = NL80211_BAND_5GHZ, .center_freq = 5785, .hw_value = 157, },
389*4882a593Smuzhiyun { .band = NL80211_BAND_5GHZ, .center_freq = 5805, .hw_value = 161, },
390*4882a593Smuzhiyun { .band = NL80211_BAND_5GHZ, .center_freq = 5825, .hw_value = 165, },
391*4882a593Smuzhiyun };
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun static const struct ieee80211_rate mwl8k_rates_50[] = {
394*4882a593Smuzhiyun { .bitrate = 60, .hw_value = 12, },
395*4882a593Smuzhiyun { .bitrate = 90, .hw_value = 18, },
396*4882a593Smuzhiyun { .bitrate = 120, .hw_value = 24, },
397*4882a593Smuzhiyun { .bitrate = 180, .hw_value = 36, },
398*4882a593Smuzhiyun { .bitrate = 240, .hw_value = 48, },
399*4882a593Smuzhiyun { .bitrate = 360, .hw_value = 72, },
400*4882a593Smuzhiyun { .bitrate = 480, .hw_value = 96, },
401*4882a593Smuzhiyun { .bitrate = 540, .hw_value = 108, },
402*4882a593Smuzhiyun };
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun /* Set or get info from Firmware */
405*4882a593Smuzhiyun #define MWL8K_CMD_GET 0x0000
406*4882a593Smuzhiyun #define MWL8K_CMD_SET 0x0001
407*4882a593Smuzhiyun #define MWL8K_CMD_SET_LIST 0x0002
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun /* Firmware command codes */
410*4882a593Smuzhiyun #define MWL8K_CMD_CODE_DNLD 0x0001
411*4882a593Smuzhiyun #define MWL8K_CMD_GET_HW_SPEC 0x0003
412*4882a593Smuzhiyun #define MWL8K_CMD_SET_HW_SPEC 0x0004
413*4882a593Smuzhiyun #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
414*4882a593Smuzhiyun #define MWL8K_CMD_GET_STAT 0x0014
415*4882a593Smuzhiyun #define MWL8K_CMD_BBP_REG_ACCESS 0x001a
416*4882a593Smuzhiyun #define MWL8K_CMD_RADIO_CONTROL 0x001c
417*4882a593Smuzhiyun #define MWL8K_CMD_RF_TX_POWER 0x001e
418*4882a593Smuzhiyun #define MWL8K_CMD_TX_POWER 0x001f
419*4882a593Smuzhiyun #define MWL8K_CMD_RF_ANTENNA 0x0020
420*4882a593Smuzhiyun #define MWL8K_CMD_SET_BEACON 0x0100 /* per-vif */
421*4882a593Smuzhiyun #define MWL8K_CMD_SET_PRE_SCAN 0x0107
422*4882a593Smuzhiyun #define MWL8K_CMD_SET_POST_SCAN 0x0108
423*4882a593Smuzhiyun #define MWL8K_CMD_SET_RF_CHANNEL 0x010a
424*4882a593Smuzhiyun #define MWL8K_CMD_SET_AID 0x010d
425*4882a593Smuzhiyun #define MWL8K_CMD_SET_RATE 0x0110
426*4882a593Smuzhiyun #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
427*4882a593Smuzhiyun #define MWL8K_CMD_RTS_THRESHOLD 0x0113
428*4882a593Smuzhiyun #define MWL8K_CMD_SET_SLOT 0x0114
429*4882a593Smuzhiyun #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
430*4882a593Smuzhiyun #define MWL8K_CMD_SET_WMM_MODE 0x0123
431*4882a593Smuzhiyun #define MWL8K_CMD_MIMO_CONFIG 0x0125
432*4882a593Smuzhiyun #define MWL8K_CMD_USE_FIXED_RATE 0x0126
433*4882a593Smuzhiyun #define MWL8K_CMD_ENABLE_SNIFFER 0x0150
434*4882a593Smuzhiyun #define MWL8K_CMD_SET_MAC_ADDR 0x0202 /* per-vif */
435*4882a593Smuzhiyun #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
436*4882a593Smuzhiyun #define MWL8K_CMD_GET_WATCHDOG_BITMAP 0x0205
437*4882a593Smuzhiyun #define MWL8K_CMD_DEL_MAC_ADDR 0x0206 /* per-vif */
438*4882a593Smuzhiyun #define MWL8K_CMD_BSS_START 0x1100 /* per-vif */
439*4882a593Smuzhiyun #define MWL8K_CMD_SET_NEW_STN 0x1111 /* per-vif */
440*4882a593Smuzhiyun #define MWL8K_CMD_UPDATE_ENCRYPTION 0x1122 /* per-vif */
441*4882a593Smuzhiyun #define MWL8K_CMD_UPDATE_STADB 0x1123
442*4882a593Smuzhiyun #define MWL8K_CMD_BASTREAM 0x1125
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun #define MWL8K_LEGACY_5G_RATE_OFFSET \
445*4882a593Smuzhiyun (ARRAY_SIZE(mwl8k_rates_24) - ARRAY_SIZE(mwl8k_rates_50))
446*4882a593Smuzhiyun
mwl8k_cmd_name(__le16 cmd,char * buf,int bufsize)447*4882a593Smuzhiyun static const char *mwl8k_cmd_name(__le16 cmd, char *buf, int bufsize)
448*4882a593Smuzhiyun {
449*4882a593Smuzhiyun u16 command = le16_to_cpu(cmd);
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
452*4882a593Smuzhiyun snprintf(buf, bufsize, "%s", #x);\
453*4882a593Smuzhiyun return buf;\
454*4882a593Smuzhiyun } while (0)
455*4882a593Smuzhiyun switch (command & ~0x8000) {
456*4882a593Smuzhiyun MWL8K_CMDNAME(CODE_DNLD);
457*4882a593Smuzhiyun MWL8K_CMDNAME(GET_HW_SPEC);
458*4882a593Smuzhiyun MWL8K_CMDNAME(SET_HW_SPEC);
459*4882a593Smuzhiyun MWL8K_CMDNAME(MAC_MULTICAST_ADR);
460*4882a593Smuzhiyun MWL8K_CMDNAME(GET_STAT);
461*4882a593Smuzhiyun MWL8K_CMDNAME(RADIO_CONTROL);
462*4882a593Smuzhiyun MWL8K_CMDNAME(RF_TX_POWER);
463*4882a593Smuzhiyun MWL8K_CMDNAME(TX_POWER);
464*4882a593Smuzhiyun MWL8K_CMDNAME(RF_ANTENNA);
465*4882a593Smuzhiyun MWL8K_CMDNAME(SET_BEACON);
466*4882a593Smuzhiyun MWL8K_CMDNAME(SET_PRE_SCAN);
467*4882a593Smuzhiyun MWL8K_CMDNAME(SET_POST_SCAN);
468*4882a593Smuzhiyun MWL8K_CMDNAME(SET_RF_CHANNEL);
469*4882a593Smuzhiyun MWL8K_CMDNAME(SET_AID);
470*4882a593Smuzhiyun MWL8K_CMDNAME(SET_RATE);
471*4882a593Smuzhiyun MWL8K_CMDNAME(SET_FINALIZE_JOIN);
472*4882a593Smuzhiyun MWL8K_CMDNAME(RTS_THRESHOLD);
473*4882a593Smuzhiyun MWL8K_CMDNAME(SET_SLOT);
474*4882a593Smuzhiyun MWL8K_CMDNAME(SET_EDCA_PARAMS);
475*4882a593Smuzhiyun MWL8K_CMDNAME(SET_WMM_MODE);
476*4882a593Smuzhiyun MWL8K_CMDNAME(MIMO_CONFIG);
477*4882a593Smuzhiyun MWL8K_CMDNAME(USE_FIXED_RATE);
478*4882a593Smuzhiyun MWL8K_CMDNAME(ENABLE_SNIFFER);
479*4882a593Smuzhiyun MWL8K_CMDNAME(SET_MAC_ADDR);
480*4882a593Smuzhiyun MWL8K_CMDNAME(SET_RATEADAPT_MODE);
481*4882a593Smuzhiyun MWL8K_CMDNAME(BSS_START);
482*4882a593Smuzhiyun MWL8K_CMDNAME(SET_NEW_STN);
483*4882a593Smuzhiyun MWL8K_CMDNAME(UPDATE_ENCRYPTION);
484*4882a593Smuzhiyun MWL8K_CMDNAME(UPDATE_STADB);
485*4882a593Smuzhiyun MWL8K_CMDNAME(BASTREAM);
486*4882a593Smuzhiyun MWL8K_CMDNAME(GET_WATCHDOG_BITMAP);
487*4882a593Smuzhiyun default:
488*4882a593Smuzhiyun snprintf(buf, bufsize, "0x%x", cmd);
489*4882a593Smuzhiyun }
490*4882a593Smuzhiyun #undef MWL8K_CMDNAME
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun return buf;
493*4882a593Smuzhiyun }
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun /* Hardware and firmware reset */
mwl8k_hw_reset(struct mwl8k_priv * priv)496*4882a593Smuzhiyun static void mwl8k_hw_reset(struct mwl8k_priv *priv)
497*4882a593Smuzhiyun {
498*4882a593Smuzhiyun iowrite32(MWL8K_H2A_INT_RESET,
499*4882a593Smuzhiyun priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
500*4882a593Smuzhiyun iowrite32(MWL8K_H2A_INT_RESET,
501*4882a593Smuzhiyun priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
502*4882a593Smuzhiyun msleep(20);
503*4882a593Smuzhiyun }
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun /* Release fw image */
mwl8k_release_fw(const struct firmware ** fw)506*4882a593Smuzhiyun static void mwl8k_release_fw(const struct firmware **fw)
507*4882a593Smuzhiyun {
508*4882a593Smuzhiyun if (*fw == NULL)
509*4882a593Smuzhiyun return;
510*4882a593Smuzhiyun release_firmware(*fw);
511*4882a593Smuzhiyun *fw = NULL;
512*4882a593Smuzhiyun }
513*4882a593Smuzhiyun
mwl8k_release_firmware(struct mwl8k_priv * priv)514*4882a593Smuzhiyun static void mwl8k_release_firmware(struct mwl8k_priv *priv)
515*4882a593Smuzhiyun {
516*4882a593Smuzhiyun mwl8k_release_fw(&priv->fw_ucode);
517*4882a593Smuzhiyun mwl8k_release_fw(&priv->fw_helper);
518*4882a593Smuzhiyun }
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun /* states for asynchronous f/w loading */
521*4882a593Smuzhiyun static void mwl8k_fw_state_machine(const struct firmware *fw, void *context);
522*4882a593Smuzhiyun enum {
523*4882a593Smuzhiyun FW_STATE_INIT = 0,
524*4882a593Smuzhiyun FW_STATE_LOADING_PREF,
525*4882a593Smuzhiyun FW_STATE_LOADING_ALT,
526*4882a593Smuzhiyun FW_STATE_ERROR,
527*4882a593Smuzhiyun };
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun /* Request fw image */
mwl8k_request_fw(struct mwl8k_priv * priv,const char * fname,const struct firmware ** fw,bool nowait)530*4882a593Smuzhiyun static int mwl8k_request_fw(struct mwl8k_priv *priv,
531*4882a593Smuzhiyun const char *fname, const struct firmware **fw,
532*4882a593Smuzhiyun bool nowait)
533*4882a593Smuzhiyun {
534*4882a593Smuzhiyun /* release current image */
535*4882a593Smuzhiyun if (*fw != NULL)
536*4882a593Smuzhiyun mwl8k_release_fw(fw);
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun if (nowait)
539*4882a593Smuzhiyun return request_firmware_nowait(THIS_MODULE, 1, fname,
540*4882a593Smuzhiyun &priv->pdev->dev, GFP_KERNEL,
541*4882a593Smuzhiyun priv, mwl8k_fw_state_machine);
542*4882a593Smuzhiyun else
543*4882a593Smuzhiyun return request_firmware(fw, fname, &priv->pdev->dev);
544*4882a593Smuzhiyun }
545*4882a593Smuzhiyun
mwl8k_request_firmware(struct mwl8k_priv * priv,char * fw_image,bool nowait)546*4882a593Smuzhiyun static int mwl8k_request_firmware(struct mwl8k_priv *priv, char *fw_image,
547*4882a593Smuzhiyun bool nowait)
548*4882a593Smuzhiyun {
549*4882a593Smuzhiyun struct mwl8k_device_info *di = priv->device_info;
550*4882a593Smuzhiyun int rc;
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun if (di->helper_image != NULL) {
553*4882a593Smuzhiyun if (nowait)
554*4882a593Smuzhiyun rc = mwl8k_request_fw(priv, di->helper_image,
555*4882a593Smuzhiyun &priv->fw_helper, true);
556*4882a593Smuzhiyun else
557*4882a593Smuzhiyun rc = mwl8k_request_fw(priv, di->helper_image,
558*4882a593Smuzhiyun &priv->fw_helper, false);
559*4882a593Smuzhiyun if (rc)
560*4882a593Smuzhiyun printk(KERN_ERR "%s: Error requesting helper fw %s\n",
561*4882a593Smuzhiyun pci_name(priv->pdev), di->helper_image);
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun if (rc || nowait)
564*4882a593Smuzhiyun return rc;
565*4882a593Smuzhiyun }
566*4882a593Smuzhiyun
567*4882a593Smuzhiyun if (nowait) {
568*4882a593Smuzhiyun /*
569*4882a593Smuzhiyun * if we get here, no helper image is needed. Skip the
570*4882a593Smuzhiyun * FW_STATE_INIT state.
571*4882a593Smuzhiyun */
572*4882a593Smuzhiyun priv->fw_state = FW_STATE_LOADING_PREF;
573*4882a593Smuzhiyun rc = mwl8k_request_fw(priv, fw_image,
574*4882a593Smuzhiyun &priv->fw_ucode,
575*4882a593Smuzhiyun true);
576*4882a593Smuzhiyun } else
577*4882a593Smuzhiyun rc = mwl8k_request_fw(priv, fw_image,
578*4882a593Smuzhiyun &priv->fw_ucode, false);
579*4882a593Smuzhiyun if (rc) {
580*4882a593Smuzhiyun printk(KERN_ERR "%s: Error requesting firmware file %s\n",
581*4882a593Smuzhiyun pci_name(priv->pdev), fw_image);
582*4882a593Smuzhiyun mwl8k_release_fw(&priv->fw_helper);
583*4882a593Smuzhiyun return rc;
584*4882a593Smuzhiyun }
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun return 0;
587*4882a593Smuzhiyun }
588*4882a593Smuzhiyun
589*4882a593Smuzhiyun struct mwl8k_cmd_pkt {
590*4882a593Smuzhiyun __le16 code;
591*4882a593Smuzhiyun __le16 length;
592*4882a593Smuzhiyun __u8 seq_num;
593*4882a593Smuzhiyun __u8 macid;
594*4882a593Smuzhiyun __le16 result;
595*4882a593Smuzhiyun char payload[];
596*4882a593Smuzhiyun } __packed;
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun /*
599*4882a593Smuzhiyun * Firmware loading.
600*4882a593Smuzhiyun */
601*4882a593Smuzhiyun static int
mwl8k_send_fw_load_cmd(struct mwl8k_priv * priv,void * data,int length)602*4882a593Smuzhiyun mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
603*4882a593Smuzhiyun {
604*4882a593Smuzhiyun void __iomem *regs = priv->regs;
605*4882a593Smuzhiyun dma_addr_t dma_addr;
606*4882a593Smuzhiyun int loops;
607*4882a593Smuzhiyun
608*4882a593Smuzhiyun dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
609*4882a593Smuzhiyun if (pci_dma_mapping_error(priv->pdev, dma_addr))
610*4882a593Smuzhiyun return -ENOMEM;
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
613*4882a593Smuzhiyun iowrite32(0, regs + MWL8K_HIU_INT_CODE);
614*4882a593Smuzhiyun iowrite32(MWL8K_H2A_INT_DOORBELL,
615*4882a593Smuzhiyun regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
616*4882a593Smuzhiyun iowrite32(MWL8K_H2A_INT_DUMMY,
617*4882a593Smuzhiyun regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
618*4882a593Smuzhiyun
619*4882a593Smuzhiyun loops = 1000;
620*4882a593Smuzhiyun do {
621*4882a593Smuzhiyun u32 int_code;
622*4882a593Smuzhiyun if (priv->is_8764) {
623*4882a593Smuzhiyun int_code = ioread32(regs +
624*4882a593Smuzhiyun MWL8K_HIU_H2A_INTERRUPT_STATUS);
625*4882a593Smuzhiyun if (int_code == 0)
626*4882a593Smuzhiyun break;
627*4882a593Smuzhiyun } else {
628*4882a593Smuzhiyun int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
629*4882a593Smuzhiyun if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
630*4882a593Smuzhiyun iowrite32(0, regs + MWL8K_HIU_INT_CODE);
631*4882a593Smuzhiyun break;
632*4882a593Smuzhiyun }
633*4882a593Smuzhiyun }
634*4882a593Smuzhiyun cond_resched();
635*4882a593Smuzhiyun udelay(1);
636*4882a593Smuzhiyun } while (--loops);
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
639*4882a593Smuzhiyun
640*4882a593Smuzhiyun return loops ? 0 : -ETIMEDOUT;
641*4882a593Smuzhiyun }
642*4882a593Smuzhiyun
mwl8k_load_fw_image(struct mwl8k_priv * priv,const u8 * data,size_t length)643*4882a593Smuzhiyun static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
644*4882a593Smuzhiyun const u8 *data, size_t length)
645*4882a593Smuzhiyun {
646*4882a593Smuzhiyun struct mwl8k_cmd_pkt *cmd;
647*4882a593Smuzhiyun int done;
648*4882a593Smuzhiyun int rc = 0;
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
651*4882a593Smuzhiyun if (cmd == NULL)
652*4882a593Smuzhiyun return -ENOMEM;
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
655*4882a593Smuzhiyun cmd->seq_num = 0;
656*4882a593Smuzhiyun cmd->macid = 0;
657*4882a593Smuzhiyun cmd->result = 0;
658*4882a593Smuzhiyun
659*4882a593Smuzhiyun done = 0;
660*4882a593Smuzhiyun while (length) {
661*4882a593Smuzhiyun int block_size = length > 256 ? 256 : length;
662*4882a593Smuzhiyun
663*4882a593Smuzhiyun memcpy(cmd->payload, data + done, block_size);
664*4882a593Smuzhiyun cmd->length = cpu_to_le16(block_size);
665*4882a593Smuzhiyun
666*4882a593Smuzhiyun rc = mwl8k_send_fw_load_cmd(priv, cmd,
667*4882a593Smuzhiyun sizeof(*cmd) + block_size);
668*4882a593Smuzhiyun if (rc)
669*4882a593Smuzhiyun break;
670*4882a593Smuzhiyun
671*4882a593Smuzhiyun done += block_size;
672*4882a593Smuzhiyun length -= block_size;
673*4882a593Smuzhiyun }
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun if (!rc) {
676*4882a593Smuzhiyun cmd->length = 0;
677*4882a593Smuzhiyun rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
678*4882a593Smuzhiyun }
679*4882a593Smuzhiyun
680*4882a593Smuzhiyun kfree(cmd);
681*4882a593Smuzhiyun
682*4882a593Smuzhiyun return rc;
683*4882a593Smuzhiyun }
684*4882a593Smuzhiyun
mwl8k_feed_fw_image(struct mwl8k_priv * priv,const u8 * data,size_t length)685*4882a593Smuzhiyun static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
686*4882a593Smuzhiyun const u8 *data, size_t length)
687*4882a593Smuzhiyun {
688*4882a593Smuzhiyun unsigned char *buffer;
689*4882a593Smuzhiyun int may_continue, rc = 0;
690*4882a593Smuzhiyun u32 done, prev_block_size;
691*4882a593Smuzhiyun
692*4882a593Smuzhiyun buffer = kmalloc(1024, GFP_KERNEL);
693*4882a593Smuzhiyun if (buffer == NULL)
694*4882a593Smuzhiyun return -ENOMEM;
695*4882a593Smuzhiyun
696*4882a593Smuzhiyun done = 0;
697*4882a593Smuzhiyun prev_block_size = 0;
698*4882a593Smuzhiyun may_continue = 1000;
699*4882a593Smuzhiyun while (may_continue > 0) {
700*4882a593Smuzhiyun u32 block_size;
701*4882a593Smuzhiyun
702*4882a593Smuzhiyun block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
703*4882a593Smuzhiyun if (block_size & 1) {
704*4882a593Smuzhiyun block_size &= ~1;
705*4882a593Smuzhiyun may_continue--;
706*4882a593Smuzhiyun } else {
707*4882a593Smuzhiyun done += prev_block_size;
708*4882a593Smuzhiyun length -= prev_block_size;
709*4882a593Smuzhiyun }
710*4882a593Smuzhiyun
711*4882a593Smuzhiyun if (block_size > 1024 || block_size > length) {
712*4882a593Smuzhiyun rc = -EOVERFLOW;
713*4882a593Smuzhiyun break;
714*4882a593Smuzhiyun }
715*4882a593Smuzhiyun
716*4882a593Smuzhiyun if (length == 0) {
717*4882a593Smuzhiyun rc = 0;
718*4882a593Smuzhiyun break;
719*4882a593Smuzhiyun }
720*4882a593Smuzhiyun
721*4882a593Smuzhiyun if (block_size == 0) {
722*4882a593Smuzhiyun rc = -EPROTO;
723*4882a593Smuzhiyun may_continue--;
724*4882a593Smuzhiyun udelay(1);
725*4882a593Smuzhiyun continue;
726*4882a593Smuzhiyun }
727*4882a593Smuzhiyun
728*4882a593Smuzhiyun prev_block_size = block_size;
729*4882a593Smuzhiyun memcpy(buffer, data + done, block_size);
730*4882a593Smuzhiyun
731*4882a593Smuzhiyun rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
732*4882a593Smuzhiyun if (rc)
733*4882a593Smuzhiyun break;
734*4882a593Smuzhiyun }
735*4882a593Smuzhiyun
736*4882a593Smuzhiyun if (!rc && length != 0)
737*4882a593Smuzhiyun rc = -EREMOTEIO;
738*4882a593Smuzhiyun
739*4882a593Smuzhiyun kfree(buffer);
740*4882a593Smuzhiyun
741*4882a593Smuzhiyun return rc;
742*4882a593Smuzhiyun }
743*4882a593Smuzhiyun
mwl8k_load_firmware(struct ieee80211_hw * hw)744*4882a593Smuzhiyun static int mwl8k_load_firmware(struct ieee80211_hw *hw)
745*4882a593Smuzhiyun {
746*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
747*4882a593Smuzhiyun const struct firmware *fw = priv->fw_ucode;
748*4882a593Smuzhiyun int rc;
749*4882a593Smuzhiyun int loops;
750*4882a593Smuzhiyun
751*4882a593Smuzhiyun if (!memcmp(fw->data, "\x01\x00\x00\x00", 4) && !priv->is_8764) {
752*4882a593Smuzhiyun const struct firmware *helper = priv->fw_helper;
753*4882a593Smuzhiyun
754*4882a593Smuzhiyun if (helper == NULL) {
755*4882a593Smuzhiyun printk(KERN_ERR "%s: helper image needed but none "
756*4882a593Smuzhiyun "given\n", pci_name(priv->pdev));
757*4882a593Smuzhiyun return -EINVAL;
758*4882a593Smuzhiyun }
759*4882a593Smuzhiyun
760*4882a593Smuzhiyun rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
761*4882a593Smuzhiyun if (rc) {
762*4882a593Smuzhiyun printk(KERN_ERR "%s: unable to load firmware "
763*4882a593Smuzhiyun "helper image\n", pci_name(priv->pdev));
764*4882a593Smuzhiyun return rc;
765*4882a593Smuzhiyun }
766*4882a593Smuzhiyun msleep(20);
767*4882a593Smuzhiyun
768*4882a593Smuzhiyun rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
769*4882a593Smuzhiyun } else {
770*4882a593Smuzhiyun if (priv->is_8764)
771*4882a593Smuzhiyun rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
772*4882a593Smuzhiyun else
773*4882a593Smuzhiyun rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
774*4882a593Smuzhiyun }
775*4882a593Smuzhiyun
776*4882a593Smuzhiyun if (rc) {
777*4882a593Smuzhiyun printk(KERN_ERR "%s: unable to load firmware image\n",
778*4882a593Smuzhiyun pci_name(priv->pdev));
779*4882a593Smuzhiyun return rc;
780*4882a593Smuzhiyun }
781*4882a593Smuzhiyun
782*4882a593Smuzhiyun iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
783*4882a593Smuzhiyun
784*4882a593Smuzhiyun loops = 500000;
785*4882a593Smuzhiyun do {
786*4882a593Smuzhiyun u32 ready_code;
787*4882a593Smuzhiyun
788*4882a593Smuzhiyun ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
789*4882a593Smuzhiyun if (ready_code == MWL8K_FWAP_READY) {
790*4882a593Smuzhiyun priv->ap_fw = true;
791*4882a593Smuzhiyun break;
792*4882a593Smuzhiyun } else if (ready_code == MWL8K_FWSTA_READY) {
793*4882a593Smuzhiyun priv->ap_fw = false;
794*4882a593Smuzhiyun break;
795*4882a593Smuzhiyun }
796*4882a593Smuzhiyun
797*4882a593Smuzhiyun cond_resched();
798*4882a593Smuzhiyun udelay(1);
799*4882a593Smuzhiyun } while (--loops);
800*4882a593Smuzhiyun
801*4882a593Smuzhiyun return loops ? 0 : -ETIMEDOUT;
802*4882a593Smuzhiyun }
803*4882a593Smuzhiyun
804*4882a593Smuzhiyun
805*4882a593Smuzhiyun /* DMA header used by firmware and hardware. */
806*4882a593Smuzhiyun struct mwl8k_dma_data {
807*4882a593Smuzhiyun __le16 fwlen;
808*4882a593Smuzhiyun struct ieee80211_hdr wh;
809*4882a593Smuzhiyun char data[];
810*4882a593Smuzhiyun } __packed;
811*4882a593Smuzhiyun
812*4882a593Smuzhiyun /* Routines to add/remove DMA header from skb. */
mwl8k_remove_dma_header(struct sk_buff * skb,__le16 qos)813*4882a593Smuzhiyun static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
814*4882a593Smuzhiyun {
815*4882a593Smuzhiyun struct mwl8k_dma_data *tr;
816*4882a593Smuzhiyun int hdrlen;
817*4882a593Smuzhiyun
818*4882a593Smuzhiyun tr = (struct mwl8k_dma_data *)skb->data;
819*4882a593Smuzhiyun hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
820*4882a593Smuzhiyun
821*4882a593Smuzhiyun if (hdrlen != sizeof(tr->wh)) {
822*4882a593Smuzhiyun if (ieee80211_is_data_qos(tr->wh.frame_control)) {
823*4882a593Smuzhiyun memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
824*4882a593Smuzhiyun *((__le16 *)(tr->data - 2)) = qos;
825*4882a593Smuzhiyun } else {
826*4882a593Smuzhiyun memmove(tr->data - hdrlen, &tr->wh, hdrlen);
827*4882a593Smuzhiyun }
828*4882a593Smuzhiyun }
829*4882a593Smuzhiyun
830*4882a593Smuzhiyun if (hdrlen != sizeof(*tr))
831*4882a593Smuzhiyun skb_pull(skb, sizeof(*tr) - hdrlen);
832*4882a593Smuzhiyun }
833*4882a593Smuzhiyun
834*4882a593Smuzhiyun #define REDUCED_TX_HEADROOM 8
835*4882a593Smuzhiyun
836*4882a593Smuzhiyun static void
mwl8k_add_dma_header(struct mwl8k_priv * priv,struct sk_buff * skb,int head_pad,int tail_pad)837*4882a593Smuzhiyun mwl8k_add_dma_header(struct mwl8k_priv *priv, struct sk_buff *skb,
838*4882a593Smuzhiyun int head_pad, int tail_pad)
839*4882a593Smuzhiyun {
840*4882a593Smuzhiyun struct ieee80211_hdr *wh;
841*4882a593Smuzhiyun int hdrlen;
842*4882a593Smuzhiyun int reqd_hdrlen;
843*4882a593Smuzhiyun struct mwl8k_dma_data *tr;
844*4882a593Smuzhiyun
845*4882a593Smuzhiyun /*
846*4882a593Smuzhiyun * Add a firmware DMA header; the firmware requires that we
847*4882a593Smuzhiyun * present a 2-byte payload length followed by a 4-address
848*4882a593Smuzhiyun * header (without QoS field), followed (optionally) by any
849*4882a593Smuzhiyun * WEP/ExtIV header (but only filled in for CCMP).
850*4882a593Smuzhiyun */
851*4882a593Smuzhiyun wh = (struct ieee80211_hdr *)skb->data;
852*4882a593Smuzhiyun
853*4882a593Smuzhiyun hdrlen = ieee80211_hdrlen(wh->frame_control);
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun /*
856*4882a593Smuzhiyun * Check if skb_resize is required because of
857*4882a593Smuzhiyun * tx_headroom adjustment.
858*4882a593Smuzhiyun */
859*4882a593Smuzhiyun if (priv->ap_fw && (hdrlen < (sizeof(struct ieee80211_cts)
860*4882a593Smuzhiyun + REDUCED_TX_HEADROOM))) {
861*4882a593Smuzhiyun if (pskb_expand_head(skb, REDUCED_TX_HEADROOM, 0, GFP_ATOMIC)) {
862*4882a593Smuzhiyun
863*4882a593Smuzhiyun wiphy_err(priv->hw->wiphy,
864*4882a593Smuzhiyun "Failed to reallocate TX buffer\n");
865*4882a593Smuzhiyun return;
866*4882a593Smuzhiyun }
867*4882a593Smuzhiyun skb->truesize += REDUCED_TX_HEADROOM;
868*4882a593Smuzhiyun }
869*4882a593Smuzhiyun
870*4882a593Smuzhiyun reqd_hdrlen = sizeof(*tr) + head_pad;
871*4882a593Smuzhiyun
872*4882a593Smuzhiyun if (hdrlen != reqd_hdrlen)
873*4882a593Smuzhiyun skb_push(skb, reqd_hdrlen - hdrlen);
874*4882a593Smuzhiyun
875*4882a593Smuzhiyun if (ieee80211_is_data_qos(wh->frame_control))
876*4882a593Smuzhiyun hdrlen -= IEEE80211_QOS_CTL_LEN;
877*4882a593Smuzhiyun
878*4882a593Smuzhiyun tr = (struct mwl8k_dma_data *)skb->data;
879*4882a593Smuzhiyun if (wh != &tr->wh)
880*4882a593Smuzhiyun memmove(&tr->wh, wh, hdrlen);
881*4882a593Smuzhiyun if (hdrlen != sizeof(tr->wh))
882*4882a593Smuzhiyun memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
883*4882a593Smuzhiyun
884*4882a593Smuzhiyun /*
885*4882a593Smuzhiyun * Firmware length is the length of the fully formed "802.11
886*4882a593Smuzhiyun * payload". That is, everything except for the 802.11 header.
887*4882a593Smuzhiyun * This includes all crypto material including the MIC.
888*4882a593Smuzhiyun */
889*4882a593Smuzhiyun tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr) + tail_pad);
890*4882a593Smuzhiyun }
891*4882a593Smuzhiyun
mwl8k_encapsulate_tx_frame(struct mwl8k_priv * priv,struct sk_buff * skb)892*4882a593Smuzhiyun static void mwl8k_encapsulate_tx_frame(struct mwl8k_priv *priv,
893*4882a593Smuzhiyun struct sk_buff *skb)
894*4882a593Smuzhiyun {
895*4882a593Smuzhiyun struct ieee80211_hdr *wh;
896*4882a593Smuzhiyun struct ieee80211_tx_info *tx_info;
897*4882a593Smuzhiyun struct ieee80211_key_conf *key_conf;
898*4882a593Smuzhiyun int data_pad;
899*4882a593Smuzhiyun int head_pad = 0;
900*4882a593Smuzhiyun
901*4882a593Smuzhiyun wh = (struct ieee80211_hdr *)skb->data;
902*4882a593Smuzhiyun
903*4882a593Smuzhiyun tx_info = IEEE80211_SKB_CB(skb);
904*4882a593Smuzhiyun
905*4882a593Smuzhiyun key_conf = NULL;
906*4882a593Smuzhiyun if (ieee80211_is_data(wh->frame_control))
907*4882a593Smuzhiyun key_conf = tx_info->control.hw_key;
908*4882a593Smuzhiyun
909*4882a593Smuzhiyun /*
910*4882a593Smuzhiyun * Make sure the packet header is in the DMA header format (4-address
911*4882a593Smuzhiyun * without QoS), and add head & tail padding when HW crypto is enabled.
912*4882a593Smuzhiyun *
913*4882a593Smuzhiyun * We have the following trailer padding requirements:
914*4882a593Smuzhiyun * - WEP: 4 trailer bytes (ICV)
915*4882a593Smuzhiyun * - TKIP: 12 trailer bytes (8 MIC + 4 ICV)
916*4882a593Smuzhiyun * - CCMP: 8 trailer bytes (MIC)
917*4882a593Smuzhiyun */
918*4882a593Smuzhiyun data_pad = 0;
919*4882a593Smuzhiyun if (key_conf != NULL) {
920*4882a593Smuzhiyun head_pad = key_conf->iv_len;
921*4882a593Smuzhiyun switch (key_conf->cipher) {
922*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_WEP40:
923*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_WEP104:
924*4882a593Smuzhiyun data_pad = 4;
925*4882a593Smuzhiyun break;
926*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_TKIP:
927*4882a593Smuzhiyun data_pad = 12;
928*4882a593Smuzhiyun break;
929*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_CCMP:
930*4882a593Smuzhiyun data_pad = 8;
931*4882a593Smuzhiyun break;
932*4882a593Smuzhiyun }
933*4882a593Smuzhiyun }
934*4882a593Smuzhiyun mwl8k_add_dma_header(priv, skb, head_pad, data_pad);
935*4882a593Smuzhiyun }
936*4882a593Smuzhiyun
937*4882a593Smuzhiyun /*
938*4882a593Smuzhiyun * Packet reception for 88w8366/88w8764 AP firmware.
939*4882a593Smuzhiyun */
940*4882a593Smuzhiyun struct mwl8k_rxd_ap {
941*4882a593Smuzhiyun __le16 pkt_len;
942*4882a593Smuzhiyun __u8 sq2;
943*4882a593Smuzhiyun __u8 rate;
944*4882a593Smuzhiyun __le32 pkt_phys_addr;
945*4882a593Smuzhiyun __le32 next_rxd_phys_addr;
946*4882a593Smuzhiyun __le16 qos_control;
947*4882a593Smuzhiyun __le16 htsig2;
948*4882a593Smuzhiyun __le32 hw_rssi_info;
949*4882a593Smuzhiyun __le32 hw_noise_floor_info;
950*4882a593Smuzhiyun __u8 noise_floor;
951*4882a593Smuzhiyun __u8 pad0[3];
952*4882a593Smuzhiyun __u8 rssi;
953*4882a593Smuzhiyun __u8 rx_status;
954*4882a593Smuzhiyun __u8 channel;
955*4882a593Smuzhiyun __u8 rx_ctrl;
956*4882a593Smuzhiyun } __packed;
957*4882a593Smuzhiyun
958*4882a593Smuzhiyun #define MWL8K_AP_RATE_INFO_MCS_FORMAT 0x80
959*4882a593Smuzhiyun #define MWL8K_AP_RATE_INFO_40MHZ 0x40
960*4882a593Smuzhiyun #define MWL8K_AP_RATE_INFO_RATEID(x) ((x) & 0x3f)
961*4882a593Smuzhiyun
962*4882a593Smuzhiyun #define MWL8K_AP_RX_CTRL_OWNED_BY_HOST 0x80
963*4882a593Smuzhiyun
964*4882a593Smuzhiyun /* 8366/8764 AP rx_status bits */
965*4882a593Smuzhiyun #define MWL8K_AP_RXSTAT_DECRYPT_ERR_MASK 0x80
966*4882a593Smuzhiyun #define MWL8K_AP_RXSTAT_GENERAL_DECRYPT_ERR 0xFF
967*4882a593Smuzhiyun #define MWL8K_AP_RXSTAT_TKIP_DECRYPT_MIC_ERR 0x02
968*4882a593Smuzhiyun #define MWL8K_AP_RXSTAT_WEP_DECRYPT_ICV_ERR 0x04
969*4882a593Smuzhiyun #define MWL8K_AP_RXSTAT_TKIP_DECRYPT_ICV_ERR 0x08
970*4882a593Smuzhiyun
mwl8k_rxd_ap_init(void * _rxd,dma_addr_t next_dma_addr)971*4882a593Smuzhiyun static void mwl8k_rxd_ap_init(void *_rxd, dma_addr_t next_dma_addr)
972*4882a593Smuzhiyun {
973*4882a593Smuzhiyun struct mwl8k_rxd_ap *rxd = _rxd;
974*4882a593Smuzhiyun
975*4882a593Smuzhiyun rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
976*4882a593Smuzhiyun rxd->rx_ctrl = MWL8K_AP_RX_CTRL_OWNED_BY_HOST;
977*4882a593Smuzhiyun }
978*4882a593Smuzhiyun
mwl8k_rxd_ap_refill(void * _rxd,dma_addr_t addr,int len)979*4882a593Smuzhiyun static void mwl8k_rxd_ap_refill(void *_rxd, dma_addr_t addr, int len)
980*4882a593Smuzhiyun {
981*4882a593Smuzhiyun struct mwl8k_rxd_ap *rxd = _rxd;
982*4882a593Smuzhiyun
983*4882a593Smuzhiyun rxd->pkt_len = cpu_to_le16(len);
984*4882a593Smuzhiyun rxd->pkt_phys_addr = cpu_to_le32(addr);
985*4882a593Smuzhiyun wmb();
986*4882a593Smuzhiyun rxd->rx_ctrl = 0;
987*4882a593Smuzhiyun }
988*4882a593Smuzhiyun
989*4882a593Smuzhiyun static int
mwl8k_rxd_ap_process(void * _rxd,struct ieee80211_rx_status * status,__le16 * qos,s8 * noise)990*4882a593Smuzhiyun mwl8k_rxd_ap_process(void *_rxd, struct ieee80211_rx_status *status,
991*4882a593Smuzhiyun __le16 *qos, s8 *noise)
992*4882a593Smuzhiyun {
993*4882a593Smuzhiyun struct mwl8k_rxd_ap *rxd = _rxd;
994*4882a593Smuzhiyun
995*4882a593Smuzhiyun if (!(rxd->rx_ctrl & MWL8K_AP_RX_CTRL_OWNED_BY_HOST))
996*4882a593Smuzhiyun return -1;
997*4882a593Smuzhiyun rmb();
998*4882a593Smuzhiyun
999*4882a593Smuzhiyun memset(status, 0, sizeof(*status));
1000*4882a593Smuzhiyun
1001*4882a593Smuzhiyun status->signal = -rxd->rssi;
1002*4882a593Smuzhiyun *noise = -rxd->noise_floor;
1003*4882a593Smuzhiyun
1004*4882a593Smuzhiyun if (rxd->rate & MWL8K_AP_RATE_INFO_MCS_FORMAT) {
1005*4882a593Smuzhiyun status->encoding = RX_ENC_HT;
1006*4882a593Smuzhiyun if (rxd->rate & MWL8K_AP_RATE_INFO_40MHZ)
1007*4882a593Smuzhiyun status->bw = RATE_INFO_BW_40;
1008*4882a593Smuzhiyun status->rate_idx = MWL8K_AP_RATE_INFO_RATEID(rxd->rate);
1009*4882a593Smuzhiyun } else {
1010*4882a593Smuzhiyun int i;
1011*4882a593Smuzhiyun
1012*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(mwl8k_rates_24); i++) {
1013*4882a593Smuzhiyun if (mwl8k_rates_24[i].hw_value == rxd->rate) {
1014*4882a593Smuzhiyun status->rate_idx = i;
1015*4882a593Smuzhiyun break;
1016*4882a593Smuzhiyun }
1017*4882a593Smuzhiyun }
1018*4882a593Smuzhiyun }
1019*4882a593Smuzhiyun
1020*4882a593Smuzhiyun if (rxd->channel > 14) {
1021*4882a593Smuzhiyun status->band = NL80211_BAND_5GHZ;
1022*4882a593Smuzhiyun if (!(status->encoding == RX_ENC_HT) &&
1023*4882a593Smuzhiyun status->rate_idx >= MWL8K_LEGACY_5G_RATE_OFFSET)
1024*4882a593Smuzhiyun status->rate_idx -= MWL8K_LEGACY_5G_RATE_OFFSET;
1025*4882a593Smuzhiyun } else {
1026*4882a593Smuzhiyun status->band = NL80211_BAND_2GHZ;
1027*4882a593Smuzhiyun }
1028*4882a593Smuzhiyun status->freq = ieee80211_channel_to_frequency(rxd->channel,
1029*4882a593Smuzhiyun status->band);
1030*4882a593Smuzhiyun
1031*4882a593Smuzhiyun *qos = rxd->qos_control;
1032*4882a593Smuzhiyun
1033*4882a593Smuzhiyun if ((rxd->rx_status != MWL8K_AP_RXSTAT_GENERAL_DECRYPT_ERR) &&
1034*4882a593Smuzhiyun (rxd->rx_status & MWL8K_AP_RXSTAT_DECRYPT_ERR_MASK) &&
1035*4882a593Smuzhiyun (rxd->rx_status & MWL8K_AP_RXSTAT_TKIP_DECRYPT_MIC_ERR))
1036*4882a593Smuzhiyun status->flag |= RX_FLAG_MMIC_ERROR;
1037*4882a593Smuzhiyun
1038*4882a593Smuzhiyun return le16_to_cpu(rxd->pkt_len);
1039*4882a593Smuzhiyun }
1040*4882a593Smuzhiyun
1041*4882a593Smuzhiyun static struct rxd_ops rxd_ap_ops = {
1042*4882a593Smuzhiyun .rxd_size = sizeof(struct mwl8k_rxd_ap),
1043*4882a593Smuzhiyun .rxd_init = mwl8k_rxd_ap_init,
1044*4882a593Smuzhiyun .rxd_refill = mwl8k_rxd_ap_refill,
1045*4882a593Smuzhiyun .rxd_process = mwl8k_rxd_ap_process,
1046*4882a593Smuzhiyun };
1047*4882a593Smuzhiyun
1048*4882a593Smuzhiyun /*
1049*4882a593Smuzhiyun * Packet reception for STA firmware.
1050*4882a593Smuzhiyun */
1051*4882a593Smuzhiyun struct mwl8k_rxd_sta {
1052*4882a593Smuzhiyun __le16 pkt_len;
1053*4882a593Smuzhiyun __u8 link_quality;
1054*4882a593Smuzhiyun __u8 noise_level;
1055*4882a593Smuzhiyun __le32 pkt_phys_addr;
1056*4882a593Smuzhiyun __le32 next_rxd_phys_addr;
1057*4882a593Smuzhiyun __le16 qos_control;
1058*4882a593Smuzhiyun __le16 rate_info;
1059*4882a593Smuzhiyun __le32 pad0[4];
1060*4882a593Smuzhiyun __u8 rssi;
1061*4882a593Smuzhiyun __u8 channel;
1062*4882a593Smuzhiyun __le16 pad1;
1063*4882a593Smuzhiyun __u8 rx_ctrl;
1064*4882a593Smuzhiyun __u8 rx_status;
1065*4882a593Smuzhiyun __u8 pad2[2];
1066*4882a593Smuzhiyun } __packed;
1067*4882a593Smuzhiyun
1068*4882a593Smuzhiyun #define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000
1069*4882a593Smuzhiyun #define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
1070*4882a593Smuzhiyun #define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
1071*4882a593Smuzhiyun #define MWL8K_STA_RATE_INFO_40MHZ 0x0004
1072*4882a593Smuzhiyun #define MWL8K_STA_RATE_INFO_SHORTGI 0x0002
1073*4882a593Smuzhiyun #define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001
1074*4882a593Smuzhiyun
1075*4882a593Smuzhiyun #define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02
1076*4882a593Smuzhiyun #define MWL8K_STA_RX_CTRL_DECRYPT_ERROR 0x04
1077*4882a593Smuzhiyun /* ICV=0 or MIC=1 */
1078*4882a593Smuzhiyun #define MWL8K_STA_RX_CTRL_DEC_ERR_TYPE 0x08
1079*4882a593Smuzhiyun /* Key is uploaded only in failure case */
1080*4882a593Smuzhiyun #define MWL8K_STA_RX_CTRL_KEY_INDEX 0x30
1081*4882a593Smuzhiyun
mwl8k_rxd_sta_init(void * _rxd,dma_addr_t next_dma_addr)1082*4882a593Smuzhiyun static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr)
1083*4882a593Smuzhiyun {
1084*4882a593Smuzhiyun struct mwl8k_rxd_sta *rxd = _rxd;
1085*4882a593Smuzhiyun
1086*4882a593Smuzhiyun rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
1087*4882a593Smuzhiyun rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST;
1088*4882a593Smuzhiyun }
1089*4882a593Smuzhiyun
mwl8k_rxd_sta_refill(void * _rxd,dma_addr_t addr,int len)1090*4882a593Smuzhiyun static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len)
1091*4882a593Smuzhiyun {
1092*4882a593Smuzhiyun struct mwl8k_rxd_sta *rxd = _rxd;
1093*4882a593Smuzhiyun
1094*4882a593Smuzhiyun rxd->pkt_len = cpu_to_le16(len);
1095*4882a593Smuzhiyun rxd->pkt_phys_addr = cpu_to_le32(addr);
1096*4882a593Smuzhiyun wmb();
1097*4882a593Smuzhiyun rxd->rx_ctrl = 0;
1098*4882a593Smuzhiyun }
1099*4882a593Smuzhiyun
1100*4882a593Smuzhiyun static int
mwl8k_rxd_sta_process(void * _rxd,struct ieee80211_rx_status * status,__le16 * qos,s8 * noise)1101*4882a593Smuzhiyun mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status,
1102*4882a593Smuzhiyun __le16 *qos, s8 *noise)
1103*4882a593Smuzhiyun {
1104*4882a593Smuzhiyun struct mwl8k_rxd_sta *rxd = _rxd;
1105*4882a593Smuzhiyun u16 rate_info;
1106*4882a593Smuzhiyun
1107*4882a593Smuzhiyun if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST))
1108*4882a593Smuzhiyun return -1;
1109*4882a593Smuzhiyun rmb();
1110*4882a593Smuzhiyun
1111*4882a593Smuzhiyun rate_info = le16_to_cpu(rxd->rate_info);
1112*4882a593Smuzhiyun
1113*4882a593Smuzhiyun memset(status, 0, sizeof(*status));
1114*4882a593Smuzhiyun
1115*4882a593Smuzhiyun status->signal = -rxd->rssi;
1116*4882a593Smuzhiyun *noise = -rxd->noise_level;
1117*4882a593Smuzhiyun status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info);
1118*4882a593Smuzhiyun status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info);
1119*4882a593Smuzhiyun
1120*4882a593Smuzhiyun if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE)
1121*4882a593Smuzhiyun status->enc_flags |= RX_ENC_FLAG_SHORTPRE;
1122*4882a593Smuzhiyun if (rate_info & MWL8K_STA_RATE_INFO_40MHZ)
1123*4882a593Smuzhiyun status->bw = RATE_INFO_BW_40;
1124*4882a593Smuzhiyun if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI)
1125*4882a593Smuzhiyun status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
1126*4882a593Smuzhiyun if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT)
1127*4882a593Smuzhiyun status->encoding = RX_ENC_HT;
1128*4882a593Smuzhiyun
1129*4882a593Smuzhiyun if (rxd->channel > 14) {
1130*4882a593Smuzhiyun status->band = NL80211_BAND_5GHZ;
1131*4882a593Smuzhiyun if (!(status->encoding == RX_ENC_HT) &&
1132*4882a593Smuzhiyun status->rate_idx >= MWL8K_LEGACY_5G_RATE_OFFSET)
1133*4882a593Smuzhiyun status->rate_idx -= MWL8K_LEGACY_5G_RATE_OFFSET;
1134*4882a593Smuzhiyun } else {
1135*4882a593Smuzhiyun status->band = NL80211_BAND_2GHZ;
1136*4882a593Smuzhiyun }
1137*4882a593Smuzhiyun status->freq = ieee80211_channel_to_frequency(rxd->channel,
1138*4882a593Smuzhiyun status->band);
1139*4882a593Smuzhiyun
1140*4882a593Smuzhiyun *qos = rxd->qos_control;
1141*4882a593Smuzhiyun if ((rxd->rx_ctrl & MWL8K_STA_RX_CTRL_DECRYPT_ERROR) &&
1142*4882a593Smuzhiyun (rxd->rx_ctrl & MWL8K_STA_RX_CTRL_DEC_ERR_TYPE))
1143*4882a593Smuzhiyun status->flag |= RX_FLAG_MMIC_ERROR;
1144*4882a593Smuzhiyun
1145*4882a593Smuzhiyun return le16_to_cpu(rxd->pkt_len);
1146*4882a593Smuzhiyun }
1147*4882a593Smuzhiyun
1148*4882a593Smuzhiyun static struct rxd_ops rxd_sta_ops = {
1149*4882a593Smuzhiyun .rxd_size = sizeof(struct mwl8k_rxd_sta),
1150*4882a593Smuzhiyun .rxd_init = mwl8k_rxd_sta_init,
1151*4882a593Smuzhiyun .rxd_refill = mwl8k_rxd_sta_refill,
1152*4882a593Smuzhiyun .rxd_process = mwl8k_rxd_sta_process,
1153*4882a593Smuzhiyun };
1154*4882a593Smuzhiyun
1155*4882a593Smuzhiyun
1156*4882a593Smuzhiyun #define MWL8K_RX_DESCS 256
1157*4882a593Smuzhiyun #define MWL8K_RX_MAXSZ 3800
1158*4882a593Smuzhiyun
mwl8k_rxq_init(struct ieee80211_hw * hw,int index)1159*4882a593Smuzhiyun static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
1160*4882a593Smuzhiyun {
1161*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
1162*4882a593Smuzhiyun struct mwl8k_rx_queue *rxq = priv->rxq + index;
1163*4882a593Smuzhiyun int size;
1164*4882a593Smuzhiyun int i;
1165*4882a593Smuzhiyun
1166*4882a593Smuzhiyun rxq->rxd_count = 0;
1167*4882a593Smuzhiyun rxq->head = 0;
1168*4882a593Smuzhiyun rxq->tail = 0;
1169*4882a593Smuzhiyun
1170*4882a593Smuzhiyun size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
1171*4882a593Smuzhiyun
1172*4882a593Smuzhiyun rxq->rxd = pci_zalloc_consistent(priv->pdev, size, &rxq->rxd_dma);
1173*4882a593Smuzhiyun if (rxq->rxd == NULL) {
1174*4882a593Smuzhiyun wiphy_err(hw->wiphy, "failed to alloc RX descriptors\n");
1175*4882a593Smuzhiyun return -ENOMEM;
1176*4882a593Smuzhiyun }
1177*4882a593Smuzhiyun
1178*4882a593Smuzhiyun rxq->buf = kcalloc(MWL8K_RX_DESCS, sizeof(*rxq->buf), GFP_KERNEL);
1179*4882a593Smuzhiyun if (rxq->buf == NULL) {
1180*4882a593Smuzhiyun pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
1181*4882a593Smuzhiyun return -ENOMEM;
1182*4882a593Smuzhiyun }
1183*4882a593Smuzhiyun
1184*4882a593Smuzhiyun for (i = 0; i < MWL8K_RX_DESCS; i++) {
1185*4882a593Smuzhiyun int desc_size;
1186*4882a593Smuzhiyun void *rxd;
1187*4882a593Smuzhiyun int nexti;
1188*4882a593Smuzhiyun dma_addr_t next_dma_addr;
1189*4882a593Smuzhiyun
1190*4882a593Smuzhiyun desc_size = priv->rxd_ops->rxd_size;
1191*4882a593Smuzhiyun rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
1192*4882a593Smuzhiyun
1193*4882a593Smuzhiyun nexti = i + 1;
1194*4882a593Smuzhiyun if (nexti == MWL8K_RX_DESCS)
1195*4882a593Smuzhiyun nexti = 0;
1196*4882a593Smuzhiyun next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
1197*4882a593Smuzhiyun
1198*4882a593Smuzhiyun priv->rxd_ops->rxd_init(rxd, next_dma_addr);
1199*4882a593Smuzhiyun }
1200*4882a593Smuzhiyun
1201*4882a593Smuzhiyun return 0;
1202*4882a593Smuzhiyun }
1203*4882a593Smuzhiyun
rxq_refill(struct ieee80211_hw * hw,int index,int limit)1204*4882a593Smuzhiyun static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
1205*4882a593Smuzhiyun {
1206*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
1207*4882a593Smuzhiyun struct mwl8k_rx_queue *rxq = priv->rxq + index;
1208*4882a593Smuzhiyun int refilled;
1209*4882a593Smuzhiyun
1210*4882a593Smuzhiyun refilled = 0;
1211*4882a593Smuzhiyun while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
1212*4882a593Smuzhiyun struct sk_buff *skb;
1213*4882a593Smuzhiyun dma_addr_t addr;
1214*4882a593Smuzhiyun int rx;
1215*4882a593Smuzhiyun void *rxd;
1216*4882a593Smuzhiyun
1217*4882a593Smuzhiyun skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
1218*4882a593Smuzhiyun if (skb == NULL)
1219*4882a593Smuzhiyun break;
1220*4882a593Smuzhiyun
1221*4882a593Smuzhiyun addr = pci_map_single(priv->pdev, skb->data,
1222*4882a593Smuzhiyun MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
1223*4882a593Smuzhiyun
1224*4882a593Smuzhiyun rxq->rxd_count++;
1225*4882a593Smuzhiyun rx = rxq->tail++;
1226*4882a593Smuzhiyun if (rxq->tail == MWL8K_RX_DESCS)
1227*4882a593Smuzhiyun rxq->tail = 0;
1228*4882a593Smuzhiyun rxq->buf[rx].skb = skb;
1229*4882a593Smuzhiyun dma_unmap_addr_set(&rxq->buf[rx], dma, addr);
1230*4882a593Smuzhiyun
1231*4882a593Smuzhiyun rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
1232*4882a593Smuzhiyun priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
1233*4882a593Smuzhiyun
1234*4882a593Smuzhiyun refilled++;
1235*4882a593Smuzhiyun }
1236*4882a593Smuzhiyun
1237*4882a593Smuzhiyun return refilled;
1238*4882a593Smuzhiyun }
1239*4882a593Smuzhiyun
1240*4882a593Smuzhiyun /* Must be called only when the card's reception is completely halted */
mwl8k_rxq_deinit(struct ieee80211_hw * hw,int index)1241*4882a593Smuzhiyun static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
1242*4882a593Smuzhiyun {
1243*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
1244*4882a593Smuzhiyun struct mwl8k_rx_queue *rxq = priv->rxq + index;
1245*4882a593Smuzhiyun int i;
1246*4882a593Smuzhiyun
1247*4882a593Smuzhiyun if (rxq->rxd == NULL)
1248*4882a593Smuzhiyun return;
1249*4882a593Smuzhiyun
1250*4882a593Smuzhiyun for (i = 0; i < MWL8K_RX_DESCS; i++) {
1251*4882a593Smuzhiyun if (rxq->buf[i].skb != NULL) {
1252*4882a593Smuzhiyun pci_unmap_single(priv->pdev,
1253*4882a593Smuzhiyun dma_unmap_addr(&rxq->buf[i], dma),
1254*4882a593Smuzhiyun MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1255*4882a593Smuzhiyun dma_unmap_addr_set(&rxq->buf[i], dma, 0);
1256*4882a593Smuzhiyun
1257*4882a593Smuzhiyun kfree_skb(rxq->buf[i].skb);
1258*4882a593Smuzhiyun rxq->buf[i].skb = NULL;
1259*4882a593Smuzhiyun }
1260*4882a593Smuzhiyun }
1261*4882a593Smuzhiyun
1262*4882a593Smuzhiyun kfree(rxq->buf);
1263*4882a593Smuzhiyun rxq->buf = NULL;
1264*4882a593Smuzhiyun
1265*4882a593Smuzhiyun pci_free_consistent(priv->pdev,
1266*4882a593Smuzhiyun MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
1267*4882a593Smuzhiyun rxq->rxd, rxq->rxd_dma);
1268*4882a593Smuzhiyun rxq->rxd = NULL;
1269*4882a593Smuzhiyun }
1270*4882a593Smuzhiyun
1271*4882a593Smuzhiyun
1272*4882a593Smuzhiyun /*
1273*4882a593Smuzhiyun * Scan a list of BSSIDs to process for finalize join.
1274*4882a593Smuzhiyun * Allows for extension to process multiple BSSIDs.
1275*4882a593Smuzhiyun */
1276*4882a593Smuzhiyun static inline int
mwl8k_capture_bssid(struct mwl8k_priv * priv,struct ieee80211_hdr * wh)1277*4882a593Smuzhiyun mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
1278*4882a593Smuzhiyun {
1279*4882a593Smuzhiyun return priv->capture_beacon &&
1280*4882a593Smuzhiyun ieee80211_is_beacon(wh->frame_control) &&
1281*4882a593Smuzhiyun ether_addr_equal_64bits(wh->addr3, priv->capture_bssid);
1282*4882a593Smuzhiyun }
1283*4882a593Smuzhiyun
mwl8k_save_beacon(struct ieee80211_hw * hw,struct sk_buff * skb)1284*4882a593Smuzhiyun static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
1285*4882a593Smuzhiyun struct sk_buff *skb)
1286*4882a593Smuzhiyun {
1287*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
1288*4882a593Smuzhiyun
1289*4882a593Smuzhiyun priv->capture_beacon = false;
1290*4882a593Smuzhiyun eth_zero_addr(priv->capture_bssid);
1291*4882a593Smuzhiyun
1292*4882a593Smuzhiyun /*
1293*4882a593Smuzhiyun * Use GFP_ATOMIC as rxq_process is called from
1294*4882a593Smuzhiyun * the primary interrupt handler, memory allocation call
1295*4882a593Smuzhiyun * must not sleep.
1296*4882a593Smuzhiyun */
1297*4882a593Smuzhiyun priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
1298*4882a593Smuzhiyun if (priv->beacon_skb != NULL)
1299*4882a593Smuzhiyun ieee80211_queue_work(hw, &priv->finalize_join_worker);
1300*4882a593Smuzhiyun }
1301*4882a593Smuzhiyun
mwl8k_find_vif_bss(struct list_head * vif_list,u8 * bssid)1302*4882a593Smuzhiyun static inline struct mwl8k_vif *mwl8k_find_vif_bss(struct list_head *vif_list,
1303*4882a593Smuzhiyun u8 *bssid)
1304*4882a593Smuzhiyun {
1305*4882a593Smuzhiyun struct mwl8k_vif *mwl8k_vif;
1306*4882a593Smuzhiyun
1307*4882a593Smuzhiyun list_for_each_entry(mwl8k_vif,
1308*4882a593Smuzhiyun vif_list, list) {
1309*4882a593Smuzhiyun if (memcmp(bssid, mwl8k_vif->bssid,
1310*4882a593Smuzhiyun ETH_ALEN) == 0)
1311*4882a593Smuzhiyun return mwl8k_vif;
1312*4882a593Smuzhiyun }
1313*4882a593Smuzhiyun
1314*4882a593Smuzhiyun return NULL;
1315*4882a593Smuzhiyun }
1316*4882a593Smuzhiyun
rxq_process(struct ieee80211_hw * hw,int index,int limit)1317*4882a593Smuzhiyun static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
1318*4882a593Smuzhiyun {
1319*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
1320*4882a593Smuzhiyun struct mwl8k_vif *mwl8k_vif = NULL;
1321*4882a593Smuzhiyun struct mwl8k_rx_queue *rxq = priv->rxq + index;
1322*4882a593Smuzhiyun int processed;
1323*4882a593Smuzhiyun
1324*4882a593Smuzhiyun processed = 0;
1325*4882a593Smuzhiyun while (rxq->rxd_count && limit--) {
1326*4882a593Smuzhiyun struct sk_buff *skb;
1327*4882a593Smuzhiyun void *rxd;
1328*4882a593Smuzhiyun int pkt_len;
1329*4882a593Smuzhiyun struct ieee80211_rx_status status;
1330*4882a593Smuzhiyun struct ieee80211_hdr *wh;
1331*4882a593Smuzhiyun __le16 qos;
1332*4882a593Smuzhiyun
1333*4882a593Smuzhiyun skb = rxq->buf[rxq->head].skb;
1334*4882a593Smuzhiyun if (skb == NULL)
1335*4882a593Smuzhiyun break;
1336*4882a593Smuzhiyun
1337*4882a593Smuzhiyun rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1338*4882a593Smuzhiyun
1339*4882a593Smuzhiyun pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos,
1340*4882a593Smuzhiyun &priv->noise);
1341*4882a593Smuzhiyun if (pkt_len < 0)
1342*4882a593Smuzhiyun break;
1343*4882a593Smuzhiyun
1344*4882a593Smuzhiyun rxq->buf[rxq->head].skb = NULL;
1345*4882a593Smuzhiyun
1346*4882a593Smuzhiyun pci_unmap_single(priv->pdev,
1347*4882a593Smuzhiyun dma_unmap_addr(&rxq->buf[rxq->head], dma),
1348*4882a593Smuzhiyun MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1349*4882a593Smuzhiyun dma_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
1350*4882a593Smuzhiyun
1351*4882a593Smuzhiyun rxq->head++;
1352*4882a593Smuzhiyun if (rxq->head == MWL8K_RX_DESCS)
1353*4882a593Smuzhiyun rxq->head = 0;
1354*4882a593Smuzhiyun
1355*4882a593Smuzhiyun rxq->rxd_count--;
1356*4882a593Smuzhiyun
1357*4882a593Smuzhiyun wh = &((struct mwl8k_dma_data *)skb->data)->wh;
1358*4882a593Smuzhiyun
1359*4882a593Smuzhiyun /*
1360*4882a593Smuzhiyun * Check for a pending join operation. Save a
1361*4882a593Smuzhiyun * copy of the beacon and schedule a tasklet to
1362*4882a593Smuzhiyun * send a FINALIZE_JOIN command to the firmware.
1363*4882a593Smuzhiyun */
1364*4882a593Smuzhiyun if (mwl8k_capture_bssid(priv, (void *)skb->data))
1365*4882a593Smuzhiyun mwl8k_save_beacon(hw, skb);
1366*4882a593Smuzhiyun
1367*4882a593Smuzhiyun if (ieee80211_has_protected(wh->frame_control)) {
1368*4882a593Smuzhiyun
1369*4882a593Smuzhiyun /* Check if hw crypto has been enabled for
1370*4882a593Smuzhiyun * this bss. If yes, set the status flags
1371*4882a593Smuzhiyun * accordingly
1372*4882a593Smuzhiyun */
1373*4882a593Smuzhiyun mwl8k_vif = mwl8k_find_vif_bss(&priv->vif_list,
1374*4882a593Smuzhiyun wh->addr1);
1375*4882a593Smuzhiyun
1376*4882a593Smuzhiyun if (mwl8k_vif != NULL &&
1377*4882a593Smuzhiyun mwl8k_vif->is_hw_crypto_enabled) {
1378*4882a593Smuzhiyun /*
1379*4882a593Smuzhiyun * When MMIC ERROR is encountered
1380*4882a593Smuzhiyun * by the firmware, payload is
1381*4882a593Smuzhiyun * dropped and only 32 bytes of
1382*4882a593Smuzhiyun * mwl8k Firmware header is sent
1383*4882a593Smuzhiyun * to the host.
1384*4882a593Smuzhiyun *
1385*4882a593Smuzhiyun * We need to add four bytes of
1386*4882a593Smuzhiyun * key information. In it
1387*4882a593Smuzhiyun * MAC80211 expects keyidx set to
1388*4882a593Smuzhiyun * 0 for triggering Counter
1389*4882a593Smuzhiyun * Measure of MMIC failure.
1390*4882a593Smuzhiyun */
1391*4882a593Smuzhiyun if (status.flag & RX_FLAG_MMIC_ERROR) {
1392*4882a593Smuzhiyun struct mwl8k_dma_data *tr;
1393*4882a593Smuzhiyun tr = (struct mwl8k_dma_data *)skb->data;
1394*4882a593Smuzhiyun memset((void *)&(tr->data), 0, 4);
1395*4882a593Smuzhiyun pkt_len += 4;
1396*4882a593Smuzhiyun }
1397*4882a593Smuzhiyun
1398*4882a593Smuzhiyun if (!ieee80211_is_auth(wh->frame_control))
1399*4882a593Smuzhiyun status.flag |= RX_FLAG_IV_STRIPPED |
1400*4882a593Smuzhiyun RX_FLAG_DECRYPTED |
1401*4882a593Smuzhiyun RX_FLAG_MMIC_STRIPPED;
1402*4882a593Smuzhiyun }
1403*4882a593Smuzhiyun }
1404*4882a593Smuzhiyun
1405*4882a593Smuzhiyun skb_put(skb, pkt_len);
1406*4882a593Smuzhiyun mwl8k_remove_dma_header(skb, qos);
1407*4882a593Smuzhiyun memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1408*4882a593Smuzhiyun ieee80211_rx_irqsafe(hw, skb);
1409*4882a593Smuzhiyun
1410*4882a593Smuzhiyun processed++;
1411*4882a593Smuzhiyun }
1412*4882a593Smuzhiyun
1413*4882a593Smuzhiyun return processed;
1414*4882a593Smuzhiyun }
1415*4882a593Smuzhiyun
1416*4882a593Smuzhiyun
1417*4882a593Smuzhiyun /*
1418*4882a593Smuzhiyun * Packet transmission.
1419*4882a593Smuzhiyun */
1420*4882a593Smuzhiyun
1421*4882a593Smuzhiyun #define MWL8K_TXD_STATUS_OK 0x00000001
1422*4882a593Smuzhiyun #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1423*4882a593Smuzhiyun #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1424*4882a593Smuzhiyun #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
1425*4882a593Smuzhiyun #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
1426*4882a593Smuzhiyun
1427*4882a593Smuzhiyun #define MWL8K_QOS_QLEN_UNSPEC 0xff00
1428*4882a593Smuzhiyun #define MWL8K_QOS_ACK_POLICY_MASK 0x0060
1429*4882a593Smuzhiyun #define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
1430*4882a593Smuzhiyun #define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
1431*4882a593Smuzhiyun #define MWL8K_QOS_EOSP 0x0010
1432*4882a593Smuzhiyun
1433*4882a593Smuzhiyun struct mwl8k_tx_desc {
1434*4882a593Smuzhiyun __le32 status;
1435*4882a593Smuzhiyun __u8 data_rate;
1436*4882a593Smuzhiyun __u8 tx_priority;
1437*4882a593Smuzhiyun __le16 qos_control;
1438*4882a593Smuzhiyun __le32 pkt_phys_addr;
1439*4882a593Smuzhiyun __le16 pkt_len;
1440*4882a593Smuzhiyun __u8 dest_MAC_addr[ETH_ALEN];
1441*4882a593Smuzhiyun __le32 next_txd_phys_addr;
1442*4882a593Smuzhiyun __le32 timestamp;
1443*4882a593Smuzhiyun __le16 rate_info;
1444*4882a593Smuzhiyun __u8 peer_id;
1445*4882a593Smuzhiyun __u8 tx_frag_cnt;
1446*4882a593Smuzhiyun } __packed;
1447*4882a593Smuzhiyun
1448*4882a593Smuzhiyun #define MWL8K_TX_DESCS 128
1449*4882a593Smuzhiyun
mwl8k_txq_init(struct ieee80211_hw * hw,int index)1450*4882a593Smuzhiyun static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1451*4882a593Smuzhiyun {
1452*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
1453*4882a593Smuzhiyun struct mwl8k_tx_queue *txq = priv->txq + index;
1454*4882a593Smuzhiyun int size;
1455*4882a593Smuzhiyun int i;
1456*4882a593Smuzhiyun
1457*4882a593Smuzhiyun txq->len = 0;
1458*4882a593Smuzhiyun txq->head = 0;
1459*4882a593Smuzhiyun txq->tail = 0;
1460*4882a593Smuzhiyun
1461*4882a593Smuzhiyun size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1462*4882a593Smuzhiyun
1463*4882a593Smuzhiyun txq->txd = pci_zalloc_consistent(priv->pdev, size, &txq->txd_dma);
1464*4882a593Smuzhiyun if (txq->txd == NULL) {
1465*4882a593Smuzhiyun wiphy_err(hw->wiphy, "failed to alloc TX descriptors\n");
1466*4882a593Smuzhiyun return -ENOMEM;
1467*4882a593Smuzhiyun }
1468*4882a593Smuzhiyun
1469*4882a593Smuzhiyun txq->skb = kcalloc(MWL8K_TX_DESCS, sizeof(*txq->skb), GFP_KERNEL);
1470*4882a593Smuzhiyun if (txq->skb == NULL) {
1471*4882a593Smuzhiyun pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
1472*4882a593Smuzhiyun txq->txd = NULL;
1473*4882a593Smuzhiyun return -ENOMEM;
1474*4882a593Smuzhiyun }
1475*4882a593Smuzhiyun
1476*4882a593Smuzhiyun for (i = 0; i < MWL8K_TX_DESCS; i++) {
1477*4882a593Smuzhiyun struct mwl8k_tx_desc *tx_desc;
1478*4882a593Smuzhiyun int nexti;
1479*4882a593Smuzhiyun
1480*4882a593Smuzhiyun tx_desc = txq->txd + i;
1481*4882a593Smuzhiyun nexti = (i + 1) % MWL8K_TX_DESCS;
1482*4882a593Smuzhiyun
1483*4882a593Smuzhiyun tx_desc->status = 0;
1484*4882a593Smuzhiyun tx_desc->next_txd_phys_addr =
1485*4882a593Smuzhiyun cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
1486*4882a593Smuzhiyun }
1487*4882a593Smuzhiyun
1488*4882a593Smuzhiyun return 0;
1489*4882a593Smuzhiyun }
1490*4882a593Smuzhiyun
mwl8k_tx_start(struct mwl8k_priv * priv)1491*4882a593Smuzhiyun static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1492*4882a593Smuzhiyun {
1493*4882a593Smuzhiyun iowrite32(MWL8K_H2A_INT_PPA_READY,
1494*4882a593Smuzhiyun priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1495*4882a593Smuzhiyun iowrite32(MWL8K_H2A_INT_DUMMY,
1496*4882a593Smuzhiyun priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1497*4882a593Smuzhiyun ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1498*4882a593Smuzhiyun }
1499*4882a593Smuzhiyun
mwl8k_dump_tx_rings(struct ieee80211_hw * hw)1500*4882a593Smuzhiyun static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
1501*4882a593Smuzhiyun {
1502*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
1503*4882a593Smuzhiyun int i;
1504*4882a593Smuzhiyun
1505*4882a593Smuzhiyun for (i = 0; i < mwl8k_tx_queues(priv); i++) {
1506*4882a593Smuzhiyun struct mwl8k_tx_queue *txq = priv->txq + i;
1507*4882a593Smuzhiyun int fw_owned = 0;
1508*4882a593Smuzhiyun int drv_owned = 0;
1509*4882a593Smuzhiyun int unused = 0;
1510*4882a593Smuzhiyun int desc;
1511*4882a593Smuzhiyun
1512*4882a593Smuzhiyun for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
1513*4882a593Smuzhiyun struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
1514*4882a593Smuzhiyun u32 status;
1515*4882a593Smuzhiyun
1516*4882a593Smuzhiyun status = le32_to_cpu(tx_desc->status);
1517*4882a593Smuzhiyun if (status & MWL8K_TXD_STATUS_FW_OWNED)
1518*4882a593Smuzhiyun fw_owned++;
1519*4882a593Smuzhiyun else
1520*4882a593Smuzhiyun drv_owned++;
1521*4882a593Smuzhiyun
1522*4882a593Smuzhiyun if (tx_desc->pkt_len == 0)
1523*4882a593Smuzhiyun unused++;
1524*4882a593Smuzhiyun }
1525*4882a593Smuzhiyun
1526*4882a593Smuzhiyun wiphy_err(hw->wiphy,
1527*4882a593Smuzhiyun "txq[%d] len=%d head=%d tail=%d "
1528*4882a593Smuzhiyun "fw_owned=%d drv_owned=%d unused=%d\n",
1529*4882a593Smuzhiyun i,
1530*4882a593Smuzhiyun txq->len, txq->head, txq->tail,
1531*4882a593Smuzhiyun fw_owned, drv_owned, unused);
1532*4882a593Smuzhiyun }
1533*4882a593Smuzhiyun }
1534*4882a593Smuzhiyun
1535*4882a593Smuzhiyun /*
1536*4882a593Smuzhiyun * Must be called with priv->fw_mutex held and tx queues stopped.
1537*4882a593Smuzhiyun */
1538*4882a593Smuzhiyun #define MWL8K_TX_WAIT_TIMEOUT_MS 5000
1539*4882a593Smuzhiyun
mwl8k_tx_wait_empty(struct ieee80211_hw * hw)1540*4882a593Smuzhiyun static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
1541*4882a593Smuzhiyun {
1542*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
1543*4882a593Smuzhiyun DECLARE_COMPLETION_ONSTACK(tx_wait);
1544*4882a593Smuzhiyun int retry;
1545*4882a593Smuzhiyun int rc;
1546*4882a593Smuzhiyun
1547*4882a593Smuzhiyun might_sleep();
1548*4882a593Smuzhiyun
1549*4882a593Smuzhiyun /* Since fw restart is in progress, allow only the firmware
1550*4882a593Smuzhiyun * commands from the restart code and block the other
1551*4882a593Smuzhiyun * commands since they are going to fail in any case since
1552*4882a593Smuzhiyun * the firmware has crashed
1553*4882a593Smuzhiyun */
1554*4882a593Smuzhiyun if (priv->hw_restart_in_progress) {
1555*4882a593Smuzhiyun if (priv->hw_restart_owner == current)
1556*4882a593Smuzhiyun return 0;
1557*4882a593Smuzhiyun else
1558*4882a593Smuzhiyun return -EBUSY;
1559*4882a593Smuzhiyun }
1560*4882a593Smuzhiyun
1561*4882a593Smuzhiyun if (atomic_read(&priv->watchdog_event_pending))
1562*4882a593Smuzhiyun return 0;
1563*4882a593Smuzhiyun
1564*4882a593Smuzhiyun /*
1565*4882a593Smuzhiyun * The TX queues are stopped at this point, so this test
1566*4882a593Smuzhiyun * doesn't need to take ->tx_lock.
1567*4882a593Smuzhiyun */
1568*4882a593Smuzhiyun if (!priv->pending_tx_pkts)
1569*4882a593Smuzhiyun return 0;
1570*4882a593Smuzhiyun
1571*4882a593Smuzhiyun retry = 1;
1572*4882a593Smuzhiyun rc = 0;
1573*4882a593Smuzhiyun
1574*4882a593Smuzhiyun spin_lock_bh(&priv->tx_lock);
1575*4882a593Smuzhiyun priv->tx_wait = &tx_wait;
1576*4882a593Smuzhiyun while (!rc) {
1577*4882a593Smuzhiyun int oldcount;
1578*4882a593Smuzhiyun unsigned long timeout;
1579*4882a593Smuzhiyun
1580*4882a593Smuzhiyun oldcount = priv->pending_tx_pkts;
1581*4882a593Smuzhiyun
1582*4882a593Smuzhiyun spin_unlock_bh(&priv->tx_lock);
1583*4882a593Smuzhiyun timeout = wait_for_completion_timeout(&tx_wait,
1584*4882a593Smuzhiyun msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
1585*4882a593Smuzhiyun
1586*4882a593Smuzhiyun if (atomic_read(&priv->watchdog_event_pending)) {
1587*4882a593Smuzhiyun spin_lock_bh(&priv->tx_lock);
1588*4882a593Smuzhiyun priv->tx_wait = NULL;
1589*4882a593Smuzhiyun spin_unlock_bh(&priv->tx_lock);
1590*4882a593Smuzhiyun return 0;
1591*4882a593Smuzhiyun }
1592*4882a593Smuzhiyun
1593*4882a593Smuzhiyun spin_lock_bh(&priv->tx_lock);
1594*4882a593Smuzhiyun
1595*4882a593Smuzhiyun if (timeout || !priv->pending_tx_pkts) {
1596*4882a593Smuzhiyun WARN_ON(priv->pending_tx_pkts);
1597*4882a593Smuzhiyun if (retry)
1598*4882a593Smuzhiyun wiphy_notice(hw->wiphy, "tx rings drained\n");
1599*4882a593Smuzhiyun break;
1600*4882a593Smuzhiyun }
1601*4882a593Smuzhiyun
1602*4882a593Smuzhiyun if (retry) {
1603*4882a593Smuzhiyun mwl8k_tx_start(priv);
1604*4882a593Smuzhiyun retry = 0;
1605*4882a593Smuzhiyun continue;
1606*4882a593Smuzhiyun }
1607*4882a593Smuzhiyun
1608*4882a593Smuzhiyun if (priv->pending_tx_pkts < oldcount) {
1609*4882a593Smuzhiyun wiphy_notice(hw->wiphy,
1610*4882a593Smuzhiyun "waiting for tx rings to drain (%d -> %d pkts)\n",
1611*4882a593Smuzhiyun oldcount, priv->pending_tx_pkts);
1612*4882a593Smuzhiyun retry = 1;
1613*4882a593Smuzhiyun continue;
1614*4882a593Smuzhiyun }
1615*4882a593Smuzhiyun
1616*4882a593Smuzhiyun priv->tx_wait = NULL;
1617*4882a593Smuzhiyun
1618*4882a593Smuzhiyun wiphy_err(hw->wiphy, "tx rings stuck for %d ms\n",
1619*4882a593Smuzhiyun MWL8K_TX_WAIT_TIMEOUT_MS);
1620*4882a593Smuzhiyun mwl8k_dump_tx_rings(hw);
1621*4882a593Smuzhiyun priv->hw_restart_in_progress = true;
1622*4882a593Smuzhiyun ieee80211_queue_work(hw, &priv->fw_reload);
1623*4882a593Smuzhiyun
1624*4882a593Smuzhiyun rc = -ETIMEDOUT;
1625*4882a593Smuzhiyun }
1626*4882a593Smuzhiyun priv->tx_wait = NULL;
1627*4882a593Smuzhiyun spin_unlock_bh(&priv->tx_lock);
1628*4882a593Smuzhiyun
1629*4882a593Smuzhiyun return rc;
1630*4882a593Smuzhiyun }
1631*4882a593Smuzhiyun
1632*4882a593Smuzhiyun #define MWL8K_TXD_SUCCESS(status) \
1633*4882a593Smuzhiyun ((status) & (MWL8K_TXD_STATUS_OK | \
1634*4882a593Smuzhiyun MWL8K_TXD_STATUS_OK_RETRY | \
1635*4882a593Smuzhiyun MWL8K_TXD_STATUS_OK_MORE_RETRY))
1636*4882a593Smuzhiyun
mwl8k_tid_queue_mapping(u8 tid)1637*4882a593Smuzhiyun static int mwl8k_tid_queue_mapping(u8 tid)
1638*4882a593Smuzhiyun {
1639*4882a593Smuzhiyun BUG_ON(tid > 7);
1640*4882a593Smuzhiyun
1641*4882a593Smuzhiyun switch (tid) {
1642*4882a593Smuzhiyun case 0:
1643*4882a593Smuzhiyun case 3:
1644*4882a593Smuzhiyun return IEEE80211_AC_BE;
1645*4882a593Smuzhiyun case 1:
1646*4882a593Smuzhiyun case 2:
1647*4882a593Smuzhiyun return IEEE80211_AC_BK;
1648*4882a593Smuzhiyun case 4:
1649*4882a593Smuzhiyun case 5:
1650*4882a593Smuzhiyun return IEEE80211_AC_VI;
1651*4882a593Smuzhiyun case 6:
1652*4882a593Smuzhiyun case 7:
1653*4882a593Smuzhiyun return IEEE80211_AC_VO;
1654*4882a593Smuzhiyun default:
1655*4882a593Smuzhiyun return -1;
1656*4882a593Smuzhiyun }
1657*4882a593Smuzhiyun }
1658*4882a593Smuzhiyun
1659*4882a593Smuzhiyun /* The firmware will fill in the rate information
1660*4882a593Smuzhiyun * for each packet that gets queued in the hardware
1661*4882a593Smuzhiyun * and these macros will interpret that info.
1662*4882a593Smuzhiyun */
1663*4882a593Smuzhiyun
1664*4882a593Smuzhiyun #define RI_FORMAT(a) (a & 0x0001)
1665*4882a593Smuzhiyun #define RI_RATE_ID_MCS(a) ((a & 0x01f8) >> 3)
1666*4882a593Smuzhiyun
1667*4882a593Smuzhiyun static int
mwl8k_txq_reclaim(struct ieee80211_hw * hw,int index,int limit,int force)1668*4882a593Smuzhiyun mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int limit, int force)
1669*4882a593Smuzhiyun {
1670*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
1671*4882a593Smuzhiyun struct mwl8k_tx_queue *txq = priv->txq + index;
1672*4882a593Smuzhiyun int processed;
1673*4882a593Smuzhiyun
1674*4882a593Smuzhiyun processed = 0;
1675*4882a593Smuzhiyun while (txq->len > 0 && limit--) {
1676*4882a593Smuzhiyun int tx;
1677*4882a593Smuzhiyun struct mwl8k_tx_desc *tx_desc;
1678*4882a593Smuzhiyun unsigned long addr;
1679*4882a593Smuzhiyun int size;
1680*4882a593Smuzhiyun struct sk_buff *skb;
1681*4882a593Smuzhiyun struct ieee80211_tx_info *info;
1682*4882a593Smuzhiyun u32 status;
1683*4882a593Smuzhiyun struct ieee80211_sta *sta;
1684*4882a593Smuzhiyun struct mwl8k_sta *sta_info = NULL;
1685*4882a593Smuzhiyun u16 rate_info;
1686*4882a593Smuzhiyun struct ieee80211_hdr *wh;
1687*4882a593Smuzhiyun
1688*4882a593Smuzhiyun tx = txq->head;
1689*4882a593Smuzhiyun tx_desc = txq->txd + tx;
1690*4882a593Smuzhiyun
1691*4882a593Smuzhiyun status = le32_to_cpu(tx_desc->status);
1692*4882a593Smuzhiyun
1693*4882a593Smuzhiyun if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1694*4882a593Smuzhiyun if (!force)
1695*4882a593Smuzhiyun break;
1696*4882a593Smuzhiyun tx_desc->status &=
1697*4882a593Smuzhiyun ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1698*4882a593Smuzhiyun }
1699*4882a593Smuzhiyun
1700*4882a593Smuzhiyun txq->head = (tx + 1) % MWL8K_TX_DESCS;
1701*4882a593Smuzhiyun BUG_ON(txq->len == 0);
1702*4882a593Smuzhiyun txq->len--;
1703*4882a593Smuzhiyun priv->pending_tx_pkts--;
1704*4882a593Smuzhiyun
1705*4882a593Smuzhiyun addr = le32_to_cpu(tx_desc->pkt_phys_addr);
1706*4882a593Smuzhiyun size = le16_to_cpu(tx_desc->pkt_len);
1707*4882a593Smuzhiyun skb = txq->skb[tx];
1708*4882a593Smuzhiyun txq->skb[tx] = NULL;
1709*4882a593Smuzhiyun
1710*4882a593Smuzhiyun BUG_ON(skb == NULL);
1711*4882a593Smuzhiyun pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1712*4882a593Smuzhiyun
1713*4882a593Smuzhiyun mwl8k_remove_dma_header(skb, tx_desc->qos_control);
1714*4882a593Smuzhiyun
1715*4882a593Smuzhiyun wh = (struct ieee80211_hdr *) skb->data;
1716*4882a593Smuzhiyun
1717*4882a593Smuzhiyun /* Mark descriptor as unused */
1718*4882a593Smuzhiyun tx_desc->pkt_phys_addr = 0;
1719*4882a593Smuzhiyun tx_desc->pkt_len = 0;
1720*4882a593Smuzhiyun
1721*4882a593Smuzhiyun info = IEEE80211_SKB_CB(skb);
1722*4882a593Smuzhiyun if (ieee80211_is_data(wh->frame_control)) {
1723*4882a593Smuzhiyun rcu_read_lock();
1724*4882a593Smuzhiyun sta = ieee80211_find_sta_by_ifaddr(hw, wh->addr1,
1725*4882a593Smuzhiyun wh->addr2);
1726*4882a593Smuzhiyun if (sta) {
1727*4882a593Smuzhiyun sta_info = MWL8K_STA(sta);
1728*4882a593Smuzhiyun BUG_ON(sta_info == NULL);
1729*4882a593Smuzhiyun rate_info = le16_to_cpu(tx_desc->rate_info);
1730*4882a593Smuzhiyun /* If rate is < 6.5 Mpbs for an ht station
1731*4882a593Smuzhiyun * do not form an ampdu. If the station is a
1732*4882a593Smuzhiyun * legacy station (format = 0), do not form an
1733*4882a593Smuzhiyun * ampdu
1734*4882a593Smuzhiyun */
1735*4882a593Smuzhiyun if (RI_RATE_ID_MCS(rate_info) < 1 ||
1736*4882a593Smuzhiyun RI_FORMAT(rate_info) == 0) {
1737*4882a593Smuzhiyun sta_info->is_ampdu_allowed = false;
1738*4882a593Smuzhiyun } else {
1739*4882a593Smuzhiyun sta_info->is_ampdu_allowed = true;
1740*4882a593Smuzhiyun }
1741*4882a593Smuzhiyun }
1742*4882a593Smuzhiyun rcu_read_unlock();
1743*4882a593Smuzhiyun }
1744*4882a593Smuzhiyun
1745*4882a593Smuzhiyun ieee80211_tx_info_clear_status(info);
1746*4882a593Smuzhiyun
1747*4882a593Smuzhiyun /* Rate control is happening in the firmware.
1748*4882a593Smuzhiyun * Ensure no tx rate is being reported.
1749*4882a593Smuzhiyun */
1750*4882a593Smuzhiyun info->status.rates[0].idx = -1;
1751*4882a593Smuzhiyun info->status.rates[0].count = 1;
1752*4882a593Smuzhiyun
1753*4882a593Smuzhiyun if (MWL8K_TXD_SUCCESS(status))
1754*4882a593Smuzhiyun info->flags |= IEEE80211_TX_STAT_ACK;
1755*4882a593Smuzhiyun
1756*4882a593Smuzhiyun ieee80211_tx_status_irqsafe(hw, skb);
1757*4882a593Smuzhiyun
1758*4882a593Smuzhiyun processed++;
1759*4882a593Smuzhiyun }
1760*4882a593Smuzhiyun
1761*4882a593Smuzhiyun return processed;
1762*4882a593Smuzhiyun }
1763*4882a593Smuzhiyun
1764*4882a593Smuzhiyun /* must be called only when the card's transmit is completely halted */
mwl8k_txq_deinit(struct ieee80211_hw * hw,int index)1765*4882a593Smuzhiyun static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1766*4882a593Smuzhiyun {
1767*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
1768*4882a593Smuzhiyun struct mwl8k_tx_queue *txq = priv->txq + index;
1769*4882a593Smuzhiyun
1770*4882a593Smuzhiyun if (txq->txd == NULL)
1771*4882a593Smuzhiyun return;
1772*4882a593Smuzhiyun
1773*4882a593Smuzhiyun mwl8k_txq_reclaim(hw, index, INT_MAX, 1);
1774*4882a593Smuzhiyun
1775*4882a593Smuzhiyun kfree(txq->skb);
1776*4882a593Smuzhiyun txq->skb = NULL;
1777*4882a593Smuzhiyun
1778*4882a593Smuzhiyun pci_free_consistent(priv->pdev,
1779*4882a593Smuzhiyun MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
1780*4882a593Smuzhiyun txq->txd, txq->txd_dma);
1781*4882a593Smuzhiyun txq->txd = NULL;
1782*4882a593Smuzhiyun }
1783*4882a593Smuzhiyun
1784*4882a593Smuzhiyun /* caller must hold priv->stream_lock when calling the stream functions */
1785*4882a593Smuzhiyun static struct mwl8k_ampdu_stream *
mwl8k_add_stream(struct ieee80211_hw * hw,struct ieee80211_sta * sta,u8 tid)1786*4882a593Smuzhiyun mwl8k_add_stream(struct ieee80211_hw *hw, struct ieee80211_sta *sta, u8 tid)
1787*4882a593Smuzhiyun {
1788*4882a593Smuzhiyun struct mwl8k_ampdu_stream *stream;
1789*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
1790*4882a593Smuzhiyun int i;
1791*4882a593Smuzhiyun
1792*4882a593Smuzhiyun for (i = 0; i < MWL8K_NUM_AMPDU_STREAMS; i++) {
1793*4882a593Smuzhiyun stream = &priv->ampdu[i];
1794*4882a593Smuzhiyun if (stream->state == AMPDU_NO_STREAM) {
1795*4882a593Smuzhiyun stream->sta = sta;
1796*4882a593Smuzhiyun stream->state = AMPDU_STREAM_NEW;
1797*4882a593Smuzhiyun stream->tid = tid;
1798*4882a593Smuzhiyun stream->idx = i;
1799*4882a593Smuzhiyun wiphy_debug(hw->wiphy, "Added a new stream for %pM %d",
1800*4882a593Smuzhiyun sta->addr, tid);
1801*4882a593Smuzhiyun return stream;
1802*4882a593Smuzhiyun }
1803*4882a593Smuzhiyun }
1804*4882a593Smuzhiyun return NULL;
1805*4882a593Smuzhiyun }
1806*4882a593Smuzhiyun
1807*4882a593Smuzhiyun static int
mwl8k_start_stream(struct ieee80211_hw * hw,struct mwl8k_ampdu_stream * stream)1808*4882a593Smuzhiyun mwl8k_start_stream(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream)
1809*4882a593Smuzhiyun {
1810*4882a593Smuzhiyun int ret;
1811*4882a593Smuzhiyun
1812*4882a593Smuzhiyun /* if the stream has already been started, don't start it again */
1813*4882a593Smuzhiyun if (stream->state != AMPDU_STREAM_NEW)
1814*4882a593Smuzhiyun return 0;
1815*4882a593Smuzhiyun ret = ieee80211_start_tx_ba_session(stream->sta, stream->tid, 0);
1816*4882a593Smuzhiyun if (ret)
1817*4882a593Smuzhiyun wiphy_debug(hw->wiphy, "Failed to start stream for %pM %d: "
1818*4882a593Smuzhiyun "%d\n", stream->sta->addr, stream->tid, ret);
1819*4882a593Smuzhiyun else
1820*4882a593Smuzhiyun wiphy_debug(hw->wiphy, "Started stream for %pM %d\n",
1821*4882a593Smuzhiyun stream->sta->addr, stream->tid);
1822*4882a593Smuzhiyun return ret;
1823*4882a593Smuzhiyun }
1824*4882a593Smuzhiyun
1825*4882a593Smuzhiyun static void
mwl8k_remove_stream(struct ieee80211_hw * hw,struct mwl8k_ampdu_stream * stream)1826*4882a593Smuzhiyun mwl8k_remove_stream(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream)
1827*4882a593Smuzhiyun {
1828*4882a593Smuzhiyun wiphy_debug(hw->wiphy, "Remove stream for %pM %d\n", stream->sta->addr,
1829*4882a593Smuzhiyun stream->tid);
1830*4882a593Smuzhiyun memset(stream, 0, sizeof(*stream));
1831*4882a593Smuzhiyun }
1832*4882a593Smuzhiyun
1833*4882a593Smuzhiyun static struct mwl8k_ampdu_stream *
mwl8k_lookup_stream(struct ieee80211_hw * hw,u8 * addr,u8 tid)1834*4882a593Smuzhiyun mwl8k_lookup_stream(struct ieee80211_hw *hw, u8 *addr, u8 tid)
1835*4882a593Smuzhiyun {
1836*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
1837*4882a593Smuzhiyun int i;
1838*4882a593Smuzhiyun
1839*4882a593Smuzhiyun for (i = 0; i < MWL8K_NUM_AMPDU_STREAMS; i++) {
1840*4882a593Smuzhiyun struct mwl8k_ampdu_stream *stream;
1841*4882a593Smuzhiyun stream = &priv->ampdu[i];
1842*4882a593Smuzhiyun if (stream->state == AMPDU_NO_STREAM)
1843*4882a593Smuzhiyun continue;
1844*4882a593Smuzhiyun if (!memcmp(stream->sta->addr, addr, ETH_ALEN) &&
1845*4882a593Smuzhiyun stream->tid == tid)
1846*4882a593Smuzhiyun return stream;
1847*4882a593Smuzhiyun }
1848*4882a593Smuzhiyun return NULL;
1849*4882a593Smuzhiyun }
1850*4882a593Smuzhiyun
1851*4882a593Smuzhiyun #define MWL8K_AMPDU_PACKET_THRESHOLD 64
mwl8k_ampdu_allowed(struct ieee80211_sta * sta,u8 tid)1852*4882a593Smuzhiyun static inline bool mwl8k_ampdu_allowed(struct ieee80211_sta *sta, u8 tid)
1853*4882a593Smuzhiyun {
1854*4882a593Smuzhiyun struct mwl8k_sta *sta_info = MWL8K_STA(sta);
1855*4882a593Smuzhiyun struct tx_traffic_info *tx_stats;
1856*4882a593Smuzhiyun
1857*4882a593Smuzhiyun BUG_ON(tid >= MWL8K_MAX_TID);
1858*4882a593Smuzhiyun tx_stats = &sta_info->tx_stats[tid];
1859*4882a593Smuzhiyun
1860*4882a593Smuzhiyun return sta_info->is_ampdu_allowed &&
1861*4882a593Smuzhiyun tx_stats->pkts > MWL8K_AMPDU_PACKET_THRESHOLD;
1862*4882a593Smuzhiyun }
1863*4882a593Smuzhiyun
mwl8k_tx_count_packet(struct ieee80211_sta * sta,u8 tid)1864*4882a593Smuzhiyun static inline void mwl8k_tx_count_packet(struct ieee80211_sta *sta, u8 tid)
1865*4882a593Smuzhiyun {
1866*4882a593Smuzhiyun struct mwl8k_sta *sta_info = MWL8K_STA(sta);
1867*4882a593Smuzhiyun struct tx_traffic_info *tx_stats;
1868*4882a593Smuzhiyun
1869*4882a593Smuzhiyun BUG_ON(tid >= MWL8K_MAX_TID);
1870*4882a593Smuzhiyun tx_stats = &sta_info->tx_stats[tid];
1871*4882a593Smuzhiyun
1872*4882a593Smuzhiyun if (tx_stats->start_time == 0)
1873*4882a593Smuzhiyun tx_stats->start_time = jiffies;
1874*4882a593Smuzhiyun
1875*4882a593Smuzhiyun /* reset the packet count after each second elapses. If the number of
1876*4882a593Smuzhiyun * packets ever exceeds the ampdu_min_traffic threshold, we will allow
1877*4882a593Smuzhiyun * an ampdu stream to be started.
1878*4882a593Smuzhiyun */
1879*4882a593Smuzhiyun if (jiffies - tx_stats->start_time > HZ) {
1880*4882a593Smuzhiyun tx_stats->pkts = 0;
1881*4882a593Smuzhiyun tx_stats->start_time = 0;
1882*4882a593Smuzhiyun } else
1883*4882a593Smuzhiyun tx_stats->pkts++;
1884*4882a593Smuzhiyun }
1885*4882a593Smuzhiyun
1886*4882a593Smuzhiyun /* The hardware ampdu queues start from 5.
1887*4882a593Smuzhiyun * txpriorities for ampdu queues are
1888*4882a593Smuzhiyun * 5 6 7 0 1 2 3 4 ie., queue 5 is highest
1889*4882a593Smuzhiyun * and queue 3 is lowest (queue 4 is reserved)
1890*4882a593Smuzhiyun */
1891*4882a593Smuzhiyun #define BA_QUEUE 5
1892*4882a593Smuzhiyun
1893*4882a593Smuzhiyun static void
mwl8k_txq_xmit(struct ieee80211_hw * hw,int index,struct ieee80211_sta * sta,struct sk_buff * skb)1894*4882a593Smuzhiyun mwl8k_txq_xmit(struct ieee80211_hw *hw,
1895*4882a593Smuzhiyun int index,
1896*4882a593Smuzhiyun struct ieee80211_sta *sta,
1897*4882a593Smuzhiyun struct sk_buff *skb)
1898*4882a593Smuzhiyun {
1899*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
1900*4882a593Smuzhiyun struct ieee80211_tx_info *tx_info;
1901*4882a593Smuzhiyun struct mwl8k_vif *mwl8k_vif;
1902*4882a593Smuzhiyun struct ieee80211_hdr *wh;
1903*4882a593Smuzhiyun struct mwl8k_tx_queue *txq;
1904*4882a593Smuzhiyun struct mwl8k_tx_desc *tx;
1905*4882a593Smuzhiyun dma_addr_t dma;
1906*4882a593Smuzhiyun u32 txstatus;
1907*4882a593Smuzhiyun u8 txdatarate;
1908*4882a593Smuzhiyun u16 qos;
1909*4882a593Smuzhiyun int txpriority;
1910*4882a593Smuzhiyun u8 tid = 0;
1911*4882a593Smuzhiyun struct mwl8k_ampdu_stream *stream = NULL;
1912*4882a593Smuzhiyun bool start_ba_session = false;
1913*4882a593Smuzhiyun bool mgmtframe = false;
1914*4882a593Smuzhiyun struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1915*4882a593Smuzhiyun bool eapol_frame = false;
1916*4882a593Smuzhiyun
1917*4882a593Smuzhiyun wh = (struct ieee80211_hdr *)skb->data;
1918*4882a593Smuzhiyun if (ieee80211_is_data_qos(wh->frame_control))
1919*4882a593Smuzhiyun qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1920*4882a593Smuzhiyun else
1921*4882a593Smuzhiyun qos = 0;
1922*4882a593Smuzhiyun
1923*4882a593Smuzhiyun if (skb->protocol == cpu_to_be16(ETH_P_PAE))
1924*4882a593Smuzhiyun eapol_frame = true;
1925*4882a593Smuzhiyun
1926*4882a593Smuzhiyun if (ieee80211_is_mgmt(wh->frame_control))
1927*4882a593Smuzhiyun mgmtframe = true;
1928*4882a593Smuzhiyun
1929*4882a593Smuzhiyun if (priv->ap_fw)
1930*4882a593Smuzhiyun mwl8k_encapsulate_tx_frame(priv, skb);
1931*4882a593Smuzhiyun else
1932*4882a593Smuzhiyun mwl8k_add_dma_header(priv, skb, 0, 0);
1933*4882a593Smuzhiyun
1934*4882a593Smuzhiyun wh = &((struct mwl8k_dma_data *)skb->data)->wh;
1935*4882a593Smuzhiyun
1936*4882a593Smuzhiyun tx_info = IEEE80211_SKB_CB(skb);
1937*4882a593Smuzhiyun mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
1938*4882a593Smuzhiyun
1939*4882a593Smuzhiyun if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1940*4882a593Smuzhiyun wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1941*4882a593Smuzhiyun wh->seq_ctrl |= cpu_to_le16(mwl8k_vif->seqno);
1942*4882a593Smuzhiyun mwl8k_vif->seqno += 0x10;
1943*4882a593Smuzhiyun }
1944*4882a593Smuzhiyun
1945*4882a593Smuzhiyun /* Setup firmware control bit fields for each frame type. */
1946*4882a593Smuzhiyun txstatus = 0;
1947*4882a593Smuzhiyun txdatarate = 0;
1948*4882a593Smuzhiyun if (ieee80211_is_mgmt(wh->frame_control) ||
1949*4882a593Smuzhiyun ieee80211_is_ctl(wh->frame_control)) {
1950*4882a593Smuzhiyun txdatarate = 0;
1951*4882a593Smuzhiyun qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP;
1952*4882a593Smuzhiyun } else if (ieee80211_is_data(wh->frame_control)) {
1953*4882a593Smuzhiyun txdatarate = 1;
1954*4882a593Smuzhiyun if (is_multicast_ether_addr(wh->addr1))
1955*4882a593Smuzhiyun txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1956*4882a593Smuzhiyun
1957*4882a593Smuzhiyun qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
1958*4882a593Smuzhiyun if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1959*4882a593Smuzhiyun qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK;
1960*4882a593Smuzhiyun else
1961*4882a593Smuzhiyun qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
1962*4882a593Smuzhiyun }
1963*4882a593Smuzhiyun
1964*4882a593Smuzhiyun /* Queue ADDBA request in the respective data queue. While setting up
1965*4882a593Smuzhiyun * the ampdu stream, mac80211 queues further packets for that
1966*4882a593Smuzhiyun * particular ra/tid pair. However, packets piled up in the hardware
1967*4882a593Smuzhiyun * for that ra/tid pair will still go out. ADDBA request and the
1968*4882a593Smuzhiyun * related data packets going out from different queues asynchronously
1969*4882a593Smuzhiyun * will cause a shift in the receiver window which might result in
1970*4882a593Smuzhiyun * ampdu packets getting dropped at the receiver after the stream has
1971*4882a593Smuzhiyun * been setup.
1972*4882a593Smuzhiyun */
1973*4882a593Smuzhiyun if (unlikely(ieee80211_is_action(wh->frame_control) &&
1974*4882a593Smuzhiyun mgmt->u.action.category == WLAN_CATEGORY_BACK &&
1975*4882a593Smuzhiyun mgmt->u.action.u.addba_req.action_code == WLAN_ACTION_ADDBA_REQ &&
1976*4882a593Smuzhiyun priv->ap_fw)) {
1977*4882a593Smuzhiyun u16 capab = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
1978*4882a593Smuzhiyun tid = (capab & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2;
1979*4882a593Smuzhiyun index = mwl8k_tid_queue_mapping(tid);
1980*4882a593Smuzhiyun }
1981*4882a593Smuzhiyun
1982*4882a593Smuzhiyun txpriority = index;
1983*4882a593Smuzhiyun
1984*4882a593Smuzhiyun if (priv->ap_fw && sta && sta->ht_cap.ht_supported && !eapol_frame &&
1985*4882a593Smuzhiyun ieee80211_is_data_qos(wh->frame_control)) {
1986*4882a593Smuzhiyun tid = qos & 0xf;
1987*4882a593Smuzhiyun mwl8k_tx_count_packet(sta, tid);
1988*4882a593Smuzhiyun spin_lock(&priv->stream_lock);
1989*4882a593Smuzhiyun stream = mwl8k_lookup_stream(hw, sta->addr, tid);
1990*4882a593Smuzhiyun if (stream != NULL) {
1991*4882a593Smuzhiyun if (stream->state == AMPDU_STREAM_ACTIVE) {
1992*4882a593Smuzhiyun WARN_ON(!(qos & MWL8K_QOS_ACK_POLICY_BLOCKACK));
1993*4882a593Smuzhiyun txpriority = (BA_QUEUE + stream->idx) %
1994*4882a593Smuzhiyun TOTAL_HW_TX_QUEUES;
1995*4882a593Smuzhiyun if (stream->idx <= 1)
1996*4882a593Smuzhiyun index = stream->idx +
1997*4882a593Smuzhiyun MWL8K_TX_WMM_QUEUES;
1998*4882a593Smuzhiyun
1999*4882a593Smuzhiyun } else if (stream->state == AMPDU_STREAM_NEW) {
2000*4882a593Smuzhiyun /* We get here if the driver sends us packets
2001*4882a593Smuzhiyun * after we've initiated a stream, but before
2002*4882a593Smuzhiyun * our ampdu_action routine has been called
2003*4882a593Smuzhiyun * with IEEE80211_AMPDU_TX_START to get the SSN
2004*4882a593Smuzhiyun * for the ADDBA request. So this packet can
2005*4882a593Smuzhiyun * go out with no risk of sequence number
2006*4882a593Smuzhiyun * mismatch. No special handling is required.
2007*4882a593Smuzhiyun */
2008*4882a593Smuzhiyun } else {
2009*4882a593Smuzhiyun /* Drop packets that would go out after the
2010*4882a593Smuzhiyun * ADDBA request was sent but before the ADDBA
2011*4882a593Smuzhiyun * response is received. If we don't do this,
2012*4882a593Smuzhiyun * the recipient would probably receive it
2013*4882a593Smuzhiyun * after the ADDBA request with SSN 0. This
2014*4882a593Smuzhiyun * will cause the recipient's BA receive window
2015*4882a593Smuzhiyun * to shift, which would cause the subsequent
2016*4882a593Smuzhiyun * packets in the BA stream to be discarded.
2017*4882a593Smuzhiyun * mac80211 queues our packets for us in this
2018*4882a593Smuzhiyun * case, so this is really just a safety check.
2019*4882a593Smuzhiyun */
2020*4882a593Smuzhiyun wiphy_warn(hw->wiphy,
2021*4882a593Smuzhiyun "Cannot send packet while ADDBA "
2022*4882a593Smuzhiyun "dialog is underway.\n");
2023*4882a593Smuzhiyun spin_unlock(&priv->stream_lock);
2024*4882a593Smuzhiyun dev_kfree_skb(skb);
2025*4882a593Smuzhiyun return;
2026*4882a593Smuzhiyun }
2027*4882a593Smuzhiyun } else {
2028*4882a593Smuzhiyun /* Defer calling mwl8k_start_stream so that the current
2029*4882a593Smuzhiyun * skb can go out before the ADDBA request. This
2030*4882a593Smuzhiyun * prevents sequence number mismatch at the recepient
2031*4882a593Smuzhiyun * as described above.
2032*4882a593Smuzhiyun */
2033*4882a593Smuzhiyun if (mwl8k_ampdu_allowed(sta, tid)) {
2034*4882a593Smuzhiyun stream = mwl8k_add_stream(hw, sta, tid);
2035*4882a593Smuzhiyun if (stream != NULL)
2036*4882a593Smuzhiyun start_ba_session = true;
2037*4882a593Smuzhiyun }
2038*4882a593Smuzhiyun }
2039*4882a593Smuzhiyun spin_unlock(&priv->stream_lock);
2040*4882a593Smuzhiyun } else {
2041*4882a593Smuzhiyun qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
2042*4882a593Smuzhiyun qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
2043*4882a593Smuzhiyun }
2044*4882a593Smuzhiyun
2045*4882a593Smuzhiyun dma = pci_map_single(priv->pdev, skb->data,
2046*4882a593Smuzhiyun skb->len, PCI_DMA_TODEVICE);
2047*4882a593Smuzhiyun
2048*4882a593Smuzhiyun if (pci_dma_mapping_error(priv->pdev, dma)) {
2049*4882a593Smuzhiyun wiphy_debug(hw->wiphy,
2050*4882a593Smuzhiyun "failed to dma map skb, dropping TX frame.\n");
2051*4882a593Smuzhiyun if (start_ba_session) {
2052*4882a593Smuzhiyun spin_lock(&priv->stream_lock);
2053*4882a593Smuzhiyun mwl8k_remove_stream(hw, stream);
2054*4882a593Smuzhiyun spin_unlock(&priv->stream_lock);
2055*4882a593Smuzhiyun }
2056*4882a593Smuzhiyun dev_kfree_skb(skb);
2057*4882a593Smuzhiyun return;
2058*4882a593Smuzhiyun }
2059*4882a593Smuzhiyun
2060*4882a593Smuzhiyun spin_lock_bh(&priv->tx_lock);
2061*4882a593Smuzhiyun
2062*4882a593Smuzhiyun txq = priv->txq + index;
2063*4882a593Smuzhiyun
2064*4882a593Smuzhiyun /* Mgmt frames that go out frequently are probe
2065*4882a593Smuzhiyun * responses. Other mgmt frames got out relatively
2066*4882a593Smuzhiyun * infrequently. Hence reserve 2 buffers so that
2067*4882a593Smuzhiyun * other mgmt frames do not get dropped due to an
2068*4882a593Smuzhiyun * already queued probe response in one of the
2069*4882a593Smuzhiyun * reserved buffers.
2070*4882a593Smuzhiyun */
2071*4882a593Smuzhiyun
2072*4882a593Smuzhiyun if (txq->len >= MWL8K_TX_DESCS - 2) {
2073*4882a593Smuzhiyun if (!mgmtframe || txq->len == MWL8K_TX_DESCS) {
2074*4882a593Smuzhiyun if (start_ba_session) {
2075*4882a593Smuzhiyun spin_lock(&priv->stream_lock);
2076*4882a593Smuzhiyun mwl8k_remove_stream(hw, stream);
2077*4882a593Smuzhiyun spin_unlock(&priv->stream_lock);
2078*4882a593Smuzhiyun }
2079*4882a593Smuzhiyun mwl8k_tx_start(priv);
2080*4882a593Smuzhiyun spin_unlock_bh(&priv->tx_lock);
2081*4882a593Smuzhiyun pci_unmap_single(priv->pdev, dma, skb->len,
2082*4882a593Smuzhiyun PCI_DMA_TODEVICE);
2083*4882a593Smuzhiyun dev_kfree_skb(skb);
2084*4882a593Smuzhiyun return;
2085*4882a593Smuzhiyun }
2086*4882a593Smuzhiyun }
2087*4882a593Smuzhiyun
2088*4882a593Smuzhiyun BUG_ON(txq->skb[txq->tail] != NULL);
2089*4882a593Smuzhiyun txq->skb[txq->tail] = skb;
2090*4882a593Smuzhiyun
2091*4882a593Smuzhiyun tx = txq->txd + txq->tail;
2092*4882a593Smuzhiyun tx->data_rate = txdatarate;
2093*4882a593Smuzhiyun tx->tx_priority = txpriority;
2094*4882a593Smuzhiyun tx->qos_control = cpu_to_le16(qos);
2095*4882a593Smuzhiyun tx->pkt_phys_addr = cpu_to_le32(dma);
2096*4882a593Smuzhiyun tx->pkt_len = cpu_to_le16(skb->len);
2097*4882a593Smuzhiyun tx->rate_info = 0;
2098*4882a593Smuzhiyun if (!priv->ap_fw && sta != NULL)
2099*4882a593Smuzhiyun tx->peer_id = MWL8K_STA(sta)->peer_id;
2100*4882a593Smuzhiyun else
2101*4882a593Smuzhiyun tx->peer_id = 0;
2102*4882a593Smuzhiyun
2103*4882a593Smuzhiyun if (priv->ap_fw && ieee80211_is_data(wh->frame_control) && !eapol_frame)
2104*4882a593Smuzhiyun tx->timestamp = cpu_to_le32(ioread32(priv->regs +
2105*4882a593Smuzhiyun MWL8K_HW_TIMER_REGISTER));
2106*4882a593Smuzhiyun else
2107*4882a593Smuzhiyun tx->timestamp = 0;
2108*4882a593Smuzhiyun
2109*4882a593Smuzhiyun wmb();
2110*4882a593Smuzhiyun tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
2111*4882a593Smuzhiyun
2112*4882a593Smuzhiyun txq->len++;
2113*4882a593Smuzhiyun priv->pending_tx_pkts++;
2114*4882a593Smuzhiyun
2115*4882a593Smuzhiyun txq->tail++;
2116*4882a593Smuzhiyun if (txq->tail == MWL8K_TX_DESCS)
2117*4882a593Smuzhiyun txq->tail = 0;
2118*4882a593Smuzhiyun
2119*4882a593Smuzhiyun mwl8k_tx_start(priv);
2120*4882a593Smuzhiyun
2121*4882a593Smuzhiyun spin_unlock_bh(&priv->tx_lock);
2122*4882a593Smuzhiyun
2123*4882a593Smuzhiyun /* Initiate the ampdu session here */
2124*4882a593Smuzhiyun if (start_ba_session) {
2125*4882a593Smuzhiyun spin_lock(&priv->stream_lock);
2126*4882a593Smuzhiyun if (mwl8k_start_stream(hw, stream))
2127*4882a593Smuzhiyun mwl8k_remove_stream(hw, stream);
2128*4882a593Smuzhiyun spin_unlock(&priv->stream_lock);
2129*4882a593Smuzhiyun }
2130*4882a593Smuzhiyun }
2131*4882a593Smuzhiyun
2132*4882a593Smuzhiyun
2133*4882a593Smuzhiyun /*
2134*4882a593Smuzhiyun * Firmware access.
2135*4882a593Smuzhiyun *
2136*4882a593Smuzhiyun * We have the following requirements for issuing firmware commands:
2137*4882a593Smuzhiyun * - Some commands require that the packet transmit path is idle when
2138*4882a593Smuzhiyun * the command is issued. (For simplicity, we'll just quiesce the
2139*4882a593Smuzhiyun * transmit path for every command.)
2140*4882a593Smuzhiyun * - There are certain sequences of commands that need to be issued to
2141*4882a593Smuzhiyun * the hardware sequentially, with no other intervening commands.
2142*4882a593Smuzhiyun *
2143*4882a593Smuzhiyun * This leads to an implementation of a "firmware lock" as a mutex that
2144*4882a593Smuzhiyun * can be taken recursively, and which is taken by both the low-level
2145*4882a593Smuzhiyun * command submission function (mwl8k_post_cmd) as well as any users of
2146*4882a593Smuzhiyun * that function that require issuing of an atomic sequence of commands,
2147*4882a593Smuzhiyun * and quiesces the transmit path whenever it's taken.
2148*4882a593Smuzhiyun */
mwl8k_fw_lock(struct ieee80211_hw * hw)2149*4882a593Smuzhiyun static int mwl8k_fw_lock(struct ieee80211_hw *hw)
2150*4882a593Smuzhiyun {
2151*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
2152*4882a593Smuzhiyun
2153*4882a593Smuzhiyun if (priv->fw_mutex_owner != current) {
2154*4882a593Smuzhiyun int rc;
2155*4882a593Smuzhiyun
2156*4882a593Smuzhiyun mutex_lock(&priv->fw_mutex);
2157*4882a593Smuzhiyun ieee80211_stop_queues(hw);
2158*4882a593Smuzhiyun
2159*4882a593Smuzhiyun rc = mwl8k_tx_wait_empty(hw);
2160*4882a593Smuzhiyun if (rc) {
2161*4882a593Smuzhiyun if (!priv->hw_restart_in_progress)
2162*4882a593Smuzhiyun ieee80211_wake_queues(hw);
2163*4882a593Smuzhiyun
2164*4882a593Smuzhiyun mutex_unlock(&priv->fw_mutex);
2165*4882a593Smuzhiyun
2166*4882a593Smuzhiyun return rc;
2167*4882a593Smuzhiyun }
2168*4882a593Smuzhiyun
2169*4882a593Smuzhiyun priv->fw_mutex_owner = current;
2170*4882a593Smuzhiyun }
2171*4882a593Smuzhiyun
2172*4882a593Smuzhiyun priv->fw_mutex_depth++;
2173*4882a593Smuzhiyun
2174*4882a593Smuzhiyun return 0;
2175*4882a593Smuzhiyun }
2176*4882a593Smuzhiyun
mwl8k_fw_unlock(struct ieee80211_hw * hw)2177*4882a593Smuzhiyun static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
2178*4882a593Smuzhiyun {
2179*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
2180*4882a593Smuzhiyun
2181*4882a593Smuzhiyun if (!--priv->fw_mutex_depth) {
2182*4882a593Smuzhiyun if (!priv->hw_restart_in_progress)
2183*4882a593Smuzhiyun ieee80211_wake_queues(hw);
2184*4882a593Smuzhiyun
2185*4882a593Smuzhiyun priv->fw_mutex_owner = NULL;
2186*4882a593Smuzhiyun mutex_unlock(&priv->fw_mutex);
2187*4882a593Smuzhiyun }
2188*4882a593Smuzhiyun }
2189*4882a593Smuzhiyun
2190*4882a593Smuzhiyun static void mwl8k_enable_bsses(struct ieee80211_hw *hw, bool enable,
2191*4882a593Smuzhiyun u32 bitmap);
2192*4882a593Smuzhiyun
2193*4882a593Smuzhiyun /*
2194*4882a593Smuzhiyun * Command processing.
2195*4882a593Smuzhiyun */
2196*4882a593Smuzhiyun
2197*4882a593Smuzhiyun /* Timeout firmware commands after 10s */
2198*4882a593Smuzhiyun #define MWL8K_CMD_TIMEOUT_MS 10000
2199*4882a593Smuzhiyun
mwl8k_post_cmd(struct ieee80211_hw * hw,struct mwl8k_cmd_pkt * cmd)2200*4882a593Smuzhiyun static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
2201*4882a593Smuzhiyun {
2202*4882a593Smuzhiyun DECLARE_COMPLETION_ONSTACK(cmd_wait);
2203*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
2204*4882a593Smuzhiyun void __iomem *regs = priv->regs;
2205*4882a593Smuzhiyun dma_addr_t dma_addr;
2206*4882a593Smuzhiyun unsigned int dma_size;
2207*4882a593Smuzhiyun int rc;
2208*4882a593Smuzhiyun unsigned long timeout = 0;
2209*4882a593Smuzhiyun u8 buf[32];
2210*4882a593Smuzhiyun u32 bitmap = 0;
2211*4882a593Smuzhiyun
2212*4882a593Smuzhiyun wiphy_dbg(hw->wiphy, "Posting %s [%d]\n",
2213*4882a593Smuzhiyun mwl8k_cmd_name(cmd->code, buf, sizeof(buf)), cmd->macid);
2214*4882a593Smuzhiyun
2215*4882a593Smuzhiyun /* Before posting firmware commands that could change the hardware
2216*4882a593Smuzhiyun * characteristics, make sure that all BSSes are stopped temporary.
2217*4882a593Smuzhiyun * Enable these stopped BSSes after completion of the commands
2218*4882a593Smuzhiyun */
2219*4882a593Smuzhiyun
2220*4882a593Smuzhiyun rc = mwl8k_fw_lock(hw);
2221*4882a593Smuzhiyun if (rc)
2222*4882a593Smuzhiyun return rc;
2223*4882a593Smuzhiyun
2224*4882a593Smuzhiyun if (priv->ap_fw && priv->running_bsses) {
2225*4882a593Smuzhiyun switch (le16_to_cpu(cmd->code)) {
2226*4882a593Smuzhiyun case MWL8K_CMD_SET_RF_CHANNEL:
2227*4882a593Smuzhiyun case MWL8K_CMD_RADIO_CONTROL:
2228*4882a593Smuzhiyun case MWL8K_CMD_RF_TX_POWER:
2229*4882a593Smuzhiyun case MWL8K_CMD_TX_POWER:
2230*4882a593Smuzhiyun case MWL8K_CMD_RF_ANTENNA:
2231*4882a593Smuzhiyun case MWL8K_CMD_RTS_THRESHOLD:
2232*4882a593Smuzhiyun case MWL8K_CMD_MIMO_CONFIG:
2233*4882a593Smuzhiyun bitmap = priv->running_bsses;
2234*4882a593Smuzhiyun mwl8k_enable_bsses(hw, false, bitmap);
2235*4882a593Smuzhiyun break;
2236*4882a593Smuzhiyun }
2237*4882a593Smuzhiyun }
2238*4882a593Smuzhiyun
2239*4882a593Smuzhiyun cmd->result = (__force __le16) 0xffff;
2240*4882a593Smuzhiyun dma_size = le16_to_cpu(cmd->length);
2241*4882a593Smuzhiyun dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
2242*4882a593Smuzhiyun PCI_DMA_BIDIRECTIONAL);
2243*4882a593Smuzhiyun if (pci_dma_mapping_error(priv->pdev, dma_addr)) {
2244*4882a593Smuzhiyun rc = -ENOMEM;
2245*4882a593Smuzhiyun goto exit;
2246*4882a593Smuzhiyun }
2247*4882a593Smuzhiyun
2248*4882a593Smuzhiyun priv->hostcmd_wait = &cmd_wait;
2249*4882a593Smuzhiyun iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
2250*4882a593Smuzhiyun iowrite32(MWL8K_H2A_INT_DOORBELL,
2251*4882a593Smuzhiyun regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
2252*4882a593Smuzhiyun iowrite32(MWL8K_H2A_INT_DUMMY,
2253*4882a593Smuzhiyun regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
2254*4882a593Smuzhiyun
2255*4882a593Smuzhiyun timeout = wait_for_completion_timeout(&cmd_wait,
2256*4882a593Smuzhiyun msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
2257*4882a593Smuzhiyun
2258*4882a593Smuzhiyun priv->hostcmd_wait = NULL;
2259*4882a593Smuzhiyun
2260*4882a593Smuzhiyun
2261*4882a593Smuzhiyun pci_unmap_single(priv->pdev, dma_addr, dma_size,
2262*4882a593Smuzhiyun PCI_DMA_BIDIRECTIONAL);
2263*4882a593Smuzhiyun
2264*4882a593Smuzhiyun if (!timeout) {
2265*4882a593Smuzhiyun wiphy_err(hw->wiphy, "Command %s timeout after %u ms\n",
2266*4882a593Smuzhiyun mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
2267*4882a593Smuzhiyun MWL8K_CMD_TIMEOUT_MS);
2268*4882a593Smuzhiyun rc = -ETIMEDOUT;
2269*4882a593Smuzhiyun } else {
2270*4882a593Smuzhiyun int ms;
2271*4882a593Smuzhiyun
2272*4882a593Smuzhiyun ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
2273*4882a593Smuzhiyun
2274*4882a593Smuzhiyun rc = cmd->result ? -EINVAL : 0;
2275*4882a593Smuzhiyun if (rc)
2276*4882a593Smuzhiyun wiphy_err(hw->wiphy, "Command %s error 0x%x\n",
2277*4882a593Smuzhiyun mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
2278*4882a593Smuzhiyun le16_to_cpu(cmd->result));
2279*4882a593Smuzhiyun else if (ms > 2000)
2280*4882a593Smuzhiyun wiphy_notice(hw->wiphy, "Command %s took %d ms\n",
2281*4882a593Smuzhiyun mwl8k_cmd_name(cmd->code,
2282*4882a593Smuzhiyun buf, sizeof(buf)),
2283*4882a593Smuzhiyun ms);
2284*4882a593Smuzhiyun }
2285*4882a593Smuzhiyun
2286*4882a593Smuzhiyun exit:
2287*4882a593Smuzhiyun if (bitmap)
2288*4882a593Smuzhiyun mwl8k_enable_bsses(hw, true, bitmap);
2289*4882a593Smuzhiyun
2290*4882a593Smuzhiyun mwl8k_fw_unlock(hw);
2291*4882a593Smuzhiyun
2292*4882a593Smuzhiyun return rc;
2293*4882a593Smuzhiyun }
2294*4882a593Smuzhiyun
mwl8k_post_pervif_cmd(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct mwl8k_cmd_pkt * cmd)2295*4882a593Smuzhiyun static int mwl8k_post_pervif_cmd(struct ieee80211_hw *hw,
2296*4882a593Smuzhiyun struct ieee80211_vif *vif,
2297*4882a593Smuzhiyun struct mwl8k_cmd_pkt *cmd)
2298*4882a593Smuzhiyun {
2299*4882a593Smuzhiyun if (vif != NULL)
2300*4882a593Smuzhiyun cmd->macid = MWL8K_VIF(vif)->macid;
2301*4882a593Smuzhiyun return mwl8k_post_cmd(hw, cmd);
2302*4882a593Smuzhiyun }
2303*4882a593Smuzhiyun
2304*4882a593Smuzhiyun /*
2305*4882a593Smuzhiyun * Setup code shared between STA and AP firmware images.
2306*4882a593Smuzhiyun */
mwl8k_setup_2ghz_band(struct ieee80211_hw * hw)2307*4882a593Smuzhiyun static void mwl8k_setup_2ghz_band(struct ieee80211_hw *hw)
2308*4882a593Smuzhiyun {
2309*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
2310*4882a593Smuzhiyun
2311*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(priv->channels_24) != sizeof(mwl8k_channels_24));
2312*4882a593Smuzhiyun memcpy(priv->channels_24, mwl8k_channels_24, sizeof(mwl8k_channels_24));
2313*4882a593Smuzhiyun
2314*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(priv->rates_24) != sizeof(mwl8k_rates_24));
2315*4882a593Smuzhiyun memcpy(priv->rates_24, mwl8k_rates_24, sizeof(mwl8k_rates_24));
2316*4882a593Smuzhiyun
2317*4882a593Smuzhiyun priv->band_24.band = NL80211_BAND_2GHZ;
2318*4882a593Smuzhiyun priv->band_24.channels = priv->channels_24;
2319*4882a593Smuzhiyun priv->band_24.n_channels = ARRAY_SIZE(mwl8k_channels_24);
2320*4882a593Smuzhiyun priv->band_24.bitrates = priv->rates_24;
2321*4882a593Smuzhiyun priv->band_24.n_bitrates = ARRAY_SIZE(mwl8k_rates_24);
2322*4882a593Smuzhiyun
2323*4882a593Smuzhiyun hw->wiphy->bands[NL80211_BAND_2GHZ] = &priv->band_24;
2324*4882a593Smuzhiyun }
2325*4882a593Smuzhiyun
mwl8k_setup_5ghz_band(struct ieee80211_hw * hw)2326*4882a593Smuzhiyun static void mwl8k_setup_5ghz_band(struct ieee80211_hw *hw)
2327*4882a593Smuzhiyun {
2328*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
2329*4882a593Smuzhiyun
2330*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(priv->channels_50) != sizeof(mwl8k_channels_50));
2331*4882a593Smuzhiyun memcpy(priv->channels_50, mwl8k_channels_50, sizeof(mwl8k_channels_50));
2332*4882a593Smuzhiyun
2333*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(priv->rates_50) != sizeof(mwl8k_rates_50));
2334*4882a593Smuzhiyun memcpy(priv->rates_50, mwl8k_rates_50, sizeof(mwl8k_rates_50));
2335*4882a593Smuzhiyun
2336*4882a593Smuzhiyun priv->band_50.band = NL80211_BAND_5GHZ;
2337*4882a593Smuzhiyun priv->band_50.channels = priv->channels_50;
2338*4882a593Smuzhiyun priv->band_50.n_channels = ARRAY_SIZE(mwl8k_channels_50);
2339*4882a593Smuzhiyun priv->band_50.bitrates = priv->rates_50;
2340*4882a593Smuzhiyun priv->band_50.n_bitrates = ARRAY_SIZE(mwl8k_rates_50);
2341*4882a593Smuzhiyun
2342*4882a593Smuzhiyun hw->wiphy->bands[NL80211_BAND_5GHZ] = &priv->band_50;
2343*4882a593Smuzhiyun }
2344*4882a593Smuzhiyun
2345*4882a593Smuzhiyun /*
2346*4882a593Smuzhiyun * CMD_GET_HW_SPEC (STA version).
2347*4882a593Smuzhiyun */
2348*4882a593Smuzhiyun struct mwl8k_cmd_get_hw_spec_sta {
2349*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
2350*4882a593Smuzhiyun __u8 hw_rev;
2351*4882a593Smuzhiyun __u8 host_interface;
2352*4882a593Smuzhiyun __le16 num_mcaddrs;
2353*4882a593Smuzhiyun __u8 perm_addr[ETH_ALEN];
2354*4882a593Smuzhiyun __le16 region_code;
2355*4882a593Smuzhiyun __le32 fw_rev;
2356*4882a593Smuzhiyun __le32 ps_cookie;
2357*4882a593Smuzhiyun __le32 caps;
2358*4882a593Smuzhiyun __u8 mcs_bitmap[16];
2359*4882a593Smuzhiyun __le32 rx_queue_ptr;
2360*4882a593Smuzhiyun __le32 num_tx_queues;
2361*4882a593Smuzhiyun __le32 tx_queue_ptrs[MWL8K_TX_WMM_QUEUES];
2362*4882a593Smuzhiyun __le32 caps2;
2363*4882a593Smuzhiyun __le32 num_tx_desc_per_queue;
2364*4882a593Smuzhiyun __le32 total_rxd;
2365*4882a593Smuzhiyun } __packed;
2366*4882a593Smuzhiyun
2367*4882a593Smuzhiyun #define MWL8K_CAP_MAX_AMSDU 0x20000000
2368*4882a593Smuzhiyun #define MWL8K_CAP_GREENFIELD 0x08000000
2369*4882a593Smuzhiyun #define MWL8K_CAP_AMPDU 0x04000000
2370*4882a593Smuzhiyun #define MWL8K_CAP_RX_STBC 0x01000000
2371*4882a593Smuzhiyun #define MWL8K_CAP_TX_STBC 0x00800000
2372*4882a593Smuzhiyun #define MWL8K_CAP_SHORTGI_40MHZ 0x00400000
2373*4882a593Smuzhiyun #define MWL8K_CAP_SHORTGI_20MHZ 0x00200000
2374*4882a593Smuzhiyun #define MWL8K_CAP_RX_ANTENNA_MASK 0x000e0000
2375*4882a593Smuzhiyun #define MWL8K_CAP_TX_ANTENNA_MASK 0x0001c000
2376*4882a593Smuzhiyun #define MWL8K_CAP_DELAY_BA 0x00003000
2377*4882a593Smuzhiyun #define MWL8K_CAP_MIMO 0x00000200
2378*4882a593Smuzhiyun #define MWL8K_CAP_40MHZ 0x00000100
2379*4882a593Smuzhiyun #define MWL8K_CAP_BAND_MASK 0x00000007
2380*4882a593Smuzhiyun #define MWL8K_CAP_5GHZ 0x00000004
2381*4882a593Smuzhiyun #define MWL8K_CAP_2GHZ4 0x00000001
2382*4882a593Smuzhiyun
2383*4882a593Smuzhiyun static void
mwl8k_set_ht_caps(struct ieee80211_hw * hw,struct ieee80211_supported_band * band,u32 cap)2384*4882a593Smuzhiyun mwl8k_set_ht_caps(struct ieee80211_hw *hw,
2385*4882a593Smuzhiyun struct ieee80211_supported_band *band, u32 cap)
2386*4882a593Smuzhiyun {
2387*4882a593Smuzhiyun int rx_streams;
2388*4882a593Smuzhiyun int tx_streams;
2389*4882a593Smuzhiyun
2390*4882a593Smuzhiyun band->ht_cap.ht_supported = 1;
2391*4882a593Smuzhiyun
2392*4882a593Smuzhiyun if (cap & MWL8K_CAP_MAX_AMSDU)
2393*4882a593Smuzhiyun band->ht_cap.cap |= IEEE80211_HT_CAP_MAX_AMSDU;
2394*4882a593Smuzhiyun if (cap & MWL8K_CAP_GREENFIELD)
2395*4882a593Smuzhiyun band->ht_cap.cap |= IEEE80211_HT_CAP_GRN_FLD;
2396*4882a593Smuzhiyun if (cap & MWL8K_CAP_AMPDU) {
2397*4882a593Smuzhiyun ieee80211_hw_set(hw, AMPDU_AGGREGATION);
2398*4882a593Smuzhiyun band->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
2399*4882a593Smuzhiyun band->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE;
2400*4882a593Smuzhiyun }
2401*4882a593Smuzhiyun if (cap & MWL8K_CAP_RX_STBC)
2402*4882a593Smuzhiyun band->ht_cap.cap |= IEEE80211_HT_CAP_RX_STBC;
2403*4882a593Smuzhiyun if (cap & MWL8K_CAP_TX_STBC)
2404*4882a593Smuzhiyun band->ht_cap.cap |= IEEE80211_HT_CAP_TX_STBC;
2405*4882a593Smuzhiyun if (cap & MWL8K_CAP_SHORTGI_40MHZ)
2406*4882a593Smuzhiyun band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
2407*4882a593Smuzhiyun if (cap & MWL8K_CAP_SHORTGI_20MHZ)
2408*4882a593Smuzhiyun band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_20;
2409*4882a593Smuzhiyun if (cap & MWL8K_CAP_DELAY_BA)
2410*4882a593Smuzhiyun band->ht_cap.cap |= IEEE80211_HT_CAP_DELAY_BA;
2411*4882a593Smuzhiyun if (cap & MWL8K_CAP_40MHZ)
2412*4882a593Smuzhiyun band->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
2413*4882a593Smuzhiyun
2414*4882a593Smuzhiyun rx_streams = hweight32(cap & MWL8K_CAP_RX_ANTENNA_MASK);
2415*4882a593Smuzhiyun tx_streams = hweight32(cap & MWL8K_CAP_TX_ANTENNA_MASK);
2416*4882a593Smuzhiyun
2417*4882a593Smuzhiyun band->ht_cap.mcs.rx_mask[0] = 0xff;
2418*4882a593Smuzhiyun if (rx_streams >= 2)
2419*4882a593Smuzhiyun band->ht_cap.mcs.rx_mask[1] = 0xff;
2420*4882a593Smuzhiyun if (rx_streams >= 3)
2421*4882a593Smuzhiyun band->ht_cap.mcs.rx_mask[2] = 0xff;
2422*4882a593Smuzhiyun band->ht_cap.mcs.rx_mask[4] = 0x01;
2423*4882a593Smuzhiyun band->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
2424*4882a593Smuzhiyun
2425*4882a593Smuzhiyun if (rx_streams != tx_streams) {
2426*4882a593Smuzhiyun band->ht_cap.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
2427*4882a593Smuzhiyun band->ht_cap.mcs.tx_params |= (tx_streams - 1) <<
2428*4882a593Smuzhiyun IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
2429*4882a593Smuzhiyun }
2430*4882a593Smuzhiyun }
2431*4882a593Smuzhiyun
2432*4882a593Smuzhiyun static void
mwl8k_set_caps(struct ieee80211_hw * hw,u32 caps)2433*4882a593Smuzhiyun mwl8k_set_caps(struct ieee80211_hw *hw, u32 caps)
2434*4882a593Smuzhiyun {
2435*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
2436*4882a593Smuzhiyun
2437*4882a593Smuzhiyun if (priv->caps)
2438*4882a593Smuzhiyun return;
2439*4882a593Smuzhiyun
2440*4882a593Smuzhiyun if ((caps & MWL8K_CAP_2GHZ4) || !(caps & MWL8K_CAP_BAND_MASK)) {
2441*4882a593Smuzhiyun mwl8k_setup_2ghz_band(hw);
2442*4882a593Smuzhiyun if (caps & MWL8K_CAP_MIMO)
2443*4882a593Smuzhiyun mwl8k_set_ht_caps(hw, &priv->band_24, caps);
2444*4882a593Smuzhiyun }
2445*4882a593Smuzhiyun
2446*4882a593Smuzhiyun if (caps & MWL8K_CAP_5GHZ) {
2447*4882a593Smuzhiyun mwl8k_setup_5ghz_band(hw);
2448*4882a593Smuzhiyun if (caps & MWL8K_CAP_MIMO)
2449*4882a593Smuzhiyun mwl8k_set_ht_caps(hw, &priv->band_50, caps);
2450*4882a593Smuzhiyun }
2451*4882a593Smuzhiyun
2452*4882a593Smuzhiyun priv->caps = caps;
2453*4882a593Smuzhiyun }
2454*4882a593Smuzhiyun
mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw * hw)2455*4882a593Smuzhiyun static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
2456*4882a593Smuzhiyun {
2457*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
2458*4882a593Smuzhiyun struct mwl8k_cmd_get_hw_spec_sta *cmd;
2459*4882a593Smuzhiyun int rc;
2460*4882a593Smuzhiyun int i;
2461*4882a593Smuzhiyun
2462*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2463*4882a593Smuzhiyun if (cmd == NULL)
2464*4882a593Smuzhiyun return -ENOMEM;
2465*4882a593Smuzhiyun
2466*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
2467*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
2468*4882a593Smuzhiyun
2469*4882a593Smuzhiyun memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
2470*4882a593Smuzhiyun cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
2471*4882a593Smuzhiyun cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
2472*4882a593Smuzhiyun cmd->num_tx_queues = cpu_to_le32(mwl8k_tx_queues(priv));
2473*4882a593Smuzhiyun for (i = 0; i < mwl8k_tx_queues(priv); i++)
2474*4882a593Smuzhiyun cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
2475*4882a593Smuzhiyun cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
2476*4882a593Smuzhiyun cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
2477*4882a593Smuzhiyun
2478*4882a593Smuzhiyun rc = mwl8k_post_cmd(hw, &cmd->header);
2479*4882a593Smuzhiyun
2480*4882a593Smuzhiyun if (!rc) {
2481*4882a593Smuzhiyun SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
2482*4882a593Smuzhiyun priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
2483*4882a593Smuzhiyun priv->fw_rev = le32_to_cpu(cmd->fw_rev);
2484*4882a593Smuzhiyun priv->hw_rev = cmd->hw_rev;
2485*4882a593Smuzhiyun mwl8k_set_caps(hw, le32_to_cpu(cmd->caps));
2486*4882a593Smuzhiyun priv->ap_macids_supported = 0x00000000;
2487*4882a593Smuzhiyun priv->sta_macids_supported = 0x00000001;
2488*4882a593Smuzhiyun }
2489*4882a593Smuzhiyun
2490*4882a593Smuzhiyun kfree(cmd);
2491*4882a593Smuzhiyun return rc;
2492*4882a593Smuzhiyun }
2493*4882a593Smuzhiyun
2494*4882a593Smuzhiyun /*
2495*4882a593Smuzhiyun * CMD_GET_HW_SPEC (AP version).
2496*4882a593Smuzhiyun */
2497*4882a593Smuzhiyun struct mwl8k_cmd_get_hw_spec_ap {
2498*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
2499*4882a593Smuzhiyun __u8 hw_rev;
2500*4882a593Smuzhiyun __u8 host_interface;
2501*4882a593Smuzhiyun __le16 num_wcb;
2502*4882a593Smuzhiyun __le16 num_mcaddrs;
2503*4882a593Smuzhiyun __u8 perm_addr[ETH_ALEN];
2504*4882a593Smuzhiyun __le16 region_code;
2505*4882a593Smuzhiyun __le16 num_antenna;
2506*4882a593Smuzhiyun __le32 fw_rev;
2507*4882a593Smuzhiyun __le32 wcbbase0;
2508*4882a593Smuzhiyun __le32 rxwrptr;
2509*4882a593Smuzhiyun __le32 rxrdptr;
2510*4882a593Smuzhiyun __le32 ps_cookie;
2511*4882a593Smuzhiyun __le32 wcbbase1;
2512*4882a593Smuzhiyun __le32 wcbbase2;
2513*4882a593Smuzhiyun __le32 wcbbase3;
2514*4882a593Smuzhiyun __le32 fw_api_version;
2515*4882a593Smuzhiyun __le32 caps;
2516*4882a593Smuzhiyun __le32 num_of_ampdu_queues;
2517*4882a593Smuzhiyun __le32 wcbbase_ampdu[MWL8K_MAX_AMPDU_QUEUES];
2518*4882a593Smuzhiyun } __packed;
2519*4882a593Smuzhiyun
mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw * hw)2520*4882a593Smuzhiyun static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
2521*4882a593Smuzhiyun {
2522*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
2523*4882a593Smuzhiyun struct mwl8k_cmd_get_hw_spec_ap *cmd;
2524*4882a593Smuzhiyun int rc, i;
2525*4882a593Smuzhiyun u32 api_version;
2526*4882a593Smuzhiyun
2527*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2528*4882a593Smuzhiyun if (cmd == NULL)
2529*4882a593Smuzhiyun return -ENOMEM;
2530*4882a593Smuzhiyun
2531*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
2532*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
2533*4882a593Smuzhiyun
2534*4882a593Smuzhiyun memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
2535*4882a593Smuzhiyun cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
2536*4882a593Smuzhiyun
2537*4882a593Smuzhiyun rc = mwl8k_post_cmd(hw, &cmd->header);
2538*4882a593Smuzhiyun
2539*4882a593Smuzhiyun if (!rc) {
2540*4882a593Smuzhiyun int off;
2541*4882a593Smuzhiyun
2542*4882a593Smuzhiyun api_version = le32_to_cpu(cmd->fw_api_version);
2543*4882a593Smuzhiyun if (priv->device_info->fw_api_ap != api_version) {
2544*4882a593Smuzhiyun printk(KERN_ERR "%s: Unsupported fw API version for %s."
2545*4882a593Smuzhiyun " Expected %d got %d.\n", MWL8K_NAME,
2546*4882a593Smuzhiyun priv->device_info->part_name,
2547*4882a593Smuzhiyun priv->device_info->fw_api_ap,
2548*4882a593Smuzhiyun api_version);
2549*4882a593Smuzhiyun rc = -EINVAL;
2550*4882a593Smuzhiyun goto done;
2551*4882a593Smuzhiyun }
2552*4882a593Smuzhiyun SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
2553*4882a593Smuzhiyun priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
2554*4882a593Smuzhiyun priv->fw_rev = le32_to_cpu(cmd->fw_rev);
2555*4882a593Smuzhiyun priv->hw_rev = cmd->hw_rev;
2556*4882a593Smuzhiyun mwl8k_set_caps(hw, le32_to_cpu(cmd->caps));
2557*4882a593Smuzhiyun priv->ap_macids_supported = 0x000000ff;
2558*4882a593Smuzhiyun priv->sta_macids_supported = 0x00000100;
2559*4882a593Smuzhiyun priv->num_ampdu_queues = le32_to_cpu(cmd->num_of_ampdu_queues);
2560*4882a593Smuzhiyun if (priv->num_ampdu_queues > MWL8K_MAX_AMPDU_QUEUES) {
2561*4882a593Smuzhiyun wiphy_warn(hw->wiphy, "fw reported %d ampdu queues"
2562*4882a593Smuzhiyun " but we only support %d.\n",
2563*4882a593Smuzhiyun priv->num_ampdu_queues,
2564*4882a593Smuzhiyun MWL8K_MAX_AMPDU_QUEUES);
2565*4882a593Smuzhiyun priv->num_ampdu_queues = MWL8K_MAX_AMPDU_QUEUES;
2566*4882a593Smuzhiyun }
2567*4882a593Smuzhiyun off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
2568*4882a593Smuzhiyun iowrite32(priv->rxq[0].rxd_dma, priv->sram + off);
2569*4882a593Smuzhiyun
2570*4882a593Smuzhiyun off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
2571*4882a593Smuzhiyun iowrite32(priv->rxq[0].rxd_dma, priv->sram + off);
2572*4882a593Smuzhiyun
2573*4882a593Smuzhiyun priv->txq_offset[0] = le32_to_cpu(cmd->wcbbase0) & 0xffff;
2574*4882a593Smuzhiyun priv->txq_offset[1] = le32_to_cpu(cmd->wcbbase1) & 0xffff;
2575*4882a593Smuzhiyun priv->txq_offset[2] = le32_to_cpu(cmd->wcbbase2) & 0xffff;
2576*4882a593Smuzhiyun priv->txq_offset[3] = le32_to_cpu(cmd->wcbbase3) & 0xffff;
2577*4882a593Smuzhiyun
2578*4882a593Smuzhiyun for (i = 0; i < priv->num_ampdu_queues; i++)
2579*4882a593Smuzhiyun priv->txq_offset[i + MWL8K_TX_WMM_QUEUES] =
2580*4882a593Smuzhiyun le32_to_cpu(cmd->wcbbase_ampdu[i]) & 0xffff;
2581*4882a593Smuzhiyun }
2582*4882a593Smuzhiyun
2583*4882a593Smuzhiyun done:
2584*4882a593Smuzhiyun kfree(cmd);
2585*4882a593Smuzhiyun return rc;
2586*4882a593Smuzhiyun }
2587*4882a593Smuzhiyun
2588*4882a593Smuzhiyun /*
2589*4882a593Smuzhiyun * CMD_SET_HW_SPEC.
2590*4882a593Smuzhiyun */
2591*4882a593Smuzhiyun struct mwl8k_cmd_set_hw_spec {
2592*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
2593*4882a593Smuzhiyun __u8 hw_rev;
2594*4882a593Smuzhiyun __u8 host_interface;
2595*4882a593Smuzhiyun __le16 num_mcaddrs;
2596*4882a593Smuzhiyun __u8 perm_addr[ETH_ALEN];
2597*4882a593Smuzhiyun __le16 region_code;
2598*4882a593Smuzhiyun __le32 fw_rev;
2599*4882a593Smuzhiyun __le32 ps_cookie;
2600*4882a593Smuzhiyun __le32 caps;
2601*4882a593Smuzhiyun __le32 rx_queue_ptr;
2602*4882a593Smuzhiyun __le32 num_tx_queues;
2603*4882a593Smuzhiyun __le32 tx_queue_ptrs[MWL8K_MAX_TX_QUEUES];
2604*4882a593Smuzhiyun __le32 flags;
2605*4882a593Smuzhiyun __le32 num_tx_desc_per_queue;
2606*4882a593Smuzhiyun __le32 total_rxd;
2607*4882a593Smuzhiyun } __packed;
2608*4882a593Smuzhiyun
2609*4882a593Smuzhiyun /* If enabled, MWL8K_SET_HW_SPEC_FLAG_ENABLE_LIFE_TIME_EXPIRY will cause
2610*4882a593Smuzhiyun * packets to expire 500 ms after the timestamp in the tx descriptor. That is,
2611*4882a593Smuzhiyun * the packets that are queued for more than 500ms, will be dropped in the
2612*4882a593Smuzhiyun * hardware. This helps minimizing the issues caused due to head-of-line
2613*4882a593Smuzhiyun * blocking where a slow client can hog the bandwidth and affect traffic to a
2614*4882a593Smuzhiyun * faster client.
2615*4882a593Smuzhiyun */
2616*4882a593Smuzhiyun #define MWL8K_SET_HW_SPEC_FLAG_ENABLE_LIFE_TIME_EXPIRY 0x00000400
2617*4882a593Smuzhiyun #define MWL8K_SET_HW_SPEC_FLAG_GENERATE_CCMP_HDR 0x00000200
2618*4882a593Smuzhiyun #define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
2619*4882a593Smuzhiyun #define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP 0x00000020
2620*4882a593Smuzhiyun #define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON 0x00000010
2621*4882a593Smuzhiyun
mwl8k_cmd_set_hw_spec(struct ieee80211_hw * hw)2622*4882a593Smuzhiyun static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
2623*4882a593Smuzhiyun {
2624*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
2625*4882a593Smuzhiyun struct mwl8k_cmd_set_hw_spec *cmd;
2626*4882a593Smuzhiyun int rc;
2627*4882a593Smuzhiyun int i;
2628*4882a593Smuzhiyun
2629*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2630*4882a593Smuzhiyun if (cmd == NULL)
2631*4882a593Smuzhiyun return -ENOMEM;
2632*4882a593Smuzhiyun
2633*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
2634*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
2635*4882a593Smuzhiyun
2636*4882a593Smuzhiyun cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
2637*4882a593Smuzhiyun cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
2638*4882a593Smuzhiyun cmd->num_tx_queues = cpu_to_le32(mwl8k_tx_queues(priv));
2639*4882a593Smuzhiyun
2640*4882a593Smuzhiyun /*
2641*4882a593Smuzhiyun * Mac80211 stack has Q0 as highest priority and Q3 as lowest in
2642*4882a593Smuzhiyun * that order. Firmware has Q3 as highest priority and Q0 as lowest
2643*4882a593Smuzhiyun * in that order. Map Q3 of mac80211 to Q0 of firmware so that the
2644*4882a593Smuzhiyun * priority is interpreted the right way in firmware.
2645*4882a593Smuzhiyun */
2646*4882a593Smuzhiyun for (i = 0; i < mwl8k_tx_queues(priv); i++) {
2647*4882a593Smuzhiyun int j = mwl8k_tx_queues(priv) - 1 - i;
2648*4882a593Smuzhiyun cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[j].txd_dma);
2649*4882a593Smuzhiyun }
2650*4882a593Smuzhiyun
2651*4882a593Smuzhiyun cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT |
2652*4882a593Smuzhiyun MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP |
2653*4882a593Smuzhiyun MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON |
2654*4882a593Smuzhiyun MWL8K_SET_HW_SPEC_FLAG_ENABLE_LIFE_TIME_EXPIRY |
2655*4882a593Smuzhiyun MWL8K_SET_HW_SPEC_FLAG_GENERATE_CCMP_HDR);
2656*4882a593Smuzhiyun cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
2657*4882a593Smuzhiyun cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
2658*4882a593Smuzhiyun
2659*4882a593Smuzhiyun rc = mwl8k_post_cmd(hw, &cmd->header);
2660*4882a593Smuzhiyun kfree(cmd);
2661*4882a593Smuzhiyun
2662*4882a593Smuzhiyun return rc;
2663*4882a593Smuzhiyun }
2664*4882a593Smuzhiyun
2665*4882a593Smuzhiyun /*
2666*4882a593Smuzhiyun * CMD_MAC_MULTICAST_ADR.
2667*4882a593Smuzhiyun */
2668*4882a593Smuzhiyun struct mwl8k_cmd_mac_multicast_adr {
2669*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
2670*4882a593Smuzhiyun __le16 action;
2671*4882a593Smuzhiyun __le16 numaddr;
2672*4882a593Smuzhiyun __u8 addr[][ETH_ALEN];
2673*4882a593Smuzhiyun };
2674*4882a593Smuzhiyun
2675*4882a593Smuzhiyun #define MWL8K_ENABLE_RX_DIRECTED 0x0001
2676*4882a593Smuzhiyun #define MWL8K_ENABLE_RX_MULTICAST 0x0002
2677*4882a593Smuzhiyun #define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
2678*4882a593Smuzhiyun #define MWL8K_ENABLE_RX_BROADCAST 0x0008
2679*4882a593Smuzhiyun
2680*4882a593Smuzhiyun static struct mwl8k_cmd_pkt *
__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw * hw,int allmulti,struct netdev_hw_addr_list * mc_list)2681*4882a593Smuzhiyun __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
2682*4882a593Smuzhiyun struct netdev_hw_addr_list *mc_list)
2683*4882a593Smuzhiyun {
2684*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
2685*4882a593Smuzhiyun struct mwl8k_cmd_mac_multicast_adr *cmd;
2686*4882a593Smuzhiyun int size;
2687*4882a593Smuzhiyun int mc_count = 0;
2688*4882a593Smuzhiyun
2689*4882a593Smuzhiyun if (mc_list)
2690*4882a593Smuzhiyun mc_count = netdev_hw_addr_list_count(mc_list);
2691*4882a593Smuzhiyun
2692*4882a593Smuzhiyun if (allmulti || mc_count > priv->num_mcaddrs) {
2693*4882a593Smuzhiyun allmulti = 1;
2694*4882a593Smuzhiyun mc_count = 0;
2695*4882a593Smuzhiyun }
2696*4882a593Smuzhiyun
2697*4882a593Smuzhiyun size = sizeof(*cmd) + mc_count * ETH_ALEN;
2698*4882a593Smuzhiyun
2699*4882a593Smuzhiyun cmd = kzalloc(size, GFP_ATOMIC);
2700*4882a593Smuzhiyun if (cmd == NULL)
2701*4882a593Smuzhiyun return NULL;
2702*4882a593Smuzhiyun
2703*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
2704*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(size);
2705*4882a593Smuzhiyun cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
2706*4882a593Smuzhiyun MWL8K_ENABLE_RX_BROADCAST);
2707*4882a593Smuzhiyun
2708*4882a593Smuzhiyun if (allmulti) {
2709*4882a593Smuzhiyun cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
2710*4882a593Smuzhiyun } else if (mc_count) {
2711*4882a593Smuzhiyun struct netdev_hw_addr *ha;
2712*4882a593Smuzhiyun int i = 0;
2713*4882a593Smuzhiyun
2714*4882a593Smuzhiyun cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
2715*4882a593Smuzhiyun cmd->numaddr = cpu_to_le16(mc_count);
2716*4882a593Smuzhiyun netdev_hw_addr_list_for_each(ha, mc_list) {
2717*4882a593Smuzhiyun memcpy(cmd->addr[i], ha->addr, ETH_ALEN);
2718*4882a593Smuzhiyun }
2719*4882a593Smuzhiyun }
2720*4882a593Smuzhiyun
2721*4882a593Smuzhiyun return &cmd->header;
2722*4882a593Smuzhiyun }
2723*4882a593Smuzhiyun
2724*4882a593Smuzhiyun /*
2725*4882a593Smuzhiyun * CMD_GET_STAT.
2726*4882a593Smuzhiyun */
2727*4882a593Smuzhiyun struct mwl8k_cmd_get_stat {
2728*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
2729*4882a593Smuzhiyun __le32 stats[64];
2730*4882a593Smuzhiyun } __packed;
2731*4882a593Smuzhiyun
2732*4882a593Smuzhiyun #define MWL8K_STAT_ACK_FAILURE 9
2733*4882a593Smuzhiyun #define MWL8K_STAT_RTS_FAILURE 12
2734*4882a593Smuzhiyun #define MWL8K_STAT_FCS_ERROR 24
2735*4882a593Smuzhiyun #define MWL8K_STAT_RTS_SUCCESS 11
2736*4882a593Smuzhiyun
mwl8k_cmd_get_stat(struct ieee80211_hw * hw,struct ieee80211_low_level_stats * stats)2737*4882a593Smuzhiyun static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw,
2738*4882a593Smuzhiyun struct ieee80211_low_level_stats *stats)
2739*4882a593Smuzhiyun {
2740*4882a593Smuzhiyun struct mwl8k_cmd_get_stat *cmd;
2741*4882a593Smuzhiyun int rc;
2742*4882a593Smuzhiyun
2743*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2744*4882a593Smuzhiyun if (cmd == NULL)
2745*4882a593Smuzhiyun return -ENOMEM;
2746*4882a593Smuzhiyun
2747*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
2748*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
2749*4882a593Smuzhiyun
2750*4882a593Smuzhiyun rc = mwl8k_post_cmd(hw, &cmd->header);
2751*4882a593Smuzhiyun if (!rc) {
2752*4882a593Smuzhiyun stats->dot11ACKFailureCount =
2753*4882a593Smuzhiyun le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
2754*4882a593Smuzhiyun stats->dot11RTSFailureCount =
2755*4882a593Smuzhiyun le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
2756*4882a593Smuzhiyun stats->dot11FCSErrorCount =
2757*4882a593Smuzhiyun le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
2758*4882a593Smuzhiyun stats->dot11RTSSuccessCount =
2759*4882a593Smuzhiyun le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
2760*4882a593Smuzhiyun }
2761*4882a593Smuzhiyun kfree(cmd);
2762*4882a593Smuzhiyun
2763*4882a593Smuzhiyun return rc;
2764*4882a593Smuzhiyun }
2765*4882a593Smuzhiyun
2766*4882a593Smuzhiyun /*
2767*4882a593Smuzhiyun * CMD_RADIO_CONTROL.
2768*4882a593Smuzhiyun */
2769*4882a593Smuzhiyun struct mwl8k_cmd_radio_control {
2770*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
2771*4882a593Smuzhiyun __le16 action;
2772*4882a593Smuzhiyun __le16 control;
2773*4882a593Smuzhiyun __le16 radio_on;
2774*4882a593Smuzhiyun } __packed;
2775*4882a593Smuzhiyun
2776*4882a593Smuzhiyun static int
mwl8k_cmd_radio_control(struct ieee80211_hw * hw,bool enable,bool force)2777*4882a593Smuzhiyun mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
2778*4882a593Smuzhiyun {
2779*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
2780*4882a593Smuzhiyun struct mwl8k_cmd_radio_control *cmd;
2781*4882a593Smuzhiyun int rc;
2782*4882a593Smuzhiyun
2783*4882a593Smuzhiyun if (enable == priv->radio_on && !force)
2784*4882a593Smuzhiyun return 0;
2785*4882a593Smuzhiyun
2786*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2787*4882a593Smuzhiyun if (cmd == NULL)
2788*4882a593Smuzhiyun return -ENOMEM;
2789*4882a593Smuzhiyun
2790*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
2791*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
2792*4882a593Smuzhiyun cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2793*4882a593Smuzhiyun cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
2794*4882a593Smuzhiyun cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
2795*4882a593Smuzhiyun
2796*4882a593Smuzhiyun rc = mwl8k_post_cmd(hw, &cmd->header);
2797*4882a593Smuzhiyun kfree(cmd);
2798*4882a593Smuzhiyun
2799*4882a593Smuzhiyun if (!rc)
2800*4882a593Smuzhiyun priv->radio_on = enable;
2801*4882a593Smuzhiyun
2802*4882a593Smuzhiyun return rc;
2803*4882a593Smuzhiyun }
2804*4882a593Smuzhiyun
mwl8k_cmd_radio_disable(struct ieee80211_hw * hw)2805*4882a593Smuzhiyun static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw)
2806*4882a593Smuzhiyun {
2807*4882a593Smuzhiyun return mwl8k_cmd_radio_control(hw, 0, 0);
2808*4882a593Smuzhiyun }
2809*4882a593Smuzhiyun
mwl8k_cmd_radio_enable(struct ieee80211_hw * hw)2810*4882a593Smuzhiyun static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw)
2811*4882a593Smuzhiyun {
2812*4882a593Smuzhiyun return mwl8k_cmd_radio_control(hw, 1, 0);
2813*4882a593Smuzhiyun }
2814*4882a593Smuzhiyun
2815*4882a593Smuzhiyun static int
mwl8k_set_radio_preamble(struct ieee80211_hw * hw,bool short_preamble)2816*4882a593Smuzhiyun mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
2817*4882a593Smuzhiyun {
2818*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
2819*4882a593Smuzhiyun
2820*4882a593Smuzhiyun priv->radio_short_preamble = short_preamble;
2821*4882a593Smuzhiyun
2822*4882a593Smuzhiyun return mwl8k_cmd_radio_control(hw, 1, 1);
2823*4882a593Smuzhiyun }
2824*4882a593Smuzhiyun
2825*4882a593Smuzhiyun /*
2826*4882a593Smuzhiyun * CMD_RF_TX_POWER.
2827*4882a593Smuzhiyun */
2828*4882a593Smuzhiyun #define MWL8K_RF_TX_POWER_LEVEL_TOTAL 8
2829*4882a593Smuzhiyun
2830*4882a593Smuzhiyun struct mwl8k_cmd_rf_tx_power {
2831*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
2832*4882a593Smuzhiyun __le16 action;
2833*4882a593Smuzhiyun __le16 support_level;
2834*4882a593Smuzhiyun __le16 current_level;
2835*4882a593Smuzhiyun __le16 reserved;
2836*4882a593Smuzhiyun __le16 power_level_list[MWL8K_RF_TX_POWER_LEVEL_TOTAL];
2837*4882a593Smuzhiyun } __packed;
2838*4882a593Smuzhiyun
mwl8k_cmd_rf_tx_power(struct ieee80211_hw * hw,int dBm)2839*4882a593Smuzhiyun static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
2840*4882a593Smuzhiyun {
2841*4882a593Smuzhiyun struct mwl8k_cmd_rf_tx_power *cmd;
2842*4882a593Smuzhiyun int rc;
2843*4882a593Smuzhiyun
2844*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2845*4882a593Smuzhiyun if (cmd == NULL)
2846*4882a593Smuzhiyun return -ENOMEM;
2847*4882a593Smuzhiyun
2848*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
2849*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
2850*4882a593Smuzhiyun cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2851*4882a593Smuzhiyun cmd->support_level = cpu_to_le16(dBm);
2852*4882a593Smuzhiyun
2853*4882a593Smuzhiyun rc = mwl8k_post_cmd(hw, &cmd->header);
2854*4882a593Smuzhiyun kfree(cmd);
2855*4882a593Smuzhiyun
2856*4882a593Smuzhiyun return rc;
2857*4882a593Smuzhiyun }
2858*4882a593Smuzhiyun
2859*4882a593Smuzhiyun /*
2860*4882a593Smuzhiyun * CMD_TX_POWER.
2861*4882a593Smuzhiyun */
2862*4882a593Smuzhiyun #define MWL8K_TX_POWER_LEVEL_TOTAL 12
2863*4882a593Smuzhiyun
2864*4882a593Smuzhiyun struct mwl8k_cmd_tx_power {
2865*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
2866*4882a593Smuzhiyun __le16 action;
2867*4882a593Smuzhiyun __le16 band;
2868*4882a593Smuzhiyun __le16 channel;
2869*4882a593Smuzhiyun __le16 bw;
2870*4882a593Smuzhiyun __le16 sub_ch;
2871*4882a593Smuzhiyun __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
2872*4882a593Smuzhiyun } __packed;
2873*4882a593Smuzhiyun
mwl8k_cmd_tx_power(struct ieee80211_hw * hw,struct ieee80211_conf * conf,unsigned short pwr)2874*4882a593Smuzhiyun static int mwl8k_cmd_tx_power(struct ieee80211_hw *hw,
2875*4882a593Smuzhiyun struct ieee80211_conf *conf,
2876*4882a593Smuzhiyun unsigned short pwr)
2877*4882a593Smuzhiyun {
2878*4882a593Smuzhiyun struct ieee80211_channel *channel = conf->chandef.chan;
2879*4882a593Smuzhiyun enum nl80211_channel_type channel_type =
2880*4882a593Smuzhiyun cfg80211_get_chandef_type(&conf->chandef);
2881*4882a593Smuzhiyun struct mwl8k_cmd_tx_power *cmd;
2882*4882a593Smuzhiyun int rc;
2883*4882a593Smuzhiyun int i;
2884*4882a593Smuzhiyun
2885*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2886*4882a593Smuzhiyun if (cmd == NULL)
2887*4882a593Smuzhiyun return -ENOMEM;
2888*4882a593Smuzhiyun
2889*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_TX_POWER);
2890*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
2891*4882a593Smuzhiyun cmd->action = cpu_to_le16(MWL8K_CMD_SET_LIST);
2892*4882a593Smuzhiyun
2893*4882a593Smuzhiyun if (channel->band == NL80211_BAND_2GHZ)
2894*4882a593Smuzhiyun cmd->band = cpu_to_le16(0x1);
2895*4882a593Smuzhiyun else if (channel->band == NL80211_BAND_5GHZ)
2896*4882a593Smuzhiyun cmd->band = cpu_to_le16(0x4);
2897*4882a593Smuzhiyun
2898*4882a593Smuzhiyun cmd->channel = cpu_to_le16(channel->hw_value);
2899*4882a593Smuzhiyun
2900*4882a593Smuzhiyun if (channel_type == NL80211_CHAN_NO_HT ||
2901*4882a593Smuzhiyun channel_type == NL80211_CHAN_HT20) {
2902*4882a593Smuzhiyun cmd->bw = cpu_to_le16(0x2);
2903*4882a593Smuzhiyun } else {
2904*4882a593Smuzhiyun cmd->bw = cpu_to_le16(0x4);
2905*4882a593Smuzhiyun if (channel_type == NL80211_CHAN_HT40MINUS)
2906*4882a593Smuzhiyun cmd->sub_ch = cpu_to_le16(0x3);
2907*4882a593Smuzhiyun else if (channel_type == NL80211_CHAN_HT40PLUS)
2908*4882a593Smuzhiyun cmd->sub_ch = cpu_to_le16(0x1);
2909*4882a593Smuzhiyun }
2910*4882a593Smuzhiyun
2911*4882a593Smuzhiyun for (i = 0; i < MWL8K_TX_POWER_LEVEL_TOTAL; i++)
2912*4882a593Smuzhiyun cmd->power_level_list[i] = cpu_to_le16(pwr);
2913*4882a593Smuzhiyun
2914*4882a593Smuzhiyun rc = mwl8k_post_cmd(hw, &cmd->header);
2915*4882a593Smuzhiyun kfree(cmd);
2916*4882a593Smuzhiyun
2917*4882a593Smuzhiyun return rc;
2918*4882a593Smuzhiyun }
2919*4882a593Smuzhiyun
2920*4882a593Smuzhiyun /*
2921*4882a593Smuzhiyun * CMD_RF_ANTENNA.
2922*4882a593Smuzhiyun */
2923*4882a593Smuzhiyun struct mwl8k_cmd_rf_antenna {
2924*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
2925*4882a593Smuzhiyun __le16 antenna;
2926*4882a593Smuzhiyun __le16 mode;
2927*4882a593Smuzhiyun } __packed;
2928*4882a593Smuzhiyun
2929*4882a593Smuzhiyun #define MWL8K_RF_ANTENNA_RX 1
2930*4882a593Smuzhiyun #define MWL8K_RF_ANTENNA_TX 2
2931*4882a593Smuzhiyun
2932*4882a593Smuzhiyun static int
mwl8k_cmd_rf_antenna(struct ieee80211_hw * hw,int antenna,int mask)2933*4882a593Smuzhiyun mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2934*4882a593Smuzhiyun {
2935*4882a593Smuzhiyun struct mwl8k_cmd_rf_antenna *cmd;
2936*4882a593Smuzhiyun int rc;
2937*4882a593Smuzhiyun
2938*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2939*4882a593Smuzhiyun if (cmd == NULL)
2940*4882a593Smuzhiyun return -ENOMEM;
2941*4882a593Smuzhiyun
2942*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2943*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
2944*4882a593Smuzhiyun cmd->antenna = cpu_to_le16(antenna);
2945*4882a593Smuzhiyun cmd->mode = cpu_to_le16(mask);
2946*4882a593Smuzhiyun
2947*4882a593Smuzhiyun rc = mwl8k_post_cmd(hw, &cmd->header);
2948*4882a593Smuzhiyun kfree(cmd);
2949*4882a593Smuzhiyun
2950*4882a593Smuzhiyun return rc;
2951*4882a593Smuzhiyun }
2952*4882a593Smuzhiyun
2953*4882a593Smuzhiyun /*
2954*4882a593Smuzhiyun * CMD_SET_BEACON.
2955*4882a593Smuzhiyun */
2956*4882a593Smuzhiyun struct mwl8k_cmd_set_beacon {
2957*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
2958*4882a593Smuzhiyun __le16 beacon_len;
2959*4882a593Smuzhiyun __u8 beacon[];
2960*4882a593Smuzhiyun };
2961*4882a593Smuzhiyun
mwl8k_cmd_set_beacon(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u8 * beacon,int len)2962*4882a593Smuzhiyun static int mwl8k_cmd_set_beacon(struct ieee80211_hw *hw,
2963*4882a593Smuzhiyun struct ieee80211_vif *vif, u8 *beacon, int len)
2964*4882a593Smuzhiyun {
2965*4882a593Smuzhiyun struct mwl8k_cmd_set_beacon *cmd;
2966*4882a593Smuzhiyun int rc;
2967*4882a593Smuzhiyun
2968*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd) + len, GFP_KERNEL);
2969*4882a593Smuzhiyun if (cmd == NULL)
2970*4882a593Smuzhiyun return -ENOMEM;
2971*4882a593Smuzhiyun
2972*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_BEACON);
2973*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd) + len);
2974*4882a593Smuzhiyun cmd->beacon_len = cpu_to_le16(len);
2975*4882a593Smuzhiyun memcpy(cmd->beacon, beacon, len);
2976*4882a593Smuzhiyun
2977*4882a593Smuzhiyun rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
2978*4882a593Smuzhiyun kfree(cmd);
2979*4882a593Smuzhiyun
2980*4882a593Smuzhiyun return rc;
2981*4882a593Smuzhiyun }
2982*4882a593Smuzhiyun
2983*4882a593Smuzhiyun /*
2984*4882a593Smuzhiyun * CMD_SET_PRE_SCAN.
2985*4882a593Smuzhiyun */
2986*4882a593Smuzhiyun struct mwl8k_cmd_set_pre_scan {
2987*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
2988*4882a593Smuzhiyun } __packed;
2989*4882a593Smuzhiyun
mwl8k_cmd_set_pre_scan(struct ieee80211_hw * hw)2990*4882a593Smuzhiyun static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2991*4882a593Smuzhiyun {
2992*4882a593Smuzhiyun struct mwl8k_cmd_set_pre_scan *cmd;
2993*4882a593Smuzhiyun int rc;
2994*4882a593Smuzhiyun
2995*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2996*4882a593Smuzhiyun if (cmd == NULL)
2997*4882a593Smuzhiyun return -ENOMEM;
2998*4882a593Smuzhiyun
2999*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
3000*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
3001*4882a593Smuzhiyun
3002*4882a593Smuzhiyun rc = mwl8k_post_cmd(hw, &cmd->header);
3003*4882a593Smuzhiyun kfree(cmd);
3004*4882a593Smuzhiyun
3005*4882a593Smuzhiyun return rc;
3006*4882a593Smuzhiyun }
3007*4882a593Smuzhiyun
3008*4882a593Smuzhiyun /*
3009*4882a593Smuzhiyun * CMD_BBP_REG_ACCESS.
3010*4882a593Smuzhiyun */
3011*4882a593Smuzhiyun struct mwl8k_cmd_bbp_reg_access {
3012*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
3013*4882a593Smuzhiyun __le16 action;
3014*4882a593Smuzhiyun __le16 offset;
3015*4882a593Smuzhiyun u8 value;
3016*4882a593Smuzhiyun u8 rsrv[3];
3017*4882a593Smuzhiyun } __packed;
3018*4882a593Smuzhiyun
3019*4882a593Smuzhiyun static int
mwl8k_cmd_bbp_reg_access(struct ieee80211_hw * hw,u16 action,u16 offset,u8 * value)3020*4882a593Smuzhiyun mwl8k_cmd_bbp_reg_access(struct ieee80211_hw *hw,
3021*4882a593Smuzhiyun u16 action,
3022*4882a593Smuzhiyun u16 offset,
3023*4882a593Smuzhiyun u8 *value)
3024*4882a593Smuzhiyun {
3025*4882a593Smuzhiyun struct mwl8k_cmd_bbp_reg_access *cmd;
3026*4882a593Smuzhiyun int rc;
3027*4882a593Smuzhiyun
3028*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3029*4882a593Smuzhiyun if (cmd == NULL)
3030*4882a593Smuzhiyun return -ENOMEM;
3031*4882a593Smuzhiyun
3032*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_BBP_REG_ACCESS);
3033*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
3034*4882a593Smuzhiyun cmd->action = cpu_to_le16(action);
3035*4882a593Smuzhiyun cmd->offset = cpu_to_le16(offset);
3036*4882a593Smuzhiyun
3037*4882a593Smuzhiyun rc = mwl8k_post_cmd(hw, &cmd->header);
3038*4882a593Smuzhiyun
3039*4882a593Smuzhiyun if (!rc)
3040*4882a593Smuzhiyun *value = cmd->value;
3041*4882a593Smuzhiyun else
3042*4882a593Smuzhiyun *value = 0;
3043*4882a593Smuzhiyun
3044*4882a593Smuzhiyun kfree(cmd);
3045*4882a593Smuzhiyun
3046*4882a593Smuzhiyun return rc;
3047*4882a593Smuzhiyun }
3048*4882a593Smuzhiyun
3049*4882a593Smuzhiyun /*
3050*4882a593Smuzhiyun * CMD_SET_POST_SCAN.
3051*4882a593Smuzhiyun */
3052*4882a593Smuzhiyun struct mwl8k_cmd_set_post_scan {
3053*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
3054*4882a593Smuzhiyun __le32 isibss;
3055*4882a593Smuzhiyun __u8 bssid[ETH_ALEN];
3056*4882a593Smuzhiyun } __packed;
3057*4882a593Smuzhiyun
3058*4882a593Smuzhiyun static int
mwl8k_cmd_set_post_scan(struct ieee80211_hw * hw,const __u8 * mac)3059*4882a593Smuzhiyun mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, const __u8 *mac)
3060*4882a593Smuzhiyun {
3061*4882a593Smuzhiyun struct mwl8k_cmd_set_post_scan *cmd;
3062*4882a593Smuzhiyun int rc;
3063*4882a593Smuzhiyun
3064*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3065*4882a593Smuzhiyun if (cmd == NULL)
3066*4882a593Smuzhiyun return -ENOMEM;
3067*4882a593Smuzhiyun
3068*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
3069*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
3070*4882a593Smuzhiyun cmd->isibss = 0;
3071*4882a593Smuzhiyun memcpy(cmd->bssid, mac, ETH_ALEN);
3072*4882a593Smuzhiyun
3073*4882a593Smuzhiyun rc = mwl8k_post_cmd(hw, &cmd->header);
3074*4882a593Smuzhiyun kfree(cmd);
3075*4882a593Smuzhiyun
3076*4882a593Smuzhiyun return rc;
3077*4882a593Smuzhiyun }
3078*4882a593Smuzhiyun
freq_to_idx(struct mwl8k_priv * priv,int freq)3079*4882a593Smuzhiyun static int freq_to_idx(struct mwl8k_priv *priv, int freq)
3080*4882a593Smuzhiyun {
3081*4882a593Smuzhiyun struct ieee80211_supported_band *sband;
3082*4882a593Smuzhiyun int band, ch, idx = 0;
3083*4882a593Smuzhiyun
3084*4882a593Smuzhiyun for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) {
3085*4882a593Smuzhiyun sband = priv->hw->wiphy->bands[band];
3086*4882a593Smuzhiyun if (!sband)
3087*4882a593Smuzhiyun continue;
3088*4882a593Smuzhiyun
3089*4882a593Smuzhiyun for (ch = 0; ch < sband->n_channels; ch++, idx++)
3090*4882a593Smuzhiyun if (sband->channels[ch].center_freq == freq)
3091*4882a593Smuzhiyun goto exit;
3092*4882a593Smuzhiyun }
3093*4882a593Smuzhiyun
3094*4882a593Smuzhiyun exit:
3095*4882a593Smuzhiyun return idx;
3096*4882a593Smuzhiyun }
3097*4882a593Smuzhiyun
mwl8k_update_survey(struct mwl8k_priv * priv,struct ieee80211_channel * channel)3098*4882a593Smuzhiyun static void mwl8k_update_survey(struct mwl8k_priv *priv,
3099*4882a593Smuzhiyun struct ieee80211_channel *channel)
3100*4882a593Smuzhiyun {
3101*4882a593Smuzhiyun u32 cca_cnt, rx_rdy;
3102*4882a593Smuzhiyun s8 nf = 0, idx;
3103*4882a593Smuzhiyun struct survey_info *survey;
3104*4882a593Smuzhiyun
3105*4882a593Smuzhiyun idx = freq_to_idx(priv, priv->acs_chan->center_freq);
3106*4882a593Smuzhiyun if (idx >= MWL8K_NUM_CHANS) {
3107*4882a593Smuzhiyun wiphy_err(priv->hw->wiphy, "Failed to update survey\n");
3108*4882a593Smuzhiyun return;
3109*4882a593Smuzhiyun }
3110*4882a593Smuzhiyun
3111*4882a593Smuzhiyun survey = &priv->survey[idx];
3112*4882a593Smuzhiyun
3113*4882a593Smuzhiyun cca_cnt = ioread32(priv->regs + NOK_CCA_CNT_REG);
3114*4882a593Smuzhiyun cca_cnt /= 1000; /* uSecs to mSecs */
3115*4882a593Smuzhiyun survey->time_busy = (u64) cca_cnt;
3116*4882a593Smuzhiyun
3117*4882a593Smuzhiyun rx_rdy = ioread32(priv->regs + BBU_RXRDY_CNT_REG);
3118*4882a593Smuzhiyun rx_rdy /= 1000; /* uSecs to mSecs */
3119*4882a593Smuzhiyun survey->time_rx = (u64) rx_rdy;
3120*4882a593Smuzhiyun
3121*4882a593Smuzhiyun priv->channel_time = jiffies - priv->channel_time;
3122*4882a593Smuzhiyun survey->time = jiffies_to_msecs(priv->channel_time);
3123*4882a593Smuzhiyun
3124*4882a593Smuzhiyun survey->channel = channel;
3125*4882a593Smuzhiyun
3126*4882a593Smuzhiyun mwl8k_cmd_bbp_reg_access(priv->hw, 0, BBU_AVG_NOISE_VAL, &nf);
3127*4882a593Smuzhiyun
3128*4882a593Smuzhiyun /* Make sure sign is negative else ACS at hostapd fails */
3129*4882a593Smuzhiyun survey->noise = nf * -1;
3130*4882a593Smuzhiyun
3131*4882a593Smuzhiyun survey->filled = SURVEY_INFO_NOISE_DBM |
3132*4882a593Smuzhiyun SURVEY_INFO_TIME |
3133*4882a593Smuzhiyun SURVEY_INFO_TIME_BUSY |
3134*4882a593Smuzhiyun SURVEY_INFO_TIME_RX;
3135*4882a593Smuzhiyun }
3136*4882a593Smuzhiyun
3137*4882a593Smuzhiyun /*
3138*4882a593Smuzhiyun * CMD_SET_RF_CHANNEL.
3139*4882a593Smuzhiyun */
3140*4882a593Smuzhiyun struct mwl8k_cmd_set_rf_channel {
3141*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
3142*4882a593Smuzhiyun __le16 action;
3143*4882a593Smuzhiyun __u8 current_channel;
3144*4882a593Smuzhiyun __le32 channel_flags;
3145*4882a593Smuzhiyun } __packed;
3146*4882a593Smuzhiyun
mwl8k_cmd_set_rf_channel(struct ieee80211_hw * hw,struct ieee80211_conf * conf)3147*4882a593Smuzhiyun static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
3148*4882a593Smuzhiyun struct ieee80211_conf *conf)
3149*4882a593Smuzhiyun {
3150*4882a593Smuzhiyun struct ieee80211_channel *channel = conf->chandef.chan;
3151*4882a593Smuzhiyun enum nl80211_channel_type channel_type =
3152*4882a593Smuzhiyun cfg80211_get_chandef_type(&conf->chandef);
3153*4882a593Smuzhiyun struct mwl8k_cmd_set_rf_channel *cmd;
3154*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
3155*4882a593Smuzhiyun int rc;
3156*4882a593Smuzhiyun
3157*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3158*4882a593Smuzhiyun if (cmd == NULL)
3159*4882a593Smuzhiyun return -ENOMEM;
3160*4882a593Smuzhiyun
3161*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
3162*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
3163*4882a593Smuzhiyun cmd->action = cpu_to_le16(MWL8K_CMD_SET);
3164*4882a593Smuzhiyun cmd->current_channel = channel->hw_value;
3165*4882a593Smuzhiyun
3166*4882a593Smuzhiyun if (channel->band == NL80211_BAND_2GHZ)
3167*4882a593Smuzhiyun cmd->channel_flags |= cpu_to_le32(0x00000001);
3168*4882a593Smuzhiyun else if (channel->band == NL80211_BAND_5GHZ)
3169*4882a593Smuzhiyun cmd->channel_flags |= cpu_to_le32(0x00000004);
3170*4882a593Smuzhiyun
3171*4882a593Smuzhiyun if (!priv->sw_scan_start) {
3172*4882a593Smuzhiyun if (channel_type == NL80211_CHAN_NO_HT ||
3173*4882a593Smuzhiyun channel_type == NL80211_CHAN_HT20)
3174*4882a593Smuzhiyun cmd->channel_flags |= cpu_to_le32(0x00000080);
3175*4882a593Smuzhiyun else if (channel_type == NL80211_CHAN_HT40MINUS)
3176*4882a593Smuzhiyun cmd->channel_flags |= cpu_to_le32(0x000001900);
3177*4882a593Smuzhiyun else if (channel_type == NL80211_CHAN_HT40PLUS)
3178*4882a593Smuzhiyun cmd->channel_flags |= cpu_to_le32(0x000000900);
3179*4882a593Smuzhiyun } else {
3180*4882a593Smuzhiyun cmd->channel_flags |= cpu_to_le32(0x00000080);
3181*4882a593Smuzhiyun }
3182*4882a593Smuzhiyun
3183*4882a593Smuzhiyun if (priv->sw_scan_start) {
3184*4882a593Smuzhiyun /* Store current channel stats
3185*4882a593Smuzhiyun * before switching to newer one.
3186*4882a593Smuzhiyun * This will be processed only for AP fw.
3187*4882a593Smuzhiyun */
3188*4882a593Smuzhiyun if (priv->channel_time != 0)
3189*4882a593Smuzhiyun mwl8k_update_survey(priv, priv->acs_chan);
3190*4882a593Smuzhiyun
3191*4882a593Smuzhiyun priv->channel_time = jiffies;
3192*4882a593Smuzhiyun priv->acs_chan = channel;
3193*4882a593Smuzhiyun }
3194*4882a593Smuzhiyun
3195*4882a593Smuzhiyun rc = mwl8k_post_cmd(hw, &cmd->header);
3196*4882a593Smuzhiyun kfree(cmd);
3197*4882a593Smuzhiyun
3198*4882a593Smuzhiyun return rc;
3199*4882a593Smuzhiyun }
3200*4882a593Smuzhiyun
3201*4882a593Smuzhiyun /*
3202*4882a593Smuzhiyun * CMD_SET_AID.
3203*4882a593Smuzhiyun */
3204*4882a593Smuzhiyun #define MWL8K_FRAME_PROT_DISABLED 0x00
3205*4882a593Smuzhiyun #define MWL8K_FRAME_PROT_11G 0x07
3206*4882a593Smuzhiyun #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
3207*4882a593Smuzhiyun #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
3208*4882a593Smuzhiyun
3209*4882a593Smuzhiyun struct mwl8k_cmd_update_set_aid {
3210*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
3211*4882a593Smuzhiyun __le16 aid;
3212*4882a593Smuzhiyun
3213*4882a593Smuzhiyun /* AP's MAC address (BSSID) */
3214*4882a593Smuzhiyun __u8 bssid[ETH_ALEN];
3215*4882a593Smuzhiyun __le16 protection_mode;
3216*4882a593Smuzhiyun __u8 supp_rates[14];
3217*4882a593Smuzhiyun } __packed;
3218*4882a593Smuzhiyun
legacy_rate_mask_to_array(u8 * rates,u32 mask)3219*4882a593Smuzhiyun static void legacy_rate_mask_to_array(u8 *rates, u32 mask)
3220*4882a593Smuzhiyun {
3221*4882a593Smuzhiyun int i;
3222*4882a593Smuzhiyun int j;
3223*4882a593Smuzhiyun
3224*4882a593Smuzhiyun /*
3225*4882a593Smuzhiyun * Clear nonstandard rate 4.
3226*4882a593Smuzhiyun */
3227*4882a593Smuzhiyun mask &= 0x1fef;
3228*4882a593Smuzhiyun
3229*4882a593Smuzhiyun for (i = 0, j = 0; i < 13; i++) {
3230*4882a593Smuzhiyun if (mask & (1 << i))
3231*4882a593Smuzhiyun rates[j++] = mwl8k_rates_24[i].hw_value;
3232*4882a593Smuzhiyun }
3233*4882a593Smuzhiyun }
3234*4882a593Smuzhiyun
3235*4882a593Smuzhiyun static int
mwl8k_cmd_set_aid(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u32 legacy_rate_mask)3236*4882a593Smuzhiyun mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
3237*4882a593Smuzhiyun struct ieee80211_vif *vif, u32 legacy_rate_mask)
3238*4882a593Smuzhiyun {
3239*4882a593Smuzhiyun struct mwl8k_cmd_update_set_aid *cmd;
3240*4882a593Smuzhiyun u16 prot_mode;
3241*4882a593Smuzhiyun int rc;
3242*4882a593Smuzhiyun
3243*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3244*4882a593Smuzhiyun if (cmd == NULL)
3245*4882a593Smuzhiyun return -ENOMEM;
3246*4882a593Smuzhiyun
3247*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
3248*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
3249*4882a593Smuzhiyun cmd->aid = cpu_to_le16(vif->bss_conf.aid);
3250*4882a593Smuzhiyun memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN);
3251*4882a593Smuzhiyun
3252*4882a593Smuzhiyun if (vif->bss_conf.use_cts_prot) {
3253*4882a593Smuzhiyun prot_mode = MWL8K_FRAME_PROT_11G;
3254*4882a593Smuzhiyun } else {
3255*4882a593Smuzhiyun switch (vif->bss_conf.ht_operation_mode &
3256*4882a593Smuzhiyun IEEE80211_HT_OP_MODE_PROTECTION) {
3257*4882a593Smuzhiyun case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
3258*4882a593Smuzhiyun prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
3259*4882a593Smuzhiyun break;
3260*4882a593Smuzhiyun case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
3261*4882a593Smuzhiyun prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
3262*4882a593Smuzhiyun break;
3263*4882a593Smuzhiyun default:
3264*4882a593Smuzhiyun prot_mode = MWL8K_FRAME_PROT_DISABLED;
3265*4882a593Smuzhiyun break;
3266*4882a593Smuzhiyun }
3267*4882a593Smuzhiyun }
3268*4882a593Smuzhiyun cmd->protection_mode = cpu_to_le16(prot_mode);
3269*4882a593Smuzhiyun
3270*4882a593Smuzhiyun legacy_rate_mask_to_array(cmd->supp_rates, legacy_rate_mask);
3271*4882a593Smuzhiyun
3272*4882a593Smuzhiyun rc = mwl8k_post_cmd(hw, &cmd->header);
3273*4882a593Smuzhiyun kfree(cmd);
3274*4882a593Smuzhiyun
3275*4882a593Smuzhiyun return rc;
3276*4882a593Smuzhiyun }
3277*4882a593Smuzhiyun
3278*4882a593Smuzhiyun /*
3279*4882a593Smuzhiyun * CMD_SET_RATE.
3280*4882a593Smuzhiyun */
3281*4882a593Smuzhiyun struct mwl8k_cmd_set_rate {
3282*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
3283*4882a593Smuzhiyun __u8 legacy_rates[14];
3284*4882a593Smuzhiyun
3285*4882a593Smuzhiyun /* Bitmap for supported MCS codes. */
3286*4882a593Smuzhiyun __u8 mcs_set[16];
3287*4882a593Smuzhiyun __u8 reserved[16];
3288*4882a593Smuzhiyun } __packed;
3289*4882a593Smuzhiyun
3290*4882a593Smuzhiyun static int
mwl8k_cmd_set_rate(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u32 legacy_rate_mask,u8 * mcs_rates)3291*4882a593Smuzhiyun mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3292*4882a593Smuzhiyun u32 legacy_rate_mask, u8 *mcs_rates)
3293*4882a593Smuzhiyun {
3294*4882a593Smuzhiyun struct mwl8k_cmd_set_rate *cmd;
3295*4882a593Smuzhiyun int rc;
3296*4882a593Smuzhiyun
3297*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3298*4882a593Smuzhiyun if (cmd == NULL)
3299*4882a593Smuzhiyun return -ENOMEM;
3300*4882a593Smuzhiyun
3301*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
3302*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
3303*4882a593Smuzhiyun legacy_rate_mask_to_array(cmd->legacy_rates, legacy_rate_mask);
3304*4882a593Smuzhiyun memcpy(cmd->mcs_set, mcs_rates, 16);
3305*4882a593Smuzhiyun
3306*4882a593Smuzhiyun rc = mwl8k_post_cmd(hw, &cmd->header);
3307*4882a593Smuzhiyun kfree(cmd);
3308*4882a593Smuzhiyun
3309*4882a593Smuzhiyun return rc;
3310*4882a593Smuzhiyun }
3311*4882a593Smuzhiyun
3312*4882a593Smuzhiyun /*
3313*4882a593Smuzhiyun * CMD_FINALIZE_JOIN.
3314*4882a593Smuzhiyun */
3315*4882a593Smuzhiyun #define MWL8K_FJ_BEACON_MAXLEN 128
3316*4882a593Smuzhiyun
3317*4882a593Smuzhiyun struct mwl8k_cmd_finalize_join {
3318*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
3319*4882a593Smuzhiyun __le32 sleep_interval; /* Number of beacon periods to sleep */
3320*4882a593Smuzhiyun __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
3321*4882a593Smuzhiyun } __packed;
3322*4882a593Smuzhiyun
mwl8k_cmd_finalize_join(struct ieee80211_hw * hw,void * frame,int framelen,int dtim)3323*4882a593Smuzhiyun static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame,
3324*4882a593Smuzhiyun int framelen, int dtim)
3325*4882a593Smuzhiyun {
3326*4882a593Smuzhiyun struct mwl8k_cmd_finalize_join *cmd;
3327*4882a593Smuzhiyun struct ieee80211_mgmt *payload = frame;
3328*4882a593Smuzhiyun int payload_len;
3329*4882a593Smuzhiyun int rc;
3330*4882a593Smuzhiyun
3331*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3332*4882a593Smuzhiyun if (cmd == NULL)
3333*4882a593Smuzhiyun return -ENOMEM;
3334*4882a593Smuzhiyun
3335*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
3336*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
3337*4882a593Smuzhiyun cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
3338*4882a593Smuzhiyun
3339*4882a593Smuzhiyun payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
3340*4882a593Smuzhiyun if (payload_len < 0)
3341*4882a593Smuzhiyun payload_len = 0;
3342*4882a593Smuzhiyun else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
3343*4882a593Smuzhiyun payload_len = MWL8K_FJ_BEACON_MAXLEN;
3344*4882a593Smuzhiyun
3345*4882a593Smuzhiyun memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
3346*4882a593Smuzhiyun
3347*4882a593Smuzhiyun rc = mwl8k_post_cmd(hw, &cmd->header);
3348*4882a593Smuzhiyun kfree(cmd);
3349*4882a593Smuzhiyun
3350*4882a593Smuzhiyun return rc;
3351*4882a593Smuzhiyun }
3352*4882a593Smuzhiyun
3353*4882a593Smuzhiyun /*
3354*4882a593Smuzhiyun * CMD_SET_RTS_THRESHOLD.
3355*4882a593Smuzhiyun */
3356*4882a593Smuzhiyun struct mwl8k_cmd_set_rts_threshold {
3357*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
3358*4882a593Smuzhiyun __le16 action;
3359*4882a593Smuzhiyun __le16 threshold;
3360*4882a593Smuzhiyun } __packed;
3361*4882a593Smuzhiyun
3362*4882a593Smuzhiyun static int
mwl8k_cmd_set_rts_threshold(struct ieee80211_hw * hw,int rts_thresh)3363*4882a593Smuzhiyun mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw, int rts_thresh)
3364*4882a593Smuzhiyun {
3365*4882a593Smuzhiyun struct mwl8k_cmd_set_rts_threshold *cmd;
3366*4882a593Smuzhiyun int rc;
3367*4882a593Smuzhiyun
3368*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3369*4882a593Smuzhiyun if (cmd == NULL)
3370*4882a593Smuzhiyun return -ENOMEM;
3371*4882a593Smuzhiyun
3372*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
3373*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
3374*4882a593Smuzhiyun cmd->action = cpu_to_le16(MWL8K_CMD_SET);
3375*4882a593Smuzhiyun cmd->threshold = cpu_to_le16(rts_thresh);
3376*4882a593Smuzhiyun
3377*4882a593Smuzhiyun rc = mwl8k_post_cmd(hw, &cmd->header);
3378*4882a593Smuzhiyun kfree(cmd);
3379*4882a593Smuzhiyun
3380*4882a593Smuzhiyun return rc;
3381*4882a593Smuzhiyun }
3382*4882a593Smuzhiyun
3383*4882a593Smuzhiyun /*
3384*4882a593Smuzhiyun * CMD_SET_SLOT.
3385*4882a593Smuzhiyun */
3386*4882a593Smuzhiyun struct mwl8k_cmd_set_slot {
3387*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
3388*4882a593Smuzhiyun __le16 action;
3389*4882a593Smuzhiyun __u8 short_slot;
3390*4882a593Smuzhiyun } __packed;
3391*4882a593Smuzhiyun
mwl8k_cmd_set_slot(struct ieee80211_hw * hw,bool short_slot_time)3392*4882a593Smuzhiyun static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
3393*4882a593Smuzhiyun {
3394*4882a593Smuzhiyun struct mwl8k_cmd_set_slot *cmd;
3395*4882a593Smuzhiyun int rc;
3396*4882a593Smuzhiyun
3397*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3398*4882a593Smuzhiyun if (cmd == NULL)
3399*4882a593Smuzhiyun return -ENOMEM;
3400*4882a593Smuzhiyun
3401*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
3402*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
3403*4882a593Smuzhiyun cmd->action = cpu_to_le16(MWL8K_CMD_SET);
3404*4882a593Smuzhiyun cmd->short_slot = short_slot_time;
3405*4882a593Smuzhiyun
3406*4882a593Smuzhiyun rc = mwl8k_post_cmd(hw, &cmd->header);
3407*4882a593Smuzhiyun kfree(cmd);
3408*4882a593Smuzhiyun
3409*4882a593Smuzhiyun return rc;
3410*4882a593Smuzhiyun }
3411*4882a593Smuzhiyun
3412*4882a593Smuzhiyun /*
3413*4882a593Smuzhiyun * CMD_SET_EDCA_PARAMS.
3414*4882a593Smuzhiyun */
3415*4882a593Smuzhiyun struct mwl8k_cmd_set_edca_params {
3416*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
3417*4882a593Smuzhiyun
3418*4882a593Smuzhiyun /* See MWL8K_SET_EDCA_XXX below */
3419*4882a593Smuzhiyun __le16 action;
3420*4882a593Smuzhiyun
3421*4882a593Smuzhiyun /* TX opportunity in units of 32 us */
3422*4882a593Smuzhiyun __le16 txop;
3423*4882a593Smuzhiyun
3424*4882a593Smuzhiyun union {
3425*4882a593Smuzhiyun struct {
3426*4882a593Smuzhiyun /* Log exponent of max contention period: 0...15 */
3427*4882a593Smuzhiyun __le32 log_cw_max;
3428*4882a593Smuzhiyun
3429*4882a593Smuzhiyun /* Log exponent of min contention period: 0...15 */
3430*4882a593Smuzhiyun __le32 log_cw_min;
3431*4882a593Smuzhiyun
3432*4882a593Smuzhiyun /* Adaptive interframe spacing in units of 32us */
3433*4882a593Smuzhiyun __u8 aifs;
3434*4882a593Smuzhiyun
3435*4882a593Smuzhiyun /* TX queue to configure */
3436*4882a593Smuzhiyun __u8 txq;
3437*4882a593Smuzhiyun } ap;
3438*4882a593Smuzhiyun struct {
3439*4882a593Smuzhiyun /* Log exponent of max contention period: 0...15 */
3440*4882a593Smuzhiyun __u8 log_cw_max;
3441*4882a593Smuzhiyun
3442*4882a593Smuzhiyun /* Log exponent of min contention period: 0...15 */
3443*4882a593Smuzhiyun __u8 log_cw_min;
3444*4882a593Smuzhiyun
3445*4882a593Smuzhiyun /* Adaptive interframe spacing in units of 32us */
3446*4882a593Smuzhiyun __u8 aifs;
3447*4882a593Smuzhiyun
3448*4882a593Smuzhiyun /* TX queue to configure */
3449*4882a593Smuzhiyun __u8 txq;
3450*4882a593Smuzhiyun } sta;
3451*4882a593Smuzhiyun };
3452*4882a593Smuzhiyun } __packed;
3453*4882a593Smuzhiyun
3454*4882a593Smuzhiyun #define MWL8K_SET_EDCA_CW 0x01
3455*4882a593Smuzhiyun #define MWL8K_SET_EDCA_TXOP 0x02
3456*4882a593Smuzhiyun #define MWL8K_SET_EDCA_AIFS 0x04
3457*4882a593Smuzhiyun
3458*4882a593Smuzhiyun #define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
3459*4882a593Smuzhiyun MWL8K_SET_EDCA_TXOP | \
3460*4882a593Smuzhiyun MWL8K_SET_EDCA_AIFS)
3461*4882a593Smuzhiyun
3462*4882a593Smuzhiyun static int
mwl8k_cmd_set_edca_params(struct ieee80211_hw * hw,__u8 qnum,__u16 cw_min,__u16 cw_max,__u8 aifs,__u16 txop)3463*4882a593Smuzhiyun mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
3464*4882a593Smuzhiyun __u16 cw_min, __u16 cw_max,
3465*4882a593Smuzhiyun __u8 aifs, __u16 txop)
3466*4882a593Smuzhiyun {
3467*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
3468*4882a593Smuzhiyun struct mwl8k_cmd_set_edca_params *cmd;
3469*4882a593Smuzhiyun int rc;
3470*4882a593Smuzhiyun
3471*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3472*4882a593Smuzhiyun if (cmd == NULL)
3473*4882a593Smuzhiyun return -ENOMEM;
3474*4882a593Smuzhiyun
3475*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
3476*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
3477*4882a593Smuzhiyun cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
3478*4882a593Smuzhiyun cmd->txop = cpu_to_le16(txop);
3479*4882a593Smuzhiyun if (priv->ap_fw) {
3480*4882a593Smuzhiyun cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
3481*4882a593Smuzhiyun cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
3482*4882a593Smuzhiyun cmd->ap.aifs = aifs;
3483*4882a593Smuzhiyun cmd->ap.txq = qnum;
3484*4882a593Smuzhiyun } else {
3485*4882a593Smuzhiyun cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
3486*4882a593Smuzhiyun cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
3487*4882a593Smuzhiyun cmd->sta.aifs = aifs;
3488*4882a593Smuzhiyun cmd->sta.txq = qnum;
3489*4882a593Smuzhiyun }
3490*4882a593Smuzhiyun
3491*4882a593Smuzhiyun rc = mwl8k_post_cmd(hw, &cmd->header);
3492*4882a593Smuzhiyun kfree(cmd);
3493*4882a593Smuzhiyun
3494*4882a593Smuzhiyun return rc;
3495*4882a593Smuzhiyun }
3496*4882a593Smuzhiyun
3497*4882a593Smuzhiyun /*
3498*4882a593Smuzhiyun * CMD_SET_WMM_MODE.
3499*4882a593Smuzhiyun */
3500*4882a593Smuzhiyun struct mwl8k_cmd_set_wmm_mode {
3501*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
3502*4882a593Smuzhiyun __le16 action;
3503*4882a593Smuzhiyun } __packed;
3504*4882a593Smuzhiyun
mwl8k_cmd_set_wmm_mode(struct ieee80211_hw * hw,bool enable)3505*4882a593Smuzhiyun static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable)
3506*4882a593Smuzhiyun {
3507*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
3508*4882a593Smuzhiyun struct mwl8k_cmd_set_wmm_mode *cmd;
3509*4882a593Smuzhiyun int rc;
3510*4882a593Smuzhiyun
3511*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3512*4882a593Smuzhiyun if (cmd == NULL)
3513*4882a593Smuzhiyun return -ENOMEM;
3514*4882a593Smuzhiyun
3515*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
3516*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
3517*4882a593Smuzhiyun cmd->action = cpu_to_le16(!!enable);
3518*4882a593Smuzhiyun
3519*4882a593Smuzhiyun rc = mwl8k_post_cmd(hw, &cmd->header);
3520*4882a593Smuzhiyun kfree(cmd);
3521*4882a593Smuzhiyun
3522*4882a593Smuzhiyun if (!rc)
3523*4882a593Smuzhiyun priv->wmm_enabled = enable;
3524*4882a593Smuzhiyun
3525*4882a593Smuzhiyun return rc;
3526*4882a593Smuzhiyun }
3527*4882a593Smuzhiyun
3528*4882a593Smuzhiyun /*
3529*4882a593Smuzhiyun * CMD_MIMO_CONFIG.
3530*4882a593Smuzhiyun */
3531*4882a593Smuzhiyun struct mwl8k_cmd_mimo_config {
3532*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
3533*4882a593Smuzhiyun __le32 action;
3534*4882a593Smuzhiyun __u8 rx_antenna_map;
3535*4882a593Smuzhiyun __u8 tx_antenna_map;
3536*4882a593Smuzhiyun } __packed;
3537*4882a593Smuzhiyun
mwl8k_cmd_mimo_config(struct ieee80211_hw * hw,__u8 rx,__u8 tx)3538*4882a593Smuzhiyun static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
3539*4882a593Smuzhiyun {
3540*4882a593Smuzhiyun struct mwl8k_cmd_mimo_config *cmd;
3541*4882a593Smuzhiyun int rc;
3542*4882a593Smuzhiyun
3543*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3544*4882a593Smuzhiyun if (cmd == NULL)
3545*4882a593Smuzhiyun return -ENOMEM;
3546*4882a593Smuzhiyun
3547*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
3548*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
3549*4882a593Smuzhiyun cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
3550*4882a593Smuzhiyun cmd->rx_antenna_map = rx;
3551*4882a593Smuzhiyun cmd->tx_antenna_map = tx;
3552*4882a593Smuzhiyun
3553*4882a593Smuzhiyun rc = mwl8k_post_cmd(hw, &cmd->header);
3554*4882a593Smuzhiyun kfree(cmd);
3555*4882a593Smuzhiyun
3556*4882a593Smuzhiyun return rc;
3557*4882a593Smuzhiyun }
3558*4882a593Smuzhiyun
3559*4882a593Smuzhiyun /*
3560*4882a593Smuzhiyun * CMD_USE_FIXED_RATE (STA version).
3561*4882a593Smuzhiyun */
3562*4882a593Smuzhiyun struct mwl8k_cmd_use_fixed_rate_sta {
3563*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
3564*4882a593Smuzhiyun __le32 action;
3565*4882a593Smuzhiyun __le32 allow_rate_drop;
3566*4882a593Smuzhiyun __le32 num_rates;
3567*4882a593Smuzhiyun struct {
3568*4882a593Smuzhiyun __le32 is_ht_rate;
3569*4882a593Smuzhiyun __le32 enable_retry;
3570*4882a593Smuzhiyun __le32 rate;
3571*4882a593Smuzhiyun __le32 retry_count;
3572*4882a593Smuzhiyun } rate_entry[8];
3573*4882a593Smuzhiyun __le32 rate_type;
3574*4882a593Smuzhiyun __le32 reserved1;
3575*4882a593Smuzhiyun __le32 reserved2;
3576*4882a593Smuzhiyun } __packed;
3577*4882a593Smuzhiyun
3578*4882a593Smuzhiyun #define MWL8K_USE_AUTO_RATE 0x0002
3579*4882a593Smuzhiyun #define MWL8K_UCAST_RATE 0
3580*4882a593Smuzhiyun
mwl8k_cmd_use_fixed_rate_sta(struct ieee80211_hw * hw)3581*4882a593Smuzhiyun static int mwl8k_cmd_use_fixed_rate_sta(struct ieee80211_hw *hw)
3582*4882a593Smuzhiyun {
3583*4882a593Smuzhiyun struct mwl8k_cmd_use_fixed_rate_sta *cmd;
3584*4882a593Smuzhiyun int rc;
3585*4882a593Smuzhiyun
3586*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3587*4882a593Smuzhiyun if (cmd == NULL)
3588*4882a593Smuzhiyun return -ENOMEM;
3589*4882a593Smuzhiyun
3590*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
3591*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
3592*4882a593Smuzhiyun cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
3593*4882a593Smuzhiyun cmd->rate_type = cpu_to_le32(MWL8K_UCAST_RATE);
3594*4882a593Smuzhiyun
3595*4882a593Smuzhiyun rc = mwl8k_post_cmd(hw, &cmd->header);
3596*4882a593Smuzhiyun kfree(cmd);
3597*4882a593Smuzhiyun
3598*4882a593Smuzhiyun return rc;
3599*4882a593Smuzhiyun }
3600*4882a593Smuzhiyun
3601*4882a593Smuzhiyun /*
3602*4882a593Smuzhiyun * CMD_USE_FIXED_RATE (AP version).
3603*4882a593Smuzhiyun */
3604*4882a593Smuzhiyun struct mwl8k_cmd_use_fixed_rate_ap {
3605*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
3606*4882a593Smuzhiyun __le32 action;
3607*4882a593Smuzhiyun __le32 allow_rate_drop;
3608*4882a593Smuzhiyun __le32 num_rates;
3609*4882a593Smuzhiyun struct mwl8k_rate_entry_ap {
3610*4882a593Smuzhiyun __le32 is_ht_rate;
3611*4882a593Smuzhiyun __le32 enable_retry;
3612*4882a593Smuzhiyun __le32 rate;
3613*4882a593Smuzhiyun __le32 retry_count;
3614*4882a593Smuzhiyun } rate_entry[4];
3615*4882a593Smuzhiyun u8 multicast_rate;
3616*4882a593Smuzhiyun u8 multicast_rate_type;
3617*4882a593Smuzhiyun u8 management_rate;
3618*4882a593Smuzhiyun } __packed;
3619*4882a593Smuzhiyun
3620*4882a593Smuzhiyun static int
mwl8k_cmd_use_fixed_rate_ap(struct ieee80211_hw * hw,int mcast,int mgmt)3621*4882a593Smuzhiyun mwl8k_cmd_use_fixed_rate_ap(struct ieee80211_hw *hw, int mcast, int mgmt)
3622*4882a593Smuzhiyun {
3623*4882a593Smuzhiyun struct mwl8k_cmd_use_fixed_rate_ap *cmd;
3624*4882a593Smuzhiyun int rc;
3625*4882a593Smuzhiyun
3626*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3627*4882a593Smuzhiyun if (cmd == NULL)
3628*4882a593Smuzhiyun return -ENOMEM;
3629*4882a593Smuzhiyun
3630*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
3631*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
3632*4882a593Smuzhiyun cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
3633*4882a593Smuzhiyun cmd->multicast_rate = mcast;
3634*4882a593Smuzhiyun cmd->management_rate = mgmt;
3635*4882a593Smuzhiyun
3636*4882a593Smuzhiyun rc = mwl8k_post_cmd(hw, &cmd->header);
3637*4882a593Smuzhiyun kfree(cmd);
3638*4882a593Smuzhiyun
3639*4882a593Smuzhiyun return rc;
3640*4882a593Smuzhiyun }
3641*4882a593Smuzhiyun
3642*4882a593Smuzhiyun /*
3643*4882a593Smuzhiyun * CMD_ENABLE_SNIFFER.
3644*4882a593Smuzhiyun */
3645*4882a593Smuzhiyun struct mwl8k_cmd_enable_sniffer {
3646*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
3647*4882a593Smuzhiyun __le32 action;
3648*4882a593Smuzhiyun } __packed;
3649*4882a593Smuzhiyun
mwl8k_cmd_enable_sniffer(struct ieee80211_hw * hw,bool enable)3650*4882a593Smuzhiyun static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable)
3651*4882a593Smuzhiyun {
3652*4882a593Smuzhiyun struct mwl8k_cmd_enable_sniffer *cmd;
3653*4882a593Smuzhiyun int rc;
3654*4882a593Smuzhiyun
3655*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3656*4882a593Smuzhiyun if (cmd == NULL)
3657*4882a593Smuzhiyun return -ENOMEM;
3658*4882a593Smuzhiyun
3659*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
3660*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
3661*4882a593Smuzhiyun cmd->action = cpu_to_le32(!!enable);
3662*4882a593Smuzhiyun
3663*4882a593Smuzhiyun rc = mwl8k_post_cmd(hw, &cmd->header);
3664*4882a593Smuzhiyun kfree(cmd);
3665*4882a593Smuzhiyun
3666*4882a593Smuzhiyun return rc;
3667*4882a593Smuzhiyun }
3668*4882a593Smuzhiyun
3669*4882a593Smuzhiyun struct mwl8k_cmd_update_mac_addr {
3670*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
3671*4882a593Smuzhiyun union {
3672*4882a593Smuzhiyun struct {
3673*4882a593Smuzhiyun __le16 mac_type;
3674*4882a593Smuzhiyun __u8 mac_addr[ETH_ALEN];
3675*4882a593Smuzhiyun } mbss;
3676*4882a593Smuzhiyun __u8 mac_addr[ETH_ALEN];
3677*4882a593Smuzhiyun };
3678*4882a593Smuzhiyun } __packed;
3679*4882a593Smuzhiyun
3680*4882a593Smuzhiyun #define MWL8K_MAC_TYPE_PRIMARY_CLIENT 0
3681*4882a593Smuzhiyun #define MWL8K_MAC_TYPE_SECONDARY_CLIENT 1
3682*4882a593Smuzhiyun #define MWL8K_MAC_TYPE_PRIMARY_AP 2
3683*4882a593Smuzhiyun #define MWL8K_MAC_TYPE_SECONDARY_AP 3
3684*4882a593Smuzhiyun
mwl8k_cmd_update_mac_addr(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u8 * mac,bool set)3685*4882a593Smuzhiyun static int mwl8k_cmd_update_mac_addr(struct ieee80211_hw *hw,
3686*4882a593Smuzhiyun struct ieee80211_vif *vif, u8 *mac, bool set)
3687*4882a593Smuzhiyun {
3688*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
3689*4882a593Smuzhiyun struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3690*4882a593Smuzhiyun struct mwl8k_cmd_update_mac_addr *cmd;
3691*4882a593Smuzhiyun int mac_type;
3692*4882a593Smuzhiyun int rc;
3693*4882a593Smuzhiyun
3694*4882a593Smuzhiyun mac_type = MWL8K_MAC_TYPE_PRIMARY_AP;
3695*4882a593Smuzhiyun if (vif != NULL && vif->type == NL80211_IFTYPE_STATION) {
3696*4882a593Smuzhiyun if (mwl8k_vif->macid + 1 == ffs(priv->sta_macids_supported))
3697*4882a593Smuzhiyun if (priv->ap_fw)
3698*4882a593Smuzhiyun mac_type = MWL8K_MAC_TYPE_SECONDARY_CLIENT;
3699*4882a593Smuzhiyun else
3700*4882a593Smuzhiyun mac_type = MWL8K_MAC_TYPE_PRIMARY_CLIENT;
3701*4882a593Smuzhiyun else
3702*4882a593Smuzhiyun mac_type = MWL8K_MAC_TYPE_SECONDARY_CLIENT;
3703*4882a593Smuzhiyun } else if (vif != NULL && vif->type == NL80211_IFTYPE_AP) {
3704*4882a593Smuzhiyun if (mwl8k_vif->macid + 1 == ffs(priv->ap_macids_supported))
3705*4882a593Smuzhiyun mac_type = MWL8K_MAC_TYPE_PRIMARY_AP;
3706*4882a593Smuzhiyun else
3707*4882a593Smuzhiyun mac_type = MWL8K_MAC_TYPE_SECONDARY_AP;
3708*4882a593Smuzhiyun }
3709*4882a593Smuzhiyun
3710*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3711*4882a593Smuzhiyun if (cmd == NULL)
3712*4882a593Smuzhiyun return -ENOMEM;
3713*4882a593Smuzhiyun
3714*4882a593Smuzhiyun if (set)
3715*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
3716*4882a593Smuzhiyun else
3717*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_DEL_MAC_ADDR);
3718*4882a593Smuzhiyun
3719*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
3720*4882a593Smuzhiyun if (priv->ap_fw) {
3721*4882a593Smuzhiyun cmd->mbss.mac_type = cpu_to_le16(mac_type);
3722*4882a593Smuzhiyun memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
3723*4882a593Smuzhiyun } else {
3724*4882a593Smuzhiyun memcpy(cmd->mac_addr, mac, ETH_ALEN);
3725*4882a593Smuzhiyun }
3726*4882a593Smuzhiyun
3727*4882a593Smuzhiyun rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3728*4882a593Smuzhiyun kfree(cmd);
3729*4882a593Smuzhiyun
3730*4882a593Smuzhiyun return rc;
3731*4882a593Smuzhiyun }
3732*4882a593Smuzhiyun
3733*4882a593Smuzhiyun /*
3734*4882a593Smuzhiyun * MWL8K_CMD_SET_MAC_ADDR.
3735*4882a593Smuzhiyun */
mwl8k_cmd_set_mac_addr(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u8 * mac)3736*4882a593Smuzhiyun static inline int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw,
3737*4882a593Smuzhiyun struct ieee80211_vif *vif, u8 *mac)
3738*4882a593Smuzhiyun {
3739*4882a593Smuzhiyun return mwl8k_cmd_update_mac_addr(hw, vif, mac, true);
3740*4882a593Smuzhiyun }
3741*4882a593Smuzhiyun
3742*4882a593Smuzhiyun /*
3743*4882a593Smuzhiyun * MWL8K_CMD_DEL_MAC_ADDR.
3744*4882a593Smuzhiyun */
mwl8k_cmd_del_mac_addr(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u8 * mac)3745*4882a593Smuzhiyun static inline int mwl8k_cmd_del_mac_addr(struct ieee80211_hw *hw,
3746*4882a593Smuzhiyun struct ieee80211_vif *vif, u8 *mac)
3747*4882a593Smuzhiyun {
3748*4882a593Smuzhiyun return mwl8k_cmd_update_mac_addr(hw, vif, mac, false);
3749*4882a593Smuzhiyun }
3750*4882a593Smuzhiyun
3751*4882a593Smuzhiyun /*
3752*4882a593Smuzhiyun * CMD_SET_RATEADAPT_MODE.
3753*4882a593Smuzhiyun */
3754*4882a593Smuzhiyun struct mwl8k_cmd_set_rate_adapt_mode {
3755*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
3756*4882a593Smuzhiyun __le16 action;
3757*4882a593Smuzhiyun __le16 mode;
3758*4882a593Smuzhiyun } __packed;
3759*4882a593Smuzhiyun
mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw * hw,__u16 mode)3760*4882a593Smuzhiyun static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode)
3761*4882a593Smuzhiyun {
3762*4882a593Smuzhiyun struct mwl8k_cmd_set_rate_adapt_mode *cmd;
3763*4882a593Smuzhiyun int rc;
3764*4882a593Smuzhiyun
3765*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3766*4882a593Smuzhiyun if (cmd == NULL)
3767*4882a593Smuzhiyun return -ENOMEM;
3768*4882a593Smuzhiyun
3769*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
3770*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
3771*4882a593Smuzhiyun cmd->action = cpu_to_le16(MWL8K_CMD_SET);
3772*4882a593Smuzhiyun cmd->mode = cpu_to_le16(mode);
3773*4882a593Smuzhiyun
3774*4882a593Smuzhiyun rc = mwl8k_post_cmd(hw, &cmd->header);
3775*4882a593Smuzhiyun kfree(cmd);
3776*4882a593Smuzhiyun
3777*4882a593Smuzhiyun return rc;
3778*4882a593Smuzhiyun }
3779*4882a593Smuzhiyun
3780*4882a593Smuzhiyun /*
3781*4882a593Smuzhiyun * CMD_GET_WATCHDOG_BITMAP.
3782*4882a593Smuzhiyun */
3783*4882a593Smuzhiyun struct mwl8k_cmd_get_watchdog_bitmap {
3784*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
3785*4882a593Smuzhiyun u8 bitmap;
3786*4882a593Smuzhiyun } __packed;
3787*4882a593Smuzhiyun
mwl8k_cmd_get_watchdog_bitmap(struct ieee80211_hw * hw,u8 * bitmap)3788*4882a593Smuzhiyun static int mwl8k_cmd_get_watchdog_bitmap(struct ieee80211_hw *hw, u8 *bitmap)
3789*4882a593Smuzhiyun {
3790*4882a593Smuzhiyun struct mwl8k_cmd_get_watchdog_bitmap *cmd;
3791*4882a593Smuzhiyun int rc;
3792*4882a593Smuzhiyun
3793*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3794*4882a593Smuzhiyun if (cmd == NULL)
3795*4882a593Smuzhiyun return -ENOMEM;
3796*4882a593Smuzhiyun
3797*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_WATCHDOG_BITMAP);
3798*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
3799*4882a593Smuzhiyun
3800*4882a593Smuzhiyun rc = mwl8k_post_cmd(hw, &cmd->header);
3801*4882a593Smuzhiyun if (!rc)
3802*4882a593Smuzhiyun *bitmap = cmd->bitmap;
3803*4882a593Smuzhiyun
3804*4882a593Smuzhiyun kfree(cmd);
3805*4882a593Smuzhiyun
3806*4882a593Smuzhiyun return rc;
3807*4882a593Smuzhiyun }
3808*4882a593Smuzhiyun
3809*4882a593Smuzhiyun #define MWL8K_WMM_QUEUE_NUMBER 3
3810*4882a593Smuzhiyun
3811*4882a593Smuzhiyun static void mwl8k_destroy_ba(struct ieee80211_hw *hw,
3812*4882a593Smuzhiyun u8 idx);
3813*4882a593Smuzhiyun
mwl8k_watchdog_ba_events(struct work_struct * work)3814*4882a593Smuzhiyun static void mwl8k_watchdog_ba_events(struct work_struct *work)
3815*4882a593Smuzhiyun {
3816*4882a593Smuzhiyun int rc;
3817*4882a593Smuzhiyun u8 bitmap = 0, stream_index;
3818*4882a593Smuzhiyun struct mwl8k_ampdu_stream *streams;
3819*4882a593Smuzhiyun struct mwl8k_priv *priv =
3820*4882a593Smuzhiyun container_of(work, struct mwl8k_priv, watchdog_ba_handle);
3821*4882a593Smuzhiyun struct ieee80211_hw *hw = priv->hw;
3822*4882a593Smuzhiyun int i;
3823*4882a593Smuzhiyun u32 status = 0;
3824*4882a593Smuzhiyun
3825*4882a593Smuzhiyun mwl8k_fw_lock(hw);
3826*4882a593Smuzhiyun
3827*4882a593Smuzhiyun rc = mwl8k_cmd_get_watchdog_bitmap(priv->hw, &bitmap);
3828*4882a593Smuzhiyun if (rc)
3829*4882a593Smuzhiyun goto done;
3830*4882a593Smuzhiyun
3831*4882a593Smuzhiyun spin_lock(&priv->stream_lock);
3832*4882a593Smuzhiyun
3833*4882a593Smuzhiyun /* the bitmap is the hw queue number. Map it to the ampdu queue. */
3834*4882a593Smuzhiyun for (i = 0; i < TOTAL_HW_TX_QUEUES; i++) {
3835*4882a593Smuzhiyun if (bitmap & (1 << i)) {
3836*4882a593Smuzhiyun stream_index = (i + MWL8K_WMM_QUEUE_NUMBER) %
3837*4882a593Smuzhiyun TOTAL_HW_TX_QUEUES;
3838*4882a593Smuzhiyun streams = &priv->ampdu[stream_index];
3839*4882a593Smuzhiyun if (streams->state == AMPDU_STREAM_ACTIVE) {
3840*4882a593Smuzhiyun ieee80211_stop_tx_ba_session(streams->sta,
3841*4882a593Smuzhiyun streams->tid);
3842*4882a593Smuzhiyun spin_unlock(&priv->stream_lock);
3843*4882a593Smuzhiyun mwl8k_destroy_ba(hw, stream_index);
3844*4882a593Smuzhiyun spin_lock(&priv->stream_lock);
3845*4882a593Smuzhiyun }
3846*4882a593Smuzhiyun }
3847*4882a593Smuzhiyun }
3848*4882a593Smuzhiyun
3849*4882a593Smuzhiyun spin_unlock(&priv->stream_lock);
3850*4882a593Smuzhiyun done:
3851*4882a593Smuzhiyun atomic_dec(&priv->watchdog_event_pending);
3852*4882a593Smuzhiyun status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3853*4882a593Smuzhiyun iowrite32((status | MWL8K_A2H_INT_BA_WATCHDOG),
3854*4882a593Smuzhiyun priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3855*4882a593Smuzhiyun mwl8k_fw_unlock(hw);
3856*4882a593Smuzhiyun return;
3857*4882a593Smuzhiyun }
3858*4882a593Smuzhiyun
3859*4882a593Smuzhiyun
3860*4882a593Smuzhiyun /*
3861*4882a593Smuzhiyun * CMD_BSS_START.
3862*4882a593Smuzhiyun */
3863*4882a593Smuzhiyun struct mwl8k_cmd_bss_start {
3864*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
3865*4882a593Smuzhiyun __le32 enable;
3866*4882a593Smuzhiyun } __packed;
3867*4882a593Smuzhiyun
mwl8k_cmd_bss_start(struct ieee80211_hw * hw,struct ieee80211_vif * vif,int enable)3868*4882a593Smuzhiyun static int mwl8k_cmd_bss_start(struct ieee80211_hw *hw,
3869*4882a593Smuzhiyun struct ieee80211_vif *vif, int enable)
3870*4882a593Smuzhiyun {
3871*4882a593Smuzhiyun struct mwl8k_cmd_bss_start *cmd;
3872*4882a593Smuzhiyun struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3873*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
3874*4882a593Smuzhiyun int rc;
3875*4882a593Smuzhiyun
3876*4882a593Smuzhiyun if (enable && (priv->running_bsses & (1 << mwl8k_vif->macid)))
3877*4882a593Smuzhiyun return 0;
3878*4882a593Smuzhiyun
3879*4882a593Smuzhiyun if (!enable && !(priv->running_bsses & (1 << mwl8k_vif->macid)))
3880*4882a593Smuzhiyun return 0;
3881*4882a593Smuzhiyun
3882*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3883*4882a593Smuzhiyun if (cmd == NULL)
3884*4882a593Smuzhiyun return -ENOMEM;
3885*4882a593Smuzhiyun
3886*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_BSS_START);
3887*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
3888*4882a593Smuzhiyun cmd->enable = cpu_to_le32(enable);
3889*4882a593Smuzhiyun
3890*4882a593Smuzhiyun rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3891*4882a593Smuzhiyun kfree(cmd);
3892*4882a593Smuzhiyun
3893*4882a593Smuzhiyun if (!rc) {
3894*4882a593Smuzhiyun if (enable)
3895*4882a593Smuzhiyun priv->running_bsses |= (1 << mwl8k_vif->macid);
3896*4882a593Smuzhiyun else
3897*4882a593Smuzhiyun priv->running_bsses &= ~(1 << mwl8k_vif->macid);
3898*4882a593Smuzhiyun }
3899*4882a593Smuzhiyun return rc;
3900*4882a593Smuzhiyun }
3901*4882a593Smuzhiyun
mwl8k_enable_bsses(struct ieee80211_hw * hw,bool enable,u32 bitmap)3902*4882a593Smuzhiyun static void mwl8k_enable_bsses(struct ieee80211_hw *hw, bool enable, u32 bitmap)
3903*4882a593Smuzhiyun {
3904*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
3905*4882a593Smuzhiyun struct mwl8k_vif *mwl8k_vif, *tmp_vif;
3906*4882a593Smuzhiyun struct ieee80211_vif *vif;
3907*4882a593Smuzhiyun
3908*4882a593Smuzhiyun list_for_each_entry_safe(mwl8k_vif, tmp_vif, &priv->vif_list, list) {
3909*4882a593Smuzhiyun vif = mwl8k_vif->vif;
3910*4882a593Smuzhiyun
3911*4882a593Smuzhiyun if (!(bitmap & (1 << mwl8k_vif->macid)))
3912*4882a593Smuzhiyun continue;
3913*4882a593Smuzhiyun
3914*4882a593Smuzhiyun if (vif->type == NL80211_IFTYPE_AP)
3915*4882a593Smuzhiyun mwl8k_cmd_bss_start(hw, vif, enable);
3916*4882a593Smuzhiyun }
3917*4882a593Smuzhiyun }
3918*4882a593Smuzhiyun /*
3919*4882a593Smuzhiyun * CMD_BASTREAM.
3920*4882a593Smuzhiyun */
3921*4882a593Smuzhiyun
3922*4882a593Smuzhiyun /*
3923*4882a593Smuzhiyun * UPSTREAM is tx direction
3924*4882a593Smuzhiyun */
3925*4882a593Smuzhiyun #define BASTREAM_FLAG_DIRECTION_UPSTREAM 0x00
3926*4882a593Smuzhiyun #define BASTREAM_FLAG_IMMEDIATE_TYPE 0x01
3927*4882a593Smuzhiyun
3928*4882a593Smuzhiyun enum ba_stream_action_type {
3929*4882a593Smuzhiyun MWL8K_BA_CREATE,
3930*4882a593Smuzhiyun MWL8K_BA_UPDATE,
3931*4882a593Smuzhiyun MWL8K_BA_DESTROY,
3932*4882a593Smuzhiyun MWL8K_BA_FLUSH,
3933*4882a593Smuzhiyun MWL8K_BA_CHECK,
3934*4882a593Smuzhiyun };
3935*4882a593Smuzhiyun
3936*4882a593Smuzhiyun
3937*4882a593Smuzhiyun struct mwl8k_create_ba_stream {
3938*4882a593Smuzhiyun __le32 flags;
3939*4882a593Smuzhiyun __le32 idle_thrs;
3940*4882a593Smuzhiyun __le32 bar_thrs;
3941*4882a593Smuzhiyun __le32 window_size;
3942*4882a593Smuzhiyun u8 peer_mac_addr[6];
3943*4882a593Smuzhiyun u8 dialog_token;
3944*4882a593Smuzhiyun u8 tid;
3945*4882a593Smuzhiyun u8 queue_id;
3946*4882a593Smuzhiyun u8 param_info;
3947*4882a593Smuzhiyun __le32 ba_context;
3948*4882a593Smuzhiyun u8 reset_seq_no_flag;
3949*4882a593Smuzhiyun __le16 curr_seq_no;
3950*4882a593Smuzhiyun u8 sta_src_mac_addr[6];
3951*4882a593Smuzhiyun } __packed;
3952*4882a593Smuzhiyun
3953*4882a593Smuzhiyun struct mwl8k_destroy_ba_stream {
3954*4882a593Smuzhiyun __le32 flags;
3955*4882a593Smuzhiyun __le32 ba_context;
3956*4882a593Smuzhiyun } __packed;
3957*4882a593Smuzhiyun
3958*4882a593Smuzhiyun struct mwl8k_cmd_bastream {
3959*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
3960*4882a593Smuzhiyun __le32 action;
3961*4882a593Smuzhiyun union {
3962*4882a593Smuzhiyun struct mwl8k_create_ba_stream create_params;
3963*4882a593Smuzhiyun struct mwl8k_destroy_ba_stream destroy_params;
3964*4882a593Smuzhiyun };
3965*4882a593Smuzhiyun } __packed;
3966*4882a593Smuzhiyun
3967*4882a593Smuzhiyun static int
mwl8k_check_ba(struct ieee80211_hw * hw,struct mwl8k_ampdu_stream * stream,struct ieee80211_vif * vif)3968*4882a593Smuzhiyun mwl8k_check_ba(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream,
3969*4882a593Smuzhiyun struct ieee80211_vif *vif)
3970*4882a593Smuzhiyun {
3971*4882a593Smuzhiyun struct mwl8k_cmd_bastream *cmd;
3972*4882a593Smuzhiyun int rc;
3973*4882a593Smuzhiyun
3974*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3975*4882a593Smuzhiyun if (cmd == NULL)
3976*4882a593Smuzhiyun return -ENOMEM;
3977*4882a593Smuzhiyun
3978*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_BASTREAM);
3979*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
3980*4882a593Smuzhiyun
3981*4882a593Smuzhiyun cmd->action = cpu_to_le32(MWL8K_BA_CHECK);
3982*4882a593Smuzhiyun
3983*4882a593Smuzhiyun cmd->create_params.queue_id = stream->idx;
3984*4882a593Smuzhiyun memcpy(&cmd->create_params.peer_mac_addr[0], stream->sta->addr,
3985*4882a593Smuzhiyun ETH_ALEN);
3986*4882a593Smuzhiyun cmd->create_params.tid = stream->tid;
3987*4882a593Smuzhiyun
3988*4882a593Smuzhiyun cmd->create_params.flags =
3989*4882a593Smuzhiyun cpu_to_le32(BASTREAM_FLAG_IMMEDIATE_TYPE) |
3990*4882a593Smuzhiyun cpu_to_le32(BASTREAM_FLAG_DIRECTION_UPSTREAM);
3991*4882a593Smuzhiyun
3992*4882a593Smuzhiyun rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3993*4882a593Smuzhiyun
3994*4882a593Smuzhiyun kfree(cmd);
3995*4882a593Smuzhiyun
3996*4882a593Smuzhiyun return rc;
3997*4882a593Smuzhiyun }
3998*4882a593Smuzhiyun
3999*4882a593Smuzhiyun static int
mwl8k_create_ba(struct ieee80211_hw * hw,struct mwl8k_ampdu_stream * stream,u8 buf_size,struct ieee80211_vif * vif)4000*4882a593Smuzhiyun mwl8k_create_ba(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream,
4001*4882a593Smuzhiyun u8 buf_size, struct ieee80211_vif *vif)
4002*4882a593Smuzhiyun {
4003*4882a593Smuzhiyun struct mwl8k_cmd_bastream *cmd;
4004*4882a593Smuzhiyun int rc;
4005*4882a593Smuzhiyun
4006*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4007*4882a593Smuzhiyun if (cmd == NULL)
4008*4882a593Smuzhiyun return -ENOMEM;
4009*4882a593Smuzhiyun
4010*4882a593Smuzhiyun
4011*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_BASTREAM);
4012*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
4013*4882a593Smuzhiyun
4014*4882a593Smuzhiyun cmd->action = cpu_to_le32(MWL8K_BA_CREATE);
4015*4882a593Smuzhiyun
4016*4882a593Smuzhiyun cmd->create_params.bar_thrs = cpu_to_le32((u32)buf_size);
4017*4882a593Smuzhiyun cmd->create_params.window_size = cpu_to_le32((u32)buf_size);
4018*4882a593Smuzhiyun cmd->create_params.queue_id = stream->idx;
4019*4882a593Smuzhiyun
4020*4882a593Smuzhiyun memcpy(cmd->create_params.peer_mac_addr, stream->sta->addr, ETH_ALEN);
4021*4882a593Smuzhiyun cmd->create_params.tid = stream->tid;
4022*4882a593Smuzhiyun cmd->create_params.curr_seq_no = cpu_to_le16(0);
4023*4882a593Smuzhiyun cmd->create_params.reset_seq_no_flag = 1;
4024*4882a593Smuzhiyun
4025*4882a593Smuzhiyun cmd->create_params.param_info =
4026*4882a593Smuzhiyun (stream->sta->ht_cap.ampdu_factor &
4027*4882a593Smuzhiyun IEEE80211_HT_AMPDU_PARM_FACTOR) |
4028*4882a593Smuzhiyun ((stream->sta->ht_cap.ampdu_density << 2) &
4029*4882a593Smuzhiyun IEEE80211_HT_AMPDU_PARM_DENSITY);
4030*4882a593Smuzhiyun
4031*4882a593Smuzhiyun cmd->create_params.flags =
4032*4882a593Smuzhiyun cpu_to_le32(BASTREAM_FLAG_IMMEDIATE_TYPE |
4033*4882a593Smuzhiyun BASTREAM_FLAG_DIRECTION_UPSTREAM);
4034*4882a593Smuzhiyun
4035*4882a593Smuzhiyun rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
4036*4882a593Smuzhiyun
4037*4882a593Smuzhiyun wiphy_debug(hw->wiphy, "Created a BA stream for %pM : tid %d\n",
4038*4882a593Smuzhiyun stream->sta->addr, stream->tid);
4039*4882a593Smuzhiyun kfree(cmd);
4040*4882a593Smuzhiyun
4041*4882a593Smuzhiyun return rc;
4042*4882a593Smuzhiyun }
4043*4882a593Smuzhiyun
mwl8k_destroy_ba(struct ieee80211_hw * hw,u8 idx)4044*4882a593Smuzhiyun static void mwl8k_destroy_ba(struct ieee80211_hw *hw,
4045*4882a593Smuzhiyun u8 idx)
4046*4882a593Smuzhiyun {
4047*4882a593Smuzhiyun struct mwl8k_cmd_bastream *cmd;
4048*4882a593Smuzhiyun
4049*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4050*4882a593Smuzhiyun if (cmd == NULL)
4051*4882a593Smuzhiyun return;
4052*4882a593Smuzhiyun
4053*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_BASTREAM);
4054*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
4055*4882a593Smuzhiyun cmd->action = cpu_to_le32(MWL8K_BA_DESTROY);
4056*4882a593Smuzhiyun
4057*4882a593Smuzhiyun cmd->destroy_params.ba_context = cpu_to_le32(idx);
4058*4882a593Smuzhiyun mwl8k_post_cmd(hw, &cmd->header);
4059*4882a593Smuzhiyun
4060*4882a593Smuzhiyun wiphy_debug(hw->wiphy, "Deleted BA stream index %d\n", idx);
4061*4882a593Smuzhiyun
4062*4882a593Smuzhiyun kfree(cmd);
4063*4882a593Smuzhiyun }
4064*4882a593Smuzhiyun
4065*4882a593Smuzhiyun /*
4066*4882a593Smuzhiyun * CMD_SET_NEW_STN.
4067*4882a593Smuzhiyun */
4068*4882a593Smuzhiyun struct mwl8k_cmd_set_new_stn {
4069*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
4070*4882a593Smuzhiyun __le16 aid;
4071*4882a593Smuzhiyun __u8 mac_addr[6];
4072*4882a593Smuzhiyun __le16 stn_id;
4073*4882a593Smuzhiyun __le16 action;
4074*4882a593Smuzhiyun __le16 rsvd;
4075*4882a593Smuzhiyun __le32 legacy_rates;
4076*4882a593Smuzhiyun __u8 ht_rates[4];
4077*4882a593Smuzhiyun __le16 cap_info;
4078*4882a593Smuzhiyun __le16 ht_capabilities_info;
4079*4882a593Smuzhiyun __u8 mac_ht_param_info;
4080*4882a593Smuzhiyun __u8 rev;
4081*4882a593Smuzhiyun __u8 control_channel;
4082*4882a593Smuzhiyun __u8 add_channel;
4083*4882a593Smuzhiyun __le16 op_mode;
4084*4882a593Smuzhiyun __le16 stbc;
4085*4882a593Smuzhiyun __u8 add_qos_info;
4086*4882a593Smuzhiyun __u8 is_qos_sta;
4087*4882a593Smuzhiyun __le32 fw_sta_ptr;
4088*4882a593Smuzhiyun } __packed;
4089*4882a593Smuzhiyun
4090*4882a593Smuzhiyun #define MWL8K_STA_ACTION_ADD 0
4091*4882a593Smuzhiyun #define MWL8K_STA_ACTION_REMOVE 2
4092*4882a593Smuzhiyun
mwl8k_cmd_set_new_stn_add(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta)4093*4882a593Smuzhiyun static int mwl8k_cmd_set_new_stn_add(struct ieee80211_hw *hw,
4094*4882a593Smuzhiyun struct ieee80211_vif *vif,
4095*4882a593Smuzhiyun struct ieee80211_sta *sta)
4096*4882a593Smuzhiyun {
4097*4882a593Smuzhiyun struct mwl8k_cmd_set_new_stn *cmd;
4098*4882a593Smuzhiyun u32 rates;
4099*4882a593Smuzhiyun int rc;
4100*4882a593Smuzhiyun
4101*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4102*4882a593Smuzhiyun if (cmd == NULL)
4103*4882a593Smuzhiyun return -ENOMEM;
4104*4882a593Smuzhiyun
4105*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
4106*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
4107*4882a593Smuzhiyun cmd->aid = cpu_to_le16(sta->aid);
4108*4882a593Smuzhiyun memcpy(cmd->mac_addr, sta->addr, ETH_ALEN);
4109*4882a593Smuzhiyun cmd->stn_id = cpu_to_le16(sta->aid);
4110*4882a593Smuzhiyun cmd->action = cpu_to_le16(MWL8K_STA_ACTION_ADD);
4111*4882a593Smuzhiyun if (hw->conf.chandef.chan->band == NL80211_BAND_2GHZ)
4112*4882a593Smuzhiyun rates = sta->supp_rates[NL80211_BAND_2GHZ];
4113*4882a593Smuzhiyun else
4114*4882a593Smuzhiyun rates = sta->supp_rates[NL80211_BAND_5GHZ] << 5;
4115*4882a593Smuzhiyun cmd->legacy_rates = cpu_to_le32(rates);
4116*4882a593Smuzhiyun if (sta->ht_cap.ht_supported) {
4117*4882a593Smuzhiyun cmd->ht_rates[0] = sta->ht_cap.mcs.rx_mask[0];
4118*4882a593Smuzhiyun cmd->ht_rates[1] = sta->ht_cap.mcs.rx_mask[1];
4119*4882a593Smuzhiyun cmd->ht_rates[2] = sta->ht_cap.mcs.rx_mask[2];
4120*4882a593Smuzhiyun cmd->ht_rates[3] = sta->ht_cap.mcs.rx_mask[3];
4121*4882a593Smuzhiyun cmd->ht_capabilities_info = cpu_to_le16(sta->ht_cap.cap);
4122*4882a593Smuzhiyun cmd->mac_ht_param_info = (sta->ht_cap.ampdu_factor & 3) |
4123*4882a593Smuzhiyun ((sta->ht_cap.ampdu_density & 7) << 2);
4124*4882a593Smuzhiyun cmd->is_qos_sta = 1;
4125*4882a593Smuzhiyun }
4126*4882a593Smuzhiyun
4127*4882a593Smuzhiyun rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
4128*4882a593Smuzhiyun kfree(cmd);
4129*4882a593Smuzhiyun
4130*4882a593Smuzhiyun return rc;
4131*4882a593Smuzhiyun }
4132*4882a593Smuzhiyun
mwl8k_cmd_set_new_stn_add_self(struct ieee80211_hw * hw,struct ieee80211_vif * vif)4133*4882a593Smuzhiyun static int mwl8k_cmd_set_new_stn_add_self(struct ieee80211_hw *hw,
4134*4882a593Smuzhiyun struct ieee80211_vif *vif)
4135*4882a593Smuzhiyun {
4136*4882a593Smuzhiyun struct mwl8k_cmd_set_new_stn *cmd;
4137*4882a593Smuzhiyun int rc;
4138*4882a593Smuzhiyun
4139*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4140*4882a593Smuzhiyun if (cmd == NULL)
4141*4882a593Smuzhiyun return -ENOMEM;
4142*4882a593Smuzhiyun
4143*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
4144*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
4145*4882a593Smuzhiyun memcpy(cmd->mac_addr, vif->addr, ETH_ALEN);
4146*4882a593Smuzhiyun
4147*4882a593Smuzhiyun rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
4148*4882a593Smuzhiyun kfree(cmd);
4149*4882a593Smuzhiyun
4150*4882a593Smuzhiyun return rc;
4151*4882a593Smuzhiyun }
4152*4882a593Smuzhiyun
mwl8k_cmd_set_new_stn_del(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u8 * addr)4153*4882a593Smuzhiyun static int mwl8k_cmd_set_new_stn_del(struct ieee80211_hw *hw,
4154*4882a593Smuzhiyun struct ieee80211_vif *vif, u8 *addr)
4155*4882a593Smuzhiyun {
4156*4882a593Smuzhiyun struct mwl8k_cmd_set_new_stn *cmd;
4157*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
4158*4882a593Smuzhiyun int rc, i;
4159*4882a593Smuzhiyun u8 idx;
4160*4882a593Smuzhiyun
4161*4882a593Smuzhiyun spin_lock(&priv->stream_lock);
4162*4882a593Smuzhiyun /* Destroy any active ampdu streams for this sta */
4163*4882a593Smuzhiyun for (i = 0; i < MWL8K_NUM_AMPDU_STREAMS; i++) {
4164*4882a593Smuzhiyun struct mwl8k_ampdu_stream *s;
4165*4882a593Smuzhiyun s = &priv->ampdu[i];
4166*4882a593Smuzhiyun if (s->state != AMPDU_NO_STREAM) {
4167*4882a593Smuzhiyun if (memcmp(s->sta->addr, addr, ETH_ALEN) == 0) {
4168*4882a593Smuzhiyun if (s->state == AMPDU_STREAM_ACTIVE) {
4169*4882a593Smuzhiyun idx = s->idx;
4170*4882a593Smuzhiyun spin_unlock(&priv->stream_lock);
4171*4882a593Smuzhiyun mwl8k_destroy_ba(hw, idx);
4172*4882a593Smuzhiyun spin_lock(&priv->stream_lock);
4173*4882a593Smuzhiyun } else if (s->state == AMPDU_STREAM_NEW) {
4174*4882a593Smuzhiyun mwl8k_remove_stream(hw, s);
4175*4882a593Smuzhiyun }
4176*4882a593Smuzhiyun }
4177*4882a593Smuzhiyun }
4178*4882a593Smuzhiyun }
4179*4882a593Smuzhiyun
4180*4882a593Smuzhiyun spin_unlock(&priv->stream_lock);
4181*4882a593Smuzhiyun
4182*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4183*4882a593Smuzhiyun if (cmd == NULL)
4184*4882a593Smuzhiyun return -ENOMEM;
4185*4882a593Smuzhiyun
4186*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
4187*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
4188*4882a593Smuzhiyun memcpy(cmd->mac_addr, addr, ETH_ALEN);
4189*4882a593Smuzhiyun cmd->action = cpu_to_le16(MWL8K_STA_ACTION_REMOVE);
4190*4882a593Smuzhiyun
4191*4882a593Smuzhiyun rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
4192*4882a593Smuzhiyun kfree(cmd);
4193*4882a593Smuzhiyun
4194*4882a593Smuzhiyun return rc;
4195*4882a593Smuzhiyun }
4196*4882a593Smuzhiyun
4197*4882a593Smuzhiyun /*
4198*4882a593Smuzhiyun * CMD_UPDATE_ENCRYPTION.
4199*4882a593Smuzhiyun */
4200*4882a593Smuzhiyun
4201*4882a593Smuzhiyun #define MAX_ENCR_KEY_LENGTH 16
4202*4882a593Smuzhiyun #define MIC_KEY_LENGTH 8
4203*4882a593Smuzhiyun
4204*4882a593Smuzhiyun struct mwl8k_cmd_update_encryption {
4205*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
4206*4882a593Smuzhiyun
4207*4882a593Smuzhiyun __le32 action;
4208*4882a593Smuzhiyun __le32 reserved;
4209*4882a593Smuzhiyun __u8 mac_addr[6];
4210*4882a593Smuzhiyun __u8 encr_type;
4211*4882a593Smuzhiyun
4212*4882a593Smuzhiyun } __packed;
4213*4882a593Smuzhiyun
4214*4882a593Smuzhiyun struct mwl8k_cmd_set_key {
4215*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
4216*4882a593Smuzhiyun
4217*4882a593Smuzhiyun __le32 action;
4218*4882a593Smuzhiyun __le32 reserved;
4219*4882a593Smuzhiyun __le16 length;
4220*4882a593Smuzhiyun __le16 key_type_id;
4221*4882a593Smuzhiyun __le32 key_info;
4222*4882a593Smuzhiyun __le32 key_id;
4223*4882a593Smuzhiyun __le16 key_len;
4224*4882a593Smuzhiyun __u8 key_material[MAX_ENCR_KEY_LENGTH];
4225*4882a593Smuzhiyun __u8 tkip_tx_mic_key[MIC_KEY_LENGTH];
4226*4882a593Smuzhiyun __u8 tkip_rx_mic_key[MIC_KEY_LENGTH];
4227*4882a593Smuzhiyun __le16 tkip_rsc_low;
4228*4882a593Smuzhiyun __le32 tkip_rsc_high;
4229*4882a593Smuzhiyun __le16 tkip_tsc_low;
4230*4882a593Smuzhiyun __le32 tkip_tsc_high;
4231*4882a593Smuzhiyun __u8 mac_addr[6];
4232*4882a593Smuzhiyun } __packed;
4233*4882a593Smuzhiyun
4234*4882a593Smuzhiyun enum {
4235*4882a593Smuzhiyun MWL8K_ENCR_ENABLE,
4236*4882a593Smuzhiyun MWL8K_ENCR_SET_KEY,
4237*4882a593Smuzhiyun MWL8K_ENCR_REMOVE_KEY,
4238*4882a593Smuzhiyun MWL8K_ENCR_SET_GROUP_KEY,
4239*4882a593Smuzhiyun };
4240*4882a593Smuzhiyun
4241*4882a593Smuzhiyun #define MWL8K_UPDATE_ENCRYPTION_TYPE_WEP 0
4242*4882a593Smuzhiyun #define MWL8K_UPDATE_ENCRYPTION_TYPE_DISABLE 1
4243*4882a593Smuzhiyun #define MWL8K_UPDATE_ENCRYPTION_TYPE_TKIP 4
4244*4882a593Smuzhiyun #define MWL8K_UPDATE_ENCRYPTION_TYPE_MIXED 7
4245*4882a593Smuzhiyun #define MWL8K_UPDATE_ENCRYPTION_TYPE_AES 8
4246*4882a593Smuzhiyun
4247*4882a593Smuzhiyun enum {
4248*4882a593Smuzhiyun MWL8K_ALG_WEP,
4249*4882a593Smuzhiyun MWL8K_ALG_TKIP,
4250*4882a593Smuzhiyun MWL8K_ALG_CCMP,
4251*4882a593Smuzhiyun };
4252*4882a593Smuzhiyun
4253*4882a593Smuzhiyun #define MWL8K_KEY_FLAG_TXGROUPKEY 0x00000004
4254*4882a593Smuzhiyun #define MWL8K_KEY_FLAG_PAIRWISE 0x00000008
4255*4882a593Smuzhiyun #define MWL8K_KEY_FLAG_TSC_VALID 0x00000040
4256*4882a593Smuzhiyun #define MWL8K_KEY_FLAG_WEP_TXKEY 0x01000000
4257*4882a593Smuzhiyun #define MWL8K_KEY_FLAG_MICKEY_VALID 0x02000000
4258*4882a593Smuzhiyun
mwl8k_cmd_update_encryption_enable(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u8 * addr,u8 encr_type)4259*4882a593Smuzhiyun static int mwl8k_cmd_update_encryption_enable(struct ieee80211_hw *hw,
4260*4882a593Smuzhiyun struct ieee80211_vif *vif,
4261*4882a593Smuzhiyun u8 *addr,
4262*4882a593Smuzhiyun u8 encr_type)
4263*4882a593Smuzhiyun {
4264*4882a593Smuzhiyun struct mwl8k_cmd_update_encryption *cmd;
4265*4882a593Smuzhiyun int rc;
4266*4882a593Smuzhiyun
4267*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4268*4882a593Smuzhiyun if (cmd == NULL)
4269*4882a593Smuzhiyun return -ENOMEM;
4270*4882a593Smuzhiyun
4271*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_ENCRYPTION);
4272*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
4273*4882a593Smuzhiyun cmd->action = cpu_to_le32(MWL8K_ENCR_ENABLE);
4274*4882a593Smuzhiyun memcpy(cmd->mac_addr, addr, ETH_ALEN);
4275*4882a593Smuzhiyun cmd->encr_type = encr_type;
4276*4882a593Smuzhiyun
4277*4882a593Smuzhiyun rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
4278*4882a593Smuzhiyun kfree(cmd);
4279*4882a593Smuzhiyun
4280*4882a593Smuzhiyun return rc;
4281*4882a593Smuzhiyun }
4282*4882a593Smuzhiyun
mwl8k_encryption_set_cmd_info(struct mwl8k_cmd_set_key * cmd,u8 * addr,struct ieee80211_key_conf * key)4283*4882a593Smuzhiyun static int mwl8k_encryption_set_cmd_info(struct mwl8k_cmd_set_key *cmd,
4284*4882a593Smuzhiyun u8 *addr,
4285*4882a593Smuzhiyun struct ieee80211_key_conf *key)
4286*4882a593Smuzhiyun {
4287*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_ENCRYPTION);
4288*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
4289*4882a593Smuzhiyun cmd->length = cpu_to_le16(sizeof(*cmd) -
4290*4882a593Smuzhiyun offsetof(struct mwl8k_cmd_set_key, length));
4291*4882a593Smuzhiyun cmd->key_id = cpu_to_le32(key->keyidx);
4292*4882a593Smuzhiyun cmd->key_len = cpu_to_le16(key->keylen);
4293*4882a593Smuzhiyun memcpy(cmd->mac_addr, addr, ETH_ALEN);
4294*4882a593Smuzhiyun
4295*4882a593Smuzhiyun switch (key->cipher) {
4296*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_WEP40:
4297*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_WEP104:
4298*4882a593Smuzhiyun cmd->key_type_id = cpu_to_le16(MWL8K_ALG_WEP);
4299*4882a593Smuzhiyun if (key->keyidx == 0)
4300*4882a593Smuzhiyun cmd->key_info = cpu_to_le32(MWL8K_KEY_FLAG_WEP_TXKEY);
4301*4882a593Smuzhiyun
4302*4882a593Smuzhiyun break;
4303*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_TKIP:
4304*4882a593Smuzhiyun cmd->key_type_id = cpu_to_le16(MWL8K_ALG_TKIP);
4305*4882a593Smuzhiyun cmd->key_info = (key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
4306*4882a593Smuzhiyun ? cpu_to_le32(MWL8K_KEY_FLAG_PAIRWISE)
4307*4882a593Smuzhiyun : cpu_to_le32(MWL8K_KEY_FLAG_TXGROUPKEY);
4308*4882a593Smuzhiyun cmd->key_info |= cpu_to_le32(MWL8K_KEY_FLAG_MICKEY_VALID
4309*4882a593Smuzhiyun | MWL8K_KEY_FLAG_TSC_VALID);
4310*4882a593Smuzhiyun break;
4311*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_CCMP:
4312*4882a593Smuzhiyun cmd->key_type_id = cpu_to_le16(MWL8K_ALG_CCMP);
4313*4882a593Smuzhiyun cmd->key_info = (key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
4314*4882a593Smuzhiyun ? cpu_to_le32(MWL8K_KEY_FLAG_PAIRWISE)
4315*4882a593Smuzhiyun : cpu_to_le32(MWL8K_KEY_FLAG_TXGROUPKEY);
4316*4882a593Smuzhiyun break;
4317*4882a593Smuzhiyun default:
4318*4882a593Smuzhiyun return -ENOTSUPP;
4319*4882a593Smuzhiyun }
4320*4882a593Smuzhiyun
4321*4882a593Smuzhiyun return 0;
4322*4882a593Smuzhiyun }
4323*4882a593Smuzhiyun
mwl8k_cmd_encryption_set_key(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u8 * addr,struct ieee80211_key_conf * key)4324*4882a593Smuzhiyun static int mwl8k_cmd_encryption_set_key(struct ieee80211_hw *hw,
4325*4882a593Smuzhiyun struct ieee80211_vif *vif,
4326*4882a593Smuzhiyun u8 *addr,
4327*4882a593Smuzhiyun struct ieee80211_key_conf *key)
4328*4882a593Smuzhiyun {
4329*4882a593Smuzhiyun struct mwl8k_cmd_set_key *cmd;
4330*4882a593Smuzhiyun int rc;
4331*4882a593Smuzhiyun int keymlen;
4332*4882a593Smuzhiyun u32 action;
4333*4882a593Smuzhiyun u8 idx;
4334*4882a593Smuzhiyun struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
4335*4882a593Smuzhiyun
4336*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4337*4882a593Smuzhiyun if (cmd == NULL)
4338*4882a593Smuzhiyun return -ENOMEM;
4339*4882a593Smuzhiyun
4340*4882a593Smuzhiyun rc = mwl8k_encryption_set_cmd_info(cmd, addr, key);
4341*4882a593Smuzhiyun if (rc < 0)
4342*4882a593Smuzhiyun goto done;
4343*4882a593Smuzhiyun
4344*4882a593Smuzhiyun idx = key->keyidx;
4345*4882a593Smuzhiyun
4346*4882a593Smuzhiyun if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
4347*4882a593Smuzhiyun action = MWL8K_ENCR_SET_KEY;
4348*4882a593Smuzhiyun else
4349*4882a593Smuzhiyun action = MWL8K_ENCR_SET_GROUP_KEY;
4350*4882a593Smuzhiyun
4351*4882a593Smuzhiyun switch (key->cipher) {
4352*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_WEP40:
4353*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_WEP104:
4354*4882a593Smuzhiyun if (!mwl8k_vif->wep_key_conf[idx].enabled) {
4355*4882a593Smuzhiyun memcpy(mwl8k_vif->wep_key_conf[idx].key, key,
4356*4882a593Smuzhiyun sizeof(*key) + key->keylen);
4357*4882a593Smuzhiyun mwl8k_vif->wep_key_conf[idx].enabled = 1;
4358*4882a593Smuzhiyun }
4359*4882a593Smuzhiyun
4360*4882a593Smuzhiyun keymlen = key->keylen;
4361*4882a593Smuzhiyun action = MWL8K_ENCR_SET_KEY;
4362*4882a593Smuzhiyun break;
4363*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_TKIP:
4364*4882a593Smuzhiyun keymlen = MAX_ENCR_KEY_LENGTH + 2 * MIC_KEY_LENGTH;
4365*4882a593Smuzhiyun break;
4366*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_CCMP:
4367*4882a593Smuzhiyun keymlen = key->keylen;
4368*4882a593Smuzhiyun break;
4369*4882a593Smuzhiyun default:
4370*4882a593Smuzhiyun rc = -ENOTSUPP;
4371*4882a593Smuzhiyun goto done;
4372*4882a593Smuzhiyun }
4373*4882a593Smuzhiyun
4374*4882a593Smuzhiyun memcpy(cmd->key_material, key->key, keymlen);
4375*4882a593Smuzhiyun cmd->action = cpu_to_le32(action);
4376*4882a593Smuzhiyun
4377*4882a593Smuzhiyun rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
4378*4882a593Smuzhiyun done:
4379*4882a593Smuzhiyun kfree(cmd);
4380*4882a593Smuzhiyun
4381*4882a593Smuzhiyun return rc;
4382*4882a593Smuzhiyun }
4383*4882a593Smuzhiyun
mwl8k_cmd_encryption_remove_key(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u8 * addr,struct ieee80211_key_conf * key)4384*4882a593Smuzhiyun static int mwl8k_cmd_encryption_remove_key(struct ieee80211_hw *hw,
4385*4882a593Smuzhiyun struct ieee80211_vif *vif,
4386*4882a593Smuzhiyun u8 *addr,
4387*4882a593Smuzhiyun struct ieee80211_key_conf *key)
4388*4882a593Smuzhiyun {
4389*4882a593Smuzhiyun struct mwl8k_cmd_set_key *cmd;
4390*4882a593Smuzhiyun int rc;
4391*4882a593Smuzhiyun struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
4392*4882a593Smuzhiyun
4393*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4394*4882a593Smuzhiyun if (cmd == NULL)
4395*4882a593Smuzhiyun return -ENOMEM;
4396*4882a593Smuzhiyun
4397*4882a593Smuzhiyun rc = mwl8k_encryption_set_cmd_info(cmd, addr, key);
4398*4882a593Smuzhiyun if (rc < 0)
4399*4882a593Smuzhiyun goto done;
4400*4882a593Smuzhiyun
4401*4882a593Smuzhiyun if (key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
4402*4882a593Smuzhiyun key->cipher == WLAN_CIPHER_SUITE_WEP104)
4403*4882a593Smuzhiyun mwl8k_vif->wep_key_conf[key->keyidx].enabled = 0;
4404*4882a593Smuzhiyun
4405*4882a593Smuzhiyun cmd->action = cpu_to_le32(MWL8K_ENCR_REMOVE_KEY);
4406*4882a593Smuzhiyun
4407*4882a593Smuzhiyun rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
4408*4882a593Smuzhiyun done:
4409*4882a593Smuzhiyun kfree(cmd);
4410*4882a593Smuzhiyun
4411*4882a593Smuzhiyun return rc;
4412*4882a593Smuzhiyun }
4413*4882a593Smuzhiyun
mwl8k_set_key(struct ieee80211_hw * hw,enum set_key_cmd cmd_param,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct ieee80211_key_conf * key)4414*4882a593Smuzhiyun static int mwl8k_set_key(struct ieee80211_hw *hw,
4415*4882a593Smuzhiyun enum set_key_cmd cmd_param,
4416*4882a593Smuzhiyun struct ieee80211_vif *vif,
4417*4882a593Smuzhiyun struct ieee80211_sta *sta,
4418*4882a593Smuzhiyun struct ieee80211_key_conf *key)
4419*4882a593Smuzhiyun {
4420*4882a593Smuzhiyun int rc = 0;
4421*4882a593Smuzhiyun u8 encr_type;
4422*4882a593Smuzhiyun u8 *addr;
4423*4882a593Smuzhiyun struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
4424*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
4425*4882a593Smuzhiyun
4426*4882a593Smuzhiyun if (vif->type == NL80211_IFTYPE_STATION && !priv->ap_fw)
4427*4882a593Smuzhiyun return -EOPNOTSUPP;
4428*4882a593Smuzhiyun
4429*4882a593Smuzhiyun if (sta == NULL)
4430*4882a593Smuzhiyun addr = vif->addr;
4431*4882a593Smuzhiyun else
4432*4882a593Smuzhiyun addr = sta->addr;
4433*4882a593Smuzhiyun
4434*4882a593Smuzhiyun if (cmd_param == SET_KEY) {
4435*4882a593Smuzhiyun rc = mwl8k_cmd_encryption_set_key(hw, vif, addr, key);
4436*4882a593Smuzhiyun if (rc)
4437*4882a593Smuzhiyun goto out;
4438*4882a593Smuzhiyun
4439*4882a593Smuzhiyun if ((key->cipher == WLAN_CIPHER_SUITE_WEP40)
4440*4882a593Smuzhiyun || (key->cipher == WLAN_CIPHER_SUITE_WEP104))
4441*4882a593Smuzhiyun encr_type = MWL8K_UPDATE_ENCRYPTION_TYPE_WEP;
4442*4882a593Smuzhiyun else
4443*4882a593Smuzhiyun encr_type = MWL8K_UPDATE_ENCRYPTION_TYPE_MIXED;
4444*4882a593Smuzhiyun
4445*4882a593Smuzhiyun rc = mwl8k_cmd_update_encryption_enable(hw, vif, addr,
4446*4882a593Smuzhiyun encr_type);
4447*4882a593Smuzhiyun if (rc)
4448*4882a593Smuzhiyun goto out;
4449*4882a593Smuzhiyun
4450*4882a593Smuzhiyun mwl8k_vif->is_hw_crypto_enabled = true;
4451*4882a593Smuzhiyun
4452*4882a593Smuzhiyun } else {
4453*4882a593Smuzhiyun rc = mwl8k_cmd_encryption_remove_key(hw, vif, addr, key);
4454*4882a593Smuzhiyun
4455*4882a593Smuzhiyun if (rc)
4456*4882a593Smuzhiyun goto out;
4457*4882a593Smuzhiyun }
4458*4882a593Smuzhiyun out:
4459*4882a593Smuzhiyun return rc;
4460*4882a593Smuzhiyun }
4461*4882a593Smuzhiyun
4462*4882a593Smuzhiyun /*
4463*4882a593Smuzhiyun * CMD_UPDATE_STADB.
4464*4882a593Smuzhiyun */
4465*4882a593Smuzhiyun struct ewc_ht_info {
4466*4882a593Smuzhiyun __le16 control1;
4467*4882a593Smuzhiyun __le16 control2;
4468*4882a593Smuzhiyun __le16 control3;
4469*4882a593Smuzhiyun } __packed;
4470*4882a593Smuzhiyun
4471*4882a593Smuzhiyun struct peer_capability_info {
4472*4882a593Smuzhiyun /* Peer type - AP vs. STA. */
4473*4882a593Smuzhiyun __u8 peer_type;
4474*4882a593Smuzhiyun
4475*4882a593Smuzhiyun /* Basic 802.11 capabilities from assoc resp. */
4476*4882a593Smuzhiyun __le16 basic_caps;
4477*4882a593Smuzhiyun
4478*4882a593Smuzhiyun /* Set if peer supports 802.11n high throughput (HT). */
4479*4882a593Smuzhiyun __u8 ht_support;
4480*4882a593Smuzhiyun
4481*4882a593Smuzhiyun /* Valid if HT is supported. */
4482*4882a593Smuzhiyun __le16 ht_caps;
4483*4882a593Smuzhiyun __u8 extended_ht_caps;
4484*4882a593Smuzhiyun struct ewc_ht_info ewc_info;
4485*4882a593Smuzhiyun
4486*4882a593Smuzhiyun /* Legacy rate table. Intersection of our rates and peer rates. */
4487*4882a593Smuzhiyun __u8 legacy_rates[12];
4488*4882a593Smuzhiyun
4489*4882a593Smuzhiyun /* HT rate table. Intersection of our rates and peer rates. */
4490*4882a593Smuzhiyun __u8 ht_rates[16];
4491*4882a593Smuzhiyun __u8 pad[16];
4492*4882a593Smuzhiyun
4493*4882a593Smuzhiyun /* If set, interoperability mode, no proprietary extensions. */
4494*4882a593Smuzhiyun __u8 interop;
4495*4882a593Smuzhiyun __u8 pad2;
4496*4882a593Smuzhiyun __u8 station_id;
4497*4882a593Smuzhiyun __le16 amsdu_enabled;
4498*4882a593Smuzhiyun } __packed;
4499*4882a593Smuzhiyun
4500*4882a593Smuzhiyun struct mwl8k_cmd_update_stadb {
4501*4882a593Smuzhiyun struct mwl8k_cmd_pkt header;
4502*4882a593Smuzhiyun
4503*4882a593Smuzhiyun /* See STADB_ACTION_TYPE */
4504*4882a593Smuzhiyun __le32 action;
4505*4882a593Smuzhiyun
4506*4882a593Smuzhiyun /* Peer MAC address */
4507*4882a593Smuzhiyun __u8 peer_addr[ETH_ALEN];
4508*4882a593Smuzhiyun
4509*4882a593Smuzhiyun __le32 reserved;
4510*4882a593Smuzhiyun
4511*4882a593Smuzhiyun /* Peer info - valid during add/update. */
4512*4882a593Smuzhiyun struct peer_capability_info peer_info;
4513*4882a593Smuzhiyun } __packed;
4514*4882a593Smuzhiyun
4515*4882a593Smuzhiyun #define MWL8K_STA_DB_MODIFY_ENTRY 1
4516*4882a593Smuzhiyun #define MWL8K_STA_DB_DEL_ENTRY 2
4517*4882a593Smuzhiyun
4518*4882a593Smuzhiyun /* Peer Entry flags - used to define the type of the peer node */
4519*4882a593Smuzhiyun #define MWL8K_PEER_TYPE_ACCESSPOINT 2
4520*4882a593Smuzhiyun
mwl8k_cmd_update_stadb_add(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta)4521*4882a593Smuzhiyun static int mwl8k_cmd_update_stadb_add(struct ieee80211_hw *hw,
4522*4882a593Smuzhiyun struct ieee80211_vif *vif,
4523*4882a593Smuzhiyun struct ieee80211_sta *sta)
4524*4882a593Smuzhiyun {
4525*4882a593Smuzhiyun struct mwl8k_cmd_update_stadb *cmd;
4526*4882a593Smuzhiyun struct peer_capability_info *p;
4527*4882a593Smuzhiyun u32 rates;
4528*4882a593Smuzhiyun int rc;
4529*4882a593Smuzhiyun
4530*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4531*4882a593Smuzhiyun if (cmd == NULL)
4532*4882a593Smuzhiyun return -ENOMEM;
4533*4882a593Smuzhiyun
4534*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
4535*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
4536*4882a593Smuzhiyun cmd->action = cpu_to_le32(MWL8K_STA_DB_MODIFY_ENTRY);
4537*4882a593Smuzhiyun memcpy(cmd->peer_addr, sta->addr, ETH_ALEN);
4538*4882a593Smuzhiyun
4539*4882a593Smuzhiyun p = &cmd->peer_info;
4540*4882a593Smuzhiyun p->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
4541*4882a593Smuzhiyun p->basic_caps = cpu_to_le16(vif->bss_conf.assoc_capability);
4542*4882a593Smuzhiyun p->ht_support = sta->ht_cap.ht_supported;
4543*4882a593Smuzhiyun p->ht_caps = cpu_to_le16(sta->ht_cap.cap);
4544*4882a593Smuzhiyun p->extended_ht_caps = (sta->ht_cap.ampdu_factor & 3) |
4545*4882a593Smuzhiyun ((sta->ht_cap.ampdu_density & 7) << 2);
4546*4882a593Smuzhiyun if (hw->conf.chandef.chan->band == NL80211_BAND_2GHZ)
4547*4882a593Smuzhiyun rates = sta->supp_rates[NL80211_BAND_2GHZ];
4548*4882a593Smuzhiyun else
4549*4882a593Smuzhiyun rates = sta->supp_rates[NL80211_BAND_5GHZ] << 5;
4550*4882a593Smuzhiyun legacy_rate_mask_to_array(p->legacy_rates, rates);
4551*4882a593Smuzhiyun memcpy(p->ht_rates, sta->ht_cap.mcs.rx_mask, 16);
4552*4882a593Smuzhiyun p->interop = 1;
4553*4882a593Smuzhiyun p->amsdu_enabled = 0;
4554*4882a593Smuzhiyun
4555*4882a593Smuzhiyun rc = mwl8k_post_cmd(hw, &cmd->header);
4556*4882a593Smuzhiyun if (!rc)
4557*4882a593Smuzhiyun rc = p->station_id;
4558*4882a593Smuzhiyun kfree(cmd);
4559*4882a593Smuzhiyun
4560*4882a593Smuzhiyun return rc;
4561*4882a593Smuzhiyun }
4562*4882a593Smuzhiyun
mwl8k_cmd_update_stadb_del(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u8 * addr)4563*4882a593Smuzhiyun static int mwl8k_cmd_update_stadb_del(struct ieee80211_hw *hw,
4564*4882a593Smuzhiyun struct ieee80211_vif *vif, u8 *addr)
4565*4882a593Smuzhiyun {
4566*4882a593Smuzhiyun struct mwl8k_cmd_update_stadb *cmd;
4567*4882a593Smuzhiyun int rc;
4568*4882a593Smuzhiyun
4569*4882a593Smuzhiyun cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4570*4882a593Smuzhiyun if (cmd == NULL)
4571*4882a593Smuzhiyun return -ENOMEM;
4572*4882a593Smuzhiyun
4573*4882a593Smuzhiyun cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
4574*4882a593Smuzhiyun cmd->header.length = cpu_to_le16(sizeof(*cmd));
4575*4882a593Smuzhiyun cmd->action = cpu_to_le32(MWL8K_STA_DB_DEL_ENTRY);
4576*4882a593Smuzhiyun memcpy(cmd->peer_addr, addr, ETH_ALEN);
4577*4882a593Smuzhiyun
4578*4882a593Smuzhiyun rc = mwl8k_post_cmd(hw, &cmd->header);
4579*4882a593Smuzhiyun kfree(cmd);
4580*4882a593Smuzhiyun
4581*4882a593Smuzhiyun return rc;
4582*4882a593Smuzhiyun }
4583*4882a593Smuzhiyun
4584*4882a593Smuzhiyun
4585*4882a593Smuzhiyun /*
4586*4882a593Smuzhiyun * Interrupt handling.
4587*4882a593Smuzhiyun */
mwl8k_interrupt(int irq,void * dev_id)4588*4882a593Smuzhiyun static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
4589*4882a593Smuzhiyun {
4590*4882a593Smuzhiyun struct ieee80211_hw *hw = dev_id;
4591*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
4592*4882a593Smuzhiyun u32 status;
4593*4882a593Smuzhiyun
4594*4882a593Smuzhiyun status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
4595*4882a593Smuzhiyun if (!status)
4596*4882a593Smuzhiyun return IRQ_NONE;
4597*4882a593Smuzhiyun
4598*4882a593Smuzhiyun if (status & MWL8K_A2H_INT_TX_DONE) {
4599*4882a593Smuzhiyun status &= ~MWL8K_A2H_INT_TX_DONE;
4600*4882a593Smuzhiyun tasklet_schedule(&priv->poll_tx_task);
4601*4882a593Smuzhiyun }
4602*4882a593Smuzhiyun
4603*4882a593Smuzhiyun if (status & MWL8K_A2H_INT_RX_READY) {
4604*4882a593Smuzhiyun status &= ~MWL8K_A2H_INT_RX_READY;
4605*4882a593Smuzhiyun tasklet_schedule(&priv->poll_rx_task);
4606*4882a593Smuzhiyun }
4607*4882a593Smuzhiyun
4608*4882a593Smuzhiyun if (status & MWL8K_A2H_INT_BA_WATCHDOG) {
4609*4882a593Smuzhiyun iowrite32(~MWL8K_A2H_INT_BA_WATCHDOG,
4610*4882a593Smuzhiyun priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
4611*4882a593Smuzhiyun
4612*4882a593Smuzhiyun atomic_inc(&priv->watchdog_event_pending);
4613*4882a593Smuzhiyun status &= ~MWL8K_A2H_INT_BA_WATCHDOG;
4614*4882a593Smuzhiyun ieee80211_queue_work(hw, &priv->watchdog_ba_handle);
4615*4882a593Smuzhiyun }
4616*4882a593Smuzhiyun
4617*4882a593Smuzhiyun if (status)
4618*4882a593Smuzhiyun iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
4619*4882a593Smuzhiyun
4620*4882a593Smuzhiyun if (status & MWL8K_A2H_INT_OPC_DONE) {
4621*4882a593Smuzhiyun if (priv->hostcmd_wait != NULL)
4622*4882a593Smuzhiyun complete(priv->hostcmd_wait);
4623*4882a593Smuzhiyun }
4624*4882a593Smuzhiyun
4625*4882a593Smuzhiyun if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
4626*4882a593Smuzhiyun if (!mutex_is_locked(&priv->fw_mutex) &&
4627*4882a593Smuzhiyun priv->radio_on && priv->pending_tx_pkts)
4628*4882a593Smuzhiyun mwl8k_tx_start(priv);
4629*4882a593Smuzhiyun }
4630*4882a593Smuzhiyun
4631*4882a593Smuzhiyun return IRQ_HANDLED;
4632*4882a593Smuzhiyun }
4633*4882a593Smuzhiyun
mwl8k_tx_poll(struct tasklet_struct * t)4634*4882a593Smuzhiyun static void mwl8k_tx_poll(struct tasklet_struct *t)
4635*4882a593Smuzhiyun {
4636*4882a593Smuzhiyun struct mwl8k_priv *priv = from_tasklet(priv, t, poll_tx_task);
4637*4882a593Smuzhiyun struct ieee80211_hw *hw = pci_get_drvdata(priv->pdev);
4638*4882a593Smuzhiyun int limit;
4639*4882a593Smuzhiyun int i;
4640*4882a593Smuzhiyun
4641*4882a593Smuzhiyun limit = 32;
4642*4882a593Smuzhiyun
4643*4882a593Smuzhiyun spin_lock(&priv->tx_lock);
4644*4882a593Smuzhiyun
4645*4882a593Smuzhiyun for (i = 0; i < mwl8k_tx_queues(priv); i++)
4646*4882a593Smuzhiyun limit -= mwl8k_txq_reclaim(hw, i, limit, 0);
4647*4882a593Smuzhiyun
4648*4882a593Smuzhiyun if (!priv->pending_tx_pkts && priv->tx_wait != NULL) {
4649*4882a593Smuzhiyun complete(priv->tx_wait);
4650*4882a593Smuzhiyun priv->tx_wait = NULL;
4651*4882a593Smuzhiyun }
4652*4882a593Smuzhiyun
4653*4882a593Smuzhiyun spin_unlock(&priv->tx_lock);
4654*4882a593Smuzhiyun
4655*4882a593Smuzhiyun if (limit) {
4656*4882a593Smuzhiyun writel(~MWL8K_A2H_INT_TX_DONE,
4657*4882a593Smuzhiyun priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
4658*4882a593Smuzhiyun } else {
4659*4882a593Smuzhiyun tasklet_schedule(&priv->poll_tx_task);
4660*4882a593Smuzhiyun }
4661*4882a593Smuzhiyun }
4662*4882a593Smuzhiyun
mwl8k_rx_poll(struct tasklet_struct * t)4663*4882a593Smuzhiyun static void mwl8k_rx_poll(struct tasklet_struct *t)
4664*4882a593Smuzhiyun {
4665*4882a593Smuzhiyun struct mwl8k_priv *priv = from_tasklet(priv, t, poll_rx_task);
4666*4882a593Smuzhiyun struct ieee80211_hw *hw = pci_get_drvdata(priv->pdev);
4667*4882a593Smuzhiyun int limit;
4668*4882a593Smuzhiyun
4669*4882a593Smuzhiyun limit = 32;
4670*4882a593Smuzhiyun limit -= rxq_process(hw, 0, limit);
4671*4882a593Smuzhiyun limit -= rxq_refill(hw, 0, limit);
4672*4882a593Smuzhiyun
4673*4882a593Smuzhiyun if (limit) {
4674*4882a593Smuzhiyun writel(~MWL8K_A2H_INT_RX_READY,
4675*4882a593Smuzhiyun priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
4676*4882a593Smuzhiyun } else {
4677*4882a593Smuzhiyun tasklet_schedule(&priv->poll_rx_task);
4678*4882a593Smuzhiyun }
4679*4882a593Smuzhiyun }
4680*4882a593Smuzhiyun
4681*4882a593Smuzhiyun
4682*4882a593Smuzhiyun /*
4683*4882a593Smuzhiyun * Core driver operations.
4684*4882a593Smuzhiyun */
mwl8k_tx(struct ieee80211_hw * hw,struct ieee80211_tx_control * control,struct sk_buff * skb)4685*4882a593Smuzhiyun static void mwl8k_tx(struct ieee80211_hw *hw,
4686*4882a593Smuzhiyun struct ieee80211_tx_control *control,
4687*4882a593Smuzhiyun struct sk_buff *skb)
4688*4882a593Smuzhiyun {
4689*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
4690*4882a593Smuzhiyun int index = skb_get_queue_mapping(skb);
4691*4882a593Smuzhiyun
4692*4882a593Smuzhiyun if (!priv->radio_on) {
4693*4882a593Smuzhiyun wiphy_debug(hw->wiphy,
4694*4882a593Smuzhiyun "dropped TX frame since radio disabled\n");
4695*4882a593Smuzhiyun dev_kfree_skb(skb);
4696*4882a593Smuzhiyun return;
4697*4882a593Smuzhiyun }
4698*4882a593Smuzhiyun
4699*4882a593Smuzhiyun mwl8k_txq_xmit(hw, index, control->sta, skb);
4700*4882a593Smuzhiyun }
4701*4882a593Smuzhiyun
mwl8k_start(struct ieee80211_hw * hw)4702*4882a593Smuzhiyun static int mwl8k_start(struct ieee80211_hw *hw)
4703*4882a593Smuzhiyun {
4704*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
4705*4882a593Smuzhiyun int rc;
4706*4882a593Smuzhiyun
4707*4882a593Smuzhiyun rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
4708*4882a593Smuzhiyun IRQF_SHARED, MWL8K_NAME, hw);
4709*4882a593Smuzhiyun if (rc) {
4710*4882a593Smuzhiyun priv->irq = -1;
4711*4882a593Smuzhiyun wiphy_err(hw->wiphy, "failed to register IRQ handler\n");
4712*4882a593Smuzhiyun return -EIO;
4713*4882a593Smuzhiyun }
4714*4882a593Smuzhiyun priv->irq = priv->pdev->irq;
4715*4882a593Smuzhiyun
4716*4882a593Smuzhiyun /* Enable TX reclaim and RX tasklets. */
4717*4882a593Smuzhiyun tasklet_enable(&priv->poll_tx_task);
4718*4882a593Smuzhiyun tasklet_enable(&priv->poll_rx_task);
4719*4882a593Smuzhiyun
4720*4882a593Smuzhiyun /* Enable interrupts */
4721*4882a593Smuzhiyun iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
4722*4882a593Smuzhiyun iowrite32(MWL8K_A2H_EVENTS,
4723*4882a593Smuzhiyun priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
4724*4882a593Smuzhiyun
4725*4882a593Smuzhiyun rc = mwl8k_fw_lock(hw);
4726*4882a593Smuzhiyun if (!rc) {
4727*4882a593Smuzhiyun rc = mwl8k_cmd_radio_enable(hw);
4728*4882a593Smuzhiyun
4729*4882a593Smuzhiyun if (!priv->ap_fw) {
4730*4882a593Smuzhiyun if (!rc)
4731*4882a593Smuzhiyun rc = mwl8k_cmd_enable_sniffer(hw, 0);
4732*4882a593Smuzhiyun
4733*4882a593Smuzhiyun if (!rc)
4734*4882a593Smuzhiyun rc = mwl8k_cmd_set_pre_scan(hw);
4735*4882a593Smuzhiyun
4736*4882a593Smuzhiyun if (!rc)
4737*4882a593Smuzhiyun rc = mwl8k_cmd_set_post_scan(hw,
4738*4882a593Smuzhiyun "\x00\x00\x00\x00\x00\x00");
4739*4882a593Smuzhiyun }
4740*4882a593Smuzhiyun
4741*4882a593Smuzhiyun if (!rc)
4742*4882a593Smuzhiyun rc = mwl8k_cmd_set_rateadapt_mode(hw, 0);
4743*4882a593Smuzhiyun
4744*4882a593Smuzhiyun if (!rc)
4745*4882a593Smuzhiyun rc = mwl8k_cmd_set_wmm_mode(hw, 0);
4746*4882a593Smuzhiyun
4747*4882a593Smuzhiyun mwl8k_fw_unlock(hw);
4748*4882a593Smuzhiyun }
4749*4882a593Smuzhiyun
4750*4882a593Smuzhiyun if (rc) {
4751*4882a593Smuzhiyun iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
4752*4882a593Smuzhiyun free_irq(priv->pdev->irq, hw);
4753*4882a593Smuzhiyun priv->irq = -1;
4754*4882a593Smuzhiyun tasklet_disable(&priv->poll_tx_task);
4755*4882a593Smuzhiyun tasklet_disable(&priv->poll_rx_task);
4756*4882a593Smuzhiyun } else {
4757*4882a593Smuzhiyun ieee80211_wake_queues(hw);
4758*4882a593Smuzhiyun }
4759*4882a593Smuzhiyun
4760*4882a593Smuzhiyun return rc;
4761*4882a593Smuzhiyun }
4762*4882a593Smuzhiyun
mwl8k_stop(struct ieee80211_hw * hw)4763*4882a593Smuzhiyun static void mwl8k_stop(struct ieee80211_hw *hw)
4764*4882a593Smuzhiyun {
4765*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
4766*4882a593Smuzhiyun int i;
4767*4882a593Smuzhiyun
4768*4882a593Smuzhiyun if (!priv->hw_restart_in_progress)
4769*4882a593Smuzhiyun mwl8k_cmd_radio_disable(hw);
4770*4882a593Smuzhiyun
4771*4882a593Smuzhiyun ieee80211_stop_queues(hw);
4772*4882a593Smuzhiyun
4773*4882a593Smuzhiyun /* Disable interrupts */
4774*4882a593Smuzhiyun iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
4775*4882a593Smuzhiyun if (priv->irq != -1) {
4776*4882a593Smuzhiyun free_irq(priv->pdev->irq, hw);
4777*4882a593Smuzhiyun priv->irq = -1;
4778*4882a593Smuzhiyun }
4779*4882a593Smuzhiyun
4780*4882a593Smuzhiyun /* Stop finalize join worker */
4781*4882a593Smuzhiyun cancel_work_sync(&priv->finalize_join_worker);
4782*4882a593Smuzhiyun cancel_work_sync(&priv->watchdog_ba_handle);
4783*4882a593Smuzhiyun if (priv->beacon_skb != NULL)
4784*4882a593Smuzhiyun dev_kfree_skb(priv->beacon_skb);
4785*4882a593Smuzhiyun
4786*4882a593Smuzhiyun /* Stop TX reclaim and RX tasklets. */
4787*4882a593Smuzhiyun tasklet_disable(&priv->poll_tx_task);
4788*4882a593Smuzhiyun tasklet_disable(&priv->poll_rx_task);
4789*4882a593Smuzhiyun
4790*4882a593Smuzhiyun /* Return all skbs to mac80211 */
4791*4882a593Smuzhiyun for (i = 0; i < mwl8k_tx_queues(priv); i++)
4792*4882a593Smuzhiyun mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
4793*4882a593Smuzhiyun }
4794*4882a593Smuzhiyun
4795*4882a593Smuzhiyun static int mwl8k_reload_firmware(struct ieee80211_hw *hw, char *fw_image);
4796*4882a593Smuzhiyun
mwl8k_add_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif)4797*4882a593Smuzhiyun static int mwl8k_add_interface(struct ieee80211_hw *hw,
4798*4882a593Smuzhiyun struct ieee80211_vif *vif)
4799*4882a593Smuzhiyun {
4800*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
4801*4882a593Smuzhiyun struct mwl8k_vif *mwl8k_vif;
4802*4882a593Smuzhiyun u32 macids_supported;
4803*4882a593Smuzhiyun int macid, rc;
4804*4882a593Smuzhiyun struct mwl8k_device_info *di;
4805*4882a593Smuzhiyun
4806*4882a593Smuzhiyun /*
4807*4882a593Smuzhiyun * Reject interface creation if sniffer mode is active, as
4808*4882a593Smuzhiyun * STA operation is mutually exclusive with hardware sniffer
4809*4882a593Smuzhiyun * mode. (Sniffer mode is only used on STA firmware.)
4810*4882a593Smuzhiyun */
4811*4882a593Smuzhiyun if (priv->sniffer_enabled) {
4812*4882a593Smuzhiyun wiphy_info(hw->wiphy,
4813*4882a593Smuzhiyun "unable to create STA interface because sniffer mode is enabled\n");
4814*4882a593Smuzhiyun return -EINVAL;
4815*4882a593Smuzhiyun }
4816*4882a593Smuzhiyun
4817*4882a593Smuzhiyun di = priv->device_info;
4818*4882a593Smuzhiyun switch (vif->type) {
4819*4882a593Smuzhiyun case NL80211_IFTYPE_AP:
4820*4882a593Smuzhiyun if (!priv->ap_fw && di->fw_image_ap) {
4821*4882a593Smuzhiyun /* we must load the ap fw to meet this request */
4822*4882a593Smuzhiyun if (!list_empty(&priv->vif_list))
4823*4882a593Smuzhiyun return -EBUSY;
4824*4882a593Smuzhiyun rc = mwl8k_reload_firmware(hw, di->fw_image_ap);
4825*4882a593Smuzhiyun if (rc)
4826*4882a593Smuzhiyun return rc;
4827*4882a593Smuzhiyun }
4828*4882a593Smuzhiyun macids_supported = priv->ap_macids_supported;
4829*4882a593Smuzhiyun break;
4830*4882a593Smuzhiyun case NL80211_IFTYPE_STATION:
4831*4882a593Smuzhiyun if (priv->ap_fw && di->fw_image_sta) {
4832*4882a593Smuzhiyun if (!list_empty(&priv->vif_list)) {
4833*4882a593Smuzhiyun wiphy_warn(hw->wiphy, "AP interface is running.\n"
4834*4882a593Smuzhiyun "Adding STA interface for WDS");
4835*4882a593Smuzhiyun } else {
4836*4882a593Smuzhiyun /* we must load the sta fw to
4837*4882a593Smuzhiyun * meet this request.
4838*4882a593Smuzhiyun */
4839*4882a593Smuzhiyun rc = mwl8k_reload_firmware(hw,
4840*4882a593Smuzhiyun di->fw_image_sta);
4841*4882a593Smuzhiyun if (rc)
4842*4882a593Smuzhiyun return rc;
4843*4882a593Smuzhiyun }
4844*4882a593Smuzhiyun }
4845*4882a593Smuzhiyun macids_supported = priv->sta_macids_supported;
4846*4882a593Smuzhiyun break;
4847*4882a593Smuzhiyun default:
4848*4882a593Smuzhiyun return -EINVAL;
4849*4882a593Smuzhiyun }
4850*4882a593Smuzhiyun
4851*4882a593Smuzhiyun macid = ffs(macids_supported & ~priv->macids_used);
4852*4882a593Smuzhiyun if (!macid--)
4853*4882a593Smuzhiyun return -EBUSY;
4854*4882a593Smuzhiyun
4855*4882a593Smuzhiyun /* Setup driver private area. */
4856*4882a593Smuzhiyun mwl8k_vif = MWL8K_VIF(vif);
4857*4882a593Smuzhiyun memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
4858*4882a593Smuzhiyun mwl8k_vif->vif = vif;
4859*4882a593Smuzhiyun mwl8k_vif->macid = macid;
4860*4882a593Smuzhiyun mwl8k_vif->seqno = 0;
4861*4882a593Smuzhiyun memcpy(mwl8k_vif->bssid, vif->addr, ETH_ALEN);
4862*4882a593Smuzhiyun mwl8k_vif->is_hw_crypto_enabled = false;
4863*4882a593Smuzhiyun
4864*4882a593Smuzhiyun /* Set the mac address. */
4865*4882a593Smuzhiyun mwl8k_cmd_set_mac_addr(hw, vif, vif->addr);
4866*4882a593Smuzhiyun
4867*4882a593Smuzhiyun if (vif->type == NL80211_IFTYPE_AP)
4868*4882a593Smuzhiyun mwl8k_cmd_set_new_stn_add_self(hw, vif);
4869*4882a593Smuzhiyun
4870*4882a593Smuzhiyun priv->macids_used |= 1 << mwl8k_vif->macid;
4871*4882a593Smuzhiyun list_add_tail(&mwl8k_vif->list, &priv->vif_list);
4872*4882a593Smuzhiyun
4873*4882a593Smuzhiyun return 0;
4874*4882a593Smuzhiyun }
4875*4882a593Smuzhiyun
mwl8k_remove_vif(struct mwl8k_priv * priv,struct mwl8k_vif * vif)4876*4882a593Smuzhiyun static void mwl8k_remove_vif(struct mwl8k_priv *priv, struct mwl8k_vif *vif)
4877*4882a593Smuzhiyun {
4878*4882a593Smuzhiyun /* Has ieee80211_restart_hw re-added the removed interfaces? */
4879*4882a593Smuzhiyun if (!priv->macids_used)
4880*4882a593Smuzhiyun return;
4881*4882a593Smuzhiyun
4882*4882a593Smuzhiyun priv->macids_used &= ~(1 << vif->macid);
4883*4882a593Smuzhiyun list_del(&vif->list);
4884*4882a593Smuzhiyun }
4885*4882a593Smuzhiyun
mwl8k_remove_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif)4886*4882a593Smuzhiyun static void mwl8k_remove_interface(struct ieee80211_hw *hw,
4887*4882a593Smuzhiyun struct ieee80211_vif *vif)
4888*4882a593Smuzhiyun {
4889*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
4890*4882a593Smuzhiyun struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
4891*4882a593Smuzhiyun
4892*4882a593Smuzhiyun if (vif->type == NL80211_IFTYPE_AP)
4893*4882a593Smuzhiyun mwl8k_cmd_set_new_stn_del(hw, vif, vif->addr);
4894*4882a593Smuzhiyun
4895*4882a593Smuzhiyun mwl8k_cmd_del_mac_addr(hw, vif, vif->addr);
4896*4882a593Smuzhiyun
4897*4882a593Smuzhiyun mwl8k_remove_vif(priv, mwl8k_vif);
4898*4882a593Smuzhiyun }
4899*4882a593Smuzhiyun
mwl8k_hw_restart_work(struct work_struct * work)4900*4882a593Smuzhiyun static void mwl8k_hw_restart_work(struct work_struct *work)
4901*4882a593Smuzhiyun {
4902*4882a593Smuzhiyun struct mwl8k_priv *priv =
4903*4882a593Smuzhiyun container_of(work, struct mwl8k_priv, fw_reload);
4904*4882a593Smuzhiyun struct ieee80211_hw *hw = priv->hw;
4905*4882a593Smuzhiyun struct mwl8k_device_info *di;
4906*4882a593Smuzhiyun int rc;
4907*4882a593Smuzhiyun
4908*4882a593Smuzhiyun /* If some command is waiting for a response, clear it */
4909*4882a593Smuzhiyun if (priv->hostcmd_wait != NULL) {
4910*4882a593Smuzhiyun complete(priv->hostcmd_wait);
4911*4882a593Smuzhiyun priv->hostcmd_wait = NULL;
4912*4882a593Smuzhiyun }
4913*4882a593Smuzhiyun
4914*4882a593Smuzhiyun priv->hw_restart_owner = current;
4915*4882a593Smuzhiyun di = priv->device_info;
4916*4882a593Smuzhiyun mwl8k_fw_lock(hw);
4917*4882a593Smuzhiyun
4918*4882a593Smuzhiyun if (priv->ap_fw)
4919*4882a593Smuzhiyun rc = mwl8k_reload_firmware(hw, di->fw_image_ap);
4920*4882a593Smuzhiyun else
4921*4882a593Smuzhiyun rc = mwl8k_reload_firmware(hw, di->fw_image_sta);
4922*4882a593Smuzhiyun
4923*4882a593Smuzhiyun if (rc)
4924*4882a593Smuzhiyun goto fail;
4925*4882a593Smuzhiyun
4926*4882a593Smuzhiyun priv->hw_restart_owner = NULL;
4927*4882a593Smuzhiyun priv->hw_restart_in_progress = false;
4928*4882a593Smuzhiyun
4929*4882a593Smuzhiyun /*
4930*4882a593Smuzhiyun * This unlock will wake up the queues and
4931*4882a593Smuzhiyun * also opens the command path for other
4932*4882a593Smuzhiyun * commands
4933*4882a593Smuzhiyun */
4934*4882a593Smuzhiyun mwl8k_fw_unlock(hw);
4935*4882a593Smuzhiyun
4936*4882a593Smuzhiyun ieee80211_restart_hw(hw);
4937*4882a593Smuzhiyun
4938*4882a593Smuzhiyun wiphy_err(hw->wiphy, "Firmware restarted successfully\n");
4939*4882a593Smuzhiyun
4940*4882a593Smuzhiyun return;
4941*4882a593Smuzhiyun fail:
4942*4882a593Smuzhiyun mwl8k_fw_unlock(hw);
4943*4882a593Smuzhiyun
4944*4882a593Smuzhiyun wiphy_err(hw->wiphy, "Firmware restart failed\n");
4945*4882a593Smuzhiyun }
4946*4882a593Smuzhiyun
mwl8k_config(struct ieee80211_hw * hw,u32 changed)4947*4882a593Smuzhiyun static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
4948*4882a593Smuzhiyun {
4949*4882a593Smuzhiyun struct ieee80211_conf *conf = &hw->conf;
4950*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
4951*4882a593Smuzhiyun int rc;
4952*4882a593Smuzhiyun
4953*4882a593Smuzhiyun rc = mwl8k_fw_lock(hw);
4954*4882a593Smuzhiyun if (rc)
4955*4882a593Smuzhiyun return rc;
4956*4882a593Smuzhiyun
4957*4882a593Smuzhiyun if (conf->flags & IEEE80211_CONF_IDLE)
4958*4882a593Smuzhiyun rc = mwl8k_cmd_radio_disable(hw);
4959*4882a593Smuzhiyun else
4960*4882a593Smuzhiyun rc = mwl8k_cmd_radio_enable(hw);
4961*4882a593Smuzhiyun if (rc)
4962*4882a593Smuzhiyun goto out;
4963*4882a593Smuzhiyun
4964*4882a593Smuzhiyun if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
4965*4882a593Smuzhiyun rc = mwl8k_cmd_set_rf_channel(hw, conf);
4966*4882a593Smuzhiyun if (rc)
4967*4882a593Smuzhiyun goto out;
4968*4882a593Smuzhiyun }
4969*4882a593Smuzhiyun
4970*4882a593Smuzhiyun if (conf->power_level > 18)
4971*4882a593Smuzhiyun conf->power_level = 18;
4972*4882a593Smuzhiyun
4973*4882a593Smuzhiyun if (priv->ap_fw) {
4974*4882a593Smuzhiyun
4975*4882a593Smuzhiyun if (conf->flags & IEEE80211_CONF_CHANGE_POWER) {
4976*4882a593Smuzhiyun rc = mwl8k_cmd_tx_power(hw, conf, conf->power_level);
4977*4882a593Smuzhiyun if (rc)
4978*4882a593Smuzhiyun goto out;
4979*4882a593Smuzhiyun }
4980*4882a593Smuzhiyun
4981*4882a593Smuzhiyun
4982*4882a593Smuzhiyun } else {
4983*4882a593Smuzhiyun rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
4984*4882a593Smuzhiyun if (rc)
4985*4882a593Smuzhiyun goto out;
4986*4882a593Smuzhiyun rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
4987*4882a593Smuzhiyun }
4988*4882a593Smuzhiyun
4989*4882a593Smuzhiyun out:
4990*4882a593Smuzhiyun mwl8k_fw_unlock(hw);
4991*4882a593Smuzhiyun
4992*4882a593Smuzhiyun return rc;
4993*4882a593Smuzhiyun }
4994*4882a593Smuzhiyun
4995*4882a593Smuzhiyun static void
mwl8k_bss_info_changed_sta(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_bss_conf * info,u32 changed)4996*4882a593Smuzhiyun mwl8k_bss_info_changed_sta(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4997*4882a593Smuzhiyun struct ieee80211_bss_conf *info, u32 changed)
4998*4882a593Smuzhiyun {
4999*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
5000*4882a593Smuzhiyun u32 ap_legacy_rates = 0;
5001*4882a593Smuzhiyun u8 ap_mcs_rates[16];
5002*4882a593Smuzhiyun int rc;
5003*4882a593Smuzhiyun
5004*4882a593Smuzhiyun if (mwl8k_fw_lock(hw))
5005*4882a593Smuzhiyun return;
5006*4882a593Smuzhiyun
5007*4882a593Smuzhiyun /*
5008*4882a593Smuzhiyun * No need to capture a beacon if we're no longer associated.
5009*4882a593Smuzhiyun */
5010*4882a593Smuzhiyun if ((changed & BSS_CHANGED_ASSOC) && !vif->bss_conf.assoc)
5011*4882a593Smuzhiyun priv->capture_beacon = false;
5012*4882a593Smuzhiyun
5013*4882a593Smuzhiyun /*
5014*4882a593Smuzhiyun * Get the AP's legacy and MCS rates.
5015*4882a593Smuzhiyun */
5016*4882a593Smuzhiyun if (vif->bss_conf.assoc) {
5017*4882a593Smuzhiyun struct ieee80211_sta *ap;
5018*4882a593Smuzhiyun
5019*4882a593Smuzhiyun rcu_read_lock();
5020*4882a593Smuzhiyun
5021*4882a593Smuzhiyun ap = ieee80211_find_sta(vif, vif->bss_conf.bssid);
5022*4882a593Smuzhiyun if (ap == NULL) {
5023*4882a593Smuzhiyun rcu_read_unlock();
5024*4882a593Smuzhiyun goto out;
5025*4882a593Smuzhiyun }
5026*4882a593Smuzhiyun
5027*4882a593Smuzhiyun if (hw->conf.chandef.chan->band == NL80211_BAND_2GHZ) {
5028*4882a593Smuzhiyun ap_legacy_rates = ap->supp_rates[NL80211_BAND_2GHZ];
5029*4882a593Smuzhiyun } else {
5030*4882a593Smuzhiyun ap_legacy_rates =
5031*4882a593Smuzhiyun ap->supp_rates[NL80211_BAND_5GHZ] << 5;
5032*4882a593Smuzhiyun }
5033*4882a593Smuzhiyun memcpy(ap_mcs_rates, ap->ht_cap.mcs.rx_mask, 16);
5034*4882a593Smuzhiyun
5035*4882a593Smuzhiyun rcu_read_unlock();
5036*4882a593Smuzhiyun
5037*4882a593Smuzhiyun if (changed & BSS_CHANGED_ASSOC) {
5038*4882a593Smuzhiyun if (!priv->ap_fw) {
5039*4882a593Smuzhiyun rc = mwl8k_cmd_set_rate(hw, vif,
5040*4882a593Smuzhiyun ap_legacy_rates,
5041*4882a593Smuzhiyun ap_mcs_rates);
5042*4882a593Smuzhiyun if (rc)
5043*4882a593Smuzhiyun goto out;
5044*4882a593Smuzhiyun
5045*4882a593Smuzhiyun rc = mwl8k_cmd_use_fixed_rate_sta(hw);
5046*4882a593Smuzhiyun if (rc)
5047*4882a593Smuzhiyun goto out;
5048*4882a593Smuzhiyun } else {
5049*4882a593Smuzhiyun int idx;
5050*4882a593Smuzhiyun int rate;
5051*4882a593Smuzhiyun
5052*4882a593Smuzhiyun /* Use AP firmware specific rate command.
5053*4882a593Smuzhiyun */
5054*4882a593Smuzhiyun idx = ffs(vif->bss_conf.basic_rates);
5055*4882a593Smuzhiyun if (idx)
5056*4882a593Smuzhiyun idx--;
5057*4882a593Smuzhiyun
5058*4882a593Smuzhiyun if (hw->conf.chandef.chan->band ==
5059*4882a593Smuzhiyun NL80211_BAND_2GHZ)
5060*4882a593Smuzhiyun rate = mwl8k_rates_24[idx].hw_value;
5061*4882a593Smuzhiyun else
5062*4882a593Smuzhiyun rate = mwl8k_rates_50[idx].hw_value;
5063*4882a593Smuzhiyun
5064*4882a593Smuzhiyun mwl8k_cmd_use_fixed_rate_ap(hw, rate, rate);
5065*4882a593Smuzhiyun }
5066*4882a593Smuzhiyun }
5067*4882a593Smuzhiyun }
5068*4882a593Smuzhiyun
5069*4882a593Smuzhiyun if (changed & BSS_CHANGED_ERP_PREAMBLE) {
5070*4882a593Smuzhiyun rc = mwl8k_set_radio_preamble(hw,
5071*4882a593Smuzhiyun vif->bss_conf.use_short_preamble);
5072*4882a593Smuzhiyun if (rc)
5073*4882a593Smuzhiyun goto out;
5074*4882a593Smuzhiyun }
5075*4882a593Smuzhiyun
5076*4882a593Smuzhiyun if ((changed & BSS_CHANGED_ERP_SLOT) && !priv->ap_fw) {
5077*4882a593Smuzhiyun rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot);
5078*4882a593Smuzhiyun if (rc)
5079*4882a593Smuzhiyun goto out;
5080*4882a593Smuzhiyun }
5081*4882a593Smuzhiyun
5082*4882a593Smuzhiyun if (vif->bss_conf.assoc && !priv->ap_fw &&
5083*4882a593Smuzhiyun (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_ERP_CTS_PROT |
5084*4882a593Smuzhiyun BSS_CHANGED_HT))) {
5085*4882a593Smuzhiyun rc = mwl8k_cmd_set_aid(hw, vif, ap_legacy_rates);
5086*4882a593Smuzhiyun if (rc)
5087*4882a593Smuzhiyun goto out;
5088*4882a593Smuzhiyun }
5089*4882a593Smuzhiyun
5090*4882a593Smuzhiyun if (vif->bss_conf.assoc &&
5091*4882a593Smuzhiyun (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BEACON_INT))) {
5092*4882a593Smuzhiyun /*
5093*4882a593Smuzhiyun * Finalize the join. Tell rx handler to process
5094*4882a593Smuzhiyun * next beacon from our BSSID.
5095*4882a593Smuzhiyun */
5096*4882a593Smuzhiyun memcpy(priv->capture_bssid, vif->bss_conf.bssid, ETH_ALEN);
5097*4882a593Smuzhiyun priv->capture_beacon = true;
5098*4882a593Smuzhiyun }
5099*4882a593Smuzhiyun
5100*4882a593Smuzhiyun out:
5101*4882a593Smuzhiyun mwl8k_fw_unlock(hw);
5102*4882a593Smuzhiyun }
5103*4882a593Smuzhiyun
5104*4882a593Smuzhiyun static void
mwl8k_bss_info_changed_ap(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_bss_conf * info,u32 changed)5105*4882a593Smuzhiyun mwl8k_bss_info_changed_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5106*4882a593Smuzhiyun struct ieee80211_bss_conf *info, u32 changed)
5107*4882a593Smuzhiyun {
5108*4882a593Smuzhiyun int rc;
5109*4882a593Smuzhiyun
5110*4882a593Smuzhiyun if (mwl8k_fw_lock(hw))
5111*4882a593Smuzhiyun return;
5112*4882a593Smuzhiyun
5113*4882a593Smuzhiyun if (changed & BSS_CHANGED_ERP_PREAMBLE) {
5114*4882a593Smuzhiyun rc = mwl8k_set_radio_preamble(hw,
5115*4882a593Smuzhiyun vif->bss_conf.use_short_preamble);
5116*4882a593Smuzhiyun if (rc)
5117*4882a593Smuzhiyun goto out;
5118*4882a593Smuzhiyun }
5119*4882a593Smuzhiyun
5120*4882a593Smuzhiyun if (changed & BSS_CHANGED_BASIC_RATES) {
5121*4882a593Smuzhiyun int idx;
5122*4882a593Smuzhiyun int rate;
5123*4882a593Smuzhiyun
5124*4882a593Smuzhiyun /*
5125*4882a593Smuzhiyun * Use lowest supported basic rate for multicasts
5126*4882a593Smuzhiyun * and management frames (such as probe responses --
5127*4882a593Smuzhiyun * beacons will always go out at 1 Mb/s).
5128*4882a593Smuzhiyun */
5129*4882a593Smuzhiyun idx = ffs(vif->bss_conf.basic_rates);
5130*4882a593Smuzhiyun if (idx)
5131*4882a593Smuzhiyun idx--;
5132*4882a593Smuzhiyun
5133*4882a593Smuzhiyun if (hw->conf.chandef.chan->band == NL80211_BAND_2GHZ)
5134*4882a593Smuzhiyun rate = mwl8k_rates_24[idx].hw_value;
5135*4882a593Smuzhiyun else
5136*4882a593Smuzhiyun rate = mwl8k_rates_50[idx].hw_value;
5137*4882a593Smuzhiyun
5138*4882a593Smuzhiyun mwl8k_cmd_use_fixed_rate_ap(hw, rate, rate);
5139*4882a593Smuzhiyun }
5140*4882a593Smuzhiyun
5141*4882a593Smuzhiyun if (changed & (BSS_CHANGED_BEACON_INT | BSS_CHANGED_BEACON)) {
5142*4882a593Smuzhiyun struct sk_buff *skb;
5143*4882a593Smuzhiyun
5144*4882a593Smuzhiyun skb = ieee80211_beacon_get(hw, vif);
5145*4882a593Smuzhiyun if (skb != NULL) {
5146*4882a593Smuzhiyun mwl8k_cmd_set_beacon(hw, vif, skb->data, skb->len);
5147*4882a593Smuzhiyun kfree_skb(skb);
5148*4882a593Smuzhiyun }
5149*4882a593Smuzhiyun }
5150*4882a593Smuzhiyun
5151*4882a593Smuzhiyun if (changed & BSS_CHANGED_BEACON_ENABLED)
5152*4882a593Smuzhiyun mwl8k_cmd_bss_start(hw, vif, info->enable_beacon);
5153*4882a593Smuzhiyun
5154*4882a593Smuzhiyun out:
5155*4882a593Smuzhiyun mwl8k_fw_unlock(hw);
5156*4882a593Smuzhiyun }
5157*4882a593Smuzhiyun
5158*4882a593Smuzhiyun static void
mwl8k_bss_info_changed(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_bss_conf * info,u32 changed)5159*4882a593Smuzhiyun mwl8k_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5160*4882a593Smuzhiyun struct ieee80211_bss_conf *info, u32 changed)
5161*4882a593Smuzhiyun {
5162*4882a593Smuzhiyun if (vif->type == NL80211_IFTYPE_STATION)
5163*4882a593Smuzhiyun mwl8k_bss_info_changed_sta(hw, vif, info, changed);
5164*4882a593Smuzhiyun if (vif->type == NL80211_IFTYPE_AP)
5165*4882a593Smuzhiyun mwl8k_bss_info_changed_ap(hw, vif, info, changed);
5166*4882a593Smuzhiyun }
5167*4882a593Smuzhiyun
mwl8k_prepare_multicast(struct ieee80211_hw * hw,struct netdev_hw_addr_list * mc_list)5168*4882a593Smuzhiyun static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
5169*4882a593Smuzhiyun struct netdev_hw_addr_list *mc_list)
5170*4882a593Smuzhiyun {
5171*4882a593Smuzhiyun struct mwl8k_cmd_pkt *cmd;
5172*4882a593Smuzhiyun
5173*4882a593Smuzhiyun /*
5174*4882a593Smuzhiyun * Synthesize and return a command packet that programs the
5175*4882a593Smuzhiyun * hardware multicast address filter. At this point we don't
5176*4882a593Smuzhiyun * know whether FIF_ALLMULTI is being requested, but if it is,
5177*4882a593Smuzhiyun * we'll end up throwing this packet away and creating a new
5178*4882a593Smuzhiyun * one in mwl8k_configure_filter().
5179*4882a593Smuzhiyun */
5180*4882a593Smuzhiyun cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_list);
5181*4882a593Smuzhiyun
5182*4882a593Smuzhiyun return (unsigned long)cmd;
5183*4882a593Smuzhiyun }
5184*4882a593Smuzhiyun
5185*4882a593Smuzhiyun static int
mwl8k_configure_filter_sniffer(struct ieee80211_hw * hw,unsigned int changed_flags,unsigned int * total_flags)5186*4882a593Smuzhiyun mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
5187*4882a593Smuzhiyun unsigned int changed_flags,
5188*4882a593Smuzhiyun unsigned int *total_flags)
5189*4882a593Smuzhiyun {
5190*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
5191*4882a593Smuzhiyun
5192*4882a593Smuzhiyun /*
5193*4882a593Smuzhiyun * Hardware sniffer mode is mutually exclusive with STA
5194*4882a593Smuzhiyun * operation, so refuse to enable sniffer mode if a STA
5195*4882a593Smuzhiyun * interface is active.
5196*4882a593Smuzhiyun */
5197*4882a593Smuzhiyun if (!list_empty(&priv->vif_list)) {
5198*4882a593Smuzhiyun if (net_ratelimit())
5199*4882a593Smuzhiyun wiphy_info(hw->wiphy,
5200*4882a593Smuzhiyun "not enabling sniffer mode because STA interface is active\n");
5201*4882a593Smuzhiyun return 0;
5202*4882a593Smuzhiyun }
5203*4882a593Smuzhiyun
5204*4882a593Smuzhiyun if (!priv->sniffer_enabled) {
5205*4882a593Smuzhiyun if (mwl8k_cmd_enable_sniffer(hw, 1))
5206*4882a593Smuzhiyun return 0;
5207*4882a593Smuzhiyun priv->sniffer_enabled = true;
5208*4882a593Smuzhiyun }
5209*4882a593Smuzhiyun
5210*4882a593Smuzhiyun *total_flags &= FIF_ALLMULTI |
5211*4882a593Smuzhiyun FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
5212*4882a593Smuzhiyun FIF_OTHER_BSS;
5213*4882a593Smuzhiyun
5214*4882a593Smuzhiyun return 1;
5215*4882a593Smuzhiyun }
5216*4882a593Smuzhiyun
mwl8k_first_vif(struct mwl8k_priv * priv)5217*4882a593Smuzhiyun static struct mwl8k_vif *mwl8k_first_vif(struct mwl8k_priv *priv)
5218*4882a593Smuzhiyun {
5219*4882a593Smuzhiyun if (!list_empty(&priv->vif_list))
5220*4882a593Smuzhiyun return list_entry(priv->vif_list.next, struct mwl8k_vif, list);
5221*4882a593Smuzhiyun
5222*4882a593Smuzhiyun return NULL;
5223*4882a593Smuzhiyun }
5224*4882a593Smuzhiyun
mwl8k_configure_filter(struct ieee80211_hw * hw,unsigned int changed_flags,unsigned int * total_flags,u64 multicast)5225*4882a593Smuzhiyun static void mwl8k_configure_filter(struct ieee80211_hw *hw,
5226*4882a593Smuzhiyun unsigned int changed_flags,
5227*4882a593Smuzhiyun unsigned int *total_flags,
5228*4882a593Smuzhiyun u64 multicast)
5229*4882a593Smuzhiyun {
5230*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
5231*4882a593Smuzhiyun struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
5232*4882a593Smuzhiyun
5233*4882a593Smuzhiyun /*
5234*4882a593Smuzhiyun * AP firmware doesn't allow fine-grained control over
5235*4882a593Smuzhiyun * the receive filter.
5236*4882a593Smuzhiyun */
5237*4882a593Smuzhiyun if (priv->ap_fw) {
5238*4882a593Smuzhiyun *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
5239*4882a593Smuzhiyun kfree(cmd);
5240*4882a593Smuzhiyun return;
5241*4882a593Smuzhiyun }
5242*4882a593Smuzhiyun
5243*4882a593Smuzhiyun /*
5244*4882a593Smuzhiyun * Enable hardware sniffer mode if FIF_CONTROL or
5245*4882a593Smuzhiyun * FIF_OTHER_BSS is requested.
5246*4882a593Smuzhiyun */
5247*4882a593Smuzhiyun if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
5248*4882a593Smuzhiyun mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
5249*4882a593Smuzhiyun kfree(cmd);
5250*4882a593Smuzhiyun return;
5251*4882a593Smuzhiyun }
5252*4882a593Smuzhiyun
5253*4882a593Smuzhiyun /* Clear unsupported feature flags */
5254*4882a593Smuzhiyun *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
5255*4882a593Smuzhiyun
5256*4882a593Smuzhiyun if (mwl8k_fw_lock(hw)) {
5257*4882a593Smuzhiyun kfree(cmd);
5258*4882a593Smuzhiyun return;
5259*4882a593Smuzhiyun }
5260*4882a593Smuzhiyun
5261*4882a593Smuzhiyun if (priv->sniffer_enabled) {
5262*4882a593Smuzhiyun mwl8k_cmd_enable_sniffer(hw, 0);
5263*4882a593Smuzhiyun priv->sniffer_enabled = false;
5264*4882a593Smuzhiyun }
5265*4882a593Smuzhiyun
5266*4882a593Smuzhiyun if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
5267*4882a593Smuzhiyun if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
5268*4882a593Smuzhiyun /*
5269*4882a593Smuzhiyun * Disable the BSS filter.
5270*4882a593Smuzhiyun */
5271*4882a593Smuzhiyun mwl8k_cmd_set_pre_scan(hw);
5272*4882a593Smuzhiyun } else {
5273*4882a593Smuzhiyun struct mwl8k_vif *mwl8k_vif;
5274*4882a593Smuzhiyun const u8 *bssid;
5275*4882a593Smuzhiyun
5276*4882a593Smuzhiyun /*
5277*4882a593Smuzhiyun * Enable the BSS filter.
5278*4882a593Smuzhiyun *
5279*4882a593Smuzhiyun * If there is an active STA interface, use that
5280*4882a593Smuzhiyun * interface's BSSID, otherwise use a dummy one
5281*4882a593Smuzhiyun * (where the OUI part needs to be nonzero for
5282*4882a593Smuzhiyun * the BSSID to be accepted by POST_SCAN).
5283*4882a593Smuzhiyun */
5284*4882a593Smuzhiyun mwl8k_vif = mwl8k_first_vif(priv);
5285*4882a593Smuzhiyun if (mwl8k_vif != NULL)
5286*4882a593Smuzhiyun bssid = mwl8k_vif->vif->bss_conf.bssid;
5287*4882a593Smuzhiyun else
5288*4882a593Smuzhiyun bssid = "\x01\x00\x00\x00\x00\x00";
5289*4882a593Smuzhiyun
5290*4882a593Smuzhiyun mwl8k_cmd_set_post_scan(hw, bssid);
5291*4882a593Smuzhiyun }
5292*4882a593Smuzhiyun }
5293*4882a593Smuzhiyun
5294*4882a593Smuzhiyun /*
5295*4882a593Smuzhiyun * If FIF_ALLMULTI is being requested, throw away the command
5296*4882a593Smuzhiyun * packet that ->prepare_multicast() built and replace it with
5297*4882a593Smuzhiyun * a command packet that enables reception of all multicast
5298*4882a593Smuzhiyun * packets.
5299*4882a593Smuzhiyun */
5300*4882a593Smuzhiyun if (*total_flags & FIF_ALLMULTI) {
5301*4882a593Smuzhiyun kfree(cmd);
5302*4882a593Smuzhiyun cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, NULL);
5303*4882a593Smuzhiyun }
5304*4882a593Smuzhiyun
5305*4882a593Smuzhiyun if (cmd != NULL) {
5306*4882a593Smuzhiyun mwl8k_post_cmd(hw, cmd);
5307*4882a593Smuzhiyun kfree(cmd);
5308*4882a593Smuzhiyun }
5309*4882a593Smuzhiyun
5310*4882a593Smuzhiyun mwl8k_fw_unlock(hw);
5311*4882a593Smuzhiyun }
5312*4882a593Smuzhiyun
mwl8k_set_rts_threshold(struct ieee80211_hw * hw,u32 value)5313*4882a593Smuzhiyun static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
5314*4882a593Smuzhiyun {
5315*4882a593Smuzhiyun return mwl8k_cmd_set_rts_threshold(hw, value);
5316*4882a593Smuzhiyun }
5317*4882a593Smuzhiyun
mwl8k_sta_remove(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta)5318*4882a593Smuzhiyun static int mwl8k_sta_remove(struct ieee80211_hw *hw,
5319*4882a593Smuzhiyun struct ieee80211_vif *vif,
5320*4882a593Smuzhiyun struct ieee80211_sta *sta)
5321*4882a593Smuzhiyun {
5322*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
5323*4882a593Smuzhiyun
5324*4882a593Smuzhiyun if (priv->ap_fw)
5325*4882a593Smuzhiyun return mwl8k_cmd_set_new_stn_del(hw, vif, sta->addr);
5326*4882a593Smuzhiyun else
5327*4882a593Smuzhiyun return mwl8k_cmd_update_stadb_del(hw, vif, sta->addr);
5328*4882a593Smuzhiyun }
5329*4882a593Smuzhiyun
mwl8k_sta_add(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta)5330*4882a593Smuzhiyun static int mwl8k_sta_add(struct ieee80211_hw *hw,
5331*4882a593Smuzhiyun struct ieee80211_vif *vif,
5332*4882a593Smuzhiyun struct ieee80211_sta *sta)
5333*4882a593Smuzhiyun {
5334*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
5335*4882a593Smuzhiyun int ret;
5336*4882a593Smuzhiyun int i;
5337*4882a593Smuzhiyun struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
5338*4882a593Smuzhiyun struct ieee80211_key_conf *key;
5339*4882a593Smuzhiyun
5340*4882a593Smuzhiyun if (!priv->ap_fw) {
5341*4882a593Smuzhiyun ret = mwl8k_cmd_update_stadb_add(hw, vif, sta);
5342*4882a593Smuzhiyun if (ret >= 0) {
5343*4882a593Smuzhiyun MWL8K_STA(sta)->peer_id = ret;
5344*4882a593Smuzhiyun if (sta->ht_cap.ht_supported)
5345*4882a593Smuzhiyun MWL8K_STA(sta)->is_ampdu_allowed = true;
5346*4882a593Smuzhiyun ret = 0;
5347*4882a593Smuzhiyun }
5348*4882a593Smuzhiyun
5349*4882a593Smuzhiyun } else {
5350*4882a593Smuzhiyun ret = mwl8k_cmd_set_new_stn_add(hw, vif, sta);
5351*4882a593Smuzhiyun }
5352*4882a593Smuzhiyun
5353*4882a593Smuzhiyun for (i = 0; i < NUM_WEP_KEYS; i++) {
5354*4882a593Smuzhiyun key = IEEE80211_KEY_CONF(mwl8k_vif->wep_key_conf[i].key);
5355*4882a593Smuzhiyun if (mwl8k_vif->wep_key_conf[i].enabled)
5356*4882a593Smuzhiyun mwl8k_set_key(hw, SET_KEY, vif, sta, key);
5357*4882a593Smuzhiyun }
5358*4882a593Smuzhiyun return ret;
5359*4882a593Smuzhiyun }
5360*4882a593Smuzhiyun
mwl8k_conf_tx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u16 queue,const struct ieee80211_tx_queue_params * params)5361*4882a593Smuzhiyun static int mwl8k_conf_tx(struct ieee80211_hw *hw,
5362*4882a593Smuzhiyun struct ieee80211_vif *vif, u16 queue,
5363*4882a593Smuzhiyun const struct ieee80211_tx_queue_params *params)
5364*4882a593Smuzhiyun {
5365*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
5366*4882a593Smuzhiyun int rc;
5367*4882a593Smuzhiyun
5368*4882a593Smuzhiyun rc = mwl8k_fw_lock(hw);
5369*4882a593Smuzhiyun if (!rc) {
5370*4882a593Smuzhiyun BUG_ON(queue > MWL8K_TX_WMM_QUEUES - 1);
5371*4882a593Smuzhiyun memcpy(&priv->wmm_params[queue], params, sizeof(*params));
5372*4882a593Smuzhiyun
5373*4882a593Smuzhiyun if (!priv->wmm_enabled)
5374*4882a593Smuzhiyun rc = mwl8k_cmd_set_wmm_mode(hw, 1);
5375*4882a593Smuzhiyun
5376*4882a593Smuzhiyun if (!rc) {
5377*4882a593Smuzhiyun int q = MWL8K_TX_WMM_QUEUES - 1 - queue;
5378*4882a593Smuzhiyun rc = mwl8k_cmd_set_edca_params(hw, q,
5379*4882a593Smuzhiyun params->cw_min,
5380*4882a593Smuzhiyun params->cw_max,
5381*4882a593Smuzhiyun params->aifs,
5382*4882a593Smuzhiyun params->txop);
5383*4882a593Smuzhiyun }
5384*4882a593Smuzhiyun
5385*4882a593Smuzhiyun mwl8k_fw_unlock(hw);
5386*4882a593Smuzhiyun }
5387*4882a593Smuzhiyun
5388*4882a593Smuzhiyun return rc;
5389*4882a593Smuzhiyun }
5390*4882a593Smuzhiyun
mwl8k_get_stats(struct ieee80211_hw * hw,struct ieee80211_low_level_stats * stats)5391*4882a593Smuzhiyun static int mwl8k_get_stats(struct ieee80211_hw *hw,
5392*4882a593Smuzhiyun struct ieee80211_low_level_stats *stats)
5393*4882a593Smuzhiyun {
5394*4882a593Smuzhiyun return mwl8k_cmd_get_stat(hw, stats);
5395*4882a593Smuzhiyun }
5396*4882a593Smuzhiyun
mwl8k_get_survey(struct ieee80211_hw * hw,int idx,struct survey_info * survey)5397*4882a593Smuzhiyun static int mwl8k_get_survey(struct ieee80211_hw *hw, int idx,
5398*4882a593Smuzhiyun struct survey_info *survey)
5399*4882a593Smuzhiyun {
5400*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
5401*4882a593Smuzhiyun struct ieee80211_conf *conf = &hw->conf;
5402*4882a593Smuzhiyun struct ieee80211_supported_band *sband;
5403*4882a593Smuzhiyun
5404*4882a593Smuzhiyun if (priv->ap_fw) {
5405*4882a593Smuzhiyun sband = hw->wiphy->bands[NL80211_BAND_2GHZ];
5406*4882a593Smuzhiyun
5407*4882a593Smuzhiyun if (sband && idx >= sband->n_channels) {
5408*4882a593Smuzhiyun idx -= sband->n_channels;
5409*4882a593Smuzhiyun sband = NULL;
5410*4882a593Smuzhiyun }
5411*4882a593Smuzhiyun
5412*4882a593Smuzhiyun if (!sband)
5413*4882a593Smuzhiyun sband = hw->wiphy->bands[NL80211_BAND_5GHZ];
5414*4882a593Smuzhiyun
5415*4882a593Smuzhiyun if (!sband || idx >= sband->n_channels)
5416*4882a593Smuzhiyun return -ENOENT;
5417*4882a593Smuzhiyun
5418*4882a593Smuzhiyun memcpy(survey, &priv->survey[idx], sizeof(*survey));
5419*4882a593Smuzhiyun survey->channel = &sband->channels[idx];
5420*4882a593Smuzhiyun
5421*4882a593Smuzhiyun return 0;
5422*4882a593Smuzhiyun }
5423*4882a593Smuzhiyun
5424*4882a593Smuzhiyun if (idx != 0)
5425*4882a593Smuzhiyun return -ENOENT;
5426*4882a593Smuzhiyun
5427*4882a593Smuzhiyun survey->channel = conf->chandef.chan;
5428*4882a593Smuzhiyun survey->filled = SURVEY_INFO_NOISE_DBM;
5429*4882a593Smuzhiyun survey->noise = priv->noise;
5430*4882a593Smuzhiyun
5431*4882a593Smuzhiyun return 0;
5432*4882a593Smuzhiyun }
5433*4882a593Smuzhiyun
5434*4882a593Smuzhiyun #define MAX_AMPDU_ATTEMPTS 5
5435*4882a593Smuzhiyun
5436*4882a593Smuzhiyun static int
mwl8k_ampdu_action(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_ampdu_params * params)5437*4882a593Smuzhiyun mwl8k_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5438*4882a593Smuzhiyun struct ieee80211_ampdu_params *params)
5439*4882a593Smuzhiyun {
5440*4882a593Smuzhiyun struct ieee80211_sta *sta = params->sta;
5441*4882a593Smuzhiyun enum ieee80211_ampdu_mlme_action action = params->action;
5442*4882a593Smuzhiyun u16 tid = params->tid;
5443*4882a593Smuzhiyun u16 *ssn = ¶ms->ssn;
5444*4882a593Smuzhiyun u8 buf_size = params->buf_size;
5445*4882a593Smuzhiyun int i, rc = 0;
5446*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
5447*4882a593Smuzhiyun struct mwl8k_ampdu_stream *stream;
5448*4882a593Smuzhiyun u8 *addr = sta->addr, idx;
5449*4882a593Smuzhiyun struct mwl8k_sta *sta_info = MWL8K_STA(sta);
5450*4882a593Smuzhiyun
5451*4882a593Smuzhiyun if (!ieee80211_hw_check(hw, AMPDU_AGGREGATION))
5452*4882a593Smuzhiyun return -ENOTSUPP;
5453*4882a593Smuzhiyun
5454*4882a593Smuzhiyun spin_lock(&priv->stream_lock);
5455*4882a593Smuzhiyun stream = mwl8k_lookup_stream(hw, addr, tid);
5456*4882a593Smuzhiyun
5457*4882a593Smuzhiyun switch (action) {
5458*4882a593Smuzhiyun case IEEE80211_AMPDU_RX_START:
5459*4882a593Smuzhiyun case IEEE80211_AMPDU_RX_STOP:
5460*4882a593Smuzhiyun break;
5461*4882a593Smuzhiyun case IEEE80211_AMPDU_TX_START:
5462*4882a593Smuzhiyun /* By the time we get here the hw queues may contain outgoing
5463*4882a593Smuzhiyun * packets for this RA/TID that are not part of this BA
5464*4882a593Smuzhiyun * session. The hw will assign sequence numbers to these
5465*4882a593Smuzhiyun * packets as they go out. So if we query the hw for its next
5466*4882a593Smuzhiyun * sequence number and use that for the SSN here, it may end up
5467*4882a593Smuzhiyun * being wrong, which will lead to sequence number mismatch at
5468*4882a593Smuzhiyun * the recipient. To avoid this, we reset the sequence number
5469*4882a593Smuzhiyun * to O for the first MPDU in this BA stream.
5470*4882a593Smuzhiyun */
5471*4882a593Smuzhiyun *ssn = 0;
5472*4882a593Smuzhiyun if (stream == NULL) {
5473*4882a593Smuzhiyun /* This means that somebody outside this driver called
5474*4882a593Smuzhiyun * ieee80211_start_tx_ba_session. This is unexpected
5475*4882a593Smuzhiyun * because we do our own rate control. Just warn and
5476*4882a593Smuzhiyun * move on.
5477*4882a593Smuzhiyun */
5478*4882a593Smuzhiyun wiphy_warn(hw->wiphy, "Unexpected call to %s. "
5479*4882a593Smuzhiyun "Proceeding anyway.\n", __func__);
5480*4882a593Smuzhiyun stream = mwl8k_add_stream(hw, sta, tid);
5481*4882a593Smuzhiyun }
5482*4882a593Smuzhiyun if (stream == NULL) {
5483*4882a593Smuzhiyun wiphy_debug(hw->wiphy, "no free AMPDU streams\n");
5484*4882a593Smuzhiyun rc = -EBUSY;
5485*4882a593Smuzhiyun break;
5486*4882a593Smuzhiyun }
5487*4882a593Smuzhiyun stream->state = AMPDU_STREAM_IN_PROGRESS;
5488*4882a593Smuzhiyun
5489*4882a593Smuzhiyun /* Release the lock before we do the time consuming stuff */
5490*4882a593Smuzhiyun spin_unlock(&priv->stream_lock);
5491*4882a593Smuzhiyun for (i = 0; i < MAX_AMPDU_ATTEMPTS; i++) {
5492*4882a593Smuzhiyun
5493*4882a593Smuzhiyun /* Check if link is still valid */
5494*4882a593Smuzhiyun if (!sta_info->is_ampdu_allowed) {
5495*4882a593Smuzhiyun spin_lock(&priv->stream_lock);
5496*4882a593Smuzhiyun mwl8k_remove_stream(hw, stream);
5497*4882a593Smuzhiyun spin_unlock(&priv->stream_lock);
5498*4882a593Smuzhiyun return -EBUSY;
5499*4882a593Smuzhiyun }
5500*4882a593Smuzhiyun
5501*4882a593Smuzhiyun rc = mwl8k_check_ba(hw, stream, vif);
5502*4882a593Smuzhiyun
5503*4882a593Smuzhiyun /* If HW restart is in progress mwl8k_post_cmd will
5504*4882a593Smuzhiyun * return -EBUSY. Avoid retrying mwl8k_check_ba in
5505*4882a593Smuzhiyun * such cases
5506*4882a593Smuzhiyun */
5507*4882a593Smuzhiyun if (!rc || rc == -EBUSY)
5508*4882a593Smuzhiyun break;
5509*4882a593Smuzhiyun /*
5510*4882a593Smuzhiyun * HW queues take time to be flushed, give them
5511*4882a593Smuzhiyun * sufficient time
5512*4882a593Smuzhiyun */
5513*4882a593Smuzhiyun
5514*4882a593Smuzhiyun msleep(1000);
5515*4882a593Smuzhiyun }
5516*4882a593Smuzhiyun spin_lock(&priv->stream_lock);
5517*4882a593Smuzhiyun if (rc) {
5518*4882a593Smuzhiyun wiphy_err(hw->wiphy, "Stream for tid %d busy after %d"
5519*4882a593Smuzhiyun " attempts\n", tid, MAX_AMPDU_ATTEMPTS);
5520*4882a593Smuzhiyun mwl8k_remove_stream(hw, stream);
5521*4882a593Smuzhiyun rc = -EBUSY;
5522*4882a593Smuzhiyun break;
5523*4882a593Smuzhiyun }
5524*4882a593Smuzhiyun rc = IEEE80211_AMPDU_TX_START_IMMEDIATE;
5525*4882a593Smuzhiyun break;
5526*4882a593Smuzhiyun case IEEE80211_AMPDU_TX_STOP_CONT:
5527*4882a593Smuzhiyun case IEEE80211_AMPDU_TX_STOP_FLUSH:
5528*4882a593Smuzhiyun case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
5529*4882a593Smuzhiyun if (stream) {
5530*4882a593Smuzhiyun if (stream->state == AMPDU_STREAM_ACTIVE) {
5531*4882a593Smuzhiyun idx = stream->idx;
5532*4882a593Smuzhiyun spin_unlock(&priv->stream_lock);
5533*4882a593Smuzhiyun mwl8k_destroy_ba(hw, idx);
5534*4882a593Smuzhiyun spin_lock(&priv->stream_lock);
5535*4882a593Smuzhiyun }
5536*4882a593Smuzhiyun mwl8k_remove_stream(hw, stream);
5537*4882a593Smuzhiyun }
5538*4882a593Smuzhiyun ieee80211_stop_tx_ba_cb_irqsafe(vif, addr, tid);
5539*4882a593Smuzhiyun break;
5540*4882a593Smuzhiyun case IEEE80211_AMPDU_TX_OPERATIONAL:
5541*4882a593Smuzhiyun BUG_ON(stream == NULL);
5542*4882a593Smuzhiyun BUG_ON(stream->state != AMPDU_STREAM_IN_PROGRESS);
5543*4882a593Smuzhiyun spin_unlock(&priv->stream_lock);
5544*4882a593Smuzhiyun rc = mwl8k_create_ba(hw, stream, buf_size, vif);
5545*4882a593Smuzhiyun spin_lock(&priv->stream_lock);
5546*4882a593Smuzhiyun if (!rc)
5547*4882a593Smuzhiyun stream->state = AMPDU_STREAM_ACTIVE;
5548*4882a593Smuzhiyun else {
5549*4882a593Smuzhiyun idx = stream->idx;
5550*4882a593Smuzhiyun spin_unlock(&priv->stream_lock);
5551*4882a593Smuzhiyun mwl8k_destroy_ba(hw, idx);
5552*4882a593Smuzhiyun spin_lock(&priv->stream_lock);
5553*4882a593Smuzhiyun wiphy_debug(hw->wiphy,
5554*4882a593Smuzhiyun "Failed adding stream for sta %pM tid %d\n",
5555*4882a593Smuzhiyun addr, tid);
5556*4882a593Smuzhiyun mwl8k_remove_stream(hw, stream);
5557*4882a593Smuzhiyun }
5558*4882a593Smuzhiyun break;
5559*4882a593Smuzhiyun
5560*4882a593Smuzhiyun default:
5561*4882a593Smuzhiyun rc = -ENOTSUPP;
5562*4882a593Smuzhiyun }
5563*4882a593Smuzhiyun
5564*4882a593Smuzhiyun spin_unlock(&priv->stream_lock);
5565*4882a593Smuzhiyun return rc;
5566*4882a593Smuzhiyun }
5567*4882a593Smuzhiyun
mwl8k_sw_scan_start(struct ieee80211_hw * hw,struct ieee80211_vif * vif,const u8 * mac_addr)5568*4882a593Smuzhiyun static void mwl8k_sw_scan_start(struct ieee80211_hw *hw,
5569*4882a593Smuzhiyun struct ieee80211_vif *vif,
5570*4882a593Smuzhiyun const u8 *mac_addr)
5571*4882a593Smuzhiyun {
5572*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
5573*4882a593Smuzhiyun u8 tmp;
5574*4882a593Smuzhiyun
5575*4882a593Smuzhiyun if (!priv->ap_fw)
5576*4882a593Smuzhiyun return;
5577*4882a593Smuzhiyun
5578*4882a593Smuzhiyun /* clear all stats */
5579*4882a593Smuzhiyun priv->channel_time = 0;
5580*4882a593Smuzhiyun ioread32(priv->regs + BBU_RXRDY_CNT_REG);
5581*4882a593Smuzhiyun ioread32(priv->regs + NOK_CCA_CNT_REG);
5582*4882a593Smuzhiyun mwl8k_cmd_bbp_reg_access(priv->hw, 0, BBU_AVG_NOISE_VAL, &tmp);
5583*4882a593Smuzhiyun
5584*4882a593Smuzhiyun priv->sw_scan_start = true;
5585*4882a593Smuzhiyun }
5586*4882a593Smuzhiyun
mwl8k_sw_scan_complete(struct ieee80211_hw * hw,struct ieee80211_vif * vif)5587*4882a593Smuzhiyun static void mwl8k_sw_scan_complete(struct ieee80211_hw *hw,
5588*4882a593Smuzhiyun struct ieee80211_vif *vif)
5589*4882a593Smuzhiyun {
5590*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
5591*4882a593Smuzhiyun u8 tmp;
5592*4882a593Smuzhiyun
5593*4882a593Smuzhiyun if (!priv->ap_fw)
5594*4882a593Smuzhiyun return;
5595*4882a593Smuzhiyun
5596*4882a593Smuzhiyun priv->sw_scan_start = false;
5597*4882a593Smuzhiyun
5598*4882a593Smuzhiyun /* clear all stats */
5599*4882a593Smuzhiyun priv->channel_time = 0;
5600*4882a593Smuzhiyun ioread32(priv->regs + BBU_RXRDY_CNT_REG);
5601*4882a593Smuzhiyun ioread32(priv->regs + NOK_CCA_CNT_REG);
5602*4882a593Smuzhiyun mwl8k_cmd_bbp_reg_access(priv->hw, 0, BBU_AVG_NOISE_VAL, &tmp);
5603*4882a593Smuzhiyun }
5604*4882a593Smuzhiyun
5605*4882a593Smuzhiyun static const struct ieee80211_ops mwl8k_ops = {
5606*4882a593Smuzhiyun .tx = mwl8k_tx,
5607*4882a593Smuzhiyun .start = mwl8k_start,
5608*4882a593Smuzhiyun .stop = mwl8k_stop,
5609*4882a593Smuzhiyun .add_interface = mwl8k_add_interface,
5610*4882a593Smuzhiyun .remove_interface = mwl8k_remove_interface,
5611*4882a593Smuzhiyun .config = mwl8k_config,
5612*4882a593Smuzhiyun .bss_info_changed = mwl8k_bss_info_changed,
5613*4882a593Smuzhiyun .prepare_multicast = mwl8k_prepare_multicast,
5614*4882a593Smuzhiyun .configure_filter = mwl8k_configure_filter,
5615*4882a593Smuzhiyun .set_key = mwl8k_set_key,
5616*4882a593Smuzhiyun .set_rts_threshold = mwl8k_set_rts_threshold,
5617*4882a593Smuzhiyun .sta_add = mwl8k_sta_add,
5618*4882a593Smuzhiyun .sta_remove = mwl8k_sta_remove,
5619*4882a593Smuzhiyun .conf_tx = mwl8k_conf_tx,
5620*4882a593Smuzhiyun .get_stats = mwl8k_get_stats,
5621*4882a593Smuzhiyun .get_survey = mwl8k_get_survey,
5622*4882a593Smuzhiyun .ampdu_action = mwl8k_ampdu_action,
5623*4882a593Smuzhiyun .sw_scan_start = mwl8k_sw_scan_start,
5624*4882a593Smuzhiyun .sw_scan_complete = mwl8k_sw_scan_complete,
5625*4882a593Smuzhiyun };
5626*4882a593Smuzhiyun
mwl8k_finalize_join_worker(struct work_struct * work)5627*4882a593Smuzhiyun static void mwl8k_finalize_join_worker(struct work_struct *work)
5628*4882a593Smuzhiyun {
5629*4882a593Smuzhiyun struct mwl8k_priv *priv =
5630*4882a593Smuzhiyun container_of(work, struct mwl8k_priv, finalize_join_worker);
5631*4882a593Smuzhiyun struct sk_buff *skb = priv->beacon_skb;
5632*4882a593Smuzhiyun struct ieee80211_mgmt *mgmt = (void *)skb->data;
5633*4882a593Smuzhiyun int len = skb->len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
5634*4882a593Smuzhiyun const u8 *tim = cfg80211_find_ie(WLAN_EID_TIM,
5635*4882a593Smuzhiyun mgmt->u.beacon.variable, len);
5636*4882a593Smuzhiyun int dtim_period = 1;
5637*4882a593Smuzhiyun
5638*4882a593Smuzhiyun if (tim && tim[1] >= 2)
5639*4882a593Smuzhiyun dtim_period = tim[3];
5640*4882a593Smuzhiyun
5641*4882a593Smuzhiyun mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len, dtim_period);
5642*4882a593Smuzhiyun
5643*4882a593Smuzhiyun dev_kfree_skb(skb);
5644*4882a593Smuzhiyun priv->beacon_skb = NULL;
5645*4882a593Smuzhiyun }
5646*4882a593Smuzhiyun
5647*4882a593Smuzhiyun enum {
5648*4882a593Smuzhiyun MWL8363 = 0,
5649*4882a593Smuzhiyun MWL8687,
5650*4882a593Smuzhiyun MWL8366,
5651*4882a593Smuzhiyun MWL8764,
5652*4882a593Smuzhiyun };
5653*4882a593Smuzhiyun
5654*4882a593Smuzhiyun #define MWL8K_8366_AP_FW_API 3
5655*4882a593Smuzhiyun #define _MWL8K_8366_AP_FW(api) "mwl8k/fmimage_8366_ap-" #api ".fw"
5656*4882a593Smuzhiyun #define MWL8K_8366_AP_FW(api) _MWL8K_8366_AP_FW(api)
5657*4882a593Smuzhiyun
5658*4882a593Smuzhiyun #define MWL8K_8764_AP_FW_API 1
5659*4882a593Smuzhiyun #define _MWL8K_8764_AP_FW(api) "mwl8k/fmimage_8764_ap-" #api ".fw"
5660*4882a593Smuzhiyun #define MWL8K_8764_AP_FW(api) _MWL8K_8764_AP_FW(api)
5661*4882a593Smuzhiyun
5662*4882a593Smuzhiyun static struct mwl8k_device_info mwl8k_info_tbl[] = {
5663*4882a593Smuzhiyun [MWL8363] = {
5664*4882a593Smuzhiyun .part_name = "88w8363",
5665*4882a593Smuzhiyun .helper_image = "mwl8k/helper_8363.fw",
5666*4882a593Smuzhiyun .fw_image_sta = "mwl8k/fmimage_8363.fw",
5667*4882a593Smuzhiyun },
5668*4882a593Smuzhiyun [MWL8687] = {
5669*4882a593Smuzhiyun .part_name = "88w8687",
5670*4882a593Smuzhiyun .helper_image = "mwl8k/helper_8687.fw",
5671*4882a593Smuzhiyun .fw_image_sta = "mwl8k/fmimage_8687.fw",
5672*4882a593Smuzhiyun },
5673*4882a593Smuzhiyun [MWL8366] = {
5674*4882a593Smuzhiyun .part_name = "88w8366",
5675*4882a593Smuzhiyun .helper_image = "mwl8k/helper_8366.fw",
5676*4882a593Smuzhiyun .fw_image_sta = "mwl8k/fmimage_8366.fw",
5677*4882a593Smuzhiyun .fw_image_ap = MWL8K_8366_AP_FW(MWL8K_8366_AP_FW_API),
5678*4882a593Smuzhiyun .fw_api_ap = MWL8K_8366_AP_FW_API,
5679*4882a593Smuzhiyun .ap_rxd_ops = &rxd_ap_ops,
5680*4882a593Smuzhiyun },
5681*4882a593Smuzhiyun [MWL8764] = {
5682*4882a593Smuzhiyun .part_name = "88w8764",
5683*4882a593Smuzhiyun .fw_image_ap = MWL8K_8764_AP_FW(MWL8K_8764_AP_FW_API),
5684*4882a593Smuzhiyun .fw_api_ap = MWL8K_8764_AP_FW_API,
5685*4882a593Smuzhiyun .ap_rxd_ops = &rxd_ap_ops,
5686*4882a593Smuzhiyun },
5687*4882a593Smuzhiyun };
5688*4882a593Smuzhiyun
5689*4882a593Smuzhiyun MODULE_FIRMWARE("mwl8k/helper_8363.fw");
5690*4882a593Smuzhiyun MODULE_FIRMWARE("mwl8k/fmimage_8363.fw");
5691*4882a593Smuzhiyun MODULE_FIRMWARE("mwl8k/helper_8687.fw");
5692*4882a593Smuzhiyun MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
5693*4882a593Smuzhiyun MODULE_FIRMWARE("mwl8k/helper_8366.fw");
5694*4882a593Smuzhiyun MODULE_FIRMWARE("mwl8k/fmimage_8366.fw");
5695*4882a593Smuzhiyun MODULE_FIRMWARE(MWL8K_8366_AP_FW(MWL8K_8366_AP_FW_API));
5696*4882a593Smuzhiyun
5697*4882a593Smuzhiyun static const struct pci_device_id mwl8k_pci_id_table[] = {
5698*4882a593Smuzhiyun { PCI_VDEVICE(MARVELL, 0x2a0a), .driver_data = MWL8363, },
5699*4882a593Smuzhiyun { PCI_VDEVICE(MARVELL, 0x2a0c), .driver_data = MWL8363, },
5700*4882a593Smuzhiyun { PCI_VDEVICE(MARVELL, 0x2a24), .driver_data = MWL8363, },
5701*4882a593Smuzhiyun { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
5702*4882a593Smuzhiyun { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
5703*4882a593Smuzhiyun { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
5704*4882a593Smuzhiyun { PCI_VDEVICE(MARVELL, 0x2a41), .driver_data = MWL8366, },
5705*4882a593Smuzhiyun { PCI_VDEVICE(MARVELL, 0x2a42), .driver_data = MWL8366, },
5706*4882a593Smuzhiyun { PCI_VDEVICE(MARVELL, 0x2a43), .driver_data = MWL8366, },
5707*4882a593Smuzhiyun { PCI_VDEVICE(MARVELL, 0x2b36), .driver_data = MWL8764, },
5708*4882a593Smuzhiyun { },
5709*4882a593Smuzhiyun };
5710*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
5711*4882a593Smuzhiyun
mwl8k_request_alt_fw(struct mwl8k_priv * priv)5712*4882a593Smuzhiyun static int mwl8k_request_alt_fw(struct mwl8k_priv *priv)
5713*4882a593Smuzhiyun {
5714*4882a593Smuzhiyun int rc;
5715*4882a593Smuzhiyun printk(KERN_ERR "%s: Error requesting preferred fw %s.\n"
5716*4882a593Smuzhiyun "Trying alternative firmware %s\n", pci_name(priv->pdev),
5717*4882a593Smuzhiyun priv->fw_pref, priv->fw_alt);
5718*4882a593Smuzhiyun rc = mwl8k_request_fw(priv, priv->fw_alt, &priv->fw_ucode, true);
5719*4882a593Smuzhiyun if (rc) {
5720*4882a593Smuzhiyun printk(KERN_ERR "%s: Error requesting alt fw %s\n",
5721*4882a593Smuzhiyun pci_name(priv->pdev), priv->fw_alt);
5722*4882a593Smuzhiyun return rc;
5723*4882a593Smuzhiyun }
5724*4882a593Smuzhiyun return 0;
5725*4882a593Smuzhiyun }
5726*4882a593Smuzhiyun
5727*4882a593Smuzhiyun static int mwl8k_firmware_load_success(struct mwl8k_priv *priv);
mwl8k_fw_state_machine(const struct firmware * fw,void * context)5728*4882a593Smuzhiyun static void mwl8k_fw_state_machine(const struct firmware *fw, void *context)
5729*4882a593Smuzhiyun {
5730*4882a593Smuzhiyun struct mwl8k_priv *priv = context;
5731*4882a593Smuzhiyun struct mwl8k_device_info *di = priv->device_info;
5732*4882a593Smuzhiyun int rc;
5733*4882a593Smuzhiyun
5734*4882a593Smuzhiyun switch (priv->fw_state) {
5735*4882a593Smuzhiyun case FW_STATE_INIT:
5736*4882a593Smuzhiyun if (!fw) {
5737*4882a593Smuzhiyun printk(KERN_ERR "%s: Error requesting helper fw %s\n",
5738*4882a593Smuzhiyun pci_name(priv->pdev), di->helper_image);
5739*4882a593Smuzhiyun goto fail;
5740*4882a593Smuzhiyun }
5741*4882a593Smuzhiyun priv->fw_helper = fw;
5742*4882a593Smuzhiyun rc = mwl8k_request_fw(priv, priv->fw_pref, &priv->fw_ucode,
5743*4882a593Smuzhiyun true);
5744*4882a593Smuzhiyun if (rc && priv->fw_alt) {
5745*4882a593Smuzhiyun rc = mwl8k_request_alt_fw(priv);
5746*4882a593Smuzhiyun if (rc)
5747*4882a593Smuzhiyun goto fail;
5748*4882a593Smuzhiyun priv->fw_state = FW_STATE_LOADING_ALT;
5749*4882a593Smuzhiyun } else if (rc)
5750*4882a593Smuzhiyun goto fail;
5751*4882a593Smuzhiyun else
5752*4882a593Smuzhiyun priv->fw_state = FW_STATE_LOADING_PREF;
5753*4882a593Smuzhiyun break;
5754*4882a593Smuzhiyun
5755*4882a593Smuzhiyun case FW_STATE_LOADING_PREF:
5756*4882a593Smuzhiyun if (!fw) {
5757*4882a593Smuzhiyun if (priv->fw_alt) {
5758*4882a593Smuzhiyun rc = mwl8k_request_alt_fw(priv);
5759*4882a593Smuzhiyun if (rc)
5760*4882a593Smuzhiyun goto fail;
5761*4882a593Smuzhiyun priv->fw_state = FW_STATE_LOADING_ALT;
5762*4882a593Smuzhiyun } else
5763*4882a593Smuzhiyun goto fail;
5764*4882a593Smuzhiyun } else {
5765*4882a593Smuzhiyun priv->fw_ucode = fw;
5766*4882a593Smuzhiyun rc = mwl8k_firmware_load_success(priv);
5767*4882a593Smuzhiyun if (rc)
5768*4882a593Smuzhiyun goto fail;
5769*4882a593Smuzhiyun else
5770*4882a593Smuzhiyun complete(&priv->firmware_loading_complete);
5771*4882a593Smuzhiyun }
5772*4882a593Smuzhiyun break;
5773*4882a593Smuzhiyun
5774*4882a593Smuzhiyun case FW_STATE_LOADING_ALT:
5775*4882a593Smuzhiyun if (!fw) {
5776*4882a593Smuzhiyun printk(KERN_ERR "%s: Error requesting alt fw %s\n",
5777*4882a593Smuzhiyun pci_name(priv->pdev), di->helper_image);
5778*4882a593Smuzhiyun goto fail;
5779*4882a593Smuzhiyun }
5780*4882a593Smuzhiyun priv->fw_ucode = fw;
5781*4882a593Smuzhiyun rc = mwl8k_firmware_load_success(priv);
5782*4882a593Smuzhiyun if (rc)
5783*4882a593Smuzhiyun goto fail;
5784*4882a593Smuzhiyun else
5785*4882a593Smuzhiyun complete(&priv->firmware_loading_complete);
5786*4882a593Smuzhiyun break;
5787*4882a593Smuzhiyun
5788*4882a593Smuzhiyun default:
5789*4882a593Smuzhiyun printk(KERN_ERR "%s: Unexpected firmware loading state: %d\n",
5790*4882a593Smuzhiyun MWL8K_NAME, priv->fw_state);
5791*4882a593Smuzhiyun BUG_ON(1);
5792*4882a593Smuzhiyun }
5793*4882a593Smuzhiyun
5794*4882a593Smuzhiyun return;
5795*4882a593Smuzhiyun
5796*4882a593Smuzhiyun fail:
5797*4882a593Smuzhiyun priv->fw_state = FW_STATE_ERROR;
5798*4882a593Smuzhiyun complete(&priv->firmware_loading_complete);
5799*4882a593Smuzhiyun mwl8k_release_firmware(priv);
5800*4882a593Smuzhiyun device_release_driver(&priv->pdev->dev);
5801*4882a593Smuzhiyun }
5802*4882a593Smuzhiyun
5803*4882a593Smuzhiyun #define MAX_RESTART_ATTEMPTS 1
mwl8k_init_firmware(struct ieee80211_hw * hw,char * fw_image,bool nowait)5804*4882a593Smuzhiyun static int mwl8k_init_firmware(struct ieee80211_hw *hw, char *fw_image,
5805*4882a593Smuzhiyun bool nowait)
5806*4882a593Smuzhiyun {
5807*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
5808*4882a593Smuzhiyun int rc;
5809*4882a593Smuzhiyun int count = MAX_RESTART_ATTEMPTS;
5810*4882a593Smuzhiyun
5811*4882a593Smuzhiyun retry:
5812*4882a593Smuzhiyun /* Reset firmware and hardware */
5813*4882a593Smuzhiyun mwl8k_hw_reset(priv);
5814*4882a593Smuzhiyun
5815*4882a593Smuzhiyun /* Ask userland hotplug daemon for the device firmware */
5816*4882a593Smuzhiyun rc = mwl8k_request_firmware(priv, fw_image, nowait);
5817*4882a593Smuzhiyun if (rc) {
5818*4882a593Smuzhiyun wiphy_err(hw->wiphy, "Firmware files not found\n");
5819*4882a593Smuzhiyun return rc;
5820*4882a593Smuzhiyun }
5821*4882a593Smuzhiyun
5822*4882a593Smuzhiyun if (nowait)
5823*4882a593Smuzhiyun return rc;
5824*4882a593Smuzhiyun
5825*4882a593Smuzhiyun /* Load firmware into hardware */
5826*4882a593Smuzhiyun rc = mwl8k_load_firmware(hw);
5827*4882a593Smuzhiyun if (rc)
5828*4882a593Smuzhiyun wiphy_err(hw->wiphy, "Cannot start firmware\n");
5829*4882a593Smuzhiyun
5830*4882a593Smuzhiyun /* Reclaim memory once firmware is successfully loaded */
5831*4882a593Smuzhiyun mwl8k_release_firmware(priv);
5832*4882a593Smuzhiyun
5833*4882a593Smuzhiyun if (rc && count) {
5834*4882a593Smuzhiyun /* FW did not start successfully;
5835*4882a593Smuzhiyun * lets try one more time
5836*4882a593Smuzhiyun */
5837*4882a593Smuzhiyun count--;
5838*4882a593Smuzhiyun wiphy_err(hw->wiphy, "Trying to reload the firmware again\n");
5839*4882a593Smuzhiyun msleep(20);
5840*4882a593Smuzhiyun goto retry;
5841*4882a593Smuzhiyun }
5842*4882a593Smuzhiyun
5843*4882a593Smuzhiyun return rc;
5844*4882a593Smuzhiyun }
5845*4882a593Smuzhiyun
mwl8k_init_txqs(struct ieee80211_hw * hw)5846*4882a593Smuzhiyun static int mwl8k_init_txqs(struct ieee80211_hw *hw)
5847*4882a593Smuzhiyun {
5848*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
5849*4882a593Smuzhiyun int rc = 0;
5850*4882a593Smuzhiyun int i;
5851*4882a593Smuzhiyun
5852*4882a593Smuzhiyun for (i = 0; i < mwl8k_tx_queues(priv); i++) {
5853*4882a593Smuzhiyun rc = mwl8k_txq_init(hw, i);
5854*4882a593Smuzhiyun if (rc)
5855*4882a593Smuzhiyun break;
5856*4882a593Smuzhiyun if (priv->ap_fw)
5857*4882a593Smuzhiyun iowrite32(priv->txq[i].txd_dma,
5858*4882a593Smuzhiyun priv->sram + priv->txq_offset[i]);
5859*4882a593Smuzhiyun }
5860*4882a593Smuzhiyun return rc;
5861*4882a593Smuzhiyun }
5862*4882a593Smuzhiyun
5863*4882a593Smuzhiyun /* initialize hw after successfully loading a firmware image */
mwl8k_probe_hw(struct ieee80211_hw * hw)5864*4882a593Smuzhiyun static int mwl8k_probe_hw(struct ieee80211_hw *hw)
5865*4882a593Smuzhiyun {
5866*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
5867*4882a593Smuzhiyun int rc = 0;
5868*4882a593Smuzhiyun int i;
5869*4882a593Smuzhiyun
5870*4882a593Smuzhiyun if (priv->ap_fw) {
5871*4882a593Smuzhiyun priv->rxd_ops = priv->device_info->ap_rxd_ops;
5872*4882a593Smuzhiyun if (priv->rxd_ops == NULL) {
5873*4882a593Smuzhiyun wiphy_err(hw->wiphy,
5874*4882a593Smuzhiyun "Driver does not have AP firmware image support for this hardware\n");
5875*4882a593Smuzhiyun rc = -ENOENT;
5876*4882a593Smuzhiyun goto err_stop_firmware;
5877*4882a593Smuzhiyun }
5878*4882a593Smuzhiyun } else {
5879*4882a593Smuzhiyun priv->rxd_ops = &rxd_sta_ops;
5880*4882a593Smuzhiyun }
5881*4882a593Smuzhiyun
5882*4882a593Smuzhiyun priv->sniffer_enabled = false;
5883*4882a593Smuzhiyun priv->wmm_enabled = false;
5884*4882a593Smuzhiyun priv->pending_tx_pkts = 0;
5885*4882a593Smuzhiyun atomic_set(&priv->watchdog_event_pending, 0);
5886*4882a593Smuzhiyun
5887*4882a593Smuzhiyun rc = mwl8k_rxq_init(hw, 0);
5888*4882a593Smuzhiyun if (rc)
5889*4882a593Smuzhiyun goto err_stop_firmware;
5890*4882a593Smuzhiyun rxq_refill(hw, 0, INT_MAX);
5891*4882a593Smuzhiyun
5892*4882a593Smuzhiyun /* For the sta firmware, we need to know the dma addresses of tx queues
5893*4882a593Smuzhiyun * before sending MWL8K_CMD_GET_HW_SPEC. So we must initialize them
5894*4882a593Smuzhiyun * prior to issuing this command. But for the AP case, we learn the
5895*4882a593Smuzhiyun * total number of queues from the result CMD_GET_HW_SPEC, so for this
5896*4882a593Smuzhiyun * case we must initialize the tx queues after.
5897*4882a593Smuzhiyun */
5898*4882a593Smuzhiyun priv->num_ampdu_queues = 0;
5899*4882a593Smuzhiyun if (!priv->ap_fw) {
5900*4882a593Smuzhiyun rc = mwl8k_init_txqs(hw);
5901*4882a593Smuzhiyun if (rc)
5902*4882a593Smuzhiyun goto err_free_queues;
5903*4882a593Smuzhiyun }
5904*4882a593Smuzhiyun
5905*4882a593Smuzhiyun iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
5906*4882a593Smuzhiyun iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
5907*4882a593Smuzhiyun iowrite32(MWL8K_A2H_INT_TX_DONE|MWL8K_A2H_INT_RX_READY|
5908*4882a593Smuzhiyun MWL8K_A2H_INT_BA_WATCHDOG,
5909*4882a593Smuzhiyun priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
5910*4882a593Smuzhiyun iowrite32(MWL8K_A2H_INT_OPC_DONE,
5911*4882a593Smuzhiyun priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
5912*4882a593Smuzhiyun
5913*4882a593Smuzhiyun rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
5914*4882a593Smuzhiyun IRQF_SHARED, MWL8K_NAME, hw);
5915*4882a593Smuzhiyun if (rc) {
5916*4882a593Smuzhiyun wiphy_err(hw->wiphy, "failed to register IRQ handler\n");
5917*4882a593Smuzhiyun goto err_free_queues;
5918*4882a593Smuzhiyun }
5919*4882a593Smuzhiyun
5920*4882a593Smuzhiyun /*
5921*4882a593Smuzhiyun * When hw restart is requested,
5922*4882a593Smuzhiyun * mac80211 will take care of clearing
5923*4882a593Smuzhiyun * the ampdu streams, so do not clear
5924*4882a593Smuzhiyun * the ampdu state here
5925*4882a593Smuzhiyun */
5926*4882a593Smuzhiyun if (!priv->hw_restart_in_progress)
5927*4882a593Smuzhiyun memset(priv->ampdu, 0, sizeof(priv->ampdu));
5928*4882a593Smuzhiyun
5929*4882a593Smuzhiyun /*
5930*4882a593Smuzhiyun * Temporarily enable interrupts. Initial firmware host
5931*4882a593Smuzhiyun * commands use interrupts and avoid polling. Disable
5932*4882a593Smuzhiyun * interrupts when done.
5933*4882a593Smuzhiyun */
5934*4882a593Smuzhiyun iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
5935*4882a593Smuzhiyun
5936*4882a593Smuzhiyun /* Get config data, mac addrs etc */
5937*4882a593Smuzhiyun if (priv->ap_fw) {
5938*4882a593Smuzhiyun rc = mwl8k_cmd_get_hw_spec_ap(hw);
5939*4882a593Smuzhiyun if (!rc)
5940*4882a593Smuzhiyun rc = mwl8k_init_txqs(hw);
5941*4882a593Smuzhiyun if (!rc)
5942*4882a593Smuzhiyun rc = mwl8k_cmd_set_hw_spec(hw);
5943*4882a593Smuzhiyun } else {
5944*4882a593Smuzhiyun rc = mwl8k_cmd_get_hw_spec_sta(hw);
5945*4882a593Smuzhiyun }
5946*4882a593Smuzhiyun if (rc) {
5947*4882a593Smuzhiyun wiphy_err(hw->wiphy, "Cannot initialise firmware\n");
5948*4882a593Smuzhiyun goto err_free_irq;
5949*4882a593Smuzhiyun }
5950*4882a593Smuzhiyun
5951*4882a593Smuzhiyun /* Turn radio off */
5952*4882a593Smuzhiyun rc = mwl8k_cmd_radio_disable(hw);
5953*4882a593Smuzhiyun if (rc) {
5954*4882a593Smuzhiyun wiphy_err(hw->wiphy, "Cannot disable\n");
5955*4882a593Smuzhiyun goto err_free_irq;
5956*4882a593Smuzhiyun }
5957*4882a593Smuzhiyun
5958*4882a593Smuzhiyun /* Clear MAC address */
5959*4882a593Smuzhiyun rc = mwl8k_cmd_set_mac_addr(hw, NULL, "\x00\x00\x00\x00\x00\x00");
5960*4882a593Smuzhiyun if (rc) {
5961*4882a593Smuzhiyun wiphy_err(hw->wiphy, "Cannot clear MAC address\n");
5962*4882a593Smuzhiyun goto err_free_irq;
5963*4882a593Smuzhiyun }
5964*4882a593Smuzhiyun
5965*4882a593Smuzhiyun /* Configure Antennas */
5966*4882a593Smuzhiyun rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x3);
5967*4882a593Smuzhiyun if (rc)
5968*4882a593Smuzhiyun wiphy_warn(hw->wiphy, "failed to set # of RX antennas");
5969*4882a593Smuzhiyun rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
5970*4882a593Smuzhiyun if (rc)
5971*4882a593Smuzhiyun wiphy_warn(hw->wiphy, "failed to set # of TX antennas");
5972*4882a593Smuzhiyun
5973*4882a593Smuzhiyun
5974*4882a593Smuzhiyun /* Disable interrupts */
5975*4882a593Smuzhiyun iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
5976*4882a593Smuzhiyun free_irq(priv->pdev->irq, hw);
5977*4882a593Smuzhiyun
5978*4882a593Smuzhiyun wiphy_info(hw->wiphy, "%s v%d, %pm, %s firmware %u.%u.%u.%u\n",
5979*4882a593Smuzhiyun priv->device_info->part_name,
5980*4882a593Smuzhiyun priv->hw_rev, hw->wiphy->perm_addr,
5981*4882a593Smuzhiyun priv->ap_fw ? "AP" : "STA",
5982*4882a593Smuzhiyun (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
5983*4882a593Smuzhiyun (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
5984*4882a593Smuzhiyun
5985*4882a593Smuzhiyun return 0;
5986*4882a593Smuzhiyun
5987*4882a593Smuzhiyun err_free_irq:
5988*4882a593Smuzhiyun iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
5989*4882a593Smuzhiyun free_irq(priv->pdev->irq, hw);
5990*4882a593Smuzhiyun
5991*4882a593Smuzhiyun err_free_queues:
5992*4882a593Smuzhiyun for (i = 0; i < mwl8k_tx_queues(priv); i++)
5993*4882a593Smuzhiyun mwl8k_txq_deinit(hw, i);
5994*4882a593Smuzhiyun mwl8k_rxq_deinit(hw, 0);
5995*4882a593Smuzhiyun
5996*4882a593Smuzhiyun err_stop_firmware:
5997*4882a593Smuzhiyun mwl8k_hw_reset(priv);
5998*4882a593Smuzhiyun
5999*4882a593Smuzhiyun return rc;
6000*4882a593Smuzhiyun }
6001*4882a593Smuzhiyun
6002*4882a593Smuzhiyun /*
6003*4882a593Smuzhiyun * invoke mwl8k_reload_firmware to change the firmware image after the device
6004*4882a593Smuzhiyun * has already been registered
6005*4882a593Smuzhiyun */
mwl8k_reload_firmware(struct ieee80211_hw * hw,char * fw_image)6006*4882a593Smuzhiyun static int mwl8k_reload_firmware(struct ieee80211_hw *hw, char *fw_image)
6007*4882a593Smuzhiyun {
6008*4882a593Smuzhiyun int i, rc = 0;
6009*4882a593Smuzhiyun struct mwl8k_priv *priv = hw->priv;
6010*4882a593Smuzhiyun struct mwl8k_vif *vif, *tmp_vif;
6011*4882a593Smuzhiyun
6012*4882a593Smuzhiyun mwl8k_stop(hw);
6013*4882a593Smuzhiyun mwl8k_rxq_deinit(hw, 0);
6014*4882a593Smuzhiyun
6015*4882a593Smuzhiyun /*
6016*4882a593Smuzhiyun * All the existing interfaces are re-added by the ieee80211_reconfig;
6017*4882a593Smuzhiyun * which means driver should remove existing interfaces before calling
6018*4882a593Smuzhiyun * ieee80211_restart_hw
6019*4882a593Smuzhiyun */
6020*4882a593Smuzhiyun if (priv->hw_restart_in_progress)
6021*4882a593Smuzhiyun list_for_each_entry_safe(vif, tmp_vif, &priv->vif_list, list)
6022*4882a593Smuzhiyun mwl8k_remove_vif(priv, vif);
6023*4882a593Smuzhiyun
6024*4882a593Smuzhiyun for (i = 0; i < mwl8k_tx_queues(priv); i++)
6025*4882a593Smuzhiyun mwl8k_txq_deinit(hw, i);
6026*4882a593Smuzhiyun
6027*4882a593Smuzhiyun rc = mwl8k_init_firmware(hw, fw_image, false);
6028*4882a593Smuzhiyun if (rc)
6029*4882a593Smuzhiyun goto fail;
6030*4882a593Smuzhiyun
6031*4882a593Smuzhiyun rc = mwl8k_probe_hw(hw);
6032*4882a593Smuzhiyun if (rc)
6033*4882a593Smuzhiyun goto fail;
6034*4882a593Smuzhiyun
6035*4882a593Smuzhiyun if (priv->hw_restart_in_progress)
6036*4882a593Smuzhiyun return rc;
6037*4882a593Smuzhiyun
6038*4882a593Smuzhiyun rc = mwl8k_start(hw);
6039*4882a593Smuzhiyun if (rc)
6040*4882a593Smuzhiyun goto fail;
6041*4882a593Smuzhiyun
6042*4882a593Smuzhiyun rc = mwl8k_config(hw, ~0);
6043*4882a593Smuzhiyun if (rc)
6044*4882a593Smuzhiyun goto fail;
6045*4882a593Smuzhiyun
6046*4882a593Smuzhiyun for (i = 0; i < MWL8K_TX_WMM_QUEUES; i++) {
6047*4882a593Smuzhiyun rc = mwl8k_conf_tx(hw, NULL, i, &priv->wmm_params[i]);
6048*4882a593Smuzhiyun if (rc)
6049*4882a593Smuzhiyun goto fail;
6050*4882a593Smuzhiyun }
6051*4882a593Smuzhiyun
6052*4882a593Smuzhiyun return rc;
6053*4882a593Smuzhiyun
6054*4882a593Smuzhiyun fail:
6055*4882a593Smuzhiyun printk(KERN_WARNING "mwl8k: Failed to reload firmware image.\n");
6056*4882a593Smuzhiyun return rc;
6057*4882a593Smuzhiyun }
6058*4882a593Smuzhiyun
6059*4882a593Smuzhiyun static const struct ieee80211_iface_limit ap_if_limits[] = {
6060*4882a593Smuzhiyun { .max = 8, .types = BIT(NL80211_IFTYPE_AP) },
6061*4882a593Smuzhiyun { .max = 1, .types = BIT(NL80211_IFTYPE_STATION) },
6062*4882a593Smuzhiyun };
6063*4882a593Smuzhiyun
6064*4882a593Smuzhiyun static const struct ieee80211_iface_combination ap_if_comb = {
6065*4882a593Smuzhiyun .limits = ap_if_limits,
6066*4882a593Smuzhiyun .n_limits = ARRAY_SIZE(ap_if_limits),
6067*4882a593Smuzhiyun .max_interfaces = 8,
6068*4882a593Smuzhiyun .num_different_channels = 1,
6069*4882a593Smuzhiyun };
6070*4882a593Smuzhiyun
6071*4882a593Smuzhiyun
mwl8k_firmware_load_success(struct mwl8k_priv * priv)6072*4882a593Smuzhiyun static int mwl8k_firmware_load_success(struct mwl8k_priv *priv)
6073*4882a593Smuzhiyun {
6074*4882a593Smuzhiyun struct ieee80211_hw *hw = priv->hw;
6075*4882a593Smuzhiyun int i, rc;
6076*4882a593Smuzhiyun
6077*4882a593Smuzhiyun rc = mwl8k_load_firmware(hw);
6078*4882a593Smuzhiyun mwl8k_release_firmware(priv);
6079*4882a593Smuzhiyun if (rc) {
6080*4882a593Smuzhiyun wiphy_err(hw->wiphy, "Cannot start firmware\n");
6081*4882a593Smuzhiyun return rc;
6082*4882a593Smuzhiyun }
6083*4882a593Smuzhiyun
6084*4882a593Smuzhiyun /*
6085*4882a593Smuzhiyun * Extra headroom is the size of the required DMA header
6086*4882a593Smuzhiyun * minus the size of the smallest 802.11 frame (CTS frame).
6087*4882a593Smuzhiyun */
6088*4882a593Smuzhiyun hw->extra_tx_headroom =
6089*4882a593Smuzhiyun sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
6090*4882a593Smuzhiyun
6091*4882a593Smuzhiyun hw->extra_tx_headroom -= priv->ap_fw ? REDUCED_TX_HEADROOM : 0;
6092*4882a593Smuzhiyun
6093*4882a593Smuzhiyun hw->queues = MWL8K_TX_WMM_QUEUES;
6094*4882a593Smuzhiyun
6095*4882a593Smuzhiyun /* Set rssi values to dBm */
6096*4882a593Smuzhiyun ieee80211_hw_set(hw, SIGNAL_DBM);
6097*4882a593Smuzhiyun ieee80211_hw_set(hw, HAS_RATE_CONTROL);
6098*4882a593Smuzhiyun
6099*4882a593Smuzhiyun /*
6100*4882a593Smuzhiyun * Ask mac80211 to not to trigger PS mode
6101*4882a593Smuzhiyun * based on PM bit of incoming frames.
6102*4882a593Smuzhiyun */
6103*4882a593Smuzhiyun if (priv->ap_fw)
6104*4882a593Smuzhiyun ieee80211_hw_set(hw, AP_LINK_PS);
6105*4882a593Smuzhiyun
6106*4882a593Smuzhiyun hw->vif_data_size = sizeof(struct mwl8k_vif);
6107*4882a593Smuzhiyun hw->sta_data_size = sizeof(struct mwl8k_sta);
6108*4882a593Smuzhiyun
6109*4882a593Smuzhiyun priv->macids_used = 0;
6110*4882a593Smuzhiyun INIT_LIST_HEAD(&priv->vif_list);
6111*4882a593Smuzhiyun
6112*4882a593Smuzhiyun /* Set default radio state and preamble */
6113*4882a593Smuzhiyun priv->radio_on = false;
6114*4882a593Smuzhiyun priv->radio_short_preamble = false;
6115*4882a593Smuzhiyun
6116*4882a593Smuzhiyun /* Finalize join worker */
6117*4882a593Smuzhiyun INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
6118*4882a593Smuzhiyun /* Handle watchdog ba events */
6119*4882a593Smuzhiyun INIT_WORK(&priv->watchdog_ba_handle, mwl8k_watchdog_ba_events);
6120*4882a593Smuzhiyun /* To reload the firmware if it crashes */
6121*4882a593Smuzhiyun INIT_WORK(&priv->fw_reload, mwl8k_hw_restart_work);
6122*4882a593Smuzhiyun
6123*4882a593Smuzhiyun /* TX reclaim and RX tasklets. */
6124*4882a593Smuzhiyun tasklet_setup(&priv->poll_tx_task, mwl8k_tx_poll);
6125*4882a593Smuzhiyun tasklet_disable(&priv->poll_tx_task);
6126*4882a593Smuzhiyun tasklet_setup(&priv->poll_rx_task, mwl8k_rx_poll);
6127*4882a593Smuzhiyun tasklet_disable(&priv->poll_rx_task);
6128*4882a593Smuzhiyun
6129*4882a593Smuzhiyun /* Power management cookie */
6130*4882a593Smuzhiyun priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
6131*4882a593Smuzhiyun if (priv->cookie == NULL)
6132*4882a593Smuzhiyun return -ENOMEM;
6133*4882a593Smuzhiyun
6134*4882a593Smuzhiyun mutex_init(&priv->fw_mutex);
6135*4882a593Smuzhiyun priv->fw_mutex_owner = NULL;
6136*4882a593Smuzhiyun priv->fw_mutex_depth = 0;
6137*4882a593Smuzhiyun priv->hostcmd_wait = NULL;
6138*4882a593Smuzhiyun
6139*4882a593Smuzhiyun spin_lock_init(&priv->tx_lock);
6140*4882a593Smuzhiyun
6141*4882a593Smuzhiyun spin_lock_init(&priv->stream_lock);
6142*4882a593Smuzhiyun
6143*4882a593Smuzhiyun priv->tx_wait = NULL;
6144*4882a593Smuzhiyun
6145*4882a593Smuzhiyun rc = mwl8k_probe_hw(hw);
6146*4882a593Smuzhiyun if (rc)
6147*4882a593Smuzhiyun goto err_free_cookie;
6148*4882a593Smuzhiyun
6149*4882a593Smuzhiyun hw->wiphy->interface_modes = 0;
6150*4882a593Smuzhiyun
6151*4882a593Smuzhiyun if (priv->ap_macids_supported || priv->device_info->fw_image_ap) {
6152*4882a593Smuzhiyun hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP);
6153*4882a593Smuzhiyun hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_STATION);
6154*4882a593Smuzhiyun hw->wiphy->iface_combinations = &ap_if_comb;
6155*4882a593Smuzhiyun hw->wiphy->n_iface_combinations = 1;
6156*4882a593Smuzhiyun }
6157*4882a593Smuzhiyun
6158*4882a593Smuzhiyun if (priv->sta_macids_supported || priv->device_info->fw_image_sta)
6159*4882a593Smuzhiyun hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_STATION);
6160*4882a593Smuzhiyun
6161*4882a593Smuzhiyun wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
6162*4882a593Smuzhiyun
6163*4882a593Smuzhiyun rc = ieee80211_register_hw(hw);
6164*4882a593Smuzhiyun if (rc) {
6165*4882a593Smuzhiyun wiphy_err(hw->wiphy, "Cannot register device\n");
6166*4882a593Smuzhiyun goto err_unprobe_hw;
6167*4882a593Smuzhiyun }
6168*4882a593Smuzhiyun
6169*4882a593Smuzhiyun return 0;
6170*4882a593Smuzhiyun
6171*4882a593Smuzhiyun err_unprobe_hw:
6172*4882a593Smuzhiyun for (i = 0; i < mwl8k_tx_queues(priv); i++)
6173*4882a593Smuzhiyun mwl8k_txq_deinit(hw, i);
6174*4882a593Smuzhiyun mwl8k_rxq_deinit(hw, 0);
6175*4882a593Smuzhiyun
6176*4882a593Smuzhiyun err_free_cookie:
6177*4882a593Smuzhiyun if (priv->cookie != NULL)
6178*4882a593Smuzhiyun pci_free_consistent(priv->pdev, 4,
6179*4882a593Smuzhiyun priv->cookie, priv->cookie_dma);
6180*4882a593Smuzhiyun
6181*4882a593Smuzhiyun return rc;
6182*4882a593Smuzhiyun }
mwl8k_probe(struct pci_dev * pdev,const struct pci_device_id * id)6183*4882a593Smuzhiyun static int mwl8k_probe(struct pci_dev *pdev,
6184*4882a593Smuzhiyun const struct pci_device_id *id)
6185*4882a593Smuzhiyun {
6186*4882a593Smuzhiyun static int printed_version;
6187*4882a593Smuzhiyun struct ieee80211_hw *hw;
6188*4882a593Smuzhiyun struct mwl8k_priv *priv;
6189*4882a593Smuzhiyun struct mwl8k_device_info *di;
6190*4882a593Smuzhiyun int rc;
6191*4882a593Smuzhiyun
6192*4882a593Smuzhiyun if (!printed_version) {
6193*4882a593Smuzhiyun printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
6194*4882a593Smuzhiyun printed_version = 1;
6195*4882a593Smuzhiyun }
6196*4882a593Smuzhiyun
6197*4882a593Smuzhiyun
6198*4882a593Smuzhiyun rc = pci_enable_device(pdev);
6199*4882a593Smuzhiyun if (rc) {
6200*4882a593Smuzhiyun printk(KERN_ERR "%s: Cannot enable new PCI device\n",
6201*4882a593Smuzhiyun MWL8K_NAME);
6202*4882a593Smuzhiyun return rc;
6203*4882a593Smuzhiyun }
6204*4882a593Smuzhiyun
6205*4882a593Smuzhiyun rc = pci_request_regions(pdev, MWL8K_NAME);
6206*4882a593Smuzhiyun if (rc) {
6207*4882a593Smuzhiyun printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
6208*4882a593Smuzhiyun MWL8K_NAME);
6209*4882a593Smuzhiyun goto err_disable_device;
6210*4882a593Smuzhiyun }
6211*4882a593Smuzhiyun
6212*4882a593Smuzhiyun pci_set_master(pdev);
6213*4882a593Smuzhiyun
6214*4882a593Smuzhiyun
6215*4882a593Smuzhiyun hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
6216*4882a593Smuzhiyun if (hw == NULL) {
6217*4882a593Smuzhiyun printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
6218*4882a593Smuzhiyun rc = -ENOMEM;
6219*4882a593Smuzhiyun goto err_free_reg;
6220*4882a593Smuzhiyun }
6221*4882a593Smuzhiyun
6222*4882a593Smuzhiyun SET_IEEE80211_DEV(hw, &pdev->dev);
6223*4882a593Smuzhiyun pci_set_drvdata(pdev, hw);
6224*4882a593Smuzhiyun
6225*4882a593Smuzhiyun priv = hw->priv;
6226*4882a593Smuzhiyun priv->hw = hw;
6227*4882a593Smuzhiyun priv->pdev = pdev;
6228*4882a593Smuzhiyun priv->device_info = &mwl8k_info_tbl[id->driver_data];
6229*4882a593Smuzhiyun
6230*4882a593Smuzhiyun if (id->driver_data == MWL8764)
6231*4882a593Smuzhiyun priv->is_8764 = true;
6232*4882a593Smuzhiyun
6233*4882a593Smuzhiyun priv->sram = pci_iomap(pdev, 0, 0x10000);
6234*4882a593Smuzhiyun if (priv->sram == NULL) {
6235*4882a593Smuzhiyun wiphy_err(hw->wiphy, "Cannot map device SRAM\n");
6236*4882a593Smuzhiyun rc = -EIO;
6237*4882a593Smuzhiyun goto err_iounmap;
6238*4882a593Smuzhiyun }
6239*4882a593Smuzhiyun
6240*4882a593Smuzhiyun /*
6241*4882a593Smuzhiyun * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
6242*4882a593Smuzhiyun * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
6243*4882a593Smuzhiyun */
6244*4882a593Smuzhiyun priv->regs = pci_iomap(pdev, 1, 0x10000);
6245*4882a593Smuzhiyun if (priv->regs == NULL) {
6246*4882a593Smuzhiyun priv->regs = pci_iomap(pdev, 2, 0x10000);
6247*4882a593Smuzhiyun if (priv->regs == NULL) {
6248*4882a593Smuzhiyun wiphy_err(hw->wiphy, "Cannot map device registers\n");
6249*4882a593Smuzhiyun rc = -EIO;
6250*4882a593Smuzhiyun goto err_iounmap;
6251*4882a593Smuzhiyun }
6252*4882a593Smuzhiyun }
6253*4882a593Smuzhiyun
6254*4882a593Smuzhiyun /*
6255*4882a593Smuzhiyun * Choose the initial fw image depending on user input. If a second
6256*4882a593Smuzhiyun * image is available, make it the alternative image that will be
6257*4882a593Smuzhiyun * loaded if the first one fails.
6258*4882a593Smuzhiyun */
6259*4882a593Smuzhiyun init_completion(&priv->firmware_loading_complete);
6260*4882a593Smuzhiyun di = priv->device_info;
6261*4882a593Smuzhiyun if (ap_mode_default && di->fw_image_ap) {
6262*4882a593Smuzhiyun priv->fw_pref = di->fw_image_ap;
6263*4882a593Smuzhiyun priv->fw_alt = di->fw_image_sta;
6264*4882a593Smuzhiyun } else if (!ap_mode_default && di->fw_image_sta) {
6265*4882a593Smuzhiyun priv->fw_pref = di->fw_image_sta;
6266*4882a593Smuzhiyun priv->fw_alt = di->fw_image_ap;
6267*4882a593Smuzhiyun } else if (ap_mode_default && !di->fw_image_ap && di->fw_image_sta) {
6268*4882a593Smuzhiyun printk(KERN_WARNING "AP fw is unavailable. Using STA fw.");
6269*4882a593Smuzhiyun priv->fw_pref = di->fw_image_sta;
6270*4882a593Smuzhiyun } else if (!ap_mode_default && !di->fw_image_sta && di->fw_image_ap) {
6271*4882a593Smuzhiyun printk(KERN_WARNING "STA fw is unavailable. Using AP fw.");
6272*4882a593Smuzhiyun priv->fw_pref = di->fw_image_ap;
6273*4882a593Smuzhiyun }
6274*4882a593Smuzhiyun rc = mwl8k_init_firmware(hw, priv->fw_pref, true);
6275*4882a593Smuzhiyun if (rc)
6276*4882a593Smuzhiyun goto err_stop_firmware;
6277*4882a593Smuzhiyun
6278*4882a593Smuzhiyun priv->hw_restart_in_progress = false;
6279*4882a593Smuzhiyun
6280*4882a593Smuzhiyun priv->running_bsses = 0;
6281*4882a593Smuzhiyun
6282*4882a593Smuzhiyun return rc;
6283*4882a593Smuzhiyun
6284*4882a593Smuzhiyun err_stop_firmware:
6285*4882a593Smuzhiyun mwl8k_hw_reset(priv);
6286*4882a593Smuzhiyun
6287*4882a593Smuzhiyun err_iounmap:
6288*4882a593Smuzhiyun if (priv->regs != NULL)
6289*4882a593Smuzhiyun pci_iounmap(pdev, priv->regs);
6290*4882a593Smuzhiyun
6291*4882a593Smuzhiyun if (priv->sram != NULL)
6292*4882a593Smuzhiyun pci_iounmap(pdev, priv->sram);
6293*4882a593Smuzhiyun
6294*4882a593Smuzhiyun ieee80211_free_hw(hw);
6295*4882a593Smuzhiyun
6296*4882a593Smuzhiyun err_free_reg:
6297*4882a593Smuzhiyun pci_release_regions(pdev);
6298*4882a593Smuzhiyun
6299*4882a593Smuzhiyun err_disable_device:
6300*4882a593Smuzhiyun pci_disable_device(pdev);
6301*4882a593Smuzhiyun
6302*4882a593Smuzhiyun return rc;
6303*4882a593Smuzhiyun }
6304*4882a593Smuzhiyun
mwl8k_remove(struct pci_dev * pdev)6305*4882a593Smuzhiyun static void mwl8k_remove(struct pci_dev *pdev)
6306*4882a593Smuzhiyun {
6307*4882a593Smuzhiyun struct ieee80211_hw *hw = pci_get_drvdata(pdev);
6308*4882a593Smuzhiyun struct mwl8k_priv *priv;
6309*4882a593Smuzhiyun int i;
6310*4882a593Smuzhiyun
6311*4882a593Smuzhiyun if (hw == NULL)
6312*4882a593Smuzhiyun return;
6313*4882a593Smuzhiyun priv = hw->priv;
6314*4882a593Smuzhiyun
6315*4882a593Smuzhiyun wait_for_completion(&priv->firmware_loading_complete);
6316*4882a593Smuzhiyun
6317*4882a593Smuzhiyun if (priv->fw_state == FW_STATE_ERROR) {
6318*4882a593Smuzhiyun mwl8k_hw_reset(priv);
6319*4882a593Smuzhiyun goto unmap;
6320*4882a593Smuzhiyun }
6321*4882a593Smuzhiyun
6322*4882a593Smuzhiyun ieee80211_stop_queues(hw);
6323*4882a593Smuzhiyun
6324*4882a593Smuzhiyun ieee80211_unregister_hw(hw);
6325*4882a593Smuzhiyun
6326*4882a593Smuzhiyun /* Remove TX reclaim and RX tasklets. */
6327*4882a593Smuzhiyun tasklet_kill(&priv->poll_tx_task);
6328*4882a593Smuzhiyun tasklet_kill(&priv->poll_rx_task);
6329*4882a593Smuzhiyun
6330*4882a593Smuzhiyun /* Stop hardware */
6331*4882a593Smuzhiyun mwl8k_hw_reset(priv);
6332*4882a593Smuzhiyun
6333*4882a593Smuzhiyun /* Return all skbs to mac80211 */
6334*4882a593Smuzhiyun for (i = 0; i < mwl8k_tx_queues(priv); i++)
6335*4882a593Smuzhiyun mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
6336*4882a593Smuzhiyun
6337*4882a593Smuzhiyun for (i = 0; i < mwl8k_tx_queues(priv); i++)
6338*4882a593Smuzhiyun mwl8k_txq_deinit(hw, i);
6339*4882a593Smuzhiyun
6340*4882a593Smuzhiyun mwl8k_rxq_deinit(hw, 0);
6341*4882a593Smuzhiyun
6342*4882a593Smuzhiyun pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
6343*4882a593Smuzhiyun
6344*4882a593Smuzhiyun unmap:
6345*4882a593Smuzhiyun pci_iounmap(pdev, priv->regs);
6346*4882a593Smuzhiyun pci_iounmap(pdev, priv->sram);
6347*4882a593Smuzhiyun ieee80211_free_hw(hw);
6348*4882a593Smuzhiyun pci_release_regions(pdev);
6349*4882a593Smuzhiyun pci_disable_device(pdev);
6350*4882a593Smuzhiyun }
6351*4882a593Smuzhiyun
6352*4882a593Smuzhiyun static struct pci_driver mwl8k_driver = {
6353*4882a593Smuzhiyun .name = MWL8K_NAME,
6354*4882a593Smuzhiyun .id_table = mwl8k_pci_id_table,
6355*4882a593Smuzhiyun .probe = mwl8k_probe,
6356*4882a593Smuzhiyun .remove = mwl8k_remove,
6357*4882a593Smuzhiyun };
6358*4882a593Smuzhiyun
6359*4882a593Smuzhiyun module_pci_driver(mwl8k_driver);
6360*4882a593Smuzhiyun
6361*4882a593Smuzhiyun MODULE_DESCRIPTION(MWL8K_DESC);
6362*4882a593Smuzhiyun MODULE_VERSION(MWL8K_VERSION);
6363*4882a593Smuzhiyun MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
6364*4882a593Smuzhiyun MODULE_LICENSE("GPL");
6365