xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/marvell/mwifiex/ioctl.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * NXP Wireless LAN device driver: ioctl data structures & APIs
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Copyright 2011-2020 NXP
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * This software file (the "File") is distributed by NXP
7*4882a593Smuzhiyun  * under the terms of the GNU General Public License Version 2, June 1991
8*4882a593Smuzhiyun  * (the "License").  You may use, redistribute and/or modify this File in
9*4882a593Smuzhiyun  * accordance with the terms and conditions of the License, a copy of which
10*4882a593Smuzhiyun  * is available by writing to the Free Software Foundation, Inc.,
11*4882a593Smuzhiyun  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
12*4882a593Smuzhiyun  * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
15*4882a593Smuzhiyun  * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
16*4882a593Smuzhiyun  * ARE EXPRESSLY DISCLAIMED.  The License provides additional details about
17*4882a593Smuzhiyun  * this warranty disclaimer.
18*4882a593Smuzhiyun  */
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #ifndef _MWIFIEX_IOCTL_H_
21*4882a593Smuzhiyun #define _MWIFIEX_IOCTL_H_
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #include <net/lib80211.h>
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun enum {
26*4882a593Smuzhiyun 	MWIFIEX_SCAN_TYPE_UNCHANGED = 0,
27*4882a593Smuzhiyun 	MWIFIEX_SCAN_TYPE_ACTIVE,
28*4882a593Smuzhiyun 	MWIFIEX_SCAN_TYPE_PASSIVE
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun struct mwifiex_user_scan {
32*4882a593Smuzhiyun 	u32 scan_cfg_len;
33*4882a593Smuzhiyun 	u8 scan_cfg_buf[1];
34*4882a593Smuzhiyun };
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #define MWIFIEX_PROMISC_MODE            1
37*4882a593Smuzhiyun #define MWIFIEX_MULTICAST_MODE		2
38*4882a593Smuzhiyun #define	MWIFIEX_ALL_MULTI_MODE		4
39*4882a593Smuzhiyun #define MWIFIEX_MAX_MULTICAST_LIST_SIZE	32
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun struct mwifiex_multicast_list {
42*4882a593Smuzhiyun 	u32 mode;
43*4882a593Smuzhiyun 	u32 num_multicast_addr;
44*4882a593Smuzhiyun 	u8 mac_list[MWIFIEX_MAX_MULTICAST_LIST_SIZE][ETH_ALEN];
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun struct mwifiex_chan_freq {
48*4882a593Smuzhiyun 	u32 channel;
49*4882a593Smuzhiyun 	u32 freq;
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun struct mwifiex_ssid_bssid {
53*4882a593Smuzhiyun 	struct cfg80211_ssid ssid;
54*4882a593Smuzhiyun 	u8 bssid[ETH_ALEN];
55*4882a593Smuzhiyun };
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun enum {
58*4882a593Smuzhiyun 	BAND_B = 1,
59*4882a593Smuzhiyun 	BAND_G = 2,
60*4882a593Smuzhiyun 	BAND_A = 4,
61*4882a593Smuzhiyun 	BAND_GN = 8,
62*4882a593Smuzhiyun 	BAND_AN = 16,
63*4882a593Smuzhiyun 	BAND_AAC = 32,
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun #define MWIFIEX_WPA_PASSHPHRASE_LEN 64
67*4882a593Smuzhiyun struct wpa_param {
68*4882a593Smuzhiyun 	u8 pairwise_cipher_wpa;
69*4882a593Smuzhiyun 	u8 pairwise_cipher_wpa2;
70*4882a593Smuzhiyun 	u8 group_cipher;
71*4882a593Smuzhiyun 	u32 length;
72*4882a593Smuzhiyun 	u8 passphrase[MWIFIEX_WPA_PASSHPHRASE_LEN];
73*4882a593Smuzhiyun };
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun struct wep_key {
76*4882a593Smuzhiyun 	u8 key_index;
77*4882a593Smuzhiyun 	u8 is_default;
78*4882a593Smuzhiyun 	u16 length;
79*4882a593Smuzhiyun 	u8 key[WLAN_KEY_LEN_WEP104];
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun #define KEY_MGMT_ON_HOST        0x03
83*4882a593Smuzhiyun #define MWIFIEX_AUTH_MODE_AUTO  0xFF
84*4882a593Smuzhiyun #define BAND_CONFIG_BG          0x00
85*4882a593Smuzhiyun #define BAND_CONFIG_A           0x01
86*4882a593Smuzhiyun #define MWIFIEX_SEC_CHAN_BELOW	0x30
87*4882a593Smuzhiyun #define MWIFIEX_SEC_CHAN_ABOVE	0x10
88*4882a593Smuzhiyun #define MWIFIEX_SUPPORTED_RATES                 14
89*4882a593Smuzhiyun #define MWIFIEX_SUPPORTED_RATES_EXT             32
90*4882a593Smuzhiyun #define MWIFIEX_TDLS_SUPPORTED_RATES		8
91*4882a593Smuzhiyun #define MWIFIEX_TDLS_DEF_QOS_CAPAB		0xf
92*4882a593Smuzhiyun #define MWIFIEX_PRIO_BK				2
93*4882a593Smuzhiyun #define MWIFIEX_PRIO_VI				5
94*4882a593Smuzhiyun #define MWIFIEX_SUPPORTED_CHANNELS		2
95*4882a593Smuzhiyun #define MWIFIEX_OPERATING_CLASSES		16
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun struct mwifiex_uap_bss_param {
98*4882a593Smuzhiyun 	u8 channel;
99*4882a593Smuzhiyun 	u8 band_cfg;
100*4882a593Smuzhiyun 	u16 rts_threshold;
101*4882a593Smuzhiyun 	u16 frag_threshold;
102*4882a593Smuzhiyun 	u8 retry_limit;
103*4882a593Smuzhiyun 	struct mwifiex_802_11_ssid ssid;
104*4882a593Smuzhiyun 	u8 bcast_ssid_ctl;
105*4882a593Smuzhiyun 	u8 radio_ctl;
106*4882a593Smuzhiyun 	u8 dtim_period;
107*4882a593Smuzhiyun 	u16 beacon_period;
108*4882a593Smuzhiyun 	u16 auth_mode;
109*4882a593Smuzhiyun 	u16 protocol;
110*4882a593Smuzhiyun 	u16 key_mgmt;
111*4882a593Smuzhiyun 	u16 key_mgmt_operation;
112*4882a593Smuzhiyun 	struct wpa_param wpa_cfg;
113*4882a593Smuzhiyun 	struct wep_key wep_cfg[NUM_WEP_KEYS];
114*4882a593Smuzhiyun 	struct ieee80211_ht_cap ht_cap;
115*4882a593Smuzhiyun 	struct ieee80211_vht_cap vht_cap;
116*4882a593Smuzhiyun 	u8 rates[MWIFIEX_SUPPORTED_RATES];
117*4882a593Smuzhiyun 	u32 sta_ao_timer;
118*4882a593Smuzhiyun 	u32 ps_sta_ao_timer;
119*4882a593Smuzhiyun 	u8 qos_info;
120*4882a593Smuzhiyun 	u8 power_constraint;
121*4882a593Smuzhiyun 	struct mwifiex_types_wmm_info wmm_info;
122*4882a593Smuzhiyun };
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun enum {
125*4882a593Smuzhiyun 	ADHOC_IDLE,
126*4882a593Smuzhiyun 	ADHOC_STARTED,
127*4882a593Smuzhiyun 	ADHOC_JOINED,
128*4882a593Smuzhiyun 	ADHOC_COALESCED
129*4882a593Smuzhiyun };
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun struct mwifiex_ds_get_stats {
132*4882a593Smuzhiyun 	u32 mcast_tx_frame;
133*4882a593Smuzhiyun 	u32 failed;
134*4882a593Smuzhiyun 	u32 retry;
135*4882a593Smuzhiyun 	u32 multi_retry;
136*4882a593Smuzhiyun 	u32 frame_dup;
137*4882a593Smuzhiyun 	u32 rts_success;
138*4882a593Smuzhiyun 	u32 rts_failure;
139*4882a593Smuzhiyun 	u32 ack_failure;
140*4882a593Smuzhiyun 	u32 rx_frag;
141*4882a593Smuzhiyun 	u32 mcast_rx_frame;
142*4882a593Smuzhiyun 	u32 fcs_error;
143*4882a593Smuzhiyun 	u32 tx_frame;
144*4882a593Smuzhiyun 	u32 wep_icv_error[4];
145*4882a593Smuzhiyun 	u32 bcn_rcv_cnt;
146*4882a593Smuzhiyun 	u32 bcn_miss_cnt;
147*4882a593Smuzhiyun };
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun #define MWIFIEX_MAX_VER_STR_LEN    128
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun struct mwifiex_ver_ext {
152*4882a593Smuzhiyun 	u32 version_str_sel;
153*4882a593Smuzhiyun 	char version_str[MWIFIEX_MAX_VER_STR_LEN];
154*4882a593Smuzhiyun };
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun struct mwifiex_bss_info {
157*4882a593Smuzhiyun 	u32 bss_mode;
158*4882a593Smuzhiyun 	struct cfg80211_ssid ssid;
159*4882a593Smuzhiyun 	u32 bss_chan;
160*4882a593Smuzhiyun 	u8 country_code[3];
161*4882a593Smuzhiyun 	u32 media_connected;
162*4882a593Smuzhiyun 	u32 max_power_level;
163*4882a593Smuzhiyun 	u32 min_power_level;
164*4882a593Smuzhiyun 	u32 adhoc_state;
165*4882a593Smuzhiyun 	signed int bcn_nf_last;
166*4882a593Smuzhiyun 	u32 wep_status;
167*4882a593Smuzhiyun 	u32 is_hs_configured;
168*4882a593Smuzhiyun 	u32 is_deep_sleep;
169*4882a593Smuzhiyun 	u8 bssid[ETH_ALEN];
170*4882a593Smuzhiyun };
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun #define MAX_NUM_TID     8
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun #define MAX_RX_WINSIZE  64
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun struct mwifiex_ds_rx_reorder_tbl {
177*4882a593Smuzhiyun 	u16 tid;
178*4882a593Smuzhiyun 	u8 ta[ETH_ALEN];
179*4882a593Smuzhiyun 	u32 start_win;
180*4882a593Smuzhiyun 	u32 win_size;
181*4882a593Smuzhiyun 	u32 buffer[MAX_RX_WINSIZE];
182*4882a593Smuzhiyun };
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun struct mwifiex_ds_tx_ba_stream_tbl {
185*4882a593Smuzhiyun 	u16 tid;
186*4882a593Smuzhiyun 	u8 ra[ETH_ALEN];
187*4882a593Smuzhiyun 	u8 amsdu;
188*4882a593Smuzhiyun };
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun #define DBG_CMD_NUM    5
191*4882a593Smuzhiyun #define MWIFIEX_DBG_SDIO_MP_NUM    10
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun struct tdls_peer_info {
194*4882a593Smuzhiyun 	u8 peer_addr[ETH_ALEN];
195*4882a593Smuzhiyun };
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun struct mwifiex_debug_info {
198*4882a593Smuzhiyun 	unsigned int debug_mask;
199*4882a593Smuzhiyun 	u32 int_counter;
200*4882a593Smuzhiyun 	u32 packets_out[MAX_NUM_TID];
201*4882a593Smuzhiyun 	u32 tx_buf_size;
202*4882a593Smuzhiyun 	u32 curr_tx_buf_size;
203*4882a593Smuzhiyun 	u32 tx_tbl_num;
204*4882a593Smuzhiyun 	struct mwifiex_ds_tx_ba_stream_tbl
205*4882a593Smuzhiyun 		tx_tbl[MWIFIEX_MAX_TX_BASTREAM_SUPPORTED];
206*4882a593Smuzhiyun 	u32 rx_tbl_num;
207*4882a593Smuzhiyun 	struct mwifiex_ds_rx_reorder_tbl rx_tbl
208*4882a593Smuzhiyun 		[MWIFIEX_MAX_RX_BASTREAM_SUPPORTED];
209*4882a593Smuzhiyun 	u32 tdls_peer_num;
210*4882a593Smuzhiyun 	struct tdls_peer_info tdls_list
211*4882a593Smuzhiyun 		[MWIFIEX_MAX_TDLS_PEER_SUPPORTED];
212*4882a593Smuzhiyun 	u16 ps_mode;
213*4882a593Smuzhiyun 	u32 ps_state;
214*4882a593Smuzhiyun 	u8 is_deep_sleep;
215*4882a593Smuzhiyun 	u8 pm_wakeup_card_req;
216*4882a593Smuzhiyun 	u32 pm_wakeup_fw_try;
217*4882a593Smuzhiyun 	u8 is_hs_configured;
218*4882a593Smuzhiyun 	u8 hs_activated;
219*4882a593Smuzhiyun 	u32 num_cmd_host_to_card_failure;
220*4882a593Smuzhiyun 	u32 num_cmd_sleep_cfm_host_to_card_failure;
221*4882a593Smuzhiyun 	u32 num_tx_host_to_card_failure;
222*4882a593Smuzhiyun 	u32 num_event_deauth;
223*4882a593Smuzhiyun 	u32 num_event_disassoc;
224*4882a593Smuzhiyun 	u32 num_event_link_lost;
225*4882a593Smuzhiyun 	u32 num_cmd_deauth;
226*4882a593Smuzhiyun 	u32 num_cmd_assoc_success;
227*4882a593Smuzhiyun 	u32 num_cmd_assoc_failure;
228*4882a593Smuzhiyun 	u32 num_tx_timeout;
229*4882a593Smuzhiyun 	u8 is_cmd_timedout;
230*4882a593Smuzhiyun 	u16 timeout_cmd_id;
231*4882a593Smuzhiyun 	u16 timeout_cmd_act;
232*4882a593Smuzhiyun 	u16 last_cmd_id[DBG_CMD_NUM];
233*4882a593Smuzhiyun 	u16 last_cmd_act[DBG_CMD_NUM];
234*4882a593Smuzhiyun 	u16 last_cmd_index;
235*4882a593Smuzhiyun 	u16 last_cmd_resp_id[DBG_CMD_NUM];
236*4882a593Smuzhiyun 	u16 last_cmd_resp_index;
237*4882a593Smuzhiyun 	u16 last_event[DBG_CMD_NUM];
238*4882a593Smuzhiyun 	u16 last_event_index;
239*4882a593Smuzhiyun 	u8 data_sent;
240*4882a593Smuzhiyun 	u8 cmd_sent;
241*4882a593Smuzhiyun 	u8 cmd_resp_received;
242*4882a593Smuzhiyun 	u8 event_received;
243*4882a593Smuzhiyun 	u32 last_mp_wr_bitmap[MWIFIEX_DBG_SDIO_MP_NUM];
244*4882a593Smuzhiyun 	u32 last_mp_wr_ports[MWIFIEX_DBG_SDIO_MP_NUM];
245*4882a593Smuzhiyun 	u32 last_mp_wr_len[MWIFIEX_DBG_SDIO_MP_NUM];
246*4882a593Smuzhiyun 	u32 last_mp_curr_wr_port[MWIFIEX_DBG_SDIO_MP_NUM];
247*4882a593Smuzhiyun 	u8 last_sdio_mp_index;
248*4882a593Smuzhiyun };
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun #define MWIFIEX_KEY_INDEX_UNICAST	0x40000000
251*4882a593Smuzhiyun #define PN_LEN				16
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun struct mwifiex_ds_encrypt_key {
254*4882a593Smuzhiyun 	u32 key_disable;
255*4882a593Smuzhiyun 	u32 key_index;
256*4882a593Smuzhiyun 	u32 key_len;
257*4882a593Smuzhiyun 	u8 key_material[WLAN_MAX_KEY_LEN];
258*4882a593Smuzhiyun 	u8 mac_addr[ETH_ALEN];
259*4882a593Smuzhiyun 	u32 is_wapi_key;
260*4882a593Smuzhiyun 	u8 pn[PN_LEN];		/* packet number */
261*4882a593Smuzhiyun 	u8 pn_len;
262*4882a593Smuzhiyun 	u8 is_igtk_key;
263*4882a593Smuzhiyun 	u8 is_current_wep_key;
264*4882a593Smuzhiyun 	u8 is_rx_seq_valid;
265*4882a593Smuzhiyun 	u8 is_igtk_def_key;
266*4882a593Smuzhiyun };
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun struct mwifiex_power_cfg {
269*4882a593Smuzhiyun 	u32 is_power_auto;
270*4882a593Smuzhiyun 	u32 is_power_fixed;
271*4882a593Smuzhiyun 	u32 power_level;
272*4882a593Smuzhiyun };
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun struct mwifiex_ds_hs_cfg {
275*4882a593Smuzhiyun 	u32 is_invoke_hostcmd;
276*4882a593Smuzhiyun 	/*  Bit0: non-unicast data
277*4882a593Smuzhiyun 	 *  Bit1: unicast data
278*4882a593Smuzhiyun 	 *  Bit2: mac events
279*4882a593Smuzhiyun 	 *  Bit3: magic packet
280*4882a593Smuzhiyun 	 */
281*4882a593Smuzhiyun 	u32 conditions;
282*4882a593Smuzhiyun 	u32 gpio;
283*4882a593Smuzhiyun 	u32 gap;
284*4882a593Smuzhiyun };
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun struct mwifiex_ds_wakeup_reason {
287*4882a593Smuzhiyun 	u16  hs_wakeup_reason;
288*4882a593Smuzhiyun };
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun #define DEEP_SLEEP_ON  1
291*4882a593Smuzhiyun #define DEEP_SLEEP_OFF 0
292*4882a593Smuzhiyun #define DEEP_SLEEP_IDLE_TIME	100
293*4882a593Smuzhiyun #define PS_MODE_AUTO		1
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun struct mwifiex_ds_auto_ds {
296*4882a593Smuzhiyun 	u16 auto_ds;
297*4882a593Smuzhiyun 	u16 idle_time;
298*4882a593Smuzhiyun };
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun struct mwifiex_ds_pm_cfg {
301*4882a593Smuzhiyun 	union {
302*4882a593Smuzhiyun 		u32 ps_mode;
303*4882a593Smuzhiyun 		struct mwifiex_ds_hs_cfg hs_cfg;
304*4882a593Smuzhiyun 		struct mwifiex_ds_auto_ds auto_deep_sleep;
305*4882a593Smuzhiyun 		u32 sleep_period;
306*4882a593Smuzhiyun 	} param;
307*4882a593Smuzhiyun };
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun struct mwifiex_11ac_vht_cfg {
310*4882a593Smuzhiyun 	u8 band_config;
311*4882a593Smuzhiyun 	u8 misc_config;
312*4882a593Smuzhiyun 	u32 cap_info;
313*4882a593Smuzhiyun 	u32 mcs_tx_set;
314*4882a593Smuzhiyun 	u32 mcs_rx_set;
315*4882a593Smuzhiyun };
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun struct mwifiex_ds_11n_tx_cfg {
318*4882a593Smuzhiyun 	u16 tx_htcap;
319*4882a593Smuzhiyun 	u16 tx_htinfo;
320*4882a593Smuzhiyun 	u16 misc_config; /* Needed for 802.11AC cards only */
321*4882a593Smuzhiyun };
322*4882a593Smuzhiyun 
323*4882a593Smuzhiyun struct mwifiex_ds_11n_amsdu_aggr_ctrl {
324*4882a593Smuzhiyun 	u16 enable;
325*4882a593Smuzhiyun 	u16 curr_buf_size;
326*4882a593Smuzhiyun };
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun struct mwifiex_ds_ant_cfg {
329*4882a593Smuzhiyun 	u32 tx_ant;
330*4882a593Smuzhiyun 	u32 rx_ant;
331*4882a593Smuzhiyun };
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun #define MWIFIEX_NUM_OF_CMD_BUFFER	50
334*4882a593Smuzhiyun #define MWIFIEX_SIZE_OF_CMD_BUFFER	2048
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun enum {
337*4882a593Smuzhiyun 	MWIFIEX_IE_TYPE_GEN_IE = 0,
338*4882a593Smuzhiyun 	MWIFIEX_IE_TYPE_ARP_FILTER,
339*4882a593Smuzhiyun };
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun enum {
342*4882a593Smuzhiyun 	MWIFIEX_REG_MAC = 1,
343*4882a593Smuzhiyun 	MWIFIEX_REG_BBP,
344*4882a593Smuzhiyun 	MWIFIEX_REG_RF,
345*4882a593Smuzhiyun 	MWIFIEX_REG_PMIC,
346*4882a593Smuzhiyun 	MWIFIEX_REG_CAU,
347*4882a593Smuzhiyun };
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun struct mwifiex_ds_reg_rw {
350*4882a593Smuzhiyun 	u32 type;
351*4882a593Smuzhiyun 	u32 offset;
352*4882a593Smuzhiyun 	u32 value;
353*4882a593Smuzhiyun };
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun #define MAX_EEPROM_DATA 256
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun struct mwifiex_ds_read_eeprom {
358*4882a593Smuzhiyun 	u16 offset;
359*4882a593Smuzhiyun 	u16 byte_count;
360*4882a593Smuzhiyun 	u8 value[MAX_EEPROM_DATA];
361*4882a593Smuzhiyun };
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun struct mwifiex_ds_mem_rw {
364*4882a593Smuzhiyun 	u32 addr;
365*4882a593Smuzhiyun 	u32 value;
366*4882a593Smuzhiyun };
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun #define IEEE_MAX_IE_SIZE		256
369*4882a593Smuzhiyun 
370*4882a593Smuzhiyun #define MWIFIEX_IE_HDR_SIZE	(sizeof(struct mwifiex_ie) - IEEE_MAX_IE_SIZE)
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun struct mwifiex_ds_misc_gen_ie {
373*4882a593Smuzhiyun 	u32 type;
374*4882a593Smuzhiyun 	u32 len;
375*4882a593Smuzhiyun 	u8 ie_data[IEEE_MAX_IE_SIZE];
376*4882a593Smuzhiyun };
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun struct mwifiex_ds_misc_cmd {
379*4882a593Smuzhiyun 	u32 len;
380*4882a593Smuzhiyun 	u8 cmd[MWIFIEX_SIZE_OF_CMD_BUFFER];
381*4882a593Smuzhiyun };
382*4882a593Smuzhiyun 
383*4882a593Smuzhiyun #define BITMASK_BCN_RSSI_LOW	BIT(0)
384*4882a593Smuzhiyun #define BITMASK_BCN_RSSI_HIGH	BIT(4)
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun enum subsc_evt_rssi_state {
387*4882a593Smuzhiyun 	EVENT_HANDLED,
388*4882a593Smuzhiyun 	RSSI_LOW_RECVD,
389*4882a593Smuzhiyun 	RSSI_HIGH_RECVD
390*4882a593Smuzhiyun };
391*4882a593Smuzhiyun 
392*4882a593Smuzhiyun struct subsc_evt_cfg {
393*4882a593Smuzhiyun 	u8 abs_value;
394*4882a593Smuzhiyun 	u8 evt_freq;
395*4882a593Smuzhiyun };
396*4882a593Smuzhiyun 
397*4882a593Smuzhiyun struct mwifiex_ds_misc_subsc_evt {
398*4882a593Smuzhiyun 	u16 action;
399*4882a593Smuzhiyun 	u16 events;
400*4882a593Smuzhiyun 	struct subsc_evt_cfg bcn_l_rssi_cfg;
401*4882a593Smuzhiyun 	struct subsc_evt_cfg bcn_h_rssi_cfg;
402*4882a593Smuzhiyun };
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun #define MWIFIEX_MEF_MAX_BYTESEQ		6	/* non-adjustable */
405*4882a593Smuzhiyun #define MWIFIEX_MEF_MAX_FILTERS		10
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun struct mwifiex_mef_filter {
408*4882a593Smuzhiyun 	u16 repeat;
409*4882a593Smuzhiyun 	u16 offset;
410*4882a593Smuzhiyun 	s8 byte_seq[MWIFIEX_MEF_MAX_BYTESEQ + 1];
411*4882a593Smuzhiyun 	u8 filt_type;
412*4882a593Smuzhiyun 	u8 filt_action;
413*4882a593Smuzhiyun };
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun struct mwifiex_mef_entry {
416*4882a593Smuzhiyun 	u8 mode;
417*4882a593Smuzhiyun 	u8 action;
418*4882a593Smuzhiyun 	struct mwifiex_mef_filter filter[MWIFIEX_MEF_MAX_FILTERS];
419*4882a593Smuzhiyun };
420*4882a593Smuzhiyun 
421*4882a593Smuzhiyun struct mwifiex_ds_mef_cfg {
422*4882a593Smuzhiyun 	u32 criteria;
423*4882a593Smuzhiyun 	u16 num_entries;
424*4882a593Smuzhiyun 	struct mwifiex_mef_entry *mef_entry;
425*4882a593Smuzhiyun };
426*4882a593Smuzhiyun 
427*4882a593Smuzhiyun #define MWIFIEX_MAX_VSIE_LEN       (256)
428*4882a593Smuzhiyun #define MWIFIEX_MAX_VSIE_NUM       (8)
429*4882a593Smuzhiyun #define MWIFIEX_VSIE_MASK_CLEAR    0x00
430*4882a593Smuzhiyun #define MWIFIEX_VSIE_MASK_SCAN     0x01
431*4882a593Smuzhiyun #define MWIFIEX_VSIE_MASK_ASSOC    0x02
432*4882a593Smuzhiyun #define MWIFIEX_VSIE_MASK_ADHOC    0x04
433*4882a593Smuzhiyun #define MWIFIEX_VSIE_MASK_BGSCAN   0x08
434*4882a593Smuzhiyun 
435*4882a593Smuzhiyun enum {
436*4882a593Smuzhiyun 	MWIFIEX_FUNC_INIT = 1,
437*4882a593Smuzhiyun 	MWIFIEX_FUNC_SHUTDOWN,
438*4882a593Smuzhiyun };
439*4882a593Smuzhiyun 
440*4882a593Smuzhiyun enum COALESCE_OPERATION {
441*4882a593Smuzhiyun 	RECV_FILTER_MATCH_TYPE_EQ = 0x80,
442*4882a593Smuzhiyun 	RECV_FILTER_MATCH_TYPE_NE,
443*4882a593Smuzhiyun };
444*4882a593Smuzhiyun 
445*4882a593Smuzhiyun enum COALESCE_PACKET_TYPE {
446*4882a593Smuzhiyun 	PACKET_TYPE_UNICAST = 1,
447*4882a593Smuzhiyun 	PACKET_TYPE_MULTICAST = 2,
448*4882a593Smuzhiyun 	PACKET_TYPE_BROADCAST = 3
449*4882a593Smuzhiyun };
450*4882a593Smuzhiyun 
451*4882a593Smuzhiyun #define MWIFIEX_COALESCE_MAX_RULES	8
452*4882a593Smuzhiyun #define MWIFIEX_COALESCE_MAX_BYTESEQ	4	/* non-adjustable */
453*4882a593Smuzhiyun #define MWIFIEX_COALESCE_MAX_FILTERS	4
454*4882a593Smuzhiyun #define MWIFIEX_MAX_COALESCING_DELAY	100     /* in msecs */
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun struct filt_field_param {
457*4882a593Smuzhiyun 	u8 operation;
458*4882a593Smuzhiyun 	u8 operand_len;
459*4882a593Smuzhiyun 	u16 offset;
460*4882a593Smuzhiyun 	u8 operand_byte_stream[MWIFIEX_COALESCE_MAX_BYTESEQ];
461*4882a593Smuzhiyun };
462*4882a593Smuzhiyun 
463*4882a593Smuzhiyun struct mwifiex_coalesce_rule {
464*4882a593Smuzhiyun 	u16 max_coalescing_delay;
465*4882a593Smuzhiyun 	u8 num_of_fields;
466*4882a593Smuzhiyun 	u8 pkt_type;
467*4882a593Smuzhiyun 	struct filt_field_param params[MWIFIEX_COALESCE_MAX_FILTERS];
468*4882a593Smuzhiyun };
469*4882a593Smuzhiyun 
470*4882a593Smuzhiyun struct mwifiex_ds_coalesce_cfg {
471*4882a593Smuzhiyun 	u16 num_of_rules;
472*4882a593Smuzhiyun 	struct mwifiex_coalesce_rule rule[MWIFIEX_COALESCE_MAX_RULES];
473*4882a593Smuzhiyun };
474*4882a593Smuzhiyun 
475*4882a593Smuzhiyun struct mwifiex_ds_tdls_oper {
476*4882a593Smuzhiyun 	u16 tdls_action;
477*4882a593Smuzhiyun 	u8 peer_mac[ETH_ALEN];
478*4882a593Smuzhiyun 	u16 capability;
479*4882a593Smuzhiyun 	u8 qos_info;
480*4882a593Smuzhiyun 	u8 *ext_capab;
481*4882a593Smuzhiyun 	u8 ext_capab_len;
482*4882a593Smuzhiyun 	u8 *supp_rates;
483*4882a593Smuzhiyun 	u8 supp_rates_len;
484*4882a593Smuzhiyun 	u8 *ht_capab;
485*4882a593Smuzhiyun };
486*4882a593Smuzhiyun 
487*4882a593Smuzhiyun #endif /* !_MWIFIEX_IOCTL_H_ */
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