1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2002 Intersil Americas Inc.
4*4882a593Smuzhiyun * Copyright (C) 2003 Herbert Valerio Riedel <hvr@gnu.org>
5*4882a593Smuzhiyun * Copyright (C) 2003 Luis R. Rodriguez <mcgrof@ruslug.rutgers.edu>
6*4882a593Smuzhiyun * Copyright (C) 2003 Aurelien Alleaume <slts@free.fr>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #ifndef _ISLPCI_DEV_H
10*4882a593Smuzhiyun #define _ISLPCI_DEV_H
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/irqreturn.h>
13*4882a593Smuzhiyun #include <linux/netdevice.h>
14*4882a593Smuzhiyun #include <linux/wireless.h>
15*4882a593Smuzhiyun #include <net/iw_handler.h>
16*4882a593Smuzhiyun #include <linux/list.h>
17*4882a593Smuzhiyun #include <linux/mutex.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include "isl_38xx.h"
20*4882a593Smuzhiyun #include "isl_oid.h"
21*4882a593Smuzhiyun #include "islpci_mgt.h"
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /* some states might not be superflous and may be removed when
24*4882a593Smuzhiyun design is finalized (hvr) */
25*4882a593Smuzhiyun typedef enum {
26*4882a593Smuzhiyun PRV_STATE_OFF = 0, /* this means hw_unavailable is != 0 */
27*4882a593Smuzhiyun PRV_STATE_PREBOOT, /* we are in a pre-boot state (empty RAM) */
28*4882a593Smuzhiyun PRV_STATE_BOOT, /* boot state (fw upload, run fw) */
29*4882a593Smuzhiyun PRV_STATE_POSTBOOT, /* after boot state, need reset now */
30*4882a593Smuzhiyun PRV_STATE_PREINIT, /* pre-init state */
31*4882a593Smuzhiyun PRV_STATE_INIT, /* init state (restore MIB backup to device) */
32*4882a593Smuzhiyun PRV_STATE_READY, /* driver&device are in operational state */
33*4882a593Smuzhiyun PRV_STATE_SLEEP /* device in sleep mode */
34*4882a593Smuzhiyun } islpci_state_t;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* ACL using MAC address */
37*4882a593Smuzhiyun struct mac_entry {
38*4882a593Smuzhiyun struct list_head _list;
39*4882a593Smuzhiyun char addr[ETH_ALEN];
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun struct islpci_acl {
43*4882a593Smuzhiyun enum { MAC_POLICY_OPEN=0, MAC_POLICY_ACCEPT=1, MAC_POLICY_REJECT=2 } policy;
44*4882a593Smuzhiyun struct list_head mac_list; /* a list of mac_entry */
45*4882a593Smuzhiyun int size; /* size of queue */
46*4882a593Smuzhiyun struct mutex lock; /* accessed in ioctls and trap_work */
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun struct islpci_membuf {
50*4882a593Smuzhiyun int size; /* size of memory */
51*4882a593Smuzhiyun void *mem; /* address of memory as seen by CPU */
52*4882a593Smuzhiyun dma_addr_t pci_addr; /* address of memory as seen by device */
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #define MAX_BSS_WPA_IE_COUNT 64
56*4882a593Smuzhiyun #define MAX_WPA_IE_LEN 64
57*4882a593Smuzhiyun struct islpci_bss_wpa_ie {
58*4882a593Smuzhiyun struct list_head list;
59*4882a593Smuzhiyun unsigned long last_update;
60*4882a593Smuzhiyun u8 bssid[ETH_ALEN];
61*4882a593Smuzhiyun u8 wpa_ie[MAX_WPA_IE_LEN];
62*4882a593Smuzhiyun size_t wpa_ie_len;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun typedef struct {
67*4882a593Smuzhiyun spinlock_t slock; /* generic spinlock; */
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun u32 priv_oid;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun /* our mib cache */
72*4882a593Smuzhiyun u32 iw_mode;
73*4882a593Smuzhiyun struct rw_semaphore mib_sem;
74*4882a593Smuzhiyun void **mib;
75*4882a593Smuzhiyun char nickname[IW_ESSID_MAX_SIZE+1];
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /* Take care of the wireless stats */
78*4882a593Smuzhiyun struct work_struct stats_work;
79*4882a593Smuzhiyun struct mutex stats_lock;
80*4882a593Smuzhiyun /* remember when we last updated the stats */
81*4882a593Smuzhiyun unsigned long stats_timestamp;
82*4882a593Smuzhiyun /* The first is accessed under semaphore locking.
83*4882a593Smuzhiyun * The second is the clean one we return to iwconfig.
84*4882a593Smuzhiyun */
85*4882a593Smuzhiyun struct iw_statistics local_iwstatistics;
86*4882a593Smuzhiyun struct iw_statistics iwstatistics;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun struct iw_spy_data spy_data; /* iwspy support */
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun struct iw_public_data wireless_data;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun int monitor_type; /* ARPHRD_IEEE80211 or ARPHRD_IEEE80211_PRISM */
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun struct islpci_acl acl;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun /* PCI bus allocation & configuration members */
97*4882a593Smuzhiyun struct pci_dev *pdev; /* PCI structure information */
98*4882a593Smuzhiyun char firmware[33];
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun void __iomem *device_base; /* ioremapped device base address */
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun /* consistent DMA region */
103*4882a593Smuzhiyun void *driver_mem_address; /* base DMA address */
104*4882a593Smuzhiyun dma_addr_t device_host_address; /* base DMA address (bus address) */
105*4882a593Smuzhiyun dma_addr_t device_psm_buffer; /* host memory for PSM buffering (bus address) */
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /* our network_device structure */
108*4882a593Smuzhiyun struct net_device *ndev;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun /* device queue interface members */
111*4882a593Smuzhiyun struct isl38xx_cb *control_block; /* device control block
112*4882a593Smuzhiyun (== driver_mem_address!) */
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /* Each queue has three indexes:
115*4882a593Smuzhiyun * free/index_mgmt/data_rx/tx (called index, see below),
116*4882a593Smuzhiyun * driver_curr_frag, and device_curr_frag (in the control block)
117*4882a593Smuzhiyun * All indexes are ever-increasing, but interpreted modulo the
118*4882a593Smuzhiyun * device queue size when used.
119*4882a593Smuzhiyun * index <= device_curr_frag <= driver_curr_frag at all times
120*4882a593Smuzhiyun * For rx queues, [index, device_curr_frag) contains fragments
121*4882a593Smuzhiyun * that the interrupt processing needs to handle (owned by driver).
122*4882a593Smuzhiyun * [device_curr_frag, driver_curr_frag) is the free space in the
123*4882a593Smuzhiyun * rx queue, waiting for data (owned by device). The driver
124*4882a593Smuzhiyun * increments driver_curr_frag to indicate to the device that more
125*4882a593Smuzhiyun * buffers are available.
126*4882a593Smuzhiyun * If device_curr_frag == driver_curr_frag, no more rx buffers are
127*4882a593Smuzhiyun * available, and the rx DMA engine of the device is halted.
128*4882a593Smuzhiyun * For tx queues, [index, device_curr_frag) contains fragments
129*4882a593Smuzhiyun * where tx is done; they need to be freed (owned by driver).
130*4882a593Smuzhiyun * [device_curr_frag, driver_curr_frag) contains the frames
131*4882a593Smuzhiyun * that are being transferred (owned by device). The driver
132*4882a593Smuzhiyun * increments driver_curr_frag to indicate that more tx work
133*4882a593Smuzhiyun * needs to be done.
134*4882a593Smuzhiyun */
135*4882a593Smuzhiyun u32 index_mgmt_rx; /* real index mgmt rx queue */
136*4882a593Smuzhiyun u32 index_mgmt_tx; /* read index mgmt tx queue */
137*4882a593Smuzhiyun u32 free_data_rx; /* free pointer data rx queue */
138*4882a593Smuzhiyun u32 free_data_tx; /* free pointer data tx queue */
139*4882a593Smuzhiyun u32 data_low_tx_full; /* full detected flag */
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun /* frame memory buffers for the device queues */
142*4882a593Smuzhiyun struct islpci_membuf mgmt_tx[ISL38XX_CB_MGMT_QSIZE];
143*4882a593Smuzhiyun struct islpci_membuf mgmt_rx[ISL38XX_CB_MGMT_QSIZE];
144*4882a593Smuzhiyun struct sk_buff *data_low_tx[ISL38XX_CB_TX_QSIZE];
145*4882a593Smuzhiyun struct sk_buff *data_low_rx[ISL38XX_CB_RX_QSIZE];
146*4882a593Smuzhiyun dma_addr_t pci_map_tx_address[ISL38XX_CB_TX_QSIZE];
147*4882a593Smuzhiyun dma_addr_t pci_map_rx_address[ISL38XX_CB_RX_QSIZE];
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun /* wait for a reset interrupt */
150*4882a593Smuzhiyun wait_queue_head_t reset_done;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun /* used by islpci_mgt_transaction */
153*4882a593Smuzhiyun struct mutex mgmt_lock; /* serialize access to mailbox and wqueue */
154*4882a593Smuzhiyun struct islpci_mgmtframe *mgmt_received; /* mbox for incoming frame */
155*4882a593Smuzhiyun wait_queue_head_t mgmt_wqueue; /* waitqueue for mbox */
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun /* state machine */
158*4882a593Smuzhiyun islpci_state_t state;
159*4882a593Smuzhiyun int state_off; /* enumeration of off-state, if 0 then
160*4882a593Smuzhiyun * we're not in any off-state */
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun /* WPA stuff */
163*4882a593Smuzhiyun int wpa; /* WPA mode enabled */
164*4882a593Smuzhiyun struct list_head bss_wpa_list;
165*4882a593Smuzhiyun int num_bss_wpa;
166*4882a593Smuzhiyun struct mutex wpa_lock;
167*4882a593Smuzhiyun u8 wpa_ie[MAX_WPA_IE_LEN];
168*4882a593Smuzhiyun size_t wpa_ie_len;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun struct work_struct reset_task;
171*4882a593Smuzhiyun int reset_task_pending;
172*4882a593Smuzhiyun } islpci_private;
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun static inline islpci_state_t
islpci_get_state(islpci_private * priv)175*4882a593Smuzhiyun islpci_get_state(islpci_private *priv)
176*4882a593Smuzhiyun {
177*4882a593Smuzhiyun /* lock */
178*4882a593Smuzhiyun return priv->state;
179*4882a593Smuzhiyun /* unlock */
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun islpci_state_t islpci_set_state(islpci_private *priv, islpci_state_t new_state);
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun #define ISLPCI_TX_TIMEOUT (2*HZ)
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun irqreturn_t islpci_interrupt(int, void *);
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun int prism54_post_setup(islpci_private *, int);
189*4882a593Smuzhiyun int islpci_reset(islpci_private *, int);
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun static inline void
islpci_trigger(islpci_private * priv)192*4882a593Smuzhiyun islpci_trigger(islpci_private *priv)
193*4882a593Smuzhiyun {
194*4882a593Smuzhiyun isl38xx_trigger_device(islpci_get_state(priv) == PRV_STATE_SLEEP,
195*4882a593Smuzhiyun priv->device_base);
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun int islpci_free_memory(islpci_private *);
199*4882a593Smuzhiyun struct net_device *islpci_setup(struct pci_dev *);
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun #define DRV_NAME "prism54"
202*4882a593Smuzhiyun #define DRV_VERSION "1.2"
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun #endif /* _ISLPCI_DEV_H */
205