1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2002 Intersil Americas Inc.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #ifndef _ISL_38XX_H
7*4882a593Smuzhiyun #define _ISL_38XX_H
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <asm/io.h>
10*4882a593Smuzhiyun #include <asm/byteorder.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #define ISL38XX_CB_RX_QSIZE 8
13*4882a593Smuzhiyun #define ISL38XX_CB_TX_QSIZE 32
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun /* ISL38XX Access Point Specific definitions */
16*4882a593Smuzhiyun #define ISL38XX_MAX_WDS_LINKS 8
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /* ISL38xx Client Specific definitions */
19*4882a593Smuzhiyun #define ISL38XX_PSM_ACTIVE_STATE 0
20*4882a593Smuzhiyun #define ISL38XX_PSM_POWERSAVE_STATE 1
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /* ISL38XX Host Interface Definitions */
23*4882a593Smuzhiyun #define ISL38XX_PCI_MEM_SIZE 0x02000
24*4882a593Smuzhiyun #define ISL38XX_MEMORY_WINDOW_SIZE 0x01000
25*4882a593Smuzhiyun #define ISL38XX_DEV_FIRMWARE_ADDRES 0x20000
26*4882a593Smuzhiyun #define ISL38XX_WRITEIO_DELAY 10 /* in us */
27*4882a593Smuzhiyun #define ISL38XX_RESET_DELAY 50 /* in ms */
28*4882a593Smuzhiyun #define ISL38XX_WAIT_CYCLE 10 /* in 10ms */
29*4882a593Smuzhiyun #define ISL38XX_MAX_WAIT_CYCLES 10
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* PCI Memory Area */
32*4882a593Smuzhiyun #define ISL38XX_HARDWARE_REG 0x0000
33*4882a593Smuzhiyun #define ISL38XX_CARDBUS_CIS 0x0800
34*4882a593Smuzhiyun #define ISL38XX_DIRECT_MEM_WIN 0x1000
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* Hardware registers */
37*4882a593Smuzhiyun #define ISL38XX_DEV_INT_REG 0x0000
38*4882a593Smuzhiyun #define ISL38XX_INT_IDENT_REG 0x0010
39*4882a593Smuzhiyun #define ISL38XX_INT_ACK_REG 0x0014
40*4882a593Smuzhiyun #define ISL38XX_INT_EN_REG 0x0018
41*4882a593Smuzhiyun #define ISL38XX_GEN_PURP_COM_REG_1 0x0020
42*4882a593Smuzhiyun #define ISL38XX_GEN_PURP_COM_REG_2 0x0024
43*4882a593Smuzhiyun #define ISL38XX_CTRL_BLK_BASE_REG ISL38XX_GEN_PURP_COM_REG_1
44*4882a593Smuzhiyun #define ISL38XX_DIR_MEM_BASE_REG 0x0030
45*4882a593Smuzhiyun #define ISL38XX_CTRL_STAT_REG 0x0078
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /* High end mobos queue up pci writes, the following
48*4882a593Smuzhiyun * is used to "read" from after a write to force flush */
49*4882a593Smuzhiyun #define ISL38XX_PCI_POSTING_FLUSH ISL38XX_INT_EN_REG
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /**
52*4882a593Smuzhiyun * isl38xx_w32_flush - PCI iomem write helper
53*4882a593Smuzhiyun * @base: (host) memory base address of the device
54*4882a593Smuzhiyun * @val: 32bit value (host order) to write
55*4882a593Smuzhiyun * @offset: byte offset into @base to write value to
56*4882a593Smuzhiyun *
57*4882a593Smuzhiyun * This helper takes care of writing a 32bit datum to the
58*4882a593Smuzhiyun * specified offset into the device's pci memory space, and making sure
59*4882a593Smuzhiyun * the pci memory buffers get flushed by performing one harmless read
60*4882a593Smuzhiyun * from the %ISL38XX_PCI_POSTING_FLUSH offset.
61*4882a593Smuzhiyun */
62*4882a593Smuzhiyun static inline void
isl38xx_w32_flush(void __iomem * base,u32 val,unsigned long offset)63*4882a593Smuzhiyun isl38xx_w32_flush(void __iomem *base, u32 val, unsigned long offset)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun writel(val, base + offset);
66*4882a593Smuzhiyun (void) readl(base + ISL38XX_PCI_POSTING_FLUSH);
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /* Device Interrupt register bits */
70*4882a593Smuzhiyun #define ISL38XX_DEV_INT_RESET 0x0001
71*4882a593Smuzhiyun #define ISL38XX_DEV_INT_UPDATE 0x0002
72*4882a593Smuzhiyun #define ISL38XX_DEV_INT_WAKEUP 0x0008
73*4882a593Smuzhiyun #define ISL38XX_DEV_INT_SLEEP 0x0010
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* Interrupt Identification/Acknowledge/Enable register bits */
76*4882a593Smuzhiyun #define ISL38XX_INT_IDENT_UPDATE 0x0002
77*4882a593Smuzhiyun #define ISL38XX_INT_IDENT_INIT 0x0004
78*4882a593Smuzhiyun #define ISL38XX_INT_IDENT_WAKEUP 0x0008
79*4882a593Smuzhiyun #define ISL38XX_INT_IDENT_SLEEP 0x0010
80*4882a593Smuzhiyun #define ISL38XX_INT_SOURCES 0x001E
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* Control/Status register bits */
83*4882a593Smuzhiyun /* Looks like there are other meaningful bits
84*4882a593Smuzhiyun 0x20004400 seen in normal operation,
85*4882a593Smuzhiyun 0x200044db at 'timeout waiting for mgmt response'
86*4882a593Smuzhiyun */
87*4882a593Smuzhiyun #define ISL38XX_CTRL_STAT_SLEEPMODE 0x00000200
88*4882a593Smuzhiyun #define ISL38XX_CTRL_STAT_CLKRUN 0x00800000
89*4882a593Smuzhiyun #define ISL38XX_CTRL_STAT_RESET 0x10000000
90*4882a593Smuzhiyun #define ISL38XX_CTRL_STAT_RAMBOOT 0x20000000
91*4882a593Smuzhiyun #define ISL38XX_CTRL_STAT_STARTHALTED 0x40000000
92*4882a593Smuzhiyun #define ISL38XX_CTRL_STAT_HOST_OVERRIDE 0x80000000
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /* Control Block definitions */
95*4882a593Smuzhiyun #define ISL38XX_CB_RX_DATA_LQ 0
96*4882a593Smuzhiyun #define ISL38XX_CB_TX_DATA_LQ 1
97*4882a593Smuzhiyun #define ISL38XX_CB_RX_DATA_HQ 2
98*4882a593Smuzhiyun #define ISL38XX_CB_TX_DATA_HQ 3
99*4882a593Smuzhiyun #define ISL38XX_CB_RX_MGMTQ 4
100*4882a593Smuzhiyun #define ISL38XX_CB_TX_MGMTQ 5
101*4882a593Smuzhiyun #define ISL38XX_CB_QCOUNT 6
102*4882a593Smuzhiyun #define ISL38XX_CB_MGMT_QSIZE 4
103*4882a593Smuzhiyun #define ISL38XX_MIN_QTHRESHOLD 4 /* fragments */
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /* Memory Manager definitions */
106*4882a593Smuzhiyun #define MGMT_FRAME_SIZE 1500 /* >= size struct obj_bsslist */
107*4882a593Smuzhiyun #define MGMT_TX_FRAME_COUNT 24 /* max 4 + spare 4 + 8 init */
108*4882a593Smuzhiyun #define MGMT_RX_FRAME_COUNT 24 /* 4*4 + spare 8 */
109*4882a593Smuzhiyun #define MGMT_FRAME_COUNT (MGMT_TX_FRAME_COUNT + MGMT_RX_FRAME_COUNT)
110*4882a593Smuzhiyun #define CONTROL_BLOCK_SIZE 1024 /* should be enough */
111*4882a593Smuzhiyun #define PSM_FRAME_SIZE 1536
112*4882a593Smuzhiyun #define PSM_MINIMAL_STATION_COUNT 64
113*4882a593Smuzhiyun #define PSM_FRAME_COUNT PSM_MINIMAL_STATION_COUNT
114*4882a593Smuzhiyun #define PSM_BUFFER_SIZE PSM_FRAME_SIZE * PSM_FRAME_COUNT
115*4882a593Smuzhiyun #define MAX_TRAP_RX_QUEUE 4
116*4882a593Smuzhiyun #define HOST_MEM_BLOCK CONTROL_BLOCK_SIZE + PSM_BUFFER_SIZE
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun /* Fragment package definitions */
119*4882a593Smuzhiyun #define FRAGMENT_FLAG_MF 0x0001
120*4882a593Smuzhiyun #define MAX_FRAGMENT_SIZE 1536
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun /* In monitor mode frames have a header. I don't know exactly how big those
123*4882a593Smuzhiyun * frame can be but I've never seen any frame bigger than 1584... :
124*4882a593Smuzhiyun */
125*4882a593Smuzhiyun #define MAX_FRAGMENT_SIZE_RX 1600
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun typedef struct {
128*4882a593Smuzhiyun __le32 address; /* physical address on host */
129*4882a593Smuzhiyun __le16 size; /* packet size */
130*4882a593Smuzhiyun __le16 flags; /* set of bit-wise flags */
131*4882a593Smuzhiyun } isl38xx_fragment;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun struct isl38xx_cb {
134*4882a593Smuzhiyun __le32 driver_curr_frag[ISL38XX_CB_QCOUNT];
135*4882a593Smuzhiyun __le32 device_curr_frag[ISL38XX_CB_QCOUNT];
136*4882a593Smuzhiyun isl38xx_fragment rx_data_low[ISL38XX_CB_RX_QSIZE];
137*4882a593Smuzhiyun isl38xx_fragment tx_data_low[ISL38XX_CB_TX_QSIZE];
138*4882a593Smuzhiyun isl38xx_fragment rx_data_high[ISL38XX_CB_RX_QSIZE];
139*4882a593Smuzhiyun isl38xx_fragment tx_data_high[ISL38XX_CB_TX_QSIZE];
140*4882a593Smuzhiyun isl38xx_fragment rx_data_mgmt[ISL38XX_CB_MGMT_QSIZE];
141*4882a593Smuzhiyun isl38xx_fragment tx_data_mgmt[ISL38XX_CB_MGMT_QSIZE];
142*4882a593Smuzhiyun };
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun typedef struct isl38xx_cb isl38xx_control_block;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun /* determine number of entries currently in queue */
147*4882a593Smuzhiyun int isl38xx_in_queue(isl38xx_control_block *cb, int queue);
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun void isl38xx_disable_interrupts(void __iomem *);
150*4882a593Smuzhiyun void isl38xx_enable_common_interrupts(void __iomem *);
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun void isl38xx_handle_sleep_request(isl38xx_control_block *, int *,
153*4882a593Smuzhiyun void __iomem *);
154*4882a593Smuzhiyun void isl38xx_handle_wakeup(isl38xx_control_block *, int *, void __iomem *);
155*4882a593Smuzhiyun void isl38xx_trigger_device(int, void __iomem *);
156*4882a593Smuzhiyun void isl38xx_interface_reset(void __iomem *, dma_addr_t);
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun #endif /* _ISL_38XX_H */
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