1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2008 Christian Lamparter <chunkeey@web.de> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This driver is a port from stlc45xx: 6*4882a593Smuzhiyun * Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies). 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef P54SPI_H 10*4882a593Smuzhiyun #define P54SPI_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/mutex.h> 13*4882a593Smuzhiyun #include <linux/list.h> 14*4882a593Smuzhiyun #include <net/mac80211.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #include "p54.h" 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* Bit 15 is read/write bit; ON = READ, OFF = WRITE */ 19*4882a593Smuzhiyun #define SPI_ADRS_READ_BIT_15 0x8000 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define SPI_ADRS_ARM_INTERRUPTS 0x00 22*4882a593Smuzhiyun #define SPI_ADRS_ARM_INT_EN 0x04 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define SPI_ADRS_HOST_INTERRUPTS 0x08 25*4882a593Smuzhiyun #define SPI_ADRS_HOST_INT_EN 0x0c 26*4882a593Smuzhiyun #define SPI_ADRS_HOST_INT_ACK 0x10 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define SPI_ADRS_GEN_PURP_1 0x14 29*4882a593Smuzhiyun #define SPI_ADRS_GEN_PURP_2 0x18 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define SPI_ADRS_DEV_CTRL_STAT 0x26 /* high word */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define SPI_ADRS_DMA_DATA 0x28 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define SPI_ADRS_DMA_WRITE_CTRL 0x2c 36*4882a593Smuzhiyun #define SPI_ADRS_DMA_WRITE_LEN 0x2e 37*4882a593Smuzhiyun #define SPI_ADRS_DMA_WRITE_BASE 0x30 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define SPI_ADRS_DMA_READ_CTRL 0x34 40*4882a593Smuzhiyun #define SPI_ADRS_DMA_READ_LEN 0x36 41*4882a593Smuzhiyun #define SPI_ADRS_DMA_READ_BASE 0x38 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define SPI_CTRL_STAT_HOST_OVERRIDE 0x8000 44*4882a593Smuzhiyun #define SPI_CTRL_STAT_START_HALTED 0x4000 45*4882a593Smuzhiyun #define SPI_CTRL_STAT_RAM_BOOT 0x2000 46*4882a593Smuzhiyun #define SPI_CTRL_STAT_HOST_RESET 0x1000 47*4882a593Smuzhiyun #define SPI_CTRL_STAT_HOST_CPU_EN 0x0800 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define SPI_DMA_WRITE_CTRL_ENABLE 0x0001 50*4882a593Smuzhiyun #define SPI_DMA_READ_CTRL_ENABLE 0x0001 51*4882a593Smuzhiyun #define HOST_ALLOWED (1 << 7) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define SPI_TIMEOUT 100 /* msec */ 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define SPI_MAX_TX_PACKETS 32 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define SPI_MAX_PACKET_SIZE 32767 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define SPI_TARGET_INT_WAKEUP 0x00000001 60*4882a593Smuzhiyun #define SPI_TARGET_INT_SLEEP 0x00000002 61*4882a593Smuzhiyun #define SPI_TARGET_INT_RDDONE 0x00000004 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define SPI_TARGET_INT_CTS 0x00004000 64*4882a593Smuzhiyun #define SPI_TARGET_INT_DR 0x00008000 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define SPI_HOST_INT_READY 0x00000001 67*4882a593Smuzhiyun #define SPI_HOST_INT_WR_READY 0x00000002 68*4882a593Smuzhiyun #define SPI_HOST_INT_SW_UPDATE 0x00000004 69*4882a593Smuzhiyun #define SPI_HOST_INT_UPDATE 0x10000000 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* clear to send */ 72*4882a593Smuzhiyun #define SPI_HOST_INT_CR 0x00004000 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* data ready */ 75*4882a593Smuzhiyun #define SPI_HOST_INT_DR 0x00008000 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define SPI_HOST_INTS_DEFAULT \ 78*4882a593Smuzhiyun (SPI_HOST_INT_READY | SPI_HOST_INT_UPDATE | SPI_HOST_INT_SW_UPDATE) 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define TARGET_BOOT_SLEEP 50 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun struct p54s_dma_regs { 83*4882a593Smuzhiyun __le16 cmd; 84*4882a593Smuzhiyun __le16 len; 85*4882a593Smuzhiyun __le32 addr; 86*4882a593Smuzhiyun } __packed; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun struct p54s_tx_info { 89*4882a593Smuzhiyun struct list_head tx_list; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun struct p54s_priv { 93*4882a593Smuzhiyun /* p54_common has to be the first entry */ 94*4882a593Smuzhiyun struct p54_common common; 95*4882a593Smuzhiyun struct ieee80211_hw *hw; 96*4882a593Smuzhiyun struct spi_device *spi; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun struct work_struct work; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun struct mutex mutex; 101*4882a593Smuzhiyun struct completion fw_comp; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun spinlock_t tx_lock; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* protected by tx_lock */ 106*4882a593Smuzhiyun struct list_head tx_pending; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun enum fw_state fw_state; 109*4882a593Smuzhiyun const struct firmware *firmware; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #endif /* P54SPI_H */ 113