1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun #ifndef P54PCI_H 3*4882a593Smuzhiyun #define P54PCI_H 4*4882a593Smuzhiyun #include <linux/interrupt.h> 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun /* 7*4882a593Smuzhiyun * Defines for PCI based mac80211 Prism54 driver 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net> 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * Based on the islsm (softmac prism54) driver, which is: 12*4882a593Smuzhiyun * Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al. 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* Device Interrupt register bits */ 16*4882a593Smuzhiyun #define ISL38XX_DEV_INT_RESET 0x0001 17*4882a593Smuzhiyun #define ISL38XX_DEV_INT_UPDATE 0x0002 18*4882a593Smuzhiyun #define ISL38XX_DEV_INT_WAKEUP 0x0008 19*4882a593Smuzhiyun #define ISL38XX_DEV_INT_SLEEP 0x0010 20*4882a593Smuzhiyun #define ISL38XX_DEV_INT_ABORT 0x0020 21*4882a593Smuzhiyun /* these two only used in USB */ 22*4882a593Smuzhiyun #define ISL38XX_DEV_INT_DATA 0x0040 23*4882a593Smuzhiyun #define ISL38XX_DEV_INT_MGMT 0x0080 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define ISL38XX_DEV_INT_PCIUART_CTS 0x4000 26*4882a593Smuzhiyun #define ISL38XX_DEV_INT_PCIUART_DR 0x8000 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* Interrupt Identification/Acknowledge/Enable register bits */ 29*4882a593Smuzhiyun #define ISL38XX_INT_IDENT_UPDATE 0x0002 30*4882a593Smuzhiyun #define ISL38XX_INT_IDENT_INIT 0x0004 31*4882a593Smuzhiyun #define ISL38XX_INT_IDENT_WAKEUP 0x0008 32*4882a593Smuzhiyun #define ISL38XX_INT_IDENT_SLEEP 0x0010 33*4882a593Smuzhiyun #define ISL38XX_INT_IDENT_PCIUART_CTS 0x4000 34*4882a593Smuzhiyun #define ISL38XX_INT_IDENT_PCIUART_DR 0x8000 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* Control/Status register bits */ 37*4882a593Smuzhiyun #define ISL38XX_CTRL_STAT_SLEEPMODE 0x00000200 38*4882a593Smuzhiyun #define ISL38XX_CTRL_STAT_CLKRUN 0x00800000 39*4882a593Smuzhiyun #define ISL38XX_CTRL_STAT_RESET 0x10000000 40*4882a593Smuzhiyun #define ISL38XX_CTRL_STAT_RAMBOOT 0x20000000 41*4882a593Smuzhiyun #define ISL38XX_CTRL_STAT_STARTHALTED 0x40000000 42*4882a593Smuzhiyun #define ISL38XX_CTRL_STAT_HOST_OVERRIDE 0x80000000 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun struct p54p_csr { 45*4882a593Smuzhiyun __le32 dev_int; 46*4882a593Smuzhiyun u8 unused_1[12]; 47*4882a593Smuzhiyun __le32 int_ident; 48*4882a593Smuzhiyun __le32 int_ack; 49*4882a593Smuzhiyun __le32 int_enable; 50*4882a593Smuzhiyun u8 unused_2[4]; 51*4882a593Smuzhiyun union { 52*4882a593Smuzhiyun __le32 ring_control_base; 53*4882a593Smuzhiyun __le32 gen_purp_com[2]; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun u8 unused_3[8]; 56*4882a593Smuzhiyun __le32 direct_mem_base; 57*4882a593Smuzhiyun u8 unused_4[44]; 58*4882a593Smuzhiyun __le32 dma_addr; 59*4882a593Smuzhiyun __le32 dma_len; 60*4882a593Smuzhiyun __le32 dma_ctrl; 61*4882a593Smuzhiyun u8 unused_5[12]; 62*4882a593Smuzhiyun __le32 ctrl_stat; 63*4882a593Smuzhiyun u8 unused_6[1924]; 64*4882a593Smuzhiyun u8 cardbus_cis[0x800]; 65*4882a593Smuzhiyun u8 direct_mem_win[0x1000]; 66*4882a593Smuzhiyun } __packed; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* usb backend only needs the register defines above */ 69*4882a593Smuzhiyun #ifndef P54USB_H 70*4882a593Smuzhiyun struct p54p_desc { 71*4882a593Smuzhiyun __le32 host_addr; 72*4882a593Smuzhiyun __le32 device_addr; 73*4882a593Smuzhiyun __le16 len; 74*4882a593Smuzhiyun __le16 flags; 75*4882a593Smuzhiyun } __packed; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun struct p54p_ring_control { 78*4882a593Smuzhiyun __le32 host_idx[4]; 79*4882a593Smuzhiyun __le32 device_idx[4]; 80*4882a593Smuzhiyun struct p54p_desc rx_data[8]; 81*4882a593Smuzhiyun struct p54p_desc tx_data[32]; 82*4882a593Smuzhiyun struct p54p_desc rx_mgmt[4]; 83*4882a593Smuzhiyun struct p54p_desc tx_mgmt[4]; 84*4882a593Smuzhiyun } __packed; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define P54P_READ(r) (__force __le32)__raw_readl(&priv->map->r) 87*4882a593Smuzhiyun #define P54P_WRITE(r, val) __raw_writel((__force u32)(__le32)(val), &priv->map->r) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun struct p54p_priv { 90*4882a593Smuzhiyun struct p54_common common; 91*4882a593Smuzhiyun struct pci_dev *pdev; 92*4882a593Smuzhiyun struct p54p_csr __iomem *map; 93*4882a593Smuzhiyun struct tasklet_struct tasklet; 94*4882a593Smuzhiyun const struct firmware *firmware; 95*4882a593Smuzhiyun spinlock_t lock; 96*4882a593Smuzhiyun struct p54p_ring_control *ring_control; 97*4882a593Smuzhiyun dma_addr_t ring_control_dma; 98*4882a593Smuzhiyun u32 rx_idx_data, tx_idx_data; 99*4882a593Smuzhiyun u32 rx_idx_mgmt, tx_idx_mgmt; 100*4882a593Smuzhiyun struct sk_buff *rx_buf_data[8]; 101*4882a593Smuzhiyun struct sk_buff *rx_buf_mgmt[4]; 102*4882a593Smuzhiyun struct sk_buff *tx_buf_data[32]; 103*4882a593Smuzhiyun struct sk_buff *tx_buf_mgmt[4]; 104*4882a593Smuzhiyun struct completion boot_comp; 105*4882a593Smuzhiyun struct completion fw_loaded; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #endif /* P54USB_H */ 109*4882a593Smuzhiyun #endif /* P54PCI_H */ 110