1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * LMAC Interface specific definitions for mac80211 Prism54 drivers 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net> 6*4882a593Smuzhiyun * Copyright (c) 2007 - 2009, Christian Lamparter <chunkeey@web.de> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Based on: 9*4882a593Smuzhiyun * - the islsm (softmac prism54) driver, which is: 10*4882a593Smuzhiyun * Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al. 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * - LMAC API interface header file for STLC4560 (lmac_longbow.h) 13*4882a593Smuzhiyun * Copyright (C) 2007 Conexant Systems, Inc. 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #ifndef LMAC_H 17*4882a593Smuzhiyun #define LMAC_H 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun enum p54_control_frame_types { 20*4882a593Smuzhiyun P54_CONTROL_TYPE_SETUP = 0, 21*4882a593Smuzhiyun P54_CONTROL_TYPE_SCAN, 22*4882a593Smuzhiyun P54_CONTROL_TYPE_TRAP, 23*4882a593Smuzhiyun P54_CONTROL_TYPE_DCFINIT, 24*4882a593Smuzhiyun P54_CONTROL_TYPE_RX_KEYCACHE, 25*4882a593Smuzhiyun P54_CONTROL_TYPE_TIM, 26*4882a593Smuzhiyun P54_CONTROL_TYPE_PSM, 27*4882a593Smuzhiyun P54_CONTROL_TYPE_TXCANCEL, 28*4882a593Smuzhiyun P54_CONTROL_TYPE_TXDONE, 29*4882a593Smuzhiyun P54_CONTROL_TYPE_BURST, 30*4882a593Smuzhiyun P54_CONTROL_TYPE_STAT_READBACK, 31*4882a593Smuzhiyun P54_CONTROL_TYPE_BBP, 32*4882a593Smuzhiyun P54_CONTROL_TYPE_EEPROM_READBACK, 33*4882a593Smuzhiyun P54_CONTROL_TYPE_LED, 34*4882a593Smuzhiyun P54_CONTROL_TYPE_GPIO, 35*4882a593Smuzhiyun P54_CONTROL_TYPE_TIMER, 36*4882a593Smuzhiyun P54_CONTROL_TYPE_MODULATION, 37*4882a593Smuzhiyun P54_CONTROL_TYPE_SYNTH_CONFIG, 38*4882a593Smuzhiyun P54_CONTROL_TYPE_DETECTOR_VALUE, 39*4882a593Smuzhiyun P54_CONTROL_TYPE_XBOW_SYNTH_CFG, 40*4882a593Smuzhiyun P54_CONTROL_TYPE_CCE_QUIET, 41*4882a593Smuzhiyun P54_CONTROL_TYPE_PSM_STA_UNLOCK, 42*4882a593Smuzhiyun P54_CONTROL_TYPE_PCS, 43*4882a593Smuzhiyun P54_CONTROL_TYPE_BT_BALANCER = 28, 44*4882a593Smuzhiyun P54_CONTROL_TYPE_GROUP_ADDRESS_TABLE = 30, 45*4882a593Smuzhiyun P54_CONTROL_TYPE_ARPTABLE = 31, 46*4882a593Smuzhiyun P54_CONTROL_TYPE_BT_OPTIONS = 35, 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define P54_HDR_FLAG_CONTROL BIT(15) 50*4882a593Smuzhiyun #define P54_HDR_FLAG_CONTROL_OPSET (BIT(15) + BIT(0)) 51*4882a593Smuzhiyun #define P54_HDR_FLAG_DATA_ALIGN BIT(14) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define P54_HDR_FLAG_DATA_OUT_PROMISC BIT(0) 54*4882a593Smuzhiyun #define P54_HDR_FLAG_DATA_OUT_TIMESTAMP BIT(1) 55*4882a593Smuzhiyun #define P54_HDR_FLAG_DATA_OUT_SEQNR BIT(2) 56*4882a593Smuzhiyun #define P54_HDR_FLAG_DATA_OUT_BIT3 BIT(3) 57*4882a593Smuzhiyun #define P54_HDR_FLAG_DATA_OUT_BURST BIT(4) 58*4882a593Smuzhiyun #define P54_HDR_FLAG_DATA_OUT_NOCANCEL BIT(5) 59*4882a593Smuzhiyun #define P54_HDR_FLAG_DATA_OUT_CLEARTIM BIT(6) 60*4882a593Smuzhiyun #define P54_HDR_FLAG_DATA_OUT_HITCHHIKE BIT(7) 61*4882a593Smuzhiyun #define P54_HDR_FLAG_DATA_OUT_COMPRESS BIT(8) 62*4882a593Smuzhiyun #define P54_HDR_FLAG_DATA_OUT_CONCAT BIT(9) 63*4882a593Smuzhiyun #define P54_HDR_FLAG_DATA_OUT_PCS_ACCEPT BIT(10) 64*4882a593Smuzhiyun #define P54_HDR_FLAG_DATA_OUT_WAITEOSP BIT(11) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define P54_HDR_FLAG_DATA_IN_FCS_GOOD BIT(0) 67*4882a593Smuzhiyun #define P54_HDR_FLAG_DATA_IN_MATCH_MAC BIT(1) 68*4882a593Smuzhiyun #define P54_HDR_FLAG_DATA_IN_MCBC BIT(2) 69*4882a593Smuzhiyun #define P54_HDR_FLAG_DATA_IN_BEACON BIT(3) 70*4882a593Smuzhiyun #define P54_HDR_FLAG_DATA_IN_MATCH_BSS BIT(4) 71*4882a593Smuzhiyun #define P54_HDR_FLAG_DATA_IN_BCAST_BSS BIT(5) 72*4882a593Smuzhiyun #define P54_HDR_FLAG_DATA_IN_DATA BIT(6) 73*4882a593Smuzhiyun #define P54_HDR_FLAG_DATA_IN_TRUNCATED BIT(7) 74*4882a593Smuzhiyun #define P54_HDR_FLAG_DATA_IN_BIT8 BIT(8) 75*4882a593Smuzhiyun #define P54_HDR_FLAG_DATA_IN_TRANSPARENT BIT(9) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun struct p54_hdr { 78*4882a593Smuzhiyun __le16 flags; 79*4882a593Smuzhiyun __le16 len; 80*4882a593Smuzhiyun __le32 req_id; 81*4882a593Smuzhiyun __le16 type; /* enum p54_control_frame_types */ 82*4882a593Smuzhiyun u8 rts_tries; 83*4882a593Smuzhiyun u8 tries; 84*4882a593Smuzhiyun u8 data[]; 85*4882a593Smuzhiyun } __packed; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define GET_REQ_ID(skb) \ 88*4882a593Smuzhiyun (((struct p54_hdr *) ((struct sk_buff *) skb)->data)->req_id) \ 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define FREE_AFTER_TX(skb) \ 91*4882a593Smuzhiyun ((((struct p54_hdr *) ((struct sk_buff *) skb)->data)-> \ 92*4882a593Smuzhiyun flags) == cpu_to_le16(P54_HDR_FLAG_CONTROL_OPSET)) 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define IS_DATA_FRAME(skb) \ 95*4882a593Smuzhiyun (!((((struct p54_hdr *) ((struct sk_buff *) skb)->data)-> \ 96*4882a593Smuzhiyun flags) & cpu_to_le16(P54_HDR_FLAG_CONTROL))) 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #define GET_HW_QUEUE(skb) \ 99*4882a593Smuzhiyun (((struct p54_tx_data *)((struct p54_hdr *) \ 100*4882a593Smuzhiyun skb->data)->data)->hw_queue) 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* 103*4882a593Smuzhiyun * shared interface ID definitions 104*4882a593Smuzhiyun * The interface ID is a unique identification of a specific interface. 105*4882a593Smuzhiyun * The following values are reserved: 0x0000, 0x0002, 0x0012, 0x0014, 0x0015 106*4882a593Smuzhiyun */ 107*4882a593Smuzhiyun #define IF_ID_ISL36356A 0x0001 /* ISL36356A <-> Firmware */ 108*4882a593Smuzhiyun #define IF_ID_MVC 0x0003 /* MAC Virtual Coprocessor */ 109*4882a593Smuzhiyun #define IF_ID_DEBUG 0x0008 /* PolDebug Interface */ 110*4882a593Smuzhiyun #define IF_ID_PRODUCT 0x0009 111*4882a593Smuzhiyun #define IF_ID_OEM 0x000a 112*4882a593Smuzhiyun #define IF_ID_PCI3877 0x000b /* 3877 <-> Host PCI */ 113*4882a593Smuzhiyun #define IF_ID_ISL37704C 0x000c /* ISL37704C <-> Fw */ 114*4882a593Smuzhiyun #define IF_ID_ISL39000 0x000f /* ISL39000 <-> Fw */ 115*4882a593Smuzhiyun #define IF_ID_ISL39300A 0x0010 /* ISL39300A <-> Fw */ 116*4882a593Smuzhiyun #define IF_ID_ISL37700_UAP 0x0016 /* ISL37700 uAP Fw <-> Fw */ 117*4882a593Smuzhiyun #define IF_ID_ISL39000_UAP 0x0017 /* ISL39000 uAP Fw <-> Fw */ 118*4882a593Smuzhiyun #define IF_ID_LMAC 0x001a /* Interface exposed by LMAC */ 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun struct exp_if { 121*4882a593Smuzhiyun __le16 role; 122*4882a593Smuzhiyun __le16 if_id; 123*4882a593Smuzhiyun __le16 variant; 124*4882a593Smuzhiyun __le16 btm_compat; 125*4882a593Smuzhiyun __le16 top_compat; 126*4882a593Smuzhiyun } __packed; 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun struct dep_if { 129*4882a593Smuzhiyun __le16 role; 130*4882a593Smuzhiyun __le16 if_id; 131*4882a593Smuzhiyun __le16 variant; 132*4882a593Smuzhiyun } __packed; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun /* driver <-> lmac definitions */ 135*4882a593Smuzhiyun struct p54_eeprom_lm86 { 136*4882a593Smuzhiyun union { 137*4882a593Smuzhiyun struct { 138*4882a593Smuzhiyun __le16 offset; 139*4882a593Smuzhiyun __le16 len; 140*4882a593Smuzhiyun u8 data[0]; 141*4882a593Smuzhiyun } __packed v1; 142*4882a593Smuzhiyun struct { 143*4882a593Smuzhiyun __le32 offset; 144*4882a593Smuzhiyun __le16 len; 145*4882a593Smuzhiyun u8 magic2; 146*4882a593Smuzhiyun u8 pad; 147*4882a593Smuzhiyun u8 magic[4]; 148*4882a593Smuzhiyun u8 data[0]; 149*4882a593Smuzhiyun } __packed v2; 150*4882a593Smuzhiyun } __packed; 151*4882a593Smuzhiyun } __packed; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun enum p54_rx_decrypt_status { 154*4882a593Smuzhiyun P54_DECRYPT_NONE = 0, 155*4882a593Smuzhiyun P54_DECRYPT_OK, 156*4882a593Smuzhiyun P54_DECRYPT_NOKEY, 157*4882a593Smuzhiyun P54_DECRYPT_NOMICHAEL, 158*4882a593Smuzhiyun P54_DECRYPT_NOCKIPMIC, 159*4882a593Smuzhiyun P54_DECRYPT_FAIL_WEP, 160*4882a593Smuzhiyun P54_DECRYPT_FAIL_TKIP, 161*4882a593Smuzhiyun P54_DECRYPT_FAIL_MICHAEL, 162*4882a593Smuzhiyun P54_DECRYPT_FAIL_CKIPKP, 163*4882a593Smuzhiyun P54_DECRYPT_FAIL_CKIPMIC, 164*4882a593Smuzhiyun P54_DECRYPT_FAIL_AESCCMP 165*4882a593Smuzhiyun }; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun struct p54_rx_data { 168*4882a593Smuzhiyun __le16 flags; 169*4882a593Smuzhiyun __le16 len; 170*4882a593Smuzhiyun __le16 freq; 171*4882a593Smuzhiyun u8 antenna; 172*4882a593Smuzhiyun u8 rate; 173*4882a593Smuzhiyun u8 rssi; 174*4882a593Smuzhiyun u8 quality; 175*4882a593Smuzhiyun u8 decrypt_status; 176*4882a593Smuzhiyun u8 rssi_raw; 177*4882a593Smuzhiyun __le32 tsf32; 178*4882a593Smuzhiyun __le32 unalloc0; 179*4882a593Smuzhiyun u8 align[]; 180*4882a593Smuzhiyun } __packed; 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun enum p54_trap_type { 183*4882a593Smuzhiyun P54_TRAP_SCAN = 0, 184*4882a593Smuzhiyun P54_TRAP_TIMER, 185*4882a593Smuzhiyun P54_TRAP_BEACON_TX, 186*4882a593Smuzhiyun P54_TRAP_FAA_RADIO_ON, 187*4882a593Smuzhiyun P54_TRAP_FAA_RADIO_OFF, 188*4882a593Smuzhiyun P54_TRAP_RADAR, 189*4882a593Smuzhiyun P54_TRAP_NO_BEACON, 190*4882a593Smuzhiyun P54_TRAP_TBTT, 191*4882a593Smuzhiyun P54_TRAP_SCO_ENTER, 192*4882a593Smuzhiyun P54_TRAP_SCO_EXIT 193*4882a593Smuzhiyun }; 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun struct p54_trap { 196*4882a593Smuzhiyun __le16 event; 197*4882a593Smuzhiyun __le16 frequency; 198*4882a593Smuzhiyun } __packed; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun enum p54_frame_sent_status { 201*4882a593Smuzhiyun P54_TX_OK = 0, 202*4882a593Smuzhiyun P54_TX_FAILED, 203*4882a593Smuzhiyun P54_TX_PSM, 204*4882a593Smuzhiyun P54_TX_PSM_CANCELLED = 4 205*4882a593Smuzhiyun }; 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun struct p54_frame_sent { 208*4882a593Smuzhiyun u8 status; 209*4882a593Smuzhiyun u8 tries; 210*4882a593Smuzhiyun u8 ack_rssi; 211*4882a593Smuzhiyun u8 quality; 212*4882a593Smuzhiyun __le16 seq; 213*4882a593Smuzhiyun u8 antenna; 214*4882a593Smuzhiyun u8 padding; 215*4882a593Smuzhiyun } __packed; 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun enum p54_tx_data_crypt { 218*4882a593Smuzhiyun P54_CRYPTO_NONE = 0, 219*4882a593Smuzhiyun P54_CRYPTO_WEP, 220*4882a593Smuzhiyun P54_CRYPTO_TKIP, 221*4882a593Smuzhiyun P54_CRYPTO_TKIPMICHAEL, 222*4882a593Smuzhiyun P54_CRYPTO_CCX_WEPMIC, 223*4882a593Smuzhiyun P54_CRYPTO_CCX_KPMIC, 224*4882a593Smuzhiyun P54_CRYPTO_CCX_KP, 225*4882a593Smuzhiyun P54_CRYPTO_AESCCMP 226*4882a593Smuzhiyun }; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun enum p54_tx_data_queue { 229*4882a593Smuzhiyun P54_QUEUE_BEACON = 0, 230*4882a593Smuzhiyun P54_QUEUE_FWSCAN = 1, 231*4882a593Smuzhiyun P54_QUEUE_MGMT = 2, 232*4882a593Smuzhiyun P54_QUEUE_CAB = 3, 233*4882a593Smuzhiyun P54_QUEUE_DATA = 4, 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun P54_QUEUE_AC_NUM = 4, 236*4882a593Smuzhiyun P54_QUEUE_AC_VO = 4, 237*4882a593Smuzhiyun P54_QUEUE_AC_VI = 5, 238*4882a593Smuzhiyun P54_QUEUE_AC_BE = 6, 239*4882a593Smuzhiyun P54_QUEUE_AC_BK = 7, 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun /* keep last */ 242*4882a593Smuzhiyun P54_QUEUE_NUM = 8, 243*4882a593Smuzhiyun }; 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun #define IS_QOS_QUEUE(n) (n >= P54_QUEUE_DATA) 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun struct p54_tx_data { 248*4882a593Smuzhiyun u8 rateset[8]; 249*4882a593Smuzhiyun u8 rts_rate_idx; 250*4882a593Smuzhiyun u8 crypt_offset; 251*4882a593Smuzhiyun u8 key_type; 252*4882a593Smuzhiyun u8 key_len; 253*4882a593Smuzhiyun u8 key[16]; 254*4882a593Smuzhiyun u8 hw_queue; 255*4882a593Smuzhiyun u8 backlog; 256*4882a593Smuzhiyun __le16 durations[4]; 257*4882a593Smuzhiyun u8 tx_antenna; 258*4882a593Smuzhiyun union { 259*4882a593Smuzhiyun struct { 260*4882a593Smuzhiyun u8 cts_rate; 261*4882a593Smuzhiyun __le16 output_power; 262*4882a593Smuzhiyun } __packed longbow; 263*4882a593Smuzhiyun struct { 264*4882a593Smuzhiyun u8 output_power; 265*4882a593Smuzhiyun u8 cts_rate; 266*4882a593Smuzhiyun u8 unalloc; 267*4882a593Smuzhiyun } __packed normal; 268*4882a593Smuzhiyun } __packed; 269*4882a593Smuzhiyun u8 unalloc2[2]; 270*4882a593Smuzhiyun u8 align[]; 271*4882a593Smuzhiyun } __packed; 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun /* unit is ms */ 274*4882a593Smuzhiyun #define P54_TX_FRAME_LIFETIME 2000 275*4882a593Smuzhiyun #define P54_TX_TIMEOUT 4000 276*4882a593Smuzhiyun #define P54_STATISTICS_UPDATE 5000 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun #define P54_FILTER_TYPE_NONE 0 279*4882a593Smuzhiyun #define P54_FILTER_TYPE_STATION BIT(0) 280*4882a593Smuzhiyun #define P54_FILTER_TYPE_IBSS BIT(1) 281*4882a593Smuzhiyun #define P54_FILTER_TYPE_AP BIT(2) 282*4882a593Smuzhiyun #define P54_FILTER_TYPE_TRANSPARENT BIT(3) 283*4882a593Smuzhiyun #define P54_FILTER_TYPE_PROMISCUOUS BIT(4) 284*4882a593Smuzhiyun #define P54_FILTER_TYPE_HIBERNATE BIT(5) 285*4882a593Smuzhiyun #define P54_FILTER_TYPE_NOACK BIT(6) 286*4882a593Smuzhiyun #define P54_FILTER_TYPE_RX_DISABLED BIT(7) 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun struct p54_setup_mac { 289*4882a593Smuzhiyun __le16 mac_mode; 290*4882a593Smuzhiyun u8 mac_addr[ETH_ALEN]; 291*4882a593Smuzhiyun u8 bssid[ETH_ALEN]; 292*4882a593Smuzhiyun u8 rx_antenna; 293*4882a593Smuzhiyun u8 rx_align; 294*4882a593Smuzhiyun union { 295*4882a593Smuzhiyun struct { 296*4882a593Smuzhiyun __le32 basic_rate_mask; 297*4882a593Smuzhiyun u8 rts_rates[8]; 298*4882a593Smuzhiyun __le32 rx_addr; 299*4882a593Smuzhiyun __le16 max_rx; 300*4882a593Smuzhiyun __le16 rxhw; 301*4882a593Smuzhiyun __le16 wakeup_timer; 302*4882a593Smuzhiyun __le16 unalloc0; 303*4882a593Smuzhiyun } __packed v1; 304*4882a593Smuzhiyun struct { 305*4882a593Smuzhiyun __le32 rx_addr; 306*4882a593Smuzhiyun __le16 max_rx; 307*4882a593Smuzhiyun __le16 rxhw; 308*4882a593Smuzhiyun __le16 timer; 309*4882a593Smuzhiyun __le16 truncate; 310*4882a593Smuzhiyun __le32 basic_rate_mask; 311*4882a593Smuzhiyun u8 sbss_offset; 312*4882a593Smuzhiyun u8 mcast_window; 313*4882a593Smuzhiyun u8 rx_rssi_threshold; 314*4882a593Smuzhiyun u8 rx_ed_threshold; 315*4882a593Smuzhiyun __le32 ref_clock; 316*4882a593Smuzhiyun __le16 lpf_bandwidth; 317*4882a593Smuzhiyun __le16 osc_start_delay; 318*4882a593Smuzhiyun } __packed v2; 319*4882a593Smuzhiyun } __packed; 320*4882a593Smuzhiyun } __packed; 321*4882a593Smuzhiyun 322*4882a593Smuzhiyun #define P54_SETUP_V1_LEN 40 323*4882a593Smuzhiyun #define P54_SETUP_V2_LEN (sizeof(struct p54_setup_mac)) 324*4882a593Smuzhiyun 325*4882a593Smuzhiyun #define P54_SCAN_EXIT BIT(0) 326*4882a593Smuzhiyun #define P54_SCAN_TRAP BIT(1) 327*4882a593Smuzhiyun #define P54_SCAN_ACTIVE BIT(2) 328*4882a593Smuzhiyun #define P54_SCAN_FILTER BIT(3) 329*4882a593Smuzhiyun 330*4882a593Smuzhiyun struct p54_scan_head { 331*4882a593Smuzhiyun __le16 mode; 332*4882a593Smuzhiyun __le16 dwell; 333*4882a593Smuzhiyun u8 scan_params[20]; 334*4882a593Smuzhiyun __le16 freq; 335*4882a593Smuzhiyun } __packed; 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun struct p54_pa_curve_data_sample { 338*4882a593Smuzhiyun u8 rf_power; 339*4882a593Smuzhiyun u8 pa_detector; 340*4882a593Smuzhiyun u8 data_barker; 341*4882a593Smuzhiyun u8 data_bpsk; 342*4882a593Smuzhiyun u8 data_qpsk; 343*4882a593Smuzhiyun u8 data_16qam; 344*4882a593Smuzhiyun u8 data_64qam; 345*4882a593Smuzhiyun u8 padding; 346*4882a593Smuzhiyun } __packed; 347*4882a593Smuzhiyun 348*4882a593Smuzhiyun struct p54_scan_body { 349*4882a593Smuzhiyun u8 pa_points_per_curve; 350*4882a593Smuzhiyun u8 val_barker; 351*4882a593Smuzhiyun u8 val_bpsk; 352*4882a593Smuzhiyun u8 val_qpsk; 353*4882a593Smuzhiyun u8 val_16qam; 354*4882a593Smuzhiyun u8 val_64qam; 355*4882a593Smuzhiyun struct p54_pa_curve_data_sample curve_data[8]; 356*4882a593Smuzhiyun u8 dup_bpsk; 357*4882a593Smuzhiyun u8 dup_qpsk; 358*4882a593Smuzhiyun u8 dup_16qam; 359*4882a593Smuzhiyun u8 dup_64qam; 360*4882a593Smuzhiyun } __packed; 361*4882a593Smuzhiyun 362*4882a593Smuzhiyun /* 363*4882a593Smuzhiyun * Warning: Longbow's structures are bogus. 364*4882a593Smuzhiyun */ 365*4882a593Smuzhiyun struct p54_channel_output_limit_longbow { 366*4882a593Smuzhiyun __le16 rf_power_points[12]; 367*4882a593Smuzhiyun } __packed; 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun struct p54_pa_curve_data_sample_longbow { 370*4882a593Smuzhiyun __le16 rf_power; 371*4882a593Smuzhiyun __le16 pa_detector; 372*4882a593Smuzhiyun struct { 373*4882a593Smuzhiyun __le16 data[4]; 374*4882a593Smuzhiyun } points[3] __packed; 375*4882a593Smuzhiyun } __packed; 376*4882a593Smuzhiyun 377*4882a593Smuzhiyun struct p54_scan_body_longbow { 378*4882a593Smuzhiyun struct p54_channel_output_limit_longbow power_limits; 379*4882a593Smuzhiyun struct p54_pa_curve_data_sample_longbow curve_data[8]; 380*4882a593Smuzhiyun __le16 unkn[6]; /* maybe more power_limits or rate_mask */ 381*4882a593Smuzhiyun } __packed; 382*4882a593Smuzhiyun 383*4882a593Smuzhiyun union p54_scan_body_union { 384*4882a593Smuzhiyun struct p54_scan_body normal; 385*4882a593Smuzhiyun struct p54_scan_body_longbow longbow; 386*4882a593Smuzhiyun } __packed; 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun struct p54_scan_tail_rate { 389*4882a593Smuzhiyun __le32 basic_rate_mask; 390*4882a593Smuzhiyun u8 rts_rates[8]; 391*4882a593Smuzhiyun } __packed; 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun struct p54_led { 394*4882a593Smuzhiyun __le16 flags; 395*4882a593Smuzhiyun __le16 mask[2]; 396*4882a593Smuzhiyun __le16 delay[2]; 397*4882a593Smuzhiyun } __packed; 398*4882a593Smuzhiyun 399*4882a593Smuzhiyun struct p54_edcf { 400*4882a593Smuzhiyun u8 flags; 401*4882a593Smuzhiyun u8 slottime; 402*4882a593Smuzhiyun u8 sifs; 403*4882a593Smuzhiyun u8 eofpad; 404*4882a593Smuzhiyun struct p54_edcf_queue_param queue[8]; 405*4882a593Smuzhiyun u8 mapping[4]; 406*4882a593Smuzhiyun __le16 frameburst; 407*4882a593Smuzhiyun __le16 round_trip_delay; 408*4882a593Smuzhiyun } __packed; 409*4882a593Smuzhiyun 410*4882a593Smuzhiyun struct p54_statistics { 411*4882a593Smuzhiyun __le32 rx_success; 412*4882a593Smuzhiyun __le32 rx_bad_fcs; 413*4882a593Smuzhiyun __le32 rx_abort; 414*4882a593Smuzhiyun __le32 rx_abort_phy; 415*4882a593Smuzhiyun __le32 rts_success; 416*4882a593Smuzhiyun __le32 rts_fail; 417*4882a593Smuzhiyun __le32 tsf32; 418*4882a593Smuzhiyun __le32 airtime; 419*4882a593Smuzhiyun __le32 noise; 420*4882a593Smuzhiyun __le32 sample_noise[8]; 421*4882a593Smuzhiyun __le32 sample_cca; 422*4882a593Smuzhiyun __le32 sample_tx; 423*4882a593Smuzhiyun } __packed; 424*4882a593Smuzhiyun 425*4882a593Smuzhiyun struct p54_xbow_synth { 426*4882a593Smuzhiyun __le16 magic1; 427*4882a593Smuzhiyun __le16 magic2; 428*4882a593Smuzhiyun __le16 freq; 429*4882a593Smuzhiyun u32 padding[5]; 430*4882a593Smuzhiyun } __packed; 431*4882a593Smuzhiyun 432*4882a593Smuzhiyun struct p54_timer { 433*4882a593Smuzhiyun __le32 interval; 434*4882a593Smuzhiyun } __packed; 435*4882a593Smuzhiyun 436*4882a593Smuzhiyun struct p54_keycache { 437*4882a593Smuzhiyun u8 entry; 438*4882a593Smuzhiyun u8 key_id; 439*4882a593Smuzhiyun u8 mac[ETH_ALEN]; 440*4882a593Smuzhiyun u8 padding[2]; 441*4882a593Smuzhiyun u8 key_type; 442*4882a593Smuzhiyun u8 key_len; 443*4882a593Smuzhiyun u8 key[24]; 444*4882a593Smuzhiyun } __packed; 445*4882a593Smuzhiyun 446*4882a593Smuzhiyun struct p54_burst { 447*4882a593Smuzhiyun u8 flags; 448*4882a593Smuzhiyun u8 queue; 449*4882a593Smuzhiyun u8 backlog; 450*4882a593Smuzhiyun u8 pad; 451*4882a593Smuzhiyun __le16 durations[32]; 452*4882a593Smuzhiyun } __packed; 453*4882a593Smuzhiyun 454*4882a593Smuzhiyun struct p54_psm_interval { 455*4882a593Smuzhiyun __le16 interval; 456*4882a593Smuzhiyun __le16 periods; 457*4882a593Smuzhiyun } __packed; 458*4882a593Smuzhiyun 459*4882a593Smuzhiyun #define P54_PSM_CAM 0 460*4882a593Smuzhiyun #define P54_PSM BIT(0) 461*4882a593Smuzhiyun #define P54_PSM_DTIM BIT(1) 462*4882a593Smuzhiyun #define P54_PSM_MCBC BIT(2) 463*4882a593Smuzhiyun #define P54_PSM_CHECKSUM BIT(3) 464*4882a593Smuzhiyun #define P54_PSM_SKIP_MORE_DATA BIT(4) 465*4882a593Smuzhiyun #define P54_PSM_BEACON_TIMEOUT BIT(5) 466*4882a593Smuzhiyun #define P54_PSM_HFOSLEEP BIT(6) 467*4882a593Smuzhiyun #define P54_PSM_AUTOSWITCH_SLEEP BIT(7) 468*4882a593Smuzhiyun #define P54_PSM_LPIT BIT(8) 469*4882a593Smuzhiyun #define P54_PSM_BF_UCAST_SKIP BIT(9) 470*4882a593Smuzhiyun #define P54_PSM_BF_MCAST_SKIP BIT(10) 471*4882a593Smuzhiyun 472*4882a593Smuzhiyun struct p54_psm { 473*4882a593Smuzhiyun __le16 mode; 474*4882a593Smuzhiyun __le16 aid; 475*4882a593Smuzhiyun struct p54_psm_interval intervals[4]; 476*4882a593Smuzhiyun u8 beacon_rssi_skip_max; 477*4882a593Smuzhiyun u8 rssi_delta_threshold; 478*4882a593Smuzhiyun u8 nr; 479*4882a593Smuzhiyun u8 exclude[1]; 480*4882a593Smuzhiyun } __packed; 481*4882a593Smuzhiyun 482*4882a593Smuzhiyun #define MC_FILTER_ADDRESS_NUM 4 483*4882a593Smuzhiyun 484*4882a593Smuzhiyun struct p54_group_address_table { 485*4882a593Smuzhiyun __le16 filter_enable; 486*4882a593Smuzhiyun __le16 num_address; 487*4882a593Smuzhiyun u8 mac_list[MC_FILTER_ADDRESS_NUM][ETH_ALEN]; 488*4882a593Smuzhiyun } __packed; 489*4882a593Smuzhiyun 490*4882a593Smuzhiyun struct p54_txcancel { 491*4882a593Smuzhiyun __le32 req_id; 492*4882a593Smuzhiyun } __packed; 493*4882a593Smuzhiyun 494*4882a593Smuzhiyun struct p54_sta_unlock { 495*4882a593Smuzhiyun u8 addr[ETH_ALEN]; 496*4882a593Smuzhiyun u16 padding; 497*4882a593Smuzhiyun } __packed; 498*4882a593Smuzhiyun 499*4882a593Smuzhiyun #define P54_TIM_CLEAR BIT(15) 500*4882a593Smuzhiyun struct p54_tim { 501*4882a593Smuzhiyun u8 count; 502*4882a593Smuzhiyun u8 padding[3]; 503*4882a593Smuzhiyun __le16 entry[8]; 504*4882a593Smuzhiyun } __packed; 505*4882a593Smuzhiyun 506*4882a593Smuzhiyun struct p54_cce_quiet { 507*4882a593Smuzhiyun __le32 period; 508*4882a593Smuzhiyun } __packed; 509*4882a593Smuzhiyun 510*4882a593Smuzhiyun struct p54_bt_balancer { 511*4882a593Smuzhiyun __le16 prio_thresh; 512*4882a593Smuzhiyun __le16 acl_thresh; 513*4882a593Smuzhiyun } __packed; 514*4882a593Smuzhiyun 515*4882a593Smuzhiyun struct p54_arp_table { 516*4882a593Smuzhiyun __le16 filter_enable; 517*4882a593Smuzhiyun u8 ipv4_addr[4]; 518*4882a593Smuzhiyun } __packed; 519*4882a593Smuzhiyun 520*4882a593Smuzhiyun /* LED control */ 521*4882a593Smuzhiyun int p54_set_leds(struct p54_common *priv); 522*4882a593Smuzhiyun int p54_init_leds(struct p54_common *priv); 523*4882a593Smuzhiyun void p54_unregister_leds(struct p54_common *priv); 524*4882a593Smuzhiyun 525*4882a593Smuzhiyun /* xmit functions */ 526*4882a593Smuzhiyun void p54_tx_80211(struct ieee80211_hw *dev, 527*4882a593Smuzhiyun struct ieee80211_tx_control *control, 528*4882a593Smuzhiyun struct sk_buff *skb); 529*4882a593Smuzhiyun int p54_tx_cancel(struct p54_common *priv, __le32 req_id); 530*4882a593Smuzhiyun void p54_tx(struct p54_common *priv, struct sk_buff *skb); 531*4882a593Smuzhiyun 532*4882a593Smuzhiyun /* synth/phy configuration */ 533*4882a593Smuzhiyun int p54_init_xbow_synth(struct p54_common *priv); 534*4882a593Smuzhiyun int p54_scan(struct p54_common *priv, u16 mode, u16 dwell); 535*4882a593Smuzhiyun 536*4882a593Smuzhiyun /* MAC */ 537*4882a593Smuzhiyun int p54_sta_unlock(struct p54_common *priv, u8 *addr); 538*4882a593Smuzhiyun int p54_update_beacon_tim(struct p54_common *priv, u16 aid, bool set); 539*4882a593Smuzhiyun int p54_setup_mac(struct p54_common *priv); 540*4882a593Smuzhiyun int p54_set_ps(struct p54_common *priv); 541*4882a593Smuzhiyun int p54_fetch_statistics(struct p54_common *priv); 542*4882a593Smuzhiyun int p54_set_groupfilter(struct p54_common *priv); 543*4882a593Smuzhiyun 544*4882a593Smuzhiyun /* e/v DCF setup */ 545*4882a593Smuzhiyun int p54_set_edcf(struct p54_common *priv); 546*4882a593Smuzhiyun 547*4882a593Smuzhiyun /* cryptographic engine */ 548*4882a593Smuzhiyun int p54_upload_key(struct p54_common *priv, u8 algo, int slot, 549*4882a593Smuzhiyun u8 idx, u8 len, u8 *addr, u8* key); 550*4882a593Smuzhiyun 551*4882a593Smuzhiyun /* eeprom */ 552*4882a593Smuzhiyun int p54_download_eeprom(struct p54_common *priv, void *buf, 553*4882a593Smuzhiyun u16 offset, u16 len); 554*4882a593Smuzhiyun struct p54_rssi_db_entry *p54_rssi_find(struct p54_common *p, const u16 freq); 555*4882a593Smuzhiyun 556*4882a593Smuzhiyun /* utility */ 557*4882a593Smuzhiyun u8 *p54_find_ie(struct sk_buff *skb, u8 ie); 558*4882a593Smuzhiyun 559*4882a593Smuzhiyun #endif /* LMAC_H */ 560