1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Firmware I/O code for mac80211 Prism54 drivers
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
6*4882a593Smuzhiyun * Copyright (c) 2007-2009, Christian Lamparter <chunkeey@web.de>
7*4882a593Smuzhiyun * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Based on:
10*4882a593Smuzhiyun * - the islsm (softmac prism54) driver, which is:
11*4882a593Smuzhiyun * Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al.
12*4882a593Smuzhiyun * - stlc45xx driver
13*4882a593Smuzhiyun * Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
14*4882a593Smuzhiyun */
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <linux/slab.h>
17*4882a593Smuzhiyun #include <linux/firmware.h>
18*4882a593Smuzhiyun #include <linux/etherdevice.h>
19*4882a593Smuzhiyun #include <linux/export.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include <net/mac80211.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include "p54.h"
24*4882a593Smuzhiyun #include "eeprom.h"
25*4882a593Smuzhiyun #include "lmac.h"
26*4882a593Smuzhiyun
p54_parse_firmware(struct ieee80211_hw * dev,const struct firmware * fw)27*4882a593Smuzhiyun int p54_parse_firmware(struct ieee80211_hw *dev, const struct firmware *fw)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun struct p54_common *priv = dev->priv;
30*4882a593Smuzhiyun struct exp_if *exp_if;
31*4882a593Smuzhiyun struct bootrec *bootrec;
32*4882a593Smuzhiyun u32 *data = (u32 *)fw->data;
33*4882a593Smuzhiyun u32 *end_data = (u32 *)fw->data + (fw->size >> 2);
34*4882a593Smuzhiyun u8 *fw_version = NULL;
35*4882a593Smuzhiyun size_t len;
36*4882a593Smuzhiyun int i;
37*4882a593Smuzhiyun int maxlen;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun if (priv->rx_start)
40*4882a593Smuzhiyun return 0;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun while (data < end_data && *data)
43*4882a593Smuzhiyun data++;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun while (data < end_data && !*data)
46*4882a593Smuzhiyun data++;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun bootrec = (struct bootrec *) data;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun while (bootrec->data <= end_data && (bootrec->data +
51*4882a593Smuzhiyun (len = le32_to_cpu(bootrec->len))) <= end_data) {
52*4882a593Smuzhiyun u32 code = le32_to_cpu(bootrec->code);
53*4882a593Smuzhiyun switch (code) {
54*4882a593Smuzhiyun case BR_CODE_COMPONENT_ID:
55*4882a593Smuzhiyun priv->fw_interface = be32_to_cpup((__be32 *)
56*4882a593Smuzhiyun bootrec->data);
57*4882a593Smuzhiyun switch (priv->fw_interface) {
58*4882a593Smuzhiyun case FW_LM86:
59*4882a593Smuzhiyun case FW_LM20:
60*4882a593Smuzhiyun case FW_LM87: {
61*4882a593Smuzhiyun char *iftype = (char *)bootrec->data;
62*4882a593Smuzhiyun wiphy_info(priv->hw->wiphy,
63*4882a593Smuzhiyun "p54 detected a LM%c%c firmware\n",
64*4882a593Smuzhiyun iftype[2], iftype[3]);
65*4882a593Smuzhiyun break;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun case FW_FMAC:
68*4882a593Smuzhiyun default:
69*4882a593Smuzhiyun wiphy_err(priv->hw->wiphy,
70*4882a593Smuzhiyun "unsupported firmware\n");
71*4882a593Smuzhiyun return -ENODEV;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun break;
74*4882a593Smuzhiyun case BR_CODE_COMPONENT_VERSION:
75*4882a593Smuzhiyun /* 24 bytes should be enough for all firmwares */
76*4882a593Smuzhiyun if (strnlen((unsigned char *) bootrec->data, 24) < 24)
77*4882a593Smuzhiyun fw_version = (unsigned char *) bootrec->data;
78*4882a593Smuzhiyun break;
79*4882a593Smuzhiyun case BR_CODE_DESCR: {
80*4882a593Smuzhiyun struct bootrec_desc *desc =
81*4882a593Smuzhiyun (struct bootrec_desc *)bootrec->data;
82*4882a593Smuzhiyun priv->rx_start = le32_to_cpu(desc->rx_start);
83*4882a593Smuzhiyun /* FIXME add sanity checking */
84*4882a593Smuzhiyun priv->rx_end = le32_to_cpu(desc->rx_end) - 0x3500;
85*4882a593Smuzhiyun priv->headroom = desc->headroom;
86*4882a593Smuzhiyun priv->tailroom = desc->tailroom;
87*4882a593Smuzhiyun priv->privacy_caps = desc->privacy_caps;
88*4882a593Smuzhiyun priv->rx_keycache_size = desc->rx_keycache_size;
89*4882a593Smuzhiyun if (le32_to_cpu(bootrec->len) == 11)
90*4882a593Smuzhiyun priv->rx_mtu = le16_to_cpu(desc->rx_mtu);
91*4882a593Smuzhiyun else
92*4882a593Smuzhiyun priv->rx_mtu = (size_t)
93*4882a593Smuzhiyun 0x620 - priv->tx_hdr_len;
94*4882a593Smuzhiyun maxlen = priv->tx_hdr_len + /* USB devices */
95*4882a593Smuzhiyun sizeof(struct p54_rx_data) +
96*4882a593Smuzhiyun 4 + /* rx alignment */
97*4882a593Smuzhiyun IEEE80211_MAX_FRAG_THRESHOLD;
98*4882a593Smuzhiyun if (priv->rx_mtu > maxlen && PAGE_SIZE == 4096) {
99*4882a593Smuzhiyun printk(KERN_INFO "p54: rx_mtu reduced from %d "
100*4882a593Smuzhiyun "to %d\n", priv->rx_mtu, maxlen);
101*4882a593Smuzhiyun priv->rx_mtu = maxlen;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun break;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun case BR_CODE_EXPOSED_IF:
106*4882a593Smuzhiyun exp_if = (struct exp_if *) bootrec->data;
107*4882a593Smuzhiyun for (i = 0; i < (len * sizeof(*exp_if) / 4); i++)
108*4882a593Smuzhiyun if (exp_if[i].if_id == cpu_to_le16(IF_ID_LMAC))
109*4882a593Smuzhiyun priv->fw_var = le16_to_cpu(exp_if[i].variant);
110*4882a593Smuzhiyun break;
111*4882a593Smuzhiyun case BR_CODE_DEPENDENT_IF:
112*4882a593Smuzhiyun break;
113*4882a593Smuzhiyun case BR_CODE_END_OF_BRA:
114*4882a593Smuzhiyun case LEGACY_BR_CODE_END_OF_BRA:
115*4882a593Smuzhiyun end_data = NULL;
116*4882a593Smuzhiyun break;
117*4882a593Smuzhiyun default:
118*4882a593Smuzhiyun break;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun bootrec = (struct bootrec *)&bootrec->data[len];
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun if (fw_version) {
124*4882a593Smuzhiyun wiphy_info(priv->hw->wiphy,
125*4882a593Smuzhiyun "FW rev %s - Softmac protocol %x.%x\n",
126*4882a593Smuzhiyun fw_version, priv->fw_var >> 8, priv->fw_var & 0xff);
127*4882a593Smuzhiyun snprintf(dev->wiphy->fw_version, sizeof(dev->wiphy->fw_version),
128*4882a593Smuzhiyun "%s - %x.%x", fw_version,
129*4882a593Smuzhiyun priv->fw_var >> 8, priv->fw_var & 0xff);
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun if (priv->fw_var < 0x500)
133*4882a593Smuzhiyun wiphy_info(priv->hw->wiphy,
134*4882a593Smuzhiyun "you are using an obsolete firmware. "
135*4882a593Smuzhiyun "visit http://wireless.wiki.kernel.org/en/users/Drivers/p54 "
136*4882a593Smuzhiyun "and grab one for \"kernel >= 2.6.28\"!\n");
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun if (priv->fw_var >= 0x300) {
139*4882a593Smuzhiyun /* Firmware supports QoS, use it! */
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun if (priv->fw_var >= 0x500) {
142*4882a593Smuzhiyun priv->tx_stats[P54_QUEUE_AC_VO].limit = 16;
143*4882a593Smuzhiyun priv->tx_stats[P54_QUEUE_AC_VI].limit = 16;
144*4882a593Smuzhiyun priv->tx_stats[P54_QUEUE_AC_BE].limit = 16;
145*4882a593Smuzhiyun priv->tx_stats[P54_QUEUE_AC_BK].limit = 16;
146*4882a593Smuzhiyun } else {
147*4882a593Smuzhiyun priv->tx_stats[P54_QUEUE_AC_VO].limit = 3;
148*4882a593Smuzhiyun priv->tx_stats[P54_QUEUE_AC_VI].limit = 4;
149*4882a593Smuzhiyun priv->tx_stats[P54_QUEUE_AC_BE].limit = 3;
150*4882a593Smuzhiyun priv->tx_stats[P54_QUEUE_AC_BK].limit = 2;
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun priv->hw->queues = P54_QUEUE_AC_NUM;
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun wiphy_info(priv->hw->wiphy,
156*4882a593Smuzhiyun "cryptographic accelerator WEP:%s, TKIP:%s, CCMP:%s\n",
157*4882a593Smuzhiyun (priv->privacy_caps & BR_DESC_PRIV_CAP_WEP) ? "YES" : "no",
158*4882a593Smuzhiyun (priv->privacy_caps &
159*4882a593Smuzhiyun (BR_DESC_PRIV_CAP_TKIP | BR_DESC_PRIV_CAP_MICHAEL))
160*4882a593Smuzhiyun ? "YES" : "no",
161*4882a593Smuzhiyun (priv->privacy_caps & BR_DESC_PRIV_CAP_AESCCMP)
162*4882a593Smuzhiyun ? "YES" : "no");
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun if (priv->rx_keycache_size) {
165*4882a593Smuzhiyun /*
166*4882a593Smuzhiyun * NOTE:
167*4882a593Smuzhiyun *
168*4882a593Smuzhiyun * The firmware provides at most 255 (0 - 254) slots
169*4882a593Smuzhiyun * for keys which are then used to offload decryption.
170*4882a593Smuzhiyun * As a result the 255 entry (aka 0xff) can be used
171*4882a593Smuzhiyun * safely by the driver to mark keys that didn't fit
172*4882a593Smuzhiyun * into the full cache. This trick saves us from
173*4882a593Smuzhiyun * keeping a extra list for uploaded keys.
174*4882a593Smuzhiyun */
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun priv->used_rxkeys = kcalloc(BITS_TO_LONGS(priv->rx_keycache_size),
177*4882a593Smuzhiyun sizeof(long),
178*4882a593Smuzhiyun GFP_KERNEL);
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun if (!priv->used_rxkeys)
181*4882a593Smuzhiyun return -ENOMEM;
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun return 0;
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(p54_parse_firmware);
187*4882a593Smuzhiyun
p54_alloc_skb(struct p54_common * priv,u16 hdr_flags,u16 payload_len,u16 type,gfp_t memflags)188*4882a593Smuzhiyun static struct sk_buff *p54_alloc_skb(struct p54_common *priv, u16 hdr_flags,
189*4882a593Smuzhiyun u16 payload_len, u16 type, gfp_t memflags)
190*4882a593Smuzhiyun {
191*4882a593Smuzhiyun struct p54_hdr *hdr;
192*4882a593Smuzhiyun struct sk_buff *skb;
193*4882a593Smuzhiyun size_t frame_len = sizeof(*hdr) + payload_len;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun if (frame_len > P54_MAX_CTRL_FRAME_LEN)
196*4882a593Smuzhiyun return NULL;
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun if (unlikely(skb_queue_len(&priv->tx_pending) > 64))
199*4882a593Smuzhiyun return NULL;
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun skb = __dev_alloc_skb(priv->tx_hdr_len + frame_len, memflags);
202*4882a593Smuzhiyun if (!skb)
203*4882a593Smuzhiyun return NULL;
204*4882a593Smuzhiyun skb_reserve(skb, priv->tx_hdr_len);
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun hdr = skb_put(skb, sizeof(*hdr));
207*4882a593Smuzhiyun hdr->flags = cpu_to_le16(hdr_flags);
208*4882a593Smuzhiyun hdr->len = cpu_to_le16(payload_len);
209*4882a593Smuzhiyun hdr->type = cpu_to_le16(type);
210*4882a593Smuzhiyun hdr->tries = hdr->rts_tries = 0;
211*4882a593Smuzhiyun return skb;
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun
p54_download_eeprom(struct p54_common * priv,void * buf,u16 offset,u16 len)214*4882a593Smuzhiyun int p54_download_eeprom(struct p54_common *priv, void *buf,
215*4882a593Smuzhiyun u16 offset, u16 len)
216*4882a593Smuzhiyun {
217*4882a593Smuzhiyun struct p54_eeprom_lm86 *eeprom_hdr;
218*4882a593Smuzhiyun struct sk_buff *skb;
219*4882a593Smuzhiyun size_t eeprom_hdr_size;
220*4882a593Smuzhiyun int ret = 0;
221*4882a593Smuzhiyun long timeout;
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun if (priv->fw_var >= 0x509)
224*4882a593Smuzhiyun eeprom_hdr_size = sizeof(*eeprom_hdr);
225*4882a593Smuzhiyun else
226*4882a593Smuzhiyun eeprom_hdr_size = 0x4;
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun skb = p54_alloc_skb(priv, P54_HDR_FLAG_CONTROL, eeprom_hdr_size +
229*4882a593Smuzhiyun len, P54_CONTROL_TYPE_EEPROM_READBACK,
230*4882a593Smuzhiyun GFP_KERNEL);
231*4882a593Smuzhiyun if (unlikely(!skb))
232*4882a593Smuzhiyun return -ENOMEM;
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun mutex_lock(&priv->eeprom_mutex);
235*4882a593Smuzhiyun priv->eeprom = buf;
236*4882a593Smuzhiyun eeprom_hdr = skb_put(skb, eeprom_hdr_size + len);
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun if (priv->fw_var < 0x509) {
239*4882a593Smuzhiyun eeprom_hdr->v1.offset = cpu_to_le16(offset);
240*4882a593Smuzhiyun eeprom_hdr->v1.len = cpu_to_le16(len);
241*4882a593Smuzhiyun } else {
242*4882a593Smuzhiyun eeprom_hdr->v2.offset = cpu_to_le32(offset);
243*4882a593Smuzhiyun eeprom_hdr->v2.len = cpu_to_le16(len);
244*4882a593Smuzhiyun eeprom_hdr->v2.magic2 = 0xf;
245*4882a593Smuzhiyun memcpy(eeprom_hdr->v2.magic, (const char *)"LOCK", 4);
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun p54_tx(priv, skb);
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun timeout = wait_for_completion_interruptible_timeout(
251*4882a593Smuzhiyun &priv->eeprom_comp, HZ);
252*4882a593Smuzhiyun if (timeout <= 0) {
253*4882a593Smuzhiyun wiphy_err(priv->hw->wiphy,
254*4882a593Smuzhiyun "device does not respond or signal received!\n");
255*4882a593Smuzhiyun ret = -EBUSY;
256*4882a593Smuzhiyun }
257*4882a593Smuzhiyun priv->eeprom = NULL;
258*4882a593Smuzhiyun mutex_unlock(&priv->eeprom_mutex);
259*4882a593Smuzhiyun return ret;
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun
p54_update_beacon_tim(struct p54_common * priv,u16 aid,bool set)262*4882a593Smuzhiyun int p54_update_beacon_tim(struct p54_common *priv, u16 aid, bool set)
263*4882a593Smuzhiyun {
264*4882a593Smuzhiyun struct sk_buff *skb;
265*4882a593Smuzhiyun struct p54_tim *tim;
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun skb = p54_alloc_skb(priv, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*tim),
268*4882a593Smuzhiyun P54_CONTROL_TYPE_TIM, GFP_ATOMIC);
269*4882a593Smuzhiyun if (unlikely(!skb))
270*4882a593Smuzhiyun return -ENOMEM;
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun tim = skb_put(skb, sizeof(*tim));
273*4882a593Smuzhiyun tim->count = 1;
274*4882a593Smuzhiyun tim->entry[0] = cpu_to_le16(set ? (aid | 0x8000) : aid);
275*4882a593Smuzhiyun p54_tx(priv, skb);
276*4882a593Smuzhiyun return 0;
277*4882a593Smuzhiyun }
278*4882a593Smuzhiyun
p54_sta_unlock(struct p54_common * priv,u8 * addr)279*4882a593Smuzhiyun int p54_sta_unlock(struct p54_common *priv, u8 *addr)
280*4882a593Smuzhiyun {
281*4882a593Smuzhiyun struct sk_buff *skb;
282*4882a593Smuzhiyun struct p54_sta_unlock *sta;
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun skb = p54_alloc_skb(priv, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*sta),
285*4882a593Smuzhiyun P54_CONTROL_TYPE_PSM_STA_UNLOCK, GFP_ATOMIC);
286*4882a593Smuzhiyun if (unlikely(!skb))
287*4882a593Smuzhiyun return -ENOMEM;
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun sta = skb_put(skb, sizeof(*sta));
290*4882a593Smuzhiyun memcpy(sta->addr, addr, ETH_ALEN);
291*4882a593Smuzhiyun p54_tx(priv, skb);
292*4882a593Smuzhiyun return 0;
293*4882a593Smuzhiyun }
294*4882a593Smuzhiyun
p54_tx_cancel(struct p54_common * priv,__le32 req_id)295*4882a593Smuzhiyun int p54_tx_cancel(struct p54_common *priv, __le32 req_id)
296*4882a593Smuzhiyun {
297*4882a593Smuzhiyun struct sk_buff *skb;
298*4882a593Smuzhiyun struct p54_txcancel *cancel;
299*4882a593Smuzhiyun u32 _req_id = le32_to_cpu(req_id);
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun if (unlikely(_req_id < priv->rx_start || _req_id > priv->rx_end))
302*4882a593Smuzhiyun return -EINVAL;
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun skb = p54_alloc_skb(priv, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*cancel),
305*4882a593Smuzhiyun P54_CONTROL_TYPE_TXCANCEL, GFP_ATOMIC);
306*4882a593Smuzhiyun if (unlikely(!skb))
307*4882a593Smuzhiyun return -ENOMEM;
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun cancel = skb_put(skb, sizeof(*cancel));
310*4882a593Smuzhiyun cancel->req_id = req_id;
311*4882a593Smuzhiyun p54_tx(priv, skb);
312*4882a593Smuzhiyun return 0;
313*4882a593Smuzhiyun }
314*4882a593Smuzhiyun
p54_setup_mac(struct p54_common * priv)315*4882a593Smuzhiyun int p54_setup_mac(struct p54_common *priv)
316*4882a593Smuzhiyun {
317*4882a593Smuzhiyun struct sk_buff *skb;
318*4882a593Smuzhiyun struct p54_setup_mac *setup;
319*4882a593Smuzhiyun u16 mode;
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun skb = p54_alloc_skb(priv, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*setup),
322*4882a593Smuzhiyun P54_CONTROL_TYPE_SETUP, GFP_ATOMIC);
323*4882a593Smuzhiyun if (!skb)
324*4882a593Smuzhiyun return -ENOMEM;
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun setup = skb_put(skb, sizeof(*setup));
327*4882a593Smuzhiyun if (!(priv->hw->conf.flags & IEEE80211_CONF_IDLE)) {
328*4882a593Smuzhiyun switch (priv->mode) {
329*4882a593Smuzhiyun case NL80211_IFTYPE_STATION:
330*4882a593Smuzhiyun mode = P54_FILTER_TYPE_STATION;
331*4882a593Smuzhiyun break;
332*4882a593Smuzhiyun case NL80211_IFTYPE_AP:
333*4882a593Smuzhiyun mode = P54_FILTER_TYPE_AP;
334*4882a593Smuzhiyun break;
335*4882a593Smuzhiyun case NL80211_IFTYPE_ADHOC:
336*4882a593Smuzhiyun case NL80211_IFTYPE_MESH_POINT:
337*4882a593Smuzhiyun mode = P54_FILTER_TYPE_IBSS;
338*4882a593Smuzhiyun break;
339*4882a593Smuzhiyun case NL80211_IFTYPE_MONITOR:
340*4882a593Smuzhiyun mode = P54_FILTER_TYPE_PROMISCUOUS;
341*4882a593Smuzhiyun break;
342*4882a593Smuzhiyun default:
343*4882a593Smuzhiyun mode = P54_FILTER_TYPE_HIBERNATE;
344*4882a593Smuzhiyun break;
345*4882a593Smuzhiyun }
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun /*
348*4882a593Smuzhiyun * "TRANSPARENT and PROMISCUOUS are mutually exclusive"
349*4882a593Smuzhiyun * STSW45X0C LMAC API - page 12
350*4882a593Smuzhiyun */
351*4882a593Smuzhiyun if (priv->filter_flags & FIF_OTHER_BSS &&
352*4882a593Smuzhiyun (mode != P54_FILTER_TYPE_PROMISCUOUS))
353*4882a593Smuzhiyun mode |= P54_FILTER_TYPE_TRANSPARENT;
354*4882a593Smuzhiyun } else {
355*4882a593Smuzhiyun mode = P54_FILTER_TYPE_HIBERNATE;
356*4882a593Smuzhiyun }
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun setup->mac_mode = cpu_to_le16(mode);
359*4882a593Smuzhiyun memcpy(setup->mac_addr, priv->mac_addr, ETH_ALEN);
360*4882a593Smuzhiyun memcpy(setup->bssid, priv->bssid, ETH_ALEN);
361*4882a593Smuzhiyun setup->rx_antenna = 2 & priv->rx_diversity_mask; /* automatic */
362*4882a593Smuzhiyun setup->rx_align = 0;
363*4882a593Smuzhiyun if (priv->fw_var < 0x500) {
364*4882a593Smuzhiyun setup->v1.basic_rate_mask = cpu_to_le32(priv->basic_rate_mask);
365*4882a593Smuzhiyun memset(setup->v1.rts_rates, 0, 8);
366*4882a593Smuzhiyun setup->v1.rx_addr = cpu_to_le32(priv->rx_end);
367*4882a593Smuzhiyun setup->v1.max_rx = cpu_to_le16(priv->rx_mtu);
368*4882a593Smuzhiyun setup->v1.rxhw = cpu_to_le16(priv->rxhw);
369*4882a593Smuzhiyun setup->v1.wakeup_timer = cpu_to_le16(priv->wakeup_timer);
370*4882a593Smuzhiyun setup->v1.unalloc0 = cpu_to_le16(0);
371*4882a593Smuzhiyun } else {
372*4882a593Smuzhiyun setup->v2.rx_addr = cpu_to_le32(priv->rx_end);
373*4882a593Smuzhiyun setup->v2.max_rx = cpu_to_le16(priv->rx_mtu);
374*4882a593Smuzhiyun setup->v2.rxhw = cpu_to_le16(priv->rxhw);
375*4882a593Smuzhiyun setup->v2.timer = cpu_to_le16(priv->wakeup_timer);
376*4882a593Smuzhiyun setup->v2.truncate = cpu_to_le16(48896);
377*4882a593Smuzhiyun setup->v2.basic_rate_mask = cpu_to_le32(priv->basic_rate_mask);
378*4882a593Smuzhiyun setup->v2.sbss_offset = 0;
379*4882a593Smuzhiyun setup->v2.mcast_window = 0;
380*4882a593Smuzhiyun setup->v2.rx_rssi_threshold = 0;
381*4882a593Smuzhiyun setup->v2.rx_ed_threshold = 0;
382*4882a593Smuzhiyun setup->v2.ref_clock = cpu_to_le32(644245094);
383*4882a593Smuzhiyun setup->v2.lpf_bandwidth = cpu_to_le16(65535);
384*4882a593Smuzhiyun setup->v2.osc_start_delay = cpu_to_le16(65535);
385*4882a593Smuzhiyun }
386*4882a593Smuzhiyun p54_tx(priv, skb);
387*4882a593Smuzhiyun priv->phy_idle = mode == P54_FILTER_TYPE_HIBERNATE;
388*4882a593Smuzhiyun return 0;
389*4882a593Smuzhiyun }
390*4882a593Smuzhiyun
p54_scan(struct p54_common * priv,u16 mode,u16 dwell)391*4882a593Smuzhiyun int p54_scan(struct p54_common *priv, u16 mode, u16 dwell)
392*4882a593Smuzhiyun {
393*4882a593Smuzhiyun struct sk_buff *skb;
394*4882a593Smuzhiyun struct p54_hdr *hdr;
395*4882a593Smuzhiyun struct p54_scan_head *head;
396*4882a593Smuzhiyun struct p54_iq_autocal_entry *iq_autocal;
397*4882a593Smuzhiyun union p54_scan_body_union *body;
398*4882a593Smuzhiyun struct p54_scan_tail_rate *rate;
399*4882a593Smuzhiyun struct pda_rssi_cal_entry *rssi;
400*4882a593Smuzhiyun struct p54_rssi_db_entry *rssi_data;
401*4882a593Smuzhiyun unsigned int i;
402*4882a593Smuzhiyun void *entry;
403*4882a593Smuzhiyun __le16 freq = cpu_to_le16(priv->hw->conf.chandef.chan->center_freq);
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun skb = p54_alloc_skb(priv, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*head) +
406*4882a593Smuzhiyun 2 + sizeof(*iq_autocal) + sizeof(*body) +
407*4882a593Smuzhiyun sizeof(*rate) + 2 * sizeof(*rssi),
408*4882a593Smuzhiyun P54_CONTROL_TYPE_SCAN, GFP_ATOMIC);
409*4882a593Smuzhiyun if (!skb)
410*4882a593Smuzhiyun return -ENOMEM;
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun head = skb_put(skb, sizeof(*head));
413*4882a593Smuzhiyun memset(head->scan_params, 0, sizeof(head->scan_params));
414*4882a593Smuzhiyun head->mode = cpu_to_le16(mode);
415*4882a593Smuzhiyun head->dwell = cpu_to_le16(dwell);
416*4882a593Smuzhiyun head->freq = freq;
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun if (priv->rxhw == PDR_SYNTH_FRONTEND_LONGBOW) {
419*4882a593Smuzhiyun __le16 *pa_power_points = skb_put(skb, 2);
420*4882a593Smuzhiyun *pa_power_points = cpu_to_le16(0x0c);
421*4882a593Smuzhiyun }
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun iq_autocal = skb_put(skb, sizeof(*iq_autocal));
424*4882a593Smuzhiyun for (i = 0; i < priv->iq_autocal_len; i++) {
425*4882a593Smuzhiyun if (priv->iq_autocal[i].freq != freq)
426*4882a593Smuzhiyun continue;
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun memcpy(iq_autocal, &priv->iq_autocal[i].params,
429*4882a593Smuzhiyun sizeof(struct p54_iq_autocal_entry));
430*4882a593Smuzhiyun break;
431*4882a593Smuzhiyun }
432*4882a593Smuzhiyun if (i == priv->iq_autocal_len)
433*4882a593Smuzhiyun goto err;
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun if (priv->rxhw == PDR_SYNTH_FRONTEND_LONGBOW)
436*4882a593Smuzhiyun body = skb_put(skb, sizeof(body->longbow));
437*4882a593Smuzhiyun else
438*4882a593Smuzhiyun body = skb_put(skb, sizeof(body->normal));
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun for (i = 0; i < priv->output_limit->entries; i++) {
441*4882a593Smuzhiyun __le16 *entry_freq = (void *) (priv->output_limit->data +
442*4882a593Smuzhiyun priv->output_limit->entry_size * i);
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun if (*entry_freq != freq)
445*4882a593Smuzhiyun continue;
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun if (priv->rxhw == PDR_SYNTH_FRONTEND_LONGBOW) {
448*4882a593Smuzhiyun memcpy(&body->longbow.power_limits,
449*4882a593Smuzhiyun (void *) entry_freq + sizeof(__le16),
450*4882a593Smuzhiyun priv->output_limit->entry_size);
451*4882a593Smuzhiyun } else {
452*4882a593Smuzhiyun struct pda_channel_output_limit *limits =
453*4882a593Smuzhiyun (void *) entry_freq;
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun body->normal.val_barker = 0x38;
456*4882a593Smuzhiyun body->normal.val_bpsk = body->normal.dup_bpsk =
457*4882a593Smuzhiyun limits->val_bpsk;
458*4882a593Smuzhiyun body->normal.val_qpsk = body->normal.dup_qpsk =
459*4882a593Smuzhiyun limits->val_qpsk;
460*4882a593Smuzhiyun body->normal.val_16qam = body->normal.dup_16qam =
461*4882a593Smuzhiyun limits->val_16qam;
462*4882a593Smuzhiyun body->normal.val_64qam = body->normal.dup_64qam =
463*4882a593Smuzhiyun limits->val_64qam;
464*4882a593Smuzhiyun }
465*4882a593Smuzhiyun break;
466*4882a593Smuzhiyun }
467*4882a593Smuzhiyun if (i == priv->output_limit->entries)
468*4882a593Smuzhiyun goto err;
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun entry = (void *)(priv->curve_data->data + priv->curve_data->offset);
471*4882a593Smuzhiyun for (i = 0; i < priv->curve_data->entries; i++) {
472*4882a593Smuzhiyun if (*((__le16 *)entry) != freq) {
473*4882a593Smuzhiyun entry += priv->curve_data->entry_size;
474*4882a593Smuzhiyun continue;
475*4882a593Smuzhiyun }
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun if (priv->rxhw == PDR_SYNTH_FRONTEND_LONGBOW) {
478*4882a593Smuzhiyun memcpy(&body->longbow.curve_data,
479*4882a593Smuzhiyun entry + sizeof(__le16),
480*4882a593Smuzhiyun priv->curve_data->entry_size);
481*4882a593Smuzhiyun } else {
482*4882a593Smuzhiyun struct p54_scan_body *chan = &body->normal;
483*4882a593Smuzhiyun struct pda_pa_curve_data *curve_data =
484*4882a593Smuzhiyun (void *) priv->curve_data->data;
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun entry += sizeof(__le16);
487*4882a593Smuzhiyun chan->pa_points_per_curve = 8;
488*4882a593Smuzhiyun memset(chan->curve_data, 0, sizeof(chan->curve_data));
489*4882a593Smuzhiyun memcpy(chan->curve_data, entry,
490*4882a593Smuzhiyun sizeof(struct p54_pa_curve_data_sample) *
491*4882a593Smuzhiyun min((u8)8, curve_data->points_per_channel));
492*4882a593Smuzhiyun }
493*4882a593Smuzhiyun break;
494*4882a593Smuzhiyun }
495*4882a593Smuzhiyun if (i == priv->curve_data->entries)
496*4882a593Smuzhiyun goto err;
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun if ((priv->fw_var >= 0x500) && (priv->fw_var < 0x509)) {
499*4882a593Smuzhiyun rate = skb_put(skb, sizeof(*rate));
500*4882a593Smuzhiyun rate->basic_rate_mask = cpu_to_le32(priv->basic_rate_mask);
501*4882a593Smuzhiyun for (i = 0; i < sizeof(rate->rts_rates); i++)
502*4882a593Smuzhiyun rate->rts_rates[i] = i;
503*4882a593Smuzhiyun }
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun rssi = skb_put(skb, sizeof(*rssi));
506*4882a593Smuzhiyun rssi_data = p54_rssi_find(priv, le16_to_cpu(freq));
507*4882a593Smuzhiyun rssi->mul = cpu_to_le16(rssi_data->mul);
508*4882a593Smuzhiyun rssi->add = cpu_to_le16(rssi_data->add);
509*4882a593Smuzhiyun if (priv->rxhw == PDR_SYNTH_FRONTEND_LONGBOW) {
510*4882a593Smuzhiyun /* Longbow frontend needs ever more */
511*4882a593Smuzhiyun rssi = skb_put(skb, sizeof(*rssi));
512*4882a593Smuzhiyun rssi->mul = cpu_to_le16(rssi_data->longbow_unkn);
513*4882a593Smuzhiyun rssi->add = cpu_to_le16(rssi_data->longbow_unk2);
514*4882a593Smuzhiyun }
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun if (priv->fw_var >= 0x509) {
517*4882a593Smuzhiyun rate = skb_put(skb, sizeof(*rate));
518*4882a593Smuzhiyun rate->basic_rate_mask = cpu_to_le32(priv->basic_rate_mask);
519*4882a593Smuzhiyun for (i = 0; i < sizeof(rate->rts_rates); i++)
520*4882a593Smuzhiyun rate->rts_rates[i] = i;
521*4882a593Smuzhiyun }
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun hdr = (struct p54_hdr *) skb->data;
524*4882a593Smuzhiyun hdr->len = cpu_to_le16(skb->len - sizeof(*hdr));
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun p54_tx(priv, skb);
527*4882a593Smuzhiyun priv->cur_rssi = rssi_data;
528*4882a593Smuzhiyun return 0;
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun err:
531*4882a593Smuzhiyun wiphy_err(priv->hw->wiphy, "frequency change to channel %d failed.\n",
532*4882a593Smuzhiyun ieee80211_frequency_to_channel(
533*4882a593Smuzhiyun priv->hw->conf.chandef.chan->center_freq));
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun dev_kfree_skb_any(skb);
536*4882a593Smuzhiyun return -EINVAL;
537*4882a593Smuzhiyun }
538*4882a593Smuzhiyun
p54_set_leds(struct p54_common * priv)539*4882a593Smuzhiyun int p54_set_leds(struct p54_common *priv)
540*4882a593Smuzhiyun {
541*4882a593Smuzhiyun struct sk_buff *skb;
542*4882a593Smuzhiyun struct p54_led *led;
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun skb = p54_alloc_skb(priv, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*led),
545*4882a593Smuzhiyun P54_CONTROL_TYPE_LED, GFP_ATOMIC);
546*4882a593Smuzhiyun if (unlikely(!skb))
547*4882a593Smuzhiyun return -ENOMEM;
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun led = skb_put(skb, sizeof(*led));
550*4882a593Smuzhiyun led->flags = cpu_to_le16(0x0003);
551*4882a593Smuzhiyun led->mask[0] = led->mask[1] = cpu_to_le16(priv->softled_state);
552*4882a593Smuzhiyun led->delay[0] = cpu_to_le16(1);
553*4882a593Smuzhiyun led->delay[1] = cpu_to_le16(0);
554*4882a593Smuzhiyun p54_tx(priv, skb);
555*4882a593Smuzhiyun return 0;
556*4882a593Smuzhiyun }
557*4882a593Smuzhiyun
p54_set_edcf(struct p54_common * priv)558*4882a593Smuzhiyun int p54_set_edcf(struct p54_common *priv)
559*4882a593Smuzhiyun {
560*4882a593Smuzhiyun struct sk_buff *skb;
561*4882a593Smuzhiyun struct p54_edcf *edcf;
562*4882a593Smuzhiyun u8 rtd;
563*4882a593Smuzhiyun
564*4882a593Smuzhiyun skb = p54_alloc_skb(priv, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*edcf),
565*4882a593Smuzhiyun P54_CONTROL_TYPE_DCFINIT, GFP_ATOMIC);
566*4882a593Smuzhiyun if (unlikely(!skb))
567*4882a593Smuzhiyun return -ENOMEM;
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun edcf = skb_put(skb, sizeof(*edcf));
570*4882a593Smuzhiyun if (priv->use_short_slot) {
571*4882a593Smuzhiyun edcf->slottime = 9;
572*4882a593Smuzhiyun edcf->sifs = 0x10;
573*4882a593Smuzhiyun edcf->eofpad = 0x00;
574*4882a593Smuzhiyun } else {
575*4882a593Smuzhiyun edcf->slottime = 20;
576*4882a593Smuzhiyun edcf->sifs = 0x0a;
577*4882a593Smuzhiyun edcf->eofpad = 0x06;
578*4882a593Smuzhiyun }
579*4882a593Smuzhiyun /*
580*4882a593Smuzhiyun * calculate the extra round trip delay according to the
581*4882a593Smuzhiyun * formula from 802.11-2007 17.3.8.6.
582*4882a593Smuzhiyun */
583*4882a593Smuzhiyun rtd = 3 * priv->coverage_class;
584*4882a593Smuzhiyun edcf->slottime += rtd;
585*4882a593Smuzhiyun edcf->round_trip_delay = cpu_to_le16(rtd);
586*4882a593Smuzhiyun /* (see prism54/isl_oid.h for further details) */
587*4882a593Smuzhiyun edcf->frameburst = cpu_to_le16(0);
588*4882a593Smuzhiyun edcf->flags = 0;
589*4882a593Smuzhiyun memset(edcf->mapping, 0, sizeof(edcf->mapping));
590*4882a593Smuzhiyun memcpy(edcf->queue, priv->qos_params, sizeof(edcf->queue));
591*4882a593Smuzhiyun p54_tx(priv, skb);
592*4882a593Smuzhiyun return 0;
593*4882a593Smuzhiyun }
594*4882a593Smuzhiyun
p54_set_ps(struct p54_common * priv)595*4882a593Smuzhiyun int p54_set_ps(struct p54_common *priv)
596*4882a593Smuzhiyun {
597*4882a593Smuzhiyun struct sk_buff *skb;
598*4882a593Smuzhiyun struct p54_psm *psm;
599*4882a593Smuzhiyun unsigned int i;
600*4882a593Smuzhiyun u16 mode;
601*4882a593Smuzhiyun
602*4882a593Smuzhiyun if (priv->hw->conf.flags & IEEE80211_CONF_PS &&
603*4882a593Smuzhiyun !priv->powersave_override)
604*4882a593Smuzhiyun mode = P54_PSM | P54_PSM_BEACON_TIMEOUT | P54_PSM_DTIM |
605*4882a593Smuzhiyun P54_PSM_CHECKSUM | P54_PSM_MCBC;
606*4882a593Smuzhiyun else
607*4882a593Smuzhiyun mode = P54_PSM_CAM;
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun skb = p54_alloc_skb(priv, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*psm),
610*4882a593Smuzhiyun P54_CONTROL_TYPE_PSM, GFP_ATOMIC);
611*4882a593Smuzhiyun if (!skb)
612*4882a593Smuzhiyun return -ENOMEM;
613*4882a593Smuzhiyun
614*4882a593Smuzhiyun psm = skb_put(skb, sizeof(*psm));
615*4882a593Smuzhiyun psm->mode = cpu_to_le16(mode);
616*4882a593Smuzhiyun psm->aid = cpu_to_le16(priv->aid);
617*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(psm->intervals); i++) {
618*4882a593Smuzhiyun psm->intervals[i].interval =
619*4882a593Smuzhiyun cpu_to_le16(priv->hw->conf.listen_interval);
620*4882a593Smuzhiyun psm->intervals[i].periods = cpu_to_le16(1);
621*4882a593Smuzhiyun }
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun psm->beacon_rssi_skip_max = 200;
624*4882a593Smuzhiyun psm->rssi_delta_threshold = 0;
625*4882a593Smuzhiyun psm->nr = 1;
626*4882a593Smuzhiyun psm->exclude[0] = WLAN_EID_TIM;
627*4882a593Smuzhiyun
628*4882a593Smuzhiyun p54_tx(priv, skb);
629*4882a593Smuzhiyun priv->phy_ps = mode != P54_PSM_CAM;
630*4882a593Smuzhiyun return 0;
631*4882a593Smuzhiyun }
632*4882a593Smuzhiyun
p54_init_xbow_synth(struct p54_common * priv)633*4882a593Smuzhiyun int p54_init_xbow_synth(struct p54_common *priv)
634*4882a593Smuzhiyun {
635*4882a593Smuzhiyun struct sk_buff *skb;
636*4882a593Smuzhiyun struct p54_xbow_synth *xbow;
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun skb = p54_alloc_skb(priv, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*xbow),
639*4882a593Smuzhiyun P54_CONTROL_TYPE_XBOW_SYNTH_CFG, GFP_KERNEL);
640*4882a593Smuzhiyun if (unlikely(!skb))
641*4882a593Smuzhiyun return -ENOMEM;
642*4882a593Smuzhiyun
643*4882a593Smuzhiyun xbow = skb_put(skb, sizeof(*xbow));
644*4882a593Smuzhiyun xbow->magic1 = cpu_to_le16(0x1);
645*4882a593Smuzhiyun xbow->magic2 = cpu_to_le16(0x2);
646*4882a593Smuzhiyun xbow->freq = cpu_to_le16(5390);
647*4882a593Smuzhiyun memset(xbow->padding, 0, sizeof(xbow->padding));
648*4882a593Smuzhiyun p54_tx(priv, skb);
649*4882a593Smuzhiyun return 0;
650*4882a593Smuzhiyun }
651*4882a593Smuzhiyun
p54_upload_key(struct p54_common * priv,u8 algo,int slot,u8 idx,u8 len,u8 * addr,u8 * key)652*4882a593Smuzhiyun int p54_upload_key(struct p54_common *priv, u8 algo, int slot, u8 idx, u8 len,
653*4882a593Smuzhiyun u8 *addr, u8* key)
654*4882a593Smuzhiyun {
655*4882a593Smuzhiyun struct sk_buff *skb;
656*4882a593Smuzhiyun struct p54_keycache *rxkey;
657*4882a593Smuzhiyun
658*4882a593Smuzhiyun skb = p54_alloc_skb(priv, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*rxkey),
659*4882a593Smuzhiyun P54_CONTROL_TYPE_RX_KEYCACHE, GFP_KERNEL);
660*4882a593Smuzhiyun if (unlikely(!skb))
661*4882a593Smuzhiyun return -ENOMEM;
662*4882a593Smuzhiyun
663*4882a593Smuzhiyun rxkey = skb_put(skb, sizeof(*rxkey));
664*4882a593Smuzhiyun rxkey->entry = slot;
665*4882a593Smuzhiyun rxkey->key_id = idx;
666*4882a593Smuzhiyun rxkey->key_type = algo;
667*4882a593Smuzhiyun if (addr)
668*4882a593Smuzhiyun memcpy(rxkey->mac, addr, ETH_ALEN);
669*4882a593Smuzhiyun else
670*4882a593Smuzhiyun eth_broadcast_addr(rxkey->mac);
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun switch (algo) {
673*4882a593Smuzhiyun case P54_CRYPTO_WEP:
674*4882a593Smuzhiyun case P54_CRYPTO_AESCCMP:
675*4882a593Smuzhiyun rxkey->key_len = min_t(u8, 16, len);
676*4882a593Smuzhiyun memcpy(rxkey->key, key, rxkey->key_len);
677*4882a593Smuzhiyun break;
678*4882a593Smuzhiyun
679*4882a593Smuzhiyun case P54_CRYPTO_TKIPMICHAEL:
680*4882a593Smuzhiyun rxkey->key_len = 24;
681*4882a593Smuzhiyun memcpy(rxkey->key, key, 16);
682*4882a593Smuzhiyun memcpy(&(rxkey->key[16]), &(key
683*4882a593Smuzhiyun [NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY]), 8);
684*4882a593Smuzhiyun break;
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun case P54_CRYPTO_NONE:
687*4882a593Smuzhiyun rxkey->key_len = 0;
688*4882a593Smuzhiyun memset(rxkey->key, 0, sizeof(rxkey->key));
689*4882a593Smuzhiyun break;
690*4882a593Smuzhiyun
691*4882a593Smuzhiyun default:
692*4882a593Smuzhiyun wiphy_err(priv->hw->wiphy,
693*4882a593Smuzhiyun "invalid cryptographic algorithm: %d\n", algo);
694*4882a593Smuzhiyun dev_kfree_skb(skb);
695*4882a593Smuzhiyun return -EINVAL;
696*4882a593Smuzhiyun }
697*4882a593Smuzhiyun
698*4882a593Smuzhiyun p54_tx(priv, skb);
699*4882a593Smuzhiyun return 0;
700*4882a593Smuzhiyun }
701*4882a593Smuzhiyun
p54_fetch_statistics(struct p54_common * priv)702*4882a593Smuzhiyun int p54_fetch_statistics(struct p54_common *priv)
703*4882a593Smuzhiyun {
704*4882a593Smuzhiyun struct ieee80211_tx_info *txinfo;
705*4882a593Smuzhiyun struct p54_tx_info *p54info;
706*4882a593Smuzhiyun struct sk_buff *skb;
707*4882a593Smuzhiyun
708*4882a593Smuzhiyun skb = p54_alloc_skb(priv, P54_HDR_FLAG_CONTROL,
709*4882a593Smuzhiyun sizeof(struct p54_statistics),
710*4882a593Smuzhiyun P54_CONTROL_TYPE_STAT_READBACK, GFP_KERNEL);
711*4882a593Smuzhiyun if (!skb)
712*4882a593Smuzhiyun return -ENOMEM;
713*4882a593Smuzhiyun
714*4882a593Smuzhiyun /*
715*4882a593Smuzhiyun * The statistic feedback causes some extra headaches here, if it
716*4882a593Smuzhiyun * is not to crash/corrupt the firmware data structures.
717*4882a593Smuzhiyun *
718*4882a593Smuzhiyun * Unlike all other Control Get OIDs we can not use helpers like
719*4882a593Smuzhiyun * skb_put to reserve the space for the data we're requesting.
720*4882a593Smuzhiyun * Instead the extra frame length -which will hold the results later-
721*4882a593Smuzhiyun * will only be told to the p54_assign_address, so that following
722*4882a593Smuzhiyun * frames won't be placed into the allegedly empty area.
723*4882a593Smuzhiyun */
724*4882a593Smuzhiyun txinfo = IEEE80211_SKB_CB(skb);
725*4882a593Smuzhiyun p54info = (void *) txinfo->rate_driver_data;
726*4882a593Smuzhiyun p54info->extra_len = sizeof(struct p54_statistics);
727*4882a593Smuzhiyun
728*4882a593Smuzhiyun p54_tx(priv, skb);
729*4882a593Smuzhiyun return 0;
730*4882a593Smuzhiyun }
731*4882a593Smuzhiyun
p54_set_groupfilter(struct p54_common * priv)732*4882a593Smuzhiyun int p54_set_groupfilter(struct p54_common *priv)
733*4882a593Smuzhiyun {
734*4882a593Smuzhiyun struct p54_group_address_table *grp;
735*4882a593Smuzhiyun struct sk_buff *skb;
736*4882a593Smuzhiyun bool on = false;
737*4882a593Smuzhiyun
738*4882a593Smuzhiyun skb = p54_alloc_skb(priv, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*grp),
739*4882a593Smuzhiyun P54_CONTROL_TYPE_GROUP_ADDRESS_TABLE, GFP_KERNEL);
740*4882a593Smuzhiyun if (!skb)
741*4882a593Smuzhiyun return -ENOMEM;
742*4882a593Smuzhiyun
743*4882a593Smuzhiyun grp = skb_put(skb, sizeof(*grp));
744*4882a593Smuzhiyun
745*4882a593Smuzhiyun on = !(priv->filter_flags & FIF_ALLMULTI) &&
746*4882a593Smuzhiyun (priv->mc_maclist_num > 0 &&
747*4882a593Smuzhiyun priv->mc_maclist_num <= MC_FILTER_ADDRESS_NUM);
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun if (on) {
750*4882a593Smuzhiyun grp->filter_enable = cpu_to_le16(1);
751*4882a593Smuzhiyun grp->num_address = cpu_to_le16(priv->mc_maclist_num);
752*4882a593Smuzhiyun memcpy(grp->mac_list, priv->mc_maclist, sizeof(grp->mac_list));
753*4882a593Smuzhiyun } else {
754*4882a593Smuzhiyun grp->filter_enable = cpu_to_le16(0);
755*4882a593Smuzhiyun grp->num_address = cpu_to_le16(0);
756*4882a593Smuzhiyun memset(grp->mac_list, 0, sizeof(grp->mac_list));
757*4882a593Smuzhiyun }
758*4882a593Smuzhiyun
759*4882a593Smuzhiyun p54_tx(priv, skb);
760*4882a593Smuzhiyun return 0;
761*4882a593Smuzhiyun }
762