1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #ifndef HOSTAP_WLAN_H
3*4882a593Smuzhiyun #define HOSTAP_WLAN_H
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun #include <linux/interrupt.h>
6*4882a593Smuzhiyun #include <linux/wireless.h>
7*4882a593Smuzhiyun #include <linux/netdevice.h>
8*4882a593Smuzhiyun #include <linux/etherdevice.h>
9*4882a593Smuzhiyun #include <linux/mutex.h>
10*4882a593Smuzhiyun #include <linux/refcount.h>
11*4882a593Smuzhiyun #include <net/iw_handler.h>
12*4882a593Smuzhiyun #include <net/ieee80211_radiotap.h>
13*4882a593Smuzhiyun #include <net/lib80211.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include "hostap_config.h"
16*4882a593Smuzhiyun #include "hostap_common.h"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define MAX_PARM_DEVICES 8
19*4882a593Smuzhiyun #define PARM_MIN_MAX "1-" __MODULE_STRING(MAX_PARM_DEVICES)
20*4882a593Smuzhiyun #define DEF_INTS -1, -1, -1, -1, -1, -1, -1
21*4882a593Smuzhiyun #define GET_INT_PARM(var,idx) var[var[idx] < 0 ? 0 : idx]
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* Specific skb->protocol value that indicates that the packet already contains
25*4882a593Smuzhiyun * txdesc header.
26*4882a593Smuzhiyun * FIX: This might need own value that would be allocated especially for Prism2
27*4882a593Smuzhiyun * txdesc; ETH_P_CONTROL is commented as "Card specific control frames".
28*4882a593Smuzhiyun * However, these skb's should have only minimal path in the kernel side since
29*4882a593Smuzhiyun * prism2_send_mgmt() sends these with dev_queue_xmit() to prism2_tx(). */
30*4882a593Smuzhiyun #define ETH_P_HOSTAP ETH_P_CONTROL
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /* ARPHRD_IEEE80211_PRISM uses a bloated version of Prism2 RX frame header
33*4882a593Smuzhiyun * (from linux-wlan-ng) */
34*4882a593Smuzhiyun struct linux_wlan_ng_val {
35*4882a593Smuzhiyun u32 did;
36*4882a593Smuzhiyun u16 status, len;
37*4882a593Smuzhiyun u32 data;
38*4882a593Smuzhiyun } __packed;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun struct linux_wlan_ng_prism_hdr {
41*4882a593Smuzhiyun u32 msgcode, msglen;
42*4882a593Smuzhiyun char devname[16];
43*4882a593Smuzhiyun struct linux_wlan_ng_val hosttime, mactime, channel, rssi, sq, signal,
44*4882a593Smuzhiyun noise, rate, istx, frmlen;
45*4882a593Smuzhiyun } __packed;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun struct linux_wlan_ng_cap_hdr {
48*4882a593Smuzhiyun __be32 version;
49*4882a593Smuzhiyun __be32 length;
50*4882a593Smuzhiyun __be64 mactime;
51*4882a593Smuzhiyun __be64 hosttime;
52*4882a593Smuzhiyun __be32 phytype;
53*4882a593Smuzhiyun __be32 channel;
54*4882a593Smuzhiyun __be32 datarate;
55*4882a593Smuzhiyun __be32 antenna;
56*4882a593Smuzhiyun __be32 priority;
57*4882a593Smuzhiyun __be32 ssi_type;
58*4882a593Smuzhiyun __be32 ssi_signal;
59*4882a593Smuzhiyun __be32 ssi_noise;
60*4882a593Smuzhiyun __be32 preamble;
61*4882a593Smuzhiyun __be32 encoding;
62*4882a593Smuzhiyun } __packed;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun struct hostap_radiotap_rx {
65*4882a593Smuzhiyun struct ieee80211_radiotap_header hdr;
66*4882a593Smuzhiyun __le64 tsft;
67*4882a593Smuzhiyun u8 rate;
68*4882a593Smuzhiyun u8 padding;
69*4882a593Smuzhiyun __le16 chan_freq;
70*4882a593Smuzhiyun __le16 chan_flags;
71*4882a593Smuzhiyun s8 dbm_antsignal;
72*4882a593Smuzhiyun s8 dbm_antnoise;
73*4882a593Smuzhiyun } __packed;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun #define LWNG_CAP_DID_BASE (4 | (1 << 6)) /* section 4, group 1 */
76*4882a593Smuzhiyun #define LWNG_CAPHDR_VERSION 0x80211001
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun struct hfa384x_rx_frame {
79*4882a593Smuzhiyun /* HFA384X RX frame descriptor */
80*4882a593Smuzhiyun __le16 status; /* HFA384X_RX_STATUS_ flags */
81*4882a593Smuzhiyun __le32 time; /* timestamp, 1 microsecond resolution */
82*4882a593Smuzhiyun u8 silence; /* 27 .. 154; seems to be 0 */
83*4882a593Smuzhiyun u8 signal; /* 27 .. 154 */
84*4882a593Smuzhiyun u8 rate; /* 10, 20, 55, or 110 */
85*4882a593Smuzhiyun u8 rxflow;
86*4882a593Smuzhiyun __le32 reserved;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun /* 802.11 */
89*4882a593Smuzhiyun __le16 frame_control;
90*4882a593Smuzhiyun __le16 duration_id;
91*4882a593Smuzhiyun u8 addr1[ETH_ALEN];
92*4882a593Smuzhiyun u8 addr2[ETH_ALEN];
93*4882a593Smuzhiyun u8 addr3[ETH_ALEN];
94*4882a593Smuzhiyun __le16 seq_ctrl;
95*4882a593Smuzhiyun u8 addr4[ETH_ALEN];
96*4882a593Smuzhiyun __le16 data_len;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun /* 802.3 */
99*4882a593Smuzhiyun u8 dst_addr[ETH_ALEN];
100*4882a593Smuzhiyun u8 src_addr[ETH_ALEN];
101*4882a593Smuzhiyun __be16 len;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun /* followed by frame data; max 2304 bytes */
104*4882a593Smuzhiyun } __packed;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun struct hfa384x_tx_frame {
108*4882a593Smuzhiyun /* HFA384X TX frame descriptor */
109*4882a593Smuzhiyun __le16 status; /* HFA384X_TX_STATUS_ flags */
110*4882a593Smuzhiyun __le16 reserved1;
111*4882a593Smuzhiyun __le16 reserved2;
112*4882a593Smuzhiyun __le32 sw_support;
113*4882a593Smuzhiyun u8 retry_count; /* not yet implemented */
114*4882a593Smuzhiyun u8 tx_rate; /* Host AP only; 0 = firmware, or 10, 20, 55, 110 */
115*4882a593Smuzhiyun __le16 tx_control; /* HFA384X_TX_CTRL_ flags */
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun /* 802.11 */
118*4882a593Smuzhiyun __le16 frame_control; /* parts not used */
119*4882a593Smuzhiyun __le16 duration_id;
120*4882a593Smuzhiyun u8 addr1[ETH_ALEN];
121*4882a593Smuzhiyun u8 addr2[ETH_ALEN]; /* filled by firmware */
122*4882a593Smuzhiyun u8 addr3[ETH_ALEN];
123*4882a593Smuzhiyun __le16 seq_ctrl; /* filled by firmware */
124*4882a593Smuzhiyun u8 addr4[ETH_ALEN];
125*4882a593Smuzhiyun __le16 data_len;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun /* 802.3 */
128*4882a593Smuzhiyun u8 dst_addr[ETH_ALEN];
129*4882a593Smuzhiyun u8 src_addr[ETH_ALEN];
130*4882a593Smuzhiyun __be16 len;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun /* followed by frame data; max 2304 bytes */
133*4882a593Smuzhiyun } __packed;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun struct hfa384x_rid_hdr
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun __le16 len;
139*4882a593Smuzhiyun __le16 rid;
140*4882a593Smuzhiyun } __packed;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun /* Macro for converting signal levels (range 27 .. 154) to wireless ext
144*4882a593Smuzhiyun * dBm value with some accuracy */
145*4882a593Smuzhiyun #define HFA384X_LEVEL_TO_dBm(v) 0x100 + (v) * 100 / 255 - 100
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun #define HFA384X_LEVEL_TO_dBm_sign(v) (v) * 100 / 255 - 100
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun struct hfa384x_scan_request {
150*4882a593Smuzhiyun __le16 channel_list;
151*4882a593Smuzhiyun __le16 txrate; /* HFA384X_RATES_* */
152*4882a593Smuzhiyun } __packed;
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun struct hfa384x_hostscan_request {
155*4882a593Smuzhiyun __le16 channel_list;
156*4882a593Smuzhiyun __le16 txrate;
157*4882a593Smuzhiyun __le16 target_ssid_len;
158*4882a593Smuzhiyun u8 target_ssid[32];
159*4882a593Smuzhiyun } __packed;
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun struct hfa384x_join_request {
162*4882a593Smuzhiyun u8 bssid[ETH_ALEN];
163*4882a593Smuzhiyun __le16 channel;
164*4882a593Smuzhiyun } __packed;
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun struct hfa384x_info_frame {
167*4882a593Smuzhiyun __le16 len;
168*4882a593Smuzhiyun __le16 type;
169*4882a593Smuzhiyun } __packed;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun struct hfa384x_comm_tallies {
172*4882a593Smuzhiyun __le16 tx_unicast_frames;
173*4882a593Smuzhiyun __le16 tx_multicast_frames;
174*4882a593Smuzhiyun __le16 tx_fragments;
175*4882a593Smuzhiyun __le16 tx_unicast_octets;
176*4882a593Smuzhiyun __le16 tx_multicast_octets;
177*4882a593Smuzhiyun __le16 tx_deferred_transmissions;
178*4882a593Smuzhiyun __le16 tx_single_retry_frames;
179*4882a593Smuzhiyun __le16 tx_multiple_retry_frames;
180*4882a593Smuzhiyun __le16 tx_retry_limit_exceeded;
181*4882a593Smuzhiyun __le16 tx_discards;
182*4882a593Smuzhiyun __le16 rx_unicast_frames;
183*4882a593Smuzhiyun __le16 rx_multicast_frames;
184*4882a593Smuzhiyun __le16 rx_fragments;
185*4882a593Smuzhiyun __le16 rx_unicast_octets;
186*4882a593Smuzhiyun __le16 rx_multicast_octets;
187*4882a593Smuzhiyun __le16 rx_fcs_errors;
188*4882a593Smuzhiyun __le16 rx_discards_no_buffer;
189*4882a593Smuzhiyun __le16 tx_discards_wrong_sa;
190*4882a593Smuzhiyun __le16 rx_discards_wep_undecryptable;
191*4882a593Smuzhiyun __le16 rx_message_in_msg_fragments;
192*4882a593Smuzhiyun __le16 rx_message_in_bad_msg_fragments;
193*4882a593Smuzhiyun } __packed;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun struct hfa384x_comm_tallies32 {
196*4882a593Smuzhiyun __le32 tx_unicast_frames;
197*4882a593Smuzhiyun __le32 tx_multicast_frames;
198*4882a593Smuzhiyun __le32 tx_fragments;
199*4882a593Smuzhiyun __le32 tx_unicast_octets;
200*4882a593Smuzhiyun __le32 tx_multicast_octets;
201*4882a593Smuzhiyun __le32 tx_deferred_transmissions;
202*4882a593Smuzhiyun __le32 tx_single_retry_frames;
203*4882a593Smuzhiyun __le32 tx_multiple_retry_frames;
204*4882a593Smuzhiyun __le32 tx_retry_limit_exceeded;
205*4882a593Smuzhiyun __le32 tx_discards;
206*4882a593Smuzhiyun __le32 rx_unicast_frames;
207*4882a593Smuzhiyun __le32 rx_multicast_frames;
208*4882a593Smuzhiyun __le32 rx_fragments;
209*4882a593Smuzhiyun __le32 rx_unicast_octets;
210*4882a593Smuzhiyun __le32 rx_multicast_octets;
211*4882a593Smuzhiyun __le32 rx_fcs_errors;
212*4882a593Smuzhiyun __le32 rx_discards_no_buffer;
213*4882a593Smuzhiyun __le32 tx_discards_wrong_sa;
214*4882a593Smuzhiyun __le32 rx_discards_wep_undecryptable;
215*4882a593Smuzhiyun __le32 rx_message_in_msg_fragments;
216*4882a593Smuzhiyun __le32 rx_message_in_bad_msg_fragments;
217*4882a593Smuzhiyun } __packed;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun struct hfa384x_scan_result_hdr {
220*4882a593Smuzhiyun __le16 reserved;
221*4882a593Smuzhiyun __le16 scan_reason;
222*4882a593Smuzhiyun #define HFA384X_SCAN_IN_PROGRESS 0 /* no results available yet */
223*4882a593Smuzhiyun #define HFA384X_SCAN_HOST_INITIATED 1
224*4882a593Smuzhiyun #define HFA384X_SCAN_FIRMWARE_INITIATED 2
225*4882a593Smuzhiyun #define HFA384X_SCAN_INQUIRY_FROM_HOST 3
226*4882a593Smuzhiyun } __packed;
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun #define HFA384X_SCAN_MAX_RESULTS 32
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun struct hfa384x_scan_result {
231*4882a593Smuzhiyun __le16 chid;
232*4882a593Smuzhiyun __le16 anl;
233*4882a593Smuzhiyun __le16 sl;
234*4882a593Smuzhiyun u8 bssid[ETH_ALEN];
235*4882a593Smuzhiyun __le16 beacon_interval;
236*4882a593Smuzhiyun __le16 capability;
237*4882a593Smuzhiyun __le16 ssid_len;
238*4882a593Smuzhiyun u8 ssid[32];
239*4882a593Smuzhiyun u8 sup_rates[10];
240*4882a593Smuzhiyun __le16 rate;
241*4882a593Smuzhiyun } __packed;
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun struct hfa384x_hostscan_result {
244*4882a593Smuzhiyun __le16 chid;
245*4882a593Smuzhiyun __le16 anl;
246*4882a593Smuzhiyun __le16 sl;
247*4882a593Smuzhiyun u8 bssid[ETH_ALEN];
248*4882a593Smuzhiyun __le16 beacon_interval;
249*4882a593Smuzhiyun __le16 capability;
250*4882a593Smuzhiyun __le16 ssid_len;
251*4882a593Smuzhiyun u8 ssid[32];
252*4882a593Smuzhiyun u8 sup_rates[10];
253*4882a593Smuzhiyun __le16 rate;
254*4882a593Smuzhiyun __le16 atim;
255*4882a593Smuzhiyun } __packed;
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun struct comm_tallies_sums {
258*4882a593Smuzhiyun unsigned int tx_unicast_frames;
259*4882a593Smuzhiyun unsigned int tx_multicast_frames;
260*4882a593Smuzhiyun unsigned int tx_fragments;
261*4882a593Smuzhiyun unsigned int tx_unicast_octets;
262*4882a593Smuzhiyun unsigned int tx_multicast_octets;
263*4882a593Smuzhiyun unsigned int tx_deferred_transmissions;
264*4882a593Smuzhiyun unsigned int tx_single_retry_frames;
265*4882a593Smuzhiyun unsigned int tx_multiple_retry_frames;
266*4882a593Smuzhiyun unsigned int tx_retry_limit_exceeded;
267*4882a593Smuzhiyun unsigned int tx_discards;
268*4882a593Smuzhiyun unsigned int rx_unicast_frames;
269*4882a593Smuzhiyun unsigned int rx_multicast_frames;
270*4882a593Smuzhiyun unsigned int rx_fragments;
271*4882a593Smuzhiyun unsigned int rx_unicast_octets;
272*4882a593Smuzhiyun unsigned int rx_multicast_octets;
273*4882a593Smuzhiyun unsigned int rx_fcs_errors;
274*4882a593Smuzhiyun unsigned int rx_discards_no_buffer;
275*4882a593Smuzhiyun unsigned int tx_discards_wrong_sa;
276*4882a593Smuzhiyun unsigned int rx_discards_wep_undecryptable;
277*4882a593Smuzhiyun unsigned int rx_message_in_msg_fragments;
278*4882a593Smuzhiyun unsigned int rx_message_in_bad_msg_fragments;
279*4882a593Smuzhiyun };
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun struct hfa384x_regs {
283*4882a593Smuzhiyun u16 cmd;
284*4882a593Smuzhiyun u16 evstat;
285*4882a593Smuzhiyun u16 offset0;
286*4882a593Smuzhiyun u16 offset1;
287*4882a593Smuzhiyun u16 swsupport0;
288*4882a593Smuzhiyun };
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun #if defined(PRISM2_PCCARD) || defined(PRISM2_PLX)
292*4882a593Smuzhiyun /* I/O ports for HFA384X Controller access */
293*4882a593Smuzhiyun #define HFA384X_CMD_OFF 0x00
294*4882a593Smuzhiyun #define HFA384X_PARAM0_OFF 0x02
295*4882a593Smuzhiyun #define HFA384X_PARAM1_OFF 0x04
296*4882a593Smuzhiyun #define HFA384X_PARAM2_OFF 0x06
297*4882a593Smuzhiyun #define HFA384X_STATUS_OFF 0x08
298*4882a593Smuzhiyun #define HFA384X_RESP0_OFF 0x0A
299*4882a593Smuzhiyun #define HFA384X_RESP1_OFF 0x0C
300*4882a593Smuzhiyun #define HFA384X_RESP2_OFF 0x0E
301*4882a593Smuzhiyun #define HFA384X_INFOFID_OFF 0x10
302*4882a593Smuzhiyun #define HFA384X_CONTROL_OFF 0x14
303*4882a593Smuzhiyun #define HFA384X_SELECT0_OFF 0x18
304*4882a593Smuzhiyun #define HFA384X_SELECT1_OFF 0x1A
305*4882a593Smuzhiyun #define HFA384X_OFFSET0_OFF 0x1C
306*4882a593Smuzhiyun #define HFA384X_OFFSET1_OFF 0x1E
307*4882a593Smuzhiyun #define HFA384X_RXFID_OFF 0x20
308*4882a593Smuzhiyun #define HFA384X_ALLOCFID_OFF 0x22
309*4882a593Smuzhiyun #define HFA384X_TXCOMPLFID_OFF 0x24
310*4882a593Smuzhiyun #define HFA384X_SWSUPPORT0_OFF 0x28
311*4882a593Smuzhiyun #define HFA384X_SWSUPPORT1_OFF 0x2A
312*4882a593Smuzhiyun #define HFA384X_SWSUPPORT2_OFF 0x2C
313*4882a593Smuzhiyun #define HFA384X_EVSTAT_OFF 0x30
314*4882a593Smuzhiyun #define HFA384X_INTEN_OFF 0x32
315*4882a593Smuzhiyun #define HFA384X_EVACK_OFF 0x34
316*4882a593Smuzhiyun #define HFA384X_DATA0_OFF 0x36
317*4882a593Smuzhiyun #define HFA384X_DATA1_OFF 0x38
318*4882a593Smuzhiyun #define HFA384X_AUXPAGE_OFF 0x3A
319*4882a593Smuzhiyun #define HFA384X_AUXOFFSET_OFF 0x3C
320*4882a593Smuzhiyun #define HFA384X_AUXDATA_OFF 0x3E
321*4882a593Smuzhiyun #endif /* PRISM2_PCCARD || PRISM2_PLX */
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun #ifdef PRISM2_PCI
324*4882a593Smuzhiyun /* Memory addresses for ISL3874 controller access */
325*4882a593Smuzhiyun #define HFA384X_CMD_OFF 0x00
326*4882a593Smuzhiyun #define HFA384X_PARAM0_OFF 0x04
327*4882a593Smuzhiyun #define HFA384X_PARAM1_OFF 0x08
328*4882a593Smuzhiyun #define HFA384X_PARAM2_OFF 0x0C
329*4882a593Smuzhiyun #define HFA384X_STATUS_OFF 0x10
330*4882a593Smuzhiyun #define HFA384X_RESP0_OFF 0x14
331*4882a593Smuzhiyun #define HFA384X_RESP1_OFF 0x18
332*4882a593Smuzhiyun #define HFA384X_RESP2_OFF 0x1C
333*4882a593Smuzhiyun #define HFA384X_INFOFID_OFF 0x20
334*4882a593Smuzhiyun #define HFA384X_CONTROL_OFF 0x28
335*4882a593Smuzhiyun #define HFA384X_SELECT0_OFF 0x30
336*4882a593Smuzhiyun #define HFA384X_SELECT1_OFF 0x34
337*4882a593Smuzhiyun #define HFA384X_OFFSET0_OFF 0x38
338*4882a593Smuzhiyun #define HFA384X_OFFSET1_OFF 0x3C
339*4882a593Smuzhiyun #define HFA384X_RXFID_OFF 0x40
340*4882a593Smuzhiyun #define HFA384X_ALLOCFID_OFF 0x44
341*4882a593Smuzhiyun #define HFA384X_TXCOMPLFID_OFF 0x48
342*4882a593Smuzhiyun #define HFA384X_PCICOR_OFF 0x4C
343*4882a593Smuzhiyun #define HFA384X_SWSUPPORT0_OFF 0x50
344*4882a593Smuzhiyun #define HFA384X_SWSUPPORT1_OFF 0x54
345*4882a593Smuzhiyun #define HFA384X_SWSUPPORT2_OFF 0x58
346*4882a593Smuzhiyun #define HFA384X_PCIHCR_OFF 0x5C
347*4882a593Smuzhiyun #define HFA384X_EVSTAT_OFF 0x60
348*4882a593Smuzhiyun #define HFA384X_INTEN_OFF 0x64
349*4882a593Smuzhiyun #define HFA384X_EVACK_OFF 0x68
350*4882a593Smuzhiyun #define HFA384X_DATA0_OFF 0x6C
351*4882a593Smuzhiyun #define HFA384X_DATA1_OFF 0x70
352*4882a593Smuzhiyun #define HFA384X_AUXPAGE_OFF 0x74
353*4882a593Smuzhiyun #define HFA384X_AUXOFFSET_OFF 0x78
354*4882a593Smuzhiyun #define HFA384X_AUXDATA_OFF 0x7C
355*4882a593Smuzhiyun #define HFA384X_PCI_M0_ADDRH_OFF 0x80
356*4882a593Smuzhiyun #define HFA384X_PCI_M0_ADDRL_OFF 0x84
357*4882a593Smuzhiyun #define HFA384X_PCI_M0_LEN_OFF 0x88
358*4882a593Smuzhiyun #define HFA384X_PCI_M0_CTL_OFF 0x8C
359*4882a593Smuzhiyun #define HFA384X_PCI_STATUS_OFF 0x98
360*4882a593Smuzhiyun #define HFA384X_PCI_M1_ADDRH_OFF 0xA0
361*4882a593Smuzhiyun #define HFA384X_PCI_M1_ADDRL_OFF 0xA4
362*4882a593Smuzhiyun #define HFA384X_PCI_M1_LEN_OFF 0xA8
363*4882a593Smuzhiyun #define HFA384X_PCI_M1_CTL_OFF 0xAC
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun /* PCI bus master control bits (these are undocumented; based on guessing and
366*4882a593Smuzhiyun * experimenting..) */
367*4882a593Smuzhiyun #define HFA384X_PCI_CTL_FROM_BAP (BIT(5) | BIT(1) | BIT(0))
368*4882a593Smuzhiyun #define HFA384X_PCI_CTL_TO_BAP (BIT(5) | BIT(0))
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun #endif /* PRISM2_PCI */
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun /* Command codes for CMD reg. */
374*4882a593Smuzhiyun #define HFA384X_CMDCODE_INIT 0x00
375*4882a593Smuzhiyun #define HFA384X_CMDCODE_ENABLE 0x01
376*4882a593Smuzhiyun #define HFA384X_CMDCODE_DISABLE 0x02
377*4882a593Smuzhiyun #define HFA384X_CMDCODE_ALLOC 0x0A
378*4882a593Smuzhiyun #define HFA384X_CMDCODE_TRANSMIT 0x0B
379*4882a593Smuzhiyun #define HFA384X_CMDCODE_INQUIRE 0x11
380*4882a593Smuzhiyun #define HFA384X_CMDCODE_ACCESS 0x21
381*4882a593Smuzhiyun #define HFA384X_CMDCODE_ACCESS_WRITE (0x21 | BIT(8))
382*4882a593Smuzhiyun #define HFA384X_CMDCODE_DOWNLOAD 0x22
383*4882a593Smuzhiyun #define HFA384X_CMDCODE_READMIF 0x30
384*4882a593Smuzhiyun #define HFA384X_CMDCODE_WRITEMIF 0x31
385*4882a593Smuzhiyun #define HFA384X_CMDCODE_TEST 0x38
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun #define HFA384X_CMDCODE_MASK 0x3F
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun /* Test mode operations */
390*4882a593Smuzhiyun #define HFA384X_TEST_CHANGE_CHANNEL 0x08
391*4882a593Smuzhiyun #define HFA384X_TEST_MONITOR 0x0B
392*4882a593Smuzhiyun #define HFA384X_TEST_STOP 0x0F
393*4882a593Smuzhiyun #define HFA384X_TEST_CFG_BITS 0x15
394*4882a593Smuzhiyun #define HFA384X_TEST_CFG_BIT_ALC BIT(3)
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun #define HFA384X_CMD_BUSY BIT(15)
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun #define HFA384X_CMD_TX_RECLAIM BIT(8)
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun #define HFA384X_OFFSET_ERR BIT(14)
401*4882a593Smuzhiyun #define HFA384X_OFFSET_BUSY BIT(15)
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun /* ProgMode for download command */
405*4882a593Smuzhiyun #define HFA384X_PROGMODE_DISABLE 0
406*4882a593Smuzhiyun #define HFA384X_PROGMODE_ENABLE_VOLATILE 1
407*4882a593Smuzhiyun #define HFA384X_PROGMODE_ENABLE_NON_VOLATILE 2
408*4882a593Smuzhiyun #define HFA384X_PROGMODE_PROGRAM_NON_VOLATILE 3
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun #define HFA384X_AUX_MAGIC0 0xfe01
411*4882a593Smuzhiyun #define HFA384X_AUX_MAGIC1 0xdc23
412*4882a593Smuzhiyun #define HFA384X_AUX_MAGIC2 0xba45
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun #define HFA384X_AUX_PORT_DISABLED 0
415*4882a593Smuzhiyun #define HFA384X_AUX_PORT_DISABLE BIT(14)
416*4882a593Smuzhiyun #define HFA384X_AUX_PORT_ENABLE BIT(15)
417*4882a593Smuzhiyun #define HFA384X_AUX_PORT_ENABLED (BIT(14) | BIT(15))
418*4882a593Smuzhiyun #define HFA384X_AUX_PORT_MASK (BIT(14) | BIT(15))
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun #define PRISM2_PDA_SIZE 1024
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun /* Events; EvStat, Interrupt mask (IntEn), and acknowledge bits (EvAck) */
424*4882a593Smuzhiyun #define HFA384X_EV_TICK BIT(15)
425*4882a593Smuzhiyun #define HFA384X_EV_WTERR BIT(14)
426*4882a593Smuzhiyun #define HFA384X_EV_INFDROP BIT(13)
427*4882a593Smuzhiyun #ifdef PRISM2_PCI
428*4882a593Smuzhiyun #define HFA384X_EV_PCI_M1 BIT(9)
429*4882a593Smuzhiyun #define HFA384X_EV_PCI_M0 BIT(8)
430*4882a593Smuzhiyun #endif /* PRISM2_PCI */
431*4882a593Smuzhiyun #define HFA384X_EV_INFO BIT(7)
432*4882a593Smuzhiyun #define HFA384X_EV_DTIM BIT(5)
433*4882a593Smuzhiyun #define HFA384X_EV_CMD BIT(4)
434*4882a593Smuzhiyun #define HFA384X_EV_ALLOC BIT(3)
435*4882a593Smuzhiyun #define HFA384X_EV_TXEXC BIT(2)
436*4882a593Smuzhiyun #define HFA384X_EV_TX BIT(1)
437*4882a593Smuzhiyun #define HFA384X_EV_RX BIT(0)
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun /* HFA384X Information frames */
441*4882a593Smuzhiyun #define HFA384X_INFO_HANDOVERADDR 0xF000 /* AP f/w ? */
442*4882a593Smuzhiyun #define HFA384X_INFO_HANDOVERDEAUTHADDR 0xF001 /* AP f/w 1.3.7 */
443*4882a593Smuzhiyun #define HFA384X_INFO_COMMTALLIES 0xF100
444*4882a593Smuzhiyun #define HFA384X_INFO_SCANRESULTS 0xF101
445*4882a593Smuzhiyun #define HFA384X_INFO_CHANNELINFORESULTS 0xF102 /* AP f/w only */
446*4882a593Smuzhiyun #define HFA384X_INFO_HOSTSCANRESULTS 0xF103
447*4882a593Smuzhiyun #define HFA384X_INFO_LINKSTATUS 0xF200
448*4882a593Smuzhiyun #define HFA384X_INFO_ASSOCSTATUS 0xF201 /* ? */
449*4882a593Smuzhiyun #define HFA384X_INFO_AUTHREQ 0xF202 /* ? */
450*4882a593Smuzhiyun #define HFA384X_INFO_PSUSERCNT 0xF203 /* ? */
451*4882a593Smuzhiyun #define HFA384X_INFO_KEYIDCHANGED 0xF204 /* ? */
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun enum { HFA384X_LINKSTATUS_CONNECTED = 1,
454*4882a593Smuzhiyun HFA384X_LINKSTATUS_DISCONNECTED = 2,
455*4882a593Smuzhiyun HFA384X_LINKSTATUS_AP_CHANGE = 3,
456*4882a593Smuzhiyun HFA384X_LINKSTATUS_AP_OUT_OF_RANGE = 4,
457*4882a593Smuzhiyun HFA384X_LINKSTATUS_AP_IN_RANGE = 5,
458*4882a593Smuzhiyun HFA384X_LINKSTATUS_ASSOC_FAILED = 6 };
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun enum { HFA384X_PORTTYPE_BSS = 1, HFA384X_PORTTYPE_WDS = 2,
461*4882a593Smuzhiyun HFA384X_PORTTYPE_PSEUDO_IBSS = 3, HFA384X_PORTTYPE_IBSS = 0,
462*4882a593Smuzhiyun HFA384X_PORTTYPE_HOSTAP = 6 };
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun #define HFA384X_RATES_1MBPS BIT(0)
465*4882a593Smuzhiyun #define HFA384X_RATES_2MBPS BIT(1)
466*4882a593Smuzhiyun #define HFA384X_RATES_5MBPS BIT(2)
467*4882a593Smuzhiyun #define HFA384X_RATES_11MBPS BIT(3)
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun #define HFA384X_ROAMING_FIRMWARE 1
470*4882a593Smuzhiyun #define HFA384X_ROAMING_HOST 2
471*4882a593Smuzhiyun #define HFA384X_ROAMING_DISABLED 3
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun #define HFA384X_WEPFLAGS_PRIVACYINVOKED BIT(0)
474*4882a593Smuzhiyun #define HFA384X_WEPFLAGS_EXCLUDEUNENCRYPTED BIT(1)
475*4882a593Smuzhiyun #define HFA384X_WEPFLAGS_HOSTENCRYPT BIT(4)
476*4882a593Smuzhiyun #define HFA384X_WEPFLAGS_HOSTDECRYPT BIT(7)
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun #define HFA384X_RX_STATUS_MSGTYPE (BIT(15) | BIT(14) | BIT(13))
479*4882a593Smuzhiyun #define HFA384X_RX_STATUS_PCF BIT(12)
480*4882a593Smuzhiyun #define HFA384X_RX_STATUS_MACPORT (BIT(10) | BIT(9) | BIT(8))
481*4882a593Smuzhiyun #define HFA384X_RX_STATUS_UNDECR BIT(1)
482*4882a593Smuzhiyun #define HFA384X_RX_STATUS_FCSERR BIT(0)
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun #define HFA384X_RX_STATUS_GET_MSGTYPE(s) \
485*4882a593Smuzhiyun (((s) & HFA384X_RX_STATUS_MSGTYPE) >> 13)
486*4882a593Smuzhiyun #define HFA384X_RX_STATUS_GET_MACPORT(s) \
487*4882a593Smuzhiyun (((s) & HFA384X_RX_STATUS_MACPORT) >> 8)
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun enum { HFA384X_RX_MSGTYPE_NORMAL = 0, HFA384X_RX_MSGTYPE_RFC1042 = 1,
490*4882a593Smuzhiyun HFA384X_RX_MSGTYPE_BRIDGETUNNEL = 2, HFA384X_RX_MSGTYPE_MGMT = 4 };
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun #define HFA384X_TX_CTRL_ALT_RTRY BIT(5)
494*4882a593Smuzhiyun #define HFA384X_TX_CTRL_802_11 BIT(3)
495*4882a593Smuzhiyun #define HFA384X_TX_CTRL_802_3 0
496*4882a593Smuzhiyun #define HFA384X_TX_CTRL_TX_EX BIT(2)
497*4882a593Smuzhiyun #define HFA384X_TX_CTRL_TX_OK BIT(1)
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun #define HFA384X_TX_STATUS_RETRYERR BIT(0)
500*4882a593Smuzhiyun #define HFA384X_TX_STATUS_AGEDERR BIT(1)
501*4882a593Smuzhiyun #define HFA384X_TX_STATUS_DISCON BIT(2)
502*4882a593Smuzhiyun #define HFA384X_TX_STATUS_FORMERR BIT(3)
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun /* HFA3861/3863 (BBP) Control Registers */
505*4882a593Smuzhiyun #define HFA386X_CR_TX_CONFIGURE 0x12 /* CR9 */
506*4882a593Smuzhiyun #define HFA386X_CR_RX_CONFIGURE 0x14 /* CR10 */
507*4882a593Smuzhiyun #define HFA386X_CR_A_D_TEST_MODES2 0x1A /* CR13 */
508*4882a593Smuzhiyun #define HFA386X_CR_MANUAL_TX_POWER 0x3E /* CR31 */
509*4882a593Smuzhiyun #define HFA386X_CR_MEASURED_TX_POWER 0x74 /* CR58 */
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun #ifdef __KERNEL__
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun #define PRISM2_TXFID_COUNT 8
515*4882a593Smuzhiyun #define PRISM2_DATA_MAXLEN 2304
516*4882a593Smuzhiyun #define PRISM2_TXFID_LEN (PRISM2_DATA_MAXLEN + sizeof(struct hfa384x_tx_frame))
517*4882a593Smuzhiyun #define PRISM2_TXFID_EMPTY 0xffff
518*4882a593Smuzhiyun #define PRISM2_TXFID_RESERVED 0xfffe
519*4882a593Smuzhiyun #define PRISM2_DUMMY_FID 0xffff
520*4882a593Smuzhiyun #define MAX_SSID_LEN 32
521*4882a593Smuzhiyun #define MAX_NAME_LEN 32 /* this is assumed to be equal to MAX_SSID_LEN */
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun #define PRISM2_DUMP_RX_HDR BIT(0)
524*4882a593Smuzhiyun #define PRISM2_DUMP_TX_HDR BIT(1)
525*4882a593Smuzhiyun #define PRISM2_DUMP_TXEXC_HDR BIT(2)
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun struct hostap_tx_callback_info {
528*4882a593Smuzhiyun u16 idx;
529*4882a593Smuzhiyun void (*func)(struct sk_buff *, int ok, void *);
530*4882a593Smuzhiyun void *data;
531*4882a593Smuzhiyun struct hostap_tx_callback_info *next;
532*4882a593Smuzhiyun };
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun /* IEEE 802.11 requires that STA supports concurrent reception of at least
536*4882a593Smuzhiyun * three fragmented frames. This define can be increased to support more
537*4882a593Smuzhiyun * concurrent frames, but it should be noted that each entry can consume about
538*4882a593Smuzhiyun * 2 kB of RAM and increasing cache size will slow down frame reassembly. */
539*4882a593Smuzhiyun #define PRISM2_FRAG_CACHE_LEN 4
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun struct prism2_frag_entry {
542*4882a593Smuzhiyun unsigned long first_frag_time;
543*4882a593Smuzhiyun unsigned int seq;
544*4882a593Smuzhiyun unsigned int last_frag;
545*4882a593Smuzhiyun struct sk_buff *skb;
546*4882a593Smuzhiyun u8 src_addr[ETH_ALEN];
547*4882a593Smuzhiyun u8 dst_addr[ETH_ALEN];
548*4882a593Smuzhiyun };
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun struct hostap_cmd_queue {
552*4882a593Smuzhiyun struct list_head list;
553*4882a593Smuzhiyun wait_queue_head_t compl;
554*4882a593Smuzhiyun volatile enum { CMD_SLEEP, CMD_CALLBACK, CMD_COMPLETED } type;
555*4882a593Smuzhiyun void (*callback)(struct net_device *dev, long context, u16 resp0,
556*4882a593Smuzhiyun u16 res);
557*4882a593Smuzhiyun long context;
558*4882a593Smuzhiyun u16 cmd, param0, param1;
559*4882a593Smuzhiyun u16 resp0, res;
560*4882a593Smuzhiyun volatile int issued, issuing;
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun refcount_t usecnt;
563*4882a593Smuzhiyun int del_req;
564*4882a593Smuzhiyun };
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun /* options for hw_shutdown */
567*4882a593Smuzhiyun #define HOSTAP_HW_NO_DISABLE BIT(0)
568*4882a593Smuzhiyun #define HOSTAP_HW_ENABLE_CMDCOMPL BIT(1)
569*4882a593Smuzhiyun
570*4882a593Smuzhiyun typedef struct local_info local_info_t;
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun struct prism2_helper_functions {
573*4882a593Smuzhiyun /* these functions are defined in hardware model specific files
574*4882a593Smuzhiyun * (hostap_{cs,plx,pci}.c */
575*4882a593Smuzhiyun int (*card_present)(local_info_t *local);
576*4882a593Smuzhiyun void (*cor_sreset)(local_info_t *local);
577*4882a593Smuzhiyun void (*genesis_reset)(local_info_t *local, int hcr);
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun /* the following functions are from hostap_hw.c, but they may have some
580*4882a593Smuzhiyun * hardware model specific code */
581*4882a593Smuzhiyun
582*4882a593Smuzhiyun /* FIX: low-level commands like cmd might disappear at some point to
583*4882a593Smuzhiyun * make it easier to change them if needed (e.g., cmd would be replaced
584*4882a593Smuzhiyun * with write_mif/read_mif/testcmd/inquire); at least get_rid and
585*4882a593Smuzhiyun * set_rid might move to hostap_{cs,plx,pci}.c */
586*4882a593Smuzhiyun int (*cmd)(struct net_device *dev, u16 cmd, u16 param0, u16 *param1,
587*4882a593Smuzhiyun u16 *resp0);
588*4882a593Smuzhiyun void (*read_regs)(struct net_device *dev, struct hfa384x_regs *regs);
589*4882a593Smuzhiyun int (*get_rid)(struct net_device *dev, u16 rid, void *buf, int len,
590*4882a593Smuzhiyun int exact_len);
591*4882a593Smuzhiyun int (*set_rid)(struct net_device *dev, u16 rid, void *buf, int len);
592*4882a593Smuzhiyun int (*hw_enable)(struct net_device *dev, int initial);
593*4882a593Smuzhiyun int (*hw_config)(struct net_device *dev, int initial);
594*4882a593Smuzhiyun void (*hw_reset)(struct net_device *dev);
595*4882a593Smuzhiyun void (*hw_shutdown)(struct net_device *dev, int no_disable);
596*4882a593Smuzhiyun int (*reset_port)(struct net_device *dev);
597*4882a593Smuzhiyun void (*schedule_reset)(local_info_t *local);
598*4882a593Smuzhiyun int (*download)(local_info_t *local,
599*4882a593Smuzhiyun struct prism2_download_param *param);
600*4882a593Smuzhiyun int (*tx)(struct sk_buff *skb, struct net_device *dev);
601*4882a593Smuzhiyun int (*set_tim)(struct net_device *dev, int aid, int set);
602*4882a593Smuzhiyun const struct proc_ops *read_aux_proc_ops;
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun int need_tx_headroom; /* number of bytes of headroom needed before
605*4882a593Smuzhiyun * IEEE 802.11 header */
606*4882a593Smuzhiyun enum { HOSTAP_HW_PCCARD, HOSTAP_HW_PLX, HOSTAP_HW_PCI } hw_type;
607*4882a593Smuzhiyun };
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun
610*4882a593Smuzhiyun struct prism2_download_data {
611*4882a593Smuzhiyun u32 dl_cmd;
612*4882a593Smuzhiyun u32 start_addr;
613*4882a593Smuzhiyun u32 num_areas;
614*4882a593Smuzhiyun struct prism2_download_data_area {
615*4882a593Smuzhiyun u32 addr; /* wlan card address */
616*4882a593Smuzhiyun u32 len;
617*4882a593Smuzhiyun u8 *data; /* allocated data */
618*4882a593Smuzhiyun } data[];
619*4882a593Smuzhiyun };
620*4882a593Smuzhiyun
621*4882a593Smuzhiyun
622*4882a593Smuzhiyun #define HOSTAP_MAX_BSS_COUNT 64
623*4882a593Smuzhiyun #define MAX_WPA_IE_LEN 64
624*4882a593Smuzhiyun
625*4882a593Smuzhiyun struct hostap_bss_info {
626*4882a593Smuzhiyun struct list_head list;
627*4882a593Smuzhiyun unsigned long last_update;
628*4882a593Smuzhiyun unsigned int count;
629*4882a593Smuzhiyun u8 bssid[ETH_ALEN];
630*4882a593Smuzhiyun u16 capab_info;
631*4882a593Smuzhiyun u8 ssid[32];
632*4882a593Smuzhiyun size_t ssid_len;
633*4882a593Smuzhiyun u8 wpa_ie[MAX_WPA_IE_LEN];
634*4882a593Smuzhiyun size_t wpa_ie_len;
635*4882a593Smuzhiyun u8 rsn_ie[MAX_WPA_IE_LEN];
636*4882a593Smuzhiyun size_t rsn_ie_len;
637*4882a593Smuzhiyun int chan;
638*4882a593Smuzhiyun int included;
639*4882a593Smuzhiyun };
640*4882a593Smuzhiyun
641*4882a593Smuzhiyun
642*4882a593Smuzhiyun /* Per radio private Host AP data - shared by all net devices interfaces used
643*4882a593Smuzhiyun * by each radio (wlan#, wlan#ap, wlan#sta, WDS).
644*4882a593Smuzhiyun * ((struct hostap_interface *) netdev_priv(dev))->local points to this
645*4882a593Smuzhiyun * structure. */
646*4882a593Smuzhiyun struct local_info {
647*4882a593Smuzhiyun struct module *hw_module;
648*4882a593Smuzhiyun int card_idx;
649*4882a593Smuzhiyun int dev_enabled;
650*4882a593Smuzhiyun int master_dev_auto_open; /* was master device opened automatically */
651*4882a593Smuzhiyun int num_dev_open; /* number of open devices */
652*4882a593Smuzhiyun struct net_device *dev; /* master radio device */
653*4882a593Smuzhiyun struct net_device *ddev; /* main data device */
654*4882a593Smuzhiyun struct list_head hostap_interfaces; /* Host AP interface list (contains
655*4882a593Smuzhiyun * struct hostap_interface entries)
656*4882a593Smuzhiyun */
657*4882a593Smuzhiyun rwlock_t iface_lock; /* hostap_interfaces read lock; use write lock
658*4882a593Smuzhiyun * when removing entries from the list.
659*4882a593Smuzhiyun * TX and RX paths can use read lock. */
660*4882a593Smuzhiyun spinlock_t cmdlock, baplock, lock, irq_init_lock;
661*4882a593Smuzhiyun struct mutex rid_bap_mtx;
662*4882a593Smuzhiyun u16 infofid; /* MAC buffer id for info frame */
663*4882a593Smuzhiyun /* txfid, intransmitfid, next_txtid, and next_alloc are protected by
664*4882a593Smuzhiyun * txfidlock */
665*4882a593Smuzhiyun spinlock_t txfidlock;
666*4882a593Smuzhiyun int txfid_len; /* length of allocated TX buffers */
667*4882a593Smuzhiyun u16 txfid[PRISM2_TXFID_COUNT]; /* buffer IDs for TX frames */
668*4882a593Smuzhiyun /* buffer IDs for intransmit frames or PRISM2_TXFID_EMPTY if
669*4882a593Smuzhiyun * corresponding txfid is free for next TX frame */
670*4882a593Smuzhiyun u16 intransmitfid[PRISM2_TXFID_COUNT];
671*4882a593Smuzhiyun int next_txfid; /* index to the next txfid to be checked for
672*4882a593Smuzhiyun * availability */
673*4882a593Smuzhiyun int next_alloc; /* index to the next intransmitfid to be checked for
674*4882a593Smuzhiyun * allocation events */
675*4882a593Smuzhiyun
676*4882a593Smuzhiyun /* bitfield for atomic bitops */
677*4882a593Smuzhiyun #define HOSTAP_BITS_TRANSMIT 0
678*4882a593Smuzhiyun #define HOSTAP_BITS_BAP_TASKLET 1
679*4882a593Smuzhiyun #define HOSTAP_BITS_BAP_TASKLET2 2
680*4882a593Smuzhiyun unsigned long bits;
681*4882a593Smuzhiyun
682*4882a593Smuzhiyun struct ap_data *ap;
683*4882a593Smuzhiyun
684*4882a593Smuzhiyun char essid[MAX_SSID_LEN + 1];
685*4882a593Smuzhiyun char name[MAX_NAME_LEN + 1];
686*4882a593Smuzhiyun int name_set;
687*4882a593Smuzhiyun u16 channel_mask; /* mask of allowed channels */
688*4882a593Smuzhiyun u16 scan_channel_mask; /* mask of channels to be scanned */
689*4882a593Smuzhiyun struct comm_tallies_sums comm_tallies;
690*4882a593Smuzhiyun struct proc_dir_entry *proc;
691*4882a593Smuzhiyun int iw_mode; /* operating mode (IW_MODE_*) */
692*4882a593Smuzhiyun int pseudo_adhoc; /* 0: IW_MODE_ADHOC is real 802.11 compliant IBSS
693*4882a593Smuzhiyun * 1: IW_MODE_ADHOC is "pseudo IBSS" */
694*4882a593Smuzhiyun char bssid[ETH_ALEN];
695*4882a593Smuzhiyun int channel;
696*4882a593Smuzhiyun int beacon_int;
697*4882a593Smuzhiyun int dtim_period;
698*4882a593Smuzhiyun int mtu;
699*4882a593Smuzhiyun int frame_dump; /* dump RX/TX frame headers, PRISM2_DUMP_ flags */
700*4882a593Smuzhiyun int fw_tx_rate_control;
701*4882a593Smuzhiyun u16 tx_rate_control;
702*4882a593Smuzhiyun u16 basic_rates;
703*4882a593Smuzhiyun int hw_resetting;
704*4882a593Smuzhiyun int hw_ready;
705*4882a593Smuzhiyun int hw_reset_tries; /* how many times reset has been tried */
706*4882a593Smuzhiyun int hw_downloading;
707*4882a593Smuzhiyun int shutdown;
708*4882a593Smuzhiyun int pri_only;
709*4882a593Smuzhiyun int no_pri; /* no PRI f/w present */
710*4882a593Smuzhiyun int sram_type; /* 8 = x8 SRAM, 16 = x16 SRAM, -1 = unknown */
711*4882a593Smuzhiyun
712*4882a593Smuzhiyun enum {
713*4882a593Smuzhiyun PRISM2_TXPOWER_AUTO = 0, PRISM2_TXPOWER_OFF,
714*4882a593Smuzhiyun PRISM2_TXPOWER_FIXED, PRISM2_TXPOWER_UNKNOWN
715*4882a593Smuzhiyun } txpower_type;
716*4882a593Smuzhiyun int txpower; /* if txpower_type == PRISM2_TXPOWER_FIXED */
717*4882a593Smuzhiyun
718*4882a593Smuzhiyun /* command queue for hfa384x_cmd(); protected with cmdlock */
719*4882a593Smuzhiyun struct list_head cmd_queue;
720*4882a593Smuzhiyun /* max_len for cmd_queue; in addition, cmd_callback can use two
721*4882a593Smuzhiyun * additional entries to prevent sleeping commands from stopping
722*4882a593Smuzhiyun * transmits */
723*4882a593Smuzhiyun #define HOSTAP_CMD_QUEUE_MAX_LEN 16
724*4882a593Smuzhiyun int cmd_queue_len; /* number of entries in cmd_queue */
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun /* if card timeout is detected in interrupt context, reset_queue is
727*4882a593Smuzhiyun * used to schedule card reseting to be done in user context */
728*4882a593Smuzhiyun struct work_struct reset_queue;
729*4882a593Smuzhiyun
730*4882a593Smuzhiyun /* For scheduling a change of the promiscuous mode RID */
731*4882a593Smuzhiyun int is_promisc;
732*4882a593Smuzhiyun struct work_struct set_multicast_list_queue;
733*4882a593Smuzhiyun
734*4882a593Smuzhiyun struct work_struct set_tim_queue;
735*4882a593Smuzhiyun struct list_head set_tim_list;
736*4882a593Smuzhiyun spinlock_t set_tim_lock;
737*4882a593Smuzhiyun
738*4882a593Smuzhiyun int wds_max_connections;
739*4882a593Smuzhiyun int wds_connections;
740*4882a593Smuzhiyun #define HOSTAP_WDS_BROADCAST_RA BIT(0)
741*4882a593Smuzhiyun #define HOSTAP_WDS_AP_CLIENT BIT(1)
742*4882a593Smuzhiyun #define HOSTAP_WDS_STANDARD_FRAME BIT(2)
743*4882a593Smuzhiyun u32 wds_type;
744*4882a593Smuzhiyun u16 tx_control; /* flags to be used in TX description */
745*4882a593Smuzhiyun int manual_retry_count; /* -1 = use f/w default; otherwise retry count
746*4882a593Smuzhiyun * to be used with all frames */
747*4882a593Smuzhiyun
748*4882a593Smuzhiyun struct iw_statistics wstats;
749*4882a593Smuzhiyun unsigned long scan_timestamp; /* Time started to scan */
750*4882a593Smuzhiyun enum {
751*4882a593Smuzhiyun PRISM2_MONITOR_80211 = 0, PRISM2_MONITOR_PRISM = 1,
752*4882a593Smuzhiyun PRISM2_MONITOR_CAPHDR = 2, PRISM2_MONITOR_RADIOTAP = 3
753*4882a593Smuzhiyun } monitor_type;
754*4882a593Smuzhiyun int monitor_allow_fcserr;
755*4882a593Smuzhiyun
756*4882a593Smuzhiyun int hostapd; /* whether user space daemon, hostapd, is used for AP
757*4882a593Smuzhiyun * management */
758*4882a593Smuzhiyun int hostapd_sta; /* whether hostapd is used with an extra STA interface
759*4882a593Smuzhiyun */
760*4882a593Smuzhiyun struct net_device *apdev;
761*4882a593Smuzhiyun struct net_device_stats apdevstats;
762*4882a593Smuzhiyun
763*4882a593Smuzhiyun char assoc_ap_addr[ETH_ALEN];
764*4882a593Smuzhiyun struct net_device *stadev;
765*4882a593Smuzhiyun struct net_device_stats stadevstats;
766*4882a593Smuzhiyun
767*4882a593Smuzhiyun #define WEP_KEYS 4
768*4882a593Smuzhiyun #define WEP_KEY_LEN 13
769*4882a593Smuzhiyun struct lib80211_crypt_info crypt_info;
770*4882a593Smuzhiyun
771*4882a593Smuzhiyun int open_wep; /* allow unencrypted frames */
772*4882a593Smuzhiyun int host_encrypt;
773*4882a593Smuzhiyun int host_decrypt;
774*4882a593Smuzhiyun int privacy_invoked; /* force privacy invoked flag even if no keys are
775*4882a593Smuzhiyun * configured */
776*4882a593Smuzhiyun int fw_encrypt_ok; /* whether firmware-based WEP encrypt is working
777*4882a593Smuzhiyun * in Host AP mode (STA f/w 1.4.9 or newer) */
778*4882a593Smuzhiyun int bcrx_sta_key; /* use individual keys to override default keys even
779*4882a593Smuzhiyun * with RX of broad/multicast frames */
780*4882a593Smuzhiyun
781*4882a593Smuzhiyun struct prism2_frag_entry frag_cache[PRISM2_FRAG_CACHE_LEN];
782*4882a593Smuzhiyun unsigned int frag_next_idx;
783*4882a593Smuzhiyun
784*4882a593Smuzhiyun int ieee_802_1x; /* is IEEE 802.1X used */
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun int antsel_tx, antsel_rx;
787*4882a593Smuzhiyun int rts_threshold; /* dot11RTSThreshold */
788*4882a593Smuzhiyun int fragm_threshold; /* dot11FragmentationThreshold */
789*4882a593Smuzhiyun int auth_algs; /* PRISM2_AUTH_ flags */
790*4882a593Smuzhiyun
791*4882a593Smuzhiyun int enh_sec; /* cnfEnhSecurity options (broadcast SSID hide/ignore) */
792*4882a593Smuzhiyun int tallies32; /* 32-bit tallies in use */
793*4882a593Smuzhiyun
794*4882a593Smuzhiyun struct prism2_helper_functions *func;
795*4882a593Smuzhiyun
796*4882a593Smuzhiyun u8 *pda;
797*4882a593Smuzhiyun int fw_ap;
798*4882a593Smuzhiyun #define PRISM2_FW_VER(major, minor, variant) \
799*4882a593Smuzhiyun (((major) << 16) | ((minor) << 8) | variant)
800*4882a593Smuzhiyun u32 sta_fw_ver;
801*4882a593Smuzhiyun
802*4882a593Smuzhiyun /* Tasklets for handling hardware IRQ related operations outside hw IRQ
803*4882a593Smuzhiyun * handler */
804*4882a593Smuzhiyun struct tasklet_struct bap_tasklet;
805*4882a593Smuzhiyun
806*4882a593Smuzhiyun struct tasklet_struct info_tasklet;
807*4882a593Smuzhiyun struct sk_buff_head info_list; /* info frames as skb's for
808*4882a593Smuzhiyun * info_tasklet */
809*4882a593Smuzhiyun
810*4882a593Smuzhiyun struct hostap_tx_callback_info *tx_callback; /* registered TX callbacks
811*4882a593Smuzhiyun */
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun struct tasklet_struct rx_tasklet;
814*4882a593Smuzhiyun struct sk_buff_head rx_list;
815*4882a593Smuzhiyun
816*4882a593Smuzhiyun struct tasklet_struct sta_tx_exc_tasklet;
817*4882a593Smuzhiyun struct sk_buff_head sta_tx_exc_list;
818*4882a593Smuzhiyun
819*4882a593Smuzhiyun int host_roaming;
820*4882a593Smuzhiyun unsigned long last_join_time; /* time of last JoinRequest */
821*4882a593Smuzhiyun struct hfa384x_hostscan_result *last_scan_results;
822*4882a593Smuzhiyun int last_scan_results_count;
823*4882a593Smuzhiyun enum { PRISM2_SCAN, PRISM2_HOSTSCAN } last_scan_type;
824*4882a593Smuzhiyun struct work_struct info_queue;
825*4882a593Smuzhiyun unsigned long pending_info; /* bit field of pending info_queue items */
826*4882a593Smuzhiyun #define PRISM2_INFO_PENDING_LINKSTATUS 0
827*4882a593Smuzhiyun #define PRISM2_INFO_PENDING_SCANRESULTS 1
828*4882a593Smuzhiyun int prev_link_status; /* previous received LinkStatus info */
829*4882a593Smuzhiyun int prev_linkstatus_connected;
830*4882a593Smuzhiyun u8 preferred_ap[ETH_ALEN]; /* use this AP if possible */
831*4882a593Smuzhiyun
832*4882a593Smuzhiyun #ifdef PRISM2_CALLBACK
833*4882a593Smuzhiyun void *callback_data; /* Can be used in callbacks; e.g., allocate
834*4882a593Smuzhiyun * on enable event and free on disable event.
835*4882a593Smuzhiyun * Host AP driver code does not touch this. */
836*4882a593Smuzhiyun #endif /* PRISM2_CALLBACK */
837*4882a593Smuzhiyun
838*4882a593Smuzhiyun wait_queue_head_t hostscan_wq;
839*4882a593Smuzhiyun
840*4882a593Smuzhiyun /* Passive scan in Host AP mode */
841*4882a593Smuzhiyun struct timer_list passive_scan_timer;
842*4882a593Smuzhiyun int passive_scan_interval; /* in seconds, 0 = disabled */
843*4882a593Smuzhiyun int passive_scan_channel;
844*4882a593Smuzhiyun enum { PASSIVE_SCAN_WAIT, PASSIVE_SCAN_LISTEN } passive_scan_state;
845*4882a593Smuzhiyun
846*4882a593Smuzhiyun struct timer_list tick_timer;
847*4882a593Smuzhiyun unsigned long last_tick_timer;
848*4882a593Smuzhiyun unsigned int sw_tick_stuck;
849*4882a593Smuzhiyun
850*4882a593Smuzhiyun /* commsQuality / dBmCommsQuality data from periodic polling; only
851*4882a593Smuzhiyun * valid for Managed and Ad-hoc modes */
852*4882a593Smuzhiyun unsigned long last_comms_qual_update;
853*4882a593Smuzhiyun int comms_qual; /* in some odd unit.. */
854*4882a593Smuzhiyun int avg_signal; /* in dB (note: negative) */
855*4882a593Smuzhiyun int avg_noise; /* in dB (note: negative) */
856*4882a593Smuzhiyun struct work_struct comms_qual_update;
857*4882a593Smuzhiyun
858*4882a593Smuzhiyun /* RSSI to dBm adjustment (for RX descriptor fields) */
859*4882a593Smuzhiyun int rssi_to_dBm; /* subtract from RSSI to get approximate dBm value */
860*4882a593Smuzhiyun
861*4882a593Smuzhiyun /* BSS list / protected by local->lock */
862*4882a593Smuzhiyun struct list_head bss_list;
863*4882a593Smuzhiyun int num_bss_info;
864*4882a593Smuzhiyun int wpa; /* WPA support enabled */
865*4882a593Smuzhiyun int tkip_countermeasures;
866*4882a593Smuzhiyun int drop_unencrypted;
867*4882a593Smuzhiyun /* Generic IEEE 802.11 info element to be added to
868*4882a593Smuzhiyun * ProbeResp/Beacon/(Re)AssocReq */
869*4882a593Smuzhiyun u8 *generic_elem;
870*4882a593Smuzhiyun size_t generic_elem_len;
871*4882a593Smuzhiyun
872*4882a593Smuzhiyun #ifdef PRISM2_DOWNLOAD_SUPPORT
873*4882a593Smuzhiyun /* Persistent volatile download data */
874*4882a593Smuzhiyun struct prism2_download_data *dl_pri;
875*4882a593Smuzhiyun struct prism2_download_data *dl_sec;
876*4882a593Smuzhiyun #endif /* PRISM2_DOWNLOAD_SUPPORT */
877*4882a593Smuzhiyun
878*4882a593Smuzhiyun #ifdef PRISM2_IO_DEBUG
879*4882a593Smuzhiyun #define PRISM2_IO_DEBUG_SIZE 10000
880*4882a593Smuzhiyun u32 io_debug[PRISM2_IO_DEBUG_SIZE];
881*4882a593Smuzhiyun int io_debug_head;
882*4882a593Smuzhiyun int io_debug_enabled;
883*4882a593Smuzhiyun #endif /* PRISM2_IO_DEBUG */
884*4882a593Smuzhiyun
885*4882a593Smuzhiyun /* Pointer to hardware model specific (cs,pci,plx) private data. */
886*4882a593Smuzhiyun void *hw_priv;
887*4882a593Smuzhiyun };
888*4882a593Smuzhiyun
889*4882a593Smuzhiyun
890*4882a593Smuzhiyun /* Per interface private Host AP data
891*4882a593Smuzhiyun * Allocated for each net device that Host AP uses (wlan#, wlan#ap, wlan#sta,
892*4882a593Smuzhiyun * WDS) and netdev_priv(dev) points to this structure. */
893*4882a593Smuzhiyun struct hostap_interface {
894*4882a593Smuzhiyun struct list_head list; /* list entry in Host AP interface list */
895*4882a593Smuzhiyun struct net_device *dev; /* pointer to this device */
896*4882a593Smuzhiyun struct local_info *local; /* pointer to shared private data */
897*4882a593Smuzhiyun struct net_device_stats stats;
898*4882a593Smuzhiyun struct iw_spy_data spy_data; /* iwspy support */
899*4882a593Smuzhiyun struct iw_public_data wireless_data;
900*4882a593Smuzhiyun
901*4882a593Smuzhiyun enum {
902*4882a593Smuzhiyun HOSTAP_INTERFACE_MASTER,
903*4882a593Smuzhiyun HOSTAP_INTERFACE_MAIN,
904*4882a593Smuzhiyun HOSTAP_INTERFACE_AP,
905*4882a593Smuzhiyun HOSTAP_INTERFACE_STA,
906*4882a593Smuzhiyun HOSTAP_INTERFACE_WDS,
907*4882a593Smuzhiyun } type;
908*4882a593Smuzhiyun
909*4882a593Smuzhiyun union {
910*4882a593Smuzhiyun struct hostap_interface_wds {
911*4882a593Smuzhiyun u8 remote_addr[ETH_ALEN];
912*4882a593Smuzhiyun } wds;
913*4882a593Smuzhiyun } u;
914*4882a593Smuzhiyun };
915*4882a593Smuzhiyun
916*4882a593Smuzhiyun
917*4882a593Smuzhiyun #define HOSTAP_SKB_TX_DATA_MAGIC 0xf08a36a2
918*4882a593Smuzhiyun
919*4882a593Smuzhiyun /*
920*4882a593Smuzhiyun * TX meta data - stored in skb->cb buffer, so this must not be increased over
921*4882a593Smuzhiyun * the 48-byte limit.
922*4882a593Smuzhiyun * THE PADDING THIS STARTS WITH IS A HORRIBLE HACK THAT SHOULD NOT LIVE
923*4882a593Smuzhiyun * TO SEE THE DAY.
924*4882a593Smuzhiyun */
925*4882a593Smuzhiyun struct hostap_skb_tx_data {
926*4882a593Smuzhiyun unsigned int __padding_for_default_qdiscs;
927*4882a593Smuzhiyun u32 magic; /* HOSTAP_SKB_TX_DATA_MAGIC */
928*4882a593Smuzhiyun u8 rate; /* transmit rate */
929*4882a593Smuzhiyun #define HOSTAP_TX_FLAGS_WDS BIT(0)
930*4882a593Smuzhiyun #define HOSTAP_TX_FLAGS_BUFFERED_FRAME BIT(1)
931*4882a593Smuzhiyun #define HOSTAP_TX_FLAGS_ADD_MOREDATA BIT(2)
932*4882a593Smuzhiyun u8 flags; /* HOSTAP_TX_FLAGS_* */
933*4882a593Smuzhiyun u16 tx_cb_idx;
934*4882a593Smuzhiyun struct hostap_interface *iface;
935*4882a593Smuzhiyun unsigned long jiffies; /* queueing timestamp */
936*4882a593Smuzhiyun unsigned short ethertype;
937*4882a593Smuzhiyun };
938*4882a593Smuzhiyun
939*4882a593Smuzhiyun
940*4882a593Smuzhiyun #ifndef PRISM2_NO_DEBUG
941*4882a593Smuzhiyun
942*4882a593Smuzhiyun #define DEBUG_FID BIT(0)
943*4882a593Smuzhiyun #define DEBUG_PS BIT(1)
944*4882a593Smuzhiyun #define DEBUG_FLOW BIT(2)
945*4882a593Smuzhiyun #define DEBUG_AP BIT(3)
946*4882a593Smuzhiyun #define DEBUG_HW BIT(4)
947*4882a593Smuzhiyun #define DEBUG_EXTRA BIT(5)
948*4882a593Smuzhiyun #define DEBUG_EXTRA2 BIT(6)
949*4882a593Smuzhiyun #define DEBUG_PS2 BIT(7)
950*4882a593Smuzhiyun #define DEBUG_MASK (DEBUG_PS | DEBUG_AP | DEBUG_HW | DEBUG_EXTRA)
951*4882a593Smuzhiyun #define PDEBUG(n, args...) \
952*4882a593Smuzhiyun do { if ((n) & DEBUG_MASK) printk(KERN_DEBUG args); } while (0)
953*4882a593Smuzhiyun #define PDEBUG2(n, args...) \
954*4882a593Smuzhiyun do { if ((n) & DEBUG_MASK) printk(args); } while (0)
955*4882a593Smuzhiyun
956*4882a593Smuzhiyun #else /* PRISM2_NO_DEBUG */
957*4882a593Smuzhiyun
958*4882a593Smuzhiyun #define PDEBUG(n, args...)
959*4882a593Smuzhiyun #define PDEBUG2(n, args...)
960*4882a593Smuzhiyun
961*4882a593Smuzhiyun #endif /* PRISM2_NO_DEBUG */
962*4882a593Smuzhiyun
963*4882a593Smuzhiyun enum { BAP0 = 0, BAP1 = 1 };
964*4882a593Smuzhiyun
965*4882a593Smuzhiyun #define PRISM2_IO_DEBUG_CMD_INB 0
966*4882a593Smuzhiyun #define PRISM2_IO_DEBUG_CMD_INW 1
967*4882a593Smuzhiyun #define PRISM2_IO_DEBUG_CMD_INSW 2
968*4882a593Smuzhiyun #define PRISM2_IO_DEBUG_CMD_OUTB 3
969*4882a593Smuzhiyun #define PRISM2_IO_DEBUG_CMD_OUTW 4
970*4882a593Smuzhiyun #define PRISM2_IO_DEBUG_CMD_OUTSW 5
971*4882a593Smuzhiyun #define PRISM2_IO_DEBUG_CMD_ERROR 6
972*4882a593Smuzhiyun #define PRISM2_IO_DEBUG_CMD_INTERRUPT 7
973*4882a593Smuzhiyun
974*4882a593Smuzhiyun #ifdef PRISM2_IO_DEBUG
975*4882a593Smuzhiyun
976*4882a593Smuzhiyun #define PRISM2_IO_DEBUG_ENTRY(cmd, reg, value) \
977*4882a593Smuzhiyun (((cmd) << 24) | ((reg) << 16) | value)
978*4882a593Smuzhiyun
prism2_io_debug_add(struct net_device * dev,int cmd,int reg,int value)979*4882a593Smuzhiyun static inline void prism2_io_debug_add(struct net_device *dev, int cmd,
980*4882a593Smuzhiyun int reg, int value)
981*4882a593Smuzhiyun {
982*4882a593Smuzhiyun struct hostap_interface *iface = netdev_priv(dev);
983*4882a593Smuzhiyun local_info_t *local = iface->local;
984*4882a593Smuzhiyun
985*4882a593Smuzhiyun if (!local->io_debug_enabled)
986*4882a593Smuzhiyun return;
987*4882a593Smuzhiyun
988*4882a593Smuzhiyun local->io_debug[local->io_debug_head] = jiffies & 0xffffffff;
989*4882a593Smuzhiyun if (++local->io_debug_head >= PRISM2_IO_DEBUG_SIZE)
990*4882a593Smuzhiyun local->io_debug_head = 0;
991*4882a593Smuzhiyun local->io_debug[local->io_debug_head] =
992*4882a593Smuzhiyun PRISM2_IO_DEBUG_ENTRY(cmd, reg, value);
993*4882a593Smuzhiyun if (++local->io_debug_head >= PRISM2_IO_DEBUG_SIZE)
994*4882a593Smuzhiyun local->io_debug_head = 0;
995*4882a593Smuzhiyun }
996*4882a593Smuzhiyun
997*4882a593Smuzhiyun
prism2_io_debug_error(struct net_device * dev,int err)998*4882a593Smuzhiyun static inline void prism2_io_debug_error(struct net_device *dev, int err)
999*4882a593Smuzhiyun {
1000*4882a593Smuzhiyun struct hostap_interface *iface = netdev_priv(dev);
1001*4882a593Smuzhiyun local_info_t *local = iface->local;
1002*4882a593Smuzhiyun unsigned long flags;
1003*4882a593Smuzhiyun
1004*4882a593Smuzhiyun if (!local->io_debug_enabled)
1005*4882a593Smuzhiyun return;
1006*4882a593Smuzhiyun
1007*4882a593Smuzhiyun spin_lock_irqsave(&local->lock, flags);
1008*4882a593Smuzhiyun prism2_io_debug_add(dev, PRISM2_IO_DEBUG_CMD_ERROR, 0, err);
1009*4882a593Smuzhiyun if (local->io_debug_enabled == 1) {
1010*4882a593Smuzhiyun local->io_debug_enabled = 0;
1011*4882a593Smuzhiyun printk(KERN_DEBUG "%s: I/O debug stopped\n", dev->name);
1012*4882a593Smuzhiyun }
1013*4882a593Smuzhiyun spin_unlock_irqrestore(&local->lock, flags);
1014*4882a593Smuzhiyun }
1015*4882a593Smuzhiyun
1016*4882a593Smuzhiyun #else /* PRISM2_IO_DEBUG */
1017*4882a593Smuzhiyun
prism2_io_debug_add(struct net_device * dev,int cmd,int reg,int value)1018*4882a593Smuzhiyun static inline void prism2_io_debug_add(struct net_device *dev, int cmd,
1019*4882a593Smuzhiyun int reg, int value)
1020*4882a593Smuzhiyun {
1021*4882a593Smuzhiyun }
1022*4882a593Smuzhiyun
prism2_io_debug_error(struct net_device * dev,int err)1023*4882a593Smuzhiyun static inline void prism2_io_debug_error(struct net_device *dev, int err)
1024*4882a593Smuzhiyun {
1025*4882a593Smuzhiyun }
1026*4882a593Smuzhiyun
1027*4882a593Smuzhiyun #endif /* PRISM2_IO_DEBUG */
1028*4882a593Smuzhiyun
1029*4882a593Smuzhiyun
1030*4882a593Smuzhiyun #ifdef PRISM2_CALLBACK
1031*4882a593Smuzhiyun enum {
1032*4882a593Smuzhiyun /* Called when card is enabled */
1033*4882a593Smuzhiyun PRISM2_CALLBACK_ENABLE,
1034*4882a593Smuzhiyun
1035*4882a593Smuzhiyun /* Called when card is disabled */
1036*4882a593Smuzhiyun PRISM2_CALLBACK_DISABLE,
1037*4882a593Smuzhiyun
1038*4882a593Smuzhiyun /* Called when RX/TX starts/ends */
1039*4882a593Smuzhiyun PRISM2_CALLBACK_RX_START, PRISM2_CALLBACK_RX_END,
1040*4882a593Smuzhiyun PRISM2_CALLBACK_TX_START, PRISM2_CALLBACK_TX_END
1041*4882a593Smuzhiyun };
1042*4882a593Smuzhiyun void prism2_callback(local_info_t *local, int event);
1043*4882a593Smuzhiyun #else /* PRISM2_CALLBACK */
1044*4882a593Smuzhiyun #define prism2_callback(d, e) do { } while (0)
1045*4882a593Smuzhiyun #endif /* PRISM2_CALLBACK */
1046*4882a593Smuzhiyun
1047*4882a593Smuzhiyun #endif /* __KERNEL__ */
1048*4882a593Smuzhiyun
1049*4882a593Smuzhiyun #endif /* HOSTAP_WLAN_H */
1050