1*4882a593Smuzhiyun /******************************************************************************
2*4882a593Smuzhiyun *
3*4882a593Smuzhiyun * This file is provided under a dual BSD/GPLv2 license. When using or
4*4882a593Smuzhiyun * redistributing this file, you may do so under either license.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * GPL LICENSE SUMMARY
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
9*4882a593Smuzhiyun * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10*4882a593Smuzhiyun * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
11*4882a593Smuzhiyun * Copyright(c) 2018 Intel Corporation
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify
14*4882a593Smuzhiyun * it under the terms of version 2 of the GNU General Public License as
15*4882a593Smuzhiyun * published by the Free Software Foundation.
16*4882a593Smuzhiyun *
17*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but
18*4882a593Smuzhiyun * WITHOUT ANY WARRANTY; without even the implied warranty of
19*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20*4882a593Smuzhiyun * General Public License for more details.
21*4882a593Smuzhiyun *
22*4882a593Smuzhiyun * The full GNU General Public License is included in this distribution
23*4882a593Smuzhiyun * in the file called COPYING.
24*4882a593Smuzhiyun *
25*4882a593Smuzhiyun * Contact Information:
26*4882a593Smuzhiyun * Intel Linux Wireless <linuxwifi@intel.com>
27*4882a593Smuzhiyun * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28*4882a593Smuzhiyun *
29*4882a593Smuzhiyun * BSD LICENSE
30*4882a593Smuzhiyun *
31*4882a593Smuzhiyun * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
32*4882a593Smuzhiyun * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
33*4882a593Smuzhiyun * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
34*4882a593Smuzhiyun * Copyright(c) 2018 Intel Corporation
35*4882a593Smuzhiyun * All rights reserved.
36*4882a593Smuzhiyun *
37*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or without
38*4882a593Smuzhiyun * modification, are permitted provided that the following conditions
39*4882a593Smuzhiyun * are met:
40*4882a593Smuzhiyun *
41*4882a593Smuzhiyun * * Redistributions of source code must retain the above copyright
42*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer.
43*4882a593Smuzhiyun * * Redistributions in binary form must reproduce the above copyright
44*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer in
45*4882a593Smuzhiyun * the documentation and/or other materials provided with the
46*4882a593Smuzhiyun * distribution.
47*4882a593Smuzhiyun * * Neither the name Intel Corporation nor the names of its
48*4882a593Smuzhiyun * contributors may be used to endorse or promote products derived
49*4882a593Smuzhiyun * from this software without specific prior written permission.
50*4882a593Smuzhiyun *
51*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
52*4882a593Smuzhiyun * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
53*4882a593Smuzhiyun * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
54*4882a593Smuzhiyun * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
55*4882a593Smuzhiyun * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
56*4882a593Smuzhiyun * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
57*4882a593Smuzhiyun * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
58*4882a593Smuzhiyun * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
59*4882a593Smuzhiyun * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
60*4882a593Smuzhiyun * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
61*4882a593Smuzhiyun * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62*4882a593Smuzhiyun *
63*4882a593Smuzhiyun *****************************************************************************/
64*4882a593Smuzhiyun #include <linux/firmware.h>
65*4882a593Smuzhiyun #include <linux/rtnetlink.h>
66*4882a593Smuzhiyun #include "iwl-trans.h"
67*4882a593Smuzhiyun #include "iwl-csr.h"
68*4882a593Smuzhiyun #include "mvm.h"
69*4882a593Smuzhiyun #include "iwl-eeprom-parse.h"
70*4882a593Smuzhiyun #include "iwl-eeprom-read.h"
71*4882a593Smuzhiyun #include "iwl-nvm-parse.h"
72*4882a593Smuzhiyun #include "iwl-prph.h"
73*4882a593Smuzhiyun #include "fw/acpi.h"
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* Default NVM size to read */
76*4882a593Smuzhiyun #define IWL_NVM_DEFAULT_CHUNK_SIZE (2 * 1024)
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun #define NVM_WRITE_OPCODE 1
79*4882a593Smuzhiyun #define NVM_READ_OPCODE 0
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /* load nvm chunk response */
82*4882a593Smuzhiyun enum {
83*4882a593Smuzhiyun READ_NVM_CHUNK_SUCCEED = 0,
84*4882a593Smuzhiyun READ_NVM_CHUNK_NOT_VALID_ADDRESS = 1
85*4882a593Smuzhiyun };
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /*
88*4882a593Smuzhiyun * prepare the NVM host command w/ the pointers to the nvm buffer
89*4882a593Smuzhiyun * and send it to fw
90*4882a593Smuzhiyun */
iwl_nvm_write_chunk(struct iwl_mvm * mvm,u16 section,u16 offset,u16 length,const u8 * data)91*4882a593Smuzhiyun static int iwl_nvm_write_chunk(struct iwl_mvm *mvm, u16 section,
92*4882a593Smuzhiyun u16 offset, u16 length, const u8 *data)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun struct iwl_nvm_access_cmd nvm_access_cmd = {
95*4882a593Smuzhiyun .offset = cpu_to_le16(offset),
96*4882a593Smuzhiyun .length = cpu_to_le16(length),
97*4882a593Smuzhiyun .type = cpu_to_le16(section),
98*4882a593Smuzhiyun .op_code = NVM_WRITE_OPCODE,
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun struct iwl_host_cmd cmd = {
101*4882a593Smuzhiyun .id = NVM_ACCESS_CMD,
102*4882a593Smuzhiyun .len = { sizeof(struct iwl_nvm_access_cmd), length },
103*4882a593Smuzhiyun .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL,
104*4882a593Smuzhiyun .data = { &nvm_access_cmd, data },
105*4882a593Smuzhiyun /* data may come from vmalloc, so use _DUP */
106*4882a593Smuzhiyun .dataflags = { 0, IWL_HCMD_DFL_DUP },
107*4882a593Smuzhiyun };
108*4882a593Smuzhiyun struct iwl_rx_packet *pkt;
109*4882a593Smuzhiyun struct iwl_nvm_access_resp *nvm_resp;
110*4882a593Smuzhiyun int ret;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun ret = iwl_mvm_send_cmd(mvm, &cmd);
113*4882a593Smuzhiyun if (ret)
114*4882a593Smuzhiyun return ret;
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun pkt = cmd.resp_pkt;
117*4882a593Smuzhiyun /* Extract & check NVM write response */
118*4882a593Smuzhiyun nvm_resp = (void *)pkt->data;
119*4882a593Smuzhiyun if (le16_to_cpu(nvm_resp->status) != READ_NVM_CHUNK_SUCCEED) {
120*4882a593Smuzhiyun IWL_ERR(mvm,
121*4882a593Smuzhiyun "NVM access write command failed for section %u (status = 0x%x)\n",
122*4882a593Smuzhiyun section, le16_to_cpu(nvm_resp->status));
123*4882a593Smuzhiyun ret = -EIO;
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun iwl_free_resp(&cmd);
127*4882a593Smuzhiyun return ret;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
iwl_nvm_read_chunk(struct iwl_mvm * mvm,u16 section,u16 offset,u16 length,u8 * data)130*4882a593Smuzhiyun static int iwl_nvm_read_chunk(struct iwl_mvm *mvm, u16 section,
131*4882a593Smuzhiyun u16 offset, u16 length, u8 *data)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun struct iwl_nvm_access_cmd nvm_access_cmd = {
134*4882a593Smuzhiyun .offset = cpu_to_le16(offset),
135*4882a593Smuzhiyun .length = cpu_to_le16(length),
136*4882a593Smuzhiyun .type = cpu_to_le16(section),
137*4882a593Smuzhiyun .op_code = NVM_READ_OPCODE,
138*4882a593Smuzhiyun };
139*4882a593Smuzhiyun struct iwl_nvm_access_resp *nvm_resp;
140*4882a593Smuzhiyun struct iwl_rx_packet *pkt;
141*4882a593Smuzhiyun struct iwl_host_cmd cmd = {
142*4882a593Smuzhiyun .id = NVM_ACCESS_CMD,
143*4882a593Smuzhiyun .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL,
144*4882a593Smuzhiyun .data = { &nvm_access_cmd, },
145*4882a593Smuzhiyun };
146*4882a593Smuzhiyun int ret, bytes_read, offset_read;
147*4882a593Smuzhiyun u8 *resp_data;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun cmd.len[0] = sizeof(struct iwl_nvm_access_cmd);
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun ret = iwl_mvm_send_cmd(mvm, &cmd);
152*4882a593Smuzhiyun if (ret)
153*4882a593Smuzhiyun return ret;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun pkt = cmd.resp_pkt;
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun /* Extract NVM response */
158*4882a593Smuzhiyun nvm_resp = (void *)pkt->data;
159*4882a593Smuzhiyun ret = le16_to_cpu(nvm_resp->status);
160*4882a593Smuzhiyun bytes_read = le16_to_cpu(nvm_resp->length);
161*4882a593Smuzhiyun offset_read = le16_to_cpu(nvm_resp->offset);
162*4882a593Smuzhiyun resp_data = nvm_resp->data;
163*4882a593Smuzhiyun if (ret) {
164*4882a593Smuzhiyun if ((offset != 0) &&
165*4882a593Smuzhiyun (ret == READ_NVM_CHUNK_NOT_VALID_ADDRESS)) {
166*4882a593Smuzhiyun /*
167*4882a593Smuzhiyun * meaning of NOT_VALID_ADDRESS:
168*4882a593Smuzhiyun * driver try to read chunk from address that is
169*4882a593Smuzhiyun * multiple of 2K and got an error since addr is empty.
170*4882a593Smuzhiyun * meaning of (offset != 0): driver already
171*4882a593Smuzhiyun * read valid data from another chunk so this case
172*4882a593Smuzhiyun * is not an error.
173*4882a593Smuzhiyun */
174*4882a593Smuzhiyun IWL_DEBUG_EEPROM(mvm->trans->dev,
175*4882a593Smuzhiyun "NVM access command failed on offset 0x%x since that section size is multiple 2K\n",
176*4882a593Smuzhiyun offset);
177*4882a593Smuzhiyun ret = 0;
178*4882a593Smuzhiyun } else {
179*4882a593Smuzhiyun IWL_DEBUG_EEPROM(mvm->trans->dev,
180*4882a593Smuzhiyun "NVM access command failed with status %d (device: %s)\n",
181*4882a593Smuzhiyun ret, mvm->trans->name);
182*4882a593Smuzhiyun ret = -ENODATA;
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun goto exit;
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun if (offset_read != offset) {
188*4882a593Smuzhiyun IWL_ERR(mvm, "NVM ACCESS response with invalid offset %d\n",
189*4882a593Smuzhiyun offset_read);
190*4882a593Smuzhiyun ret = -EINVAL;
191*4882a593Smuzhiyun goto exit;
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun /* Write data to NVM */
195*4882a593Smuzhiyun memcpy(data + offset, resp_data, bytes_read);
196*4882a593Smuzhiyun ret = bytes_read;
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun exit:
199*4882a593Smuzhiyun iwl_free_resp(&cmd);
200*4882a593Smuzhiyun return ret;
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun
iwl_nvm_write_section(struct iwl_mvm * mvm,u16 section,const u8 * data,u16 length)203*4882a593Smuzhiyun static int iwl_nvm_write_section(struct iwl_mvm *mvm, u16 section,
204*4882a593Smuzhiyun const u8 *data, u16 length)
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun int offset = 0;
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun /* copy data in chunks of 2k (and remainder if any) */
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun while (offset < length) {
211*4882a593Smuzhiyun int chunk_size, ret;
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun chunk_size = min(IWL_NVM_DEFAULT_CHUNK_SIZE,
214*4882a593Smuzhiyun length - offset);
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun ret = iwl_nvm_write_chunk(mvm, section, offset,
217*4882a593Smuzhiyun chunk_size, data + offset);
218*4882a593Smuzhiyun if (ret < 0)
219*4882a593Smuzhiyun return ret;
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun offset += chunk_size;
222*4882a593Smuzhiyun }
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun return 0;
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun /*
228*4882a593Smuzhiyun * Reads an NVM section completely.
229*4882a593Smuzhiyun * NICs prior to 7000 family doesn't have a real NVM, but just read
230*4882a593Smuzhiyun * section 0 which is the EEPROM. Because the EEPROM reading is unlimited
231*4882a593Smuzhiyun * by uCode, we need to manually check in this case that we don't
232*4882a593Smuzhiyun * overflow and try to read more than the EEPROM size.
233*4882a593Smuzhiyun * For 7000 family NICs, we supply the maximal size we can read, and
234*4882a593Smuzhiyun * the uCode fills the response with as much data as we can,
235*4882a593Smuzhiyun * without overflowing, so no check is needed.
236*4882a593Smuzhiyun */
iwl_nvm_read_section(struct iwl_mvm * mvm,u16 section,u8 * data,u32 size_read)237*4882a593Smuzhiyun static int iwl_nvm_read_section(struct iwl_mvm *mvm, u16 section,
238*4882a593Smuzhiyun u8 *data, u32 size_read)
239*4882a593Smuzhiyun {
240*4882a593Smuzhiyun u16 length, offset = 0;
241*4882a593Smuzhiyun int ret;
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun /* Set nvm section read length */
244*4882a593Smuzhiyun length = IWL_NVM_DEFAULT_CHUNK_SIZE;
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun ret = length;
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun /* Read the NVM until exhausted (reading less than requested) */
249*4882a593Smuzhiyun while (ret == length) {
250*4882a593Smuzhiyun /* Check no memory assumptions fail and cause an overflow */
251*4882a593Smuzhiyun if ((size_read + offset + length) >
252*4882a593Smuzhiyun mvm->trans->trans_cfg->base_params->eeprom_size) {
253*4882a593Smuzhiyun IWL_ERR(mvm, "EEPROM size is too small for NVM\n");
254*4882a593Smuzhiyun return -ENOBUFS;
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun ret = iwl_nvm_read_chunk(mvm, section, offset, length, data);
258*4882a593Smuzhiyun if (ret < 0) {
259*4882a593Smuzhiyun IWL_DEBUG_EEPROM(mvm->trans->dev,
260*4882a593Smuzhiyun "Cannot read NVM from section %d offset %d, length %d\n",
261*4882a593Smuzhiyun section, offset, length);
262*4882a593Smuzhiyun return ret;
263*4882a593Smuzhiyun }
264*4882a593Smuzhiyun offset += ret;
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun iwl_nvm_fixups(mvm->trans->hw_id, section, data, offset);
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun IWL_DEBUG_EEPROM(mvm->trans->dev,
270*4882a593Smuzhiyun "NVM section %d read completed\n", section);
271*4882a593Smuzhiyun return offset;
272*4882a593Smuzhiyun }
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun static struct iwl_nvm_data *
iwl_parse_nvm_sections(struct iwl_mvm * mvm)275*4882a593Smuzhiyun iwl_parse_nvm_sections(struct iwl_mvm *mvm)
276*4882a593Smuzhiyun {
277*4882a593Smuzhiyun struct iwl_nvm_section *sections = mvm->nvm_sections;
278*4882a593Smuzhiyun const __be16 *hw;
279*4882a593Smuzhiyun const __le16 *sw, *calib, *regulatory, *mac_override, *phy_sku;
280*4882a593Smuzhiyun int regulatory_type;
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun /* Checking for required sections */
283*4882a593Smuzhiyun if (mvm->trans->cfg->nvm_type == IWL_NVM) {
284*4882a593Smuzhiyun if (!mvm->nvm_sections[NVM_SECTION_TYPE_SW].data ||
285*4882a593Smuzhiyun !mvm->nvm_sections[mvm->cfg->nvm_hw_section_num].data) {
286*4882a593Smuzhiyun IWL_ERR(mvm, "Can't parse empty OTP/NVM sections\n");
287*4882a593Smuzhiyun return NULL;
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun } else {
290*4882a593Smuzhiyun if (mvm->trans->cfg->nvm_type == IWL_NVM_SDP)
291*4882a593Smuzhiyun regulatory_type = NVM_SECTION_TYPE_REGULATORY_SDP;
292*4882a593Smuzhiyun else
293*4882a593Smuzhiyun regulatory_type = NVM_SECTION_TYPE_REGULATORY;
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun /* SW and REGULATORY sections are mandatory */
296*4882a593Smuzhiyun if (!mvm->nvm_sections[NVM_SECTION_TYPE_SW].data ||
297*4882a593Smuzhiyun !mvm->nvm_sections[regulatory_type].data) {
298*4882a593Smuzhiyun IWL_ERR(mvm,
299*4882a593Smuzhiyun "Can't parse empty family 8000 OTP/NVM sections\n");
300*4882a593Smuzhiyun return NULL;
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun /* MAC_OVERRIDE or at least HW section must exist */
303*4882a593Smuzhiyun if (!mvm->nvm_sections[mvm->cfg->nvm_hw_section_num].data &&
304*4882a593Smuzhiyun !mvm->nvm_sections[NVM_SECTION_TYPE_MAC_OVERRIDE].data) {
305*4882a593Smuzhiyun IWL_ERR(mvm,
306*4882a593Smuzhiyun "Can't parse mac_address, empty sections\n");
307*4882a593Smuzhiyun return NULL;
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun /* PHY_SKU section is mandatory in B0 */
311*4882a593Smuzhiyun if (mvm->trans->cfg->nvm_type == IWL_NVM_EXT &&
312*4882a593Smuzhiyun !mvm->nvm_sections[NVM_SECTION_TYPE_PHY_SKU].data) {
313*4882a593Smuzhiyun IWL_ERR(mvm,
314*4882a593Smuzhiyun "Can't parse phy_sku in B0, empty sections\n");
315*4882a593Smuzhiyun return NULL;
316*4882a593Smuzhiyun }
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun hw = (const __be16 *)sections[mvm->cfg->nvm_hw_section_num].data;
320*4882a593Smuzhiyun sw = (const __le16 *)sections[NVM_SECTION_TYPE_SW].data;
321*4882a593Smuzhiyun calib = (const __le16 *)sections[NVM_SECTION_TYPE_CALIBRATION].data;
322*4882a593Smuzhiyun mac_override =
323*4882a593Smuzhiyun (const __le16 *)sections[NVM_SECTION_TYPE_MAC_OVERRIDE].data;
324*4882a593Smuzhiyun phy_sku = (const __le16 *)sections[NVM_SECTION_TYPE_PHY_SKU].data;
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun regulatory = mvm->trans->cfg->nvm_type == IWL_NVM_SDP ?
327*4882a593Smuzhiyun (const __le16 *)sections[NVM_SECTION_TYPE_REGULATORY_SDP].data :
328*4882a593Smuzhiyun (const __le16 *)sections[NVM_SECTION_TYPE_REGULATORY].data;
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun return iwl_parse_nvm_data(mvm->trans, mvm->cfg, mvm->fw, hw, sw, calib,
331*4882a593Smuzhiyun regulatory, mac_override, phy_sku,
332*4882a593Smuzhiyun mvm->fw->valid_tx_ant, mvm->fw->valid_rx_ant);
333*4882a593Smuzhiyun }
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun /* Loads the NVM data stored in mvm->nvm_sections into the NIC */
iwl_mvm_load_nvm_to_nic(struct iwl_mvm * mvm)336*4882a593Smuzhiyun int iwl_mvm_load_nvm_to_nic(struct iwl_mvm *mvm)
337*4882a593Smuzhiyun {
338*4882a593Smuzhiyun int i, ret = 0;
339*4882a593Smuzhiyun struct iwl_nvm_section *sections = mvm->nvm_sections;
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun IWL_DEBUG_EEPROM(mvm->trans->dev, "'Write to NVM\n");
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(mvm->nvm_sections); i++) {
344*4882a593Smuzhiyun if (!mvm->nvm_sections[i].data || !mvm->nvm_sections[i].length)
345*4882a593Smuzhiyun continue;
346*4882a593Smuzhiyun ret = iwl_nvm_write_section(mvm, i, sections[i].data,
347*4882a593Smuzhiyun sections[i].length);
348*4882a593Smuzhiyun if (ret < 0) {
349*4882a593Smuzhiyun IWL_ERR(mvm, "iwl_mvm_send_cmd failed: %d\n", ret);
350*4882a593Smuzhiyun break;
351*4882a593Smuzhiyun }
352*4882a593Smuzhiyun }
353*4882a593Smuzhiyun return ret;
354*4882a593Smuzhiyun }
355*4882a593Smuzhiyun
iwl_nvm_init(struct iwl_mvm * mvm)356*4882a593Smuzhiyun int iwl_nvm_init(struct iwl_mvm *mvm)
357*4882a593Smuzhiyun {
358*4882a593Smuzhiyun int ret, section;
359*4882a593Smuzhiyun u32 size_read = 0;
360*4882a593Smuzhiyun u8 *nvm_buffer, *temp;
361*4882a593Smuzhiyun const char *nvm_file_C = mvm->cfg->default_nvm_file_C_step;
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun if (WARN_ON_ONCE(mvm->cfg->nvm_hw_section_num >= NVM_MAX_NUM_SECTIONS))
364*4882a593Smuzhiyun return -EINVAL;
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun /* load NVM values from nic */
367*4882a593Smuzhiyun /* Read From FW NVM */
368*4882a593Smuzhiyun IWL_DEBUG_EEPROM(mvm->trans->dev, "Read from NVM\n");
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun nvm_buffer = kmalloc(mvm->trans->trans_cfg->base_params->eeprom_size,
371*4882a593Smuzhiyun GFP_KERNEL);
372*4882a593Smuzhiyun if (!nvm_buffer)
373*4882a593Smuzhiyun return -ENOMEM;
374*4882a593Smuzhiyun for (section = 0; section < NVM_MAX_NUM_SECTIONS; section++) {
375*4882a593Smuzhiyun /* we override the constness for initial read */
376*4882a593Smuzhiyun ret = iwl_nvm_read_section(mvm, section, nvm_buffer,
377*4882a593Smuzhiyun size_read);
378*4882a593Smuzhiyun if (ret == -ENODATA) {
379*4882a593Smuzhiyun ret = 0;
380*4882a593Smuzhiyun continue;
381*4882a593Smuzhiyun }
382*4882a593Smuzhiyun if (ret < 0)
383*4882a593Smuzhiyun break;
384*4882a593Smuzhiyun size_read += ret;
385*4882a593Smuzhiyun temp = kmemdup(nvm_buffer, ret, GFP_KERNEL);
386*4882a593Smuzhiyun if (!temp) {
387*4882a593Smuzhiyun ret = -ENOMEM;
388*4882a593Smuzhiyun break;
389*4882a593Smuzhiyun }
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun iwl_nvm_fixups(mvm->trans->hw_id, section, temp, ret);
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun mvm->nvm_sections[section].data = temp;
394*4882a593Smuzhiyun mvm->nvm_sections[section].length = ret;
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun #ifdef CONFIG_IWLWIFI_DEBUGFS
397*4882a593Smuzhiyun switch (section) {
398*4882a593Smuzhiyun case NVM_SECTION_TYPE_SW:
399*4882a593Smuzhiyun mvm->nvm_sw_blob.data = temp;
400*4882a593Smuzhiyun mvm->nvm_sw_blob.size = ret;
401*4882a593Smuzhiyun break;
402*4882a593Smuzhiyun case NVM_SECTION_TYPE_CALIBRATION:
403*4882a593Smuzhiyun mvm->nvm_calib_blob.data = temp;
404*4882a593Smuzhiyun mvm->nvm_calib_blob.size = ret;
405*4882a593Smuzhiyun break;
406*4882a593Smuzhiyun case NVM_SECTION_TYPE_PRODUCTION:
407*4882a593Smuzhiyun mvm->nvm_prod_blob.data = temp;
408*4882a593Smuzhiyun mvm->nvm_prod_blob.size = ret;
409*4882a593Smuzhiyun break;
410*4882a593Smuzhiyun case NVM_SECTION_TYPE_PHY_SKU:
411*4882a593Smuzhiyun mvm->nvm_phy_sku_blob.data = temp;
412*4882a593Smuzhiyun mvm->nvm_phy_sku_blob.size = ret;
413*4882a593Smuzhiyun break;
414*4882a593Smuzhiyun case NVM_SECTION_TYPE_REGULATORY_SDP:
415*4882a593Smuzhiyun case NVM_SECTION_TYPE_REGULATORY:
416*4882a593Smuzhiyun mvm->nvm_reg_blob.data = temp;
417*4882a593Smuzhiyun mvm->nvm_reg_blob.size = ret;
418*4882a593Smuzhiyun break;
419*4882a593Smuzhiyun default:
420*4882a593Smuzhiyun if (section == mvm->cfg->nvm_hw_section_num) {
421*4882a593Smuzhiyun mvm->nvm_hw_blob.data = temp;
422*4882a593Smuzhiyun mvm->nvm_hw_blob.size = ret;
423*4882a593Smuzhiyun break;
424*4882a593Smuzhiyun }
425*4882a593Smuzhiyun }
426*4882a593Smuzhiyun #endif
427*4882a593Smuzhiyun }
428*4882a593Smuzhiyun if (!size_read)
429*4882a593Smuzhiyun IWL_ERR(mvm, "OTP is blank\n");
430*4882a593Smuzhiyun kfree(nvm_buffer);
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun /* Only if PNVM selected in the mod param - load external NVM */
433*4882a593Smuzhiyun if (mvm->nvm_file_name) {
434*4882a593Smuzhiyun /* read External NVM file from the mod param */
435*4882a593Smuzhiyun ret = iwl_read_external_nvm(mvm->trans, mvm->nvm_file_name,
436*4882a593Smuzhiyun mvm->nvm_sections);
437*4882a593Smuzhiyun if (ret) {
438*4882a593Smuzhiyun mvm->nvm_file_name = nvm_file_C;
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun if ((ret == -EFAULT || ret == -ENOENT) &&
441*4882a593Smuzhiyun mvm->nvm_file_name) {
442*4882a593Smuzhiyun /* in case nvm file was failed try again */
443*4882a593Smuzhiyun ret = iwl_read_external_nvm(mvm->trans,
444*4882a593Smuzhiyun mvm->nvm_file_name,
445*4882a593Smuzhiyun mvm->nvm_sections);
446*4882a593Smuzhiyun if (ret)
447*4882a593Smuzhiyun return ret;
448*4882a593Smuzhiyun } else {
449*4882a593Smuzhiyun return ret;
450*4882a593Smuzhiyun }
451*4882a593Smuzhiyun }
452*4882a593Smuzhiyun }
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun /* parse the relevant nvm sections */
455*4882a593Smuzhiyun mvm->nvm_data = iwl_parse_nvm_sections(mvm);
456*4882a593Smuzhiyun if (!mvm->nvm_data)
457*4882a593Smuzhiyun return -ENODATA;
458*4882a593Smuzhiyun IWL_DEBUG_EEPROM(mvm->trans->dev, "nvm version = %x\n",
459*4882a593Smuzhiyun mvm->nvm_data->nvm_version);
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun return ret < 0 ? ret : 0;
462*4882a593Smuzhiyun }
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun struct iwl_mcc_update_resp *
iwl_mvm_update_mcc(struct iwl_mvm * mvm,const char * alpha2,enum iwl_mcc_source src_id)465*4882a593Smuzhiyun iwl_mvm_update_mcc(struct iwl_mvm *mvm, const char *alpha2,
466*4882a593Smuzhiyun enum iwl_mcc_source src_id)
467*4882a593Smuzhiyun {
468*4882a593Smuzhiyun struct iwl_mcc_update_cmd mcc_update_cmd = {
469*4882a593Smuzhiyun .mcc = cpu_to_le16(alpha2[0] << 8 | alpha2[1]),
470*4882a593Smuzhiyun .source_id = (u8)src_id,
471*4882a593Smuzhiyun };
472*4882a593Smuzhiyun struct iwl_mcc_update_resp *resp_cp;
473*4882a593Smuzhiyun struct iwl_rx_packet *pkt;
474*4882a593Smuzhiyun struct iwl_host_cmd cmd = {
475*4882a593Smuzhiyun .id = MCC_UPDATE_CMD,
476*4882a593Smuzhiyun .flags = CMD_WANT_SKB,
477*4882a593Smuzhiyun .data = { &mcc_update_cmd },
478*4882a593Smuzhiyun };
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun int ret;
481*4882a593Smuzhiyun u32 status;
482*4882a593Smuzhiyun int resp_len, n_channels;
483*4882a593Smuzhiyun u16 mcc;
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun if (WARN_ON_ONCE(!iwl_mvm_is_lar_supported(mvm)))
486*4882a593Smuzhiyun return ERR_PTR(-EOPNOTSUPP);
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun cmd.len[0] = sizeof(struct iwl_mcc_update_cmd);
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun IWL_DEBUG_LAR(mvm, "send MCC update to FW with '%c%c' src = %d\n",
491*4882a593Smuzhiyun alpha2[0], alpha2[1], src_id);
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun ret = iwl_mvm_send_cmd(mvm, &cmd);
494*4882a593Smuzhiyun if (ret)
495*4882a593Smuzhiyun return ERR_PTR(ret);
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun pkt = cmd.resp_pkt;
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun /* Extract MCC response */
500*4882a593Smuzhiyun if (fw_has_capa(&mvm->fw->ucode_capa,
501*4882a593Smuzhiyun IWL_UCODE_TLV_CAPA_MCC_UPDATE_11AX_SUPPORT)) {
502*4882a593Smuzhiyun struct iwl_mcc_update_resp *mcc_resp = (void *)pkt->data;
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun n_channels = __le32_to_cpu(mcc_resp->n_channels);
505*4882a593Smuzhiyun resp_len = sizeof(struct iwl_mcc_update_resp) +
506*4882a593Smuzhiyun n_channels * sizeof(__le32);
507*4882a593Smuzhiyun resp_cp = kmemdup(mcc_resp, resp_len, GFP_KERNEL);
508*4882a593Smuzhiyun if (!resp_cp) {
509*4882a593Smuzhiyun resp_cp = ERR_PTR(-ENOMEM);
510*4882a593Smuzhiyun goto exit;
511*4882a593Smuzhiyun }
512*4882a593Smuzhiyun } else {
513*4882a593Smuzhiyun struct iwl_mcc_update_resp_v3 *mcc_resp_v3 = (void *)pkt->data;
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun n_channels = __le32_to_cpu(mcc_resp_v3->n_channels);
516*4882a593Smuzhiyun resp_len = sizeof(struct iwl_mcc_update_resp) +
517*4882a593Smuzhiyun n_channels * sizeof(__le32);
518*4882a593Smuzhiyun resp_cp = kzalloc(resp_len, GFP_KERNEL);
519*4882a593Smuzhiyun if (!resp_cp) {
520*4882a593Smuzhiyun resp_cp = ERR_PTR(-ENOMEM);
521*4882a593Smuzhiyun goto exit;
522*4882a593Smuzhiyun }
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun resp_cp->status = mcc_resp_v3->status;
525*4882a593Smuzhiyun resp_cp->mcc = mcc_resp_v3->mcc;
526*4882a593Smuzhiyun resp_cp->cap = cpu_to_le16(mcc_resp_v3->cap);
527*4882a593Smuzhiyun resp_cp->source_id = mcc_resp_v3->source_id;
528*4882a593Smuzhiyun resp_cp->time = mcc_resp_v3->time;
529*4882a593Smuzhiyun resp_cp->geo_info = mcc_resp_v3->geo_info;
530*4882a593Smuzhiyun resp_cp->n_channels = mcc_resp_v3->n_channels;
531*4882a593Smuzhiyun memcpy(resp_cp->channels, mcc_resp_v3->channels,
532*4882a593Smuzhiyun n_channels * sizeof(__le32));
533*4882a593Smuzhiyun }
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun status = le32_to_cpu(resp_cp->status);
536*4882a593Smuzhiyun
537*4882a593Smuzhiyun mcc = le16_to_cpu(resp_cp->mcc);
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun /* W/A for a FW/NVM issue - returns 0x00 for the world domain */
540*4882a593Smuzhiyun if (mcc == 0) {
541*4882a593Smuzhiyun mcc = 0x3030; /* "00" - world */
542*4882a593Smuzhiyun resp_cp->mcc = cpu_to_le16(mcc);
543*4882a593Smuzhiyun }
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun IWL_DEBUG_LAR(mvm,
546*4882a593Smuzhiyun "MCC response status: 0x%x. new MCC: 0x%x ('%c%c') n_chans: %d\n",
547*4882a593Smuzhiyun status, mcc, mcc >> 8, mcc & 0xff, n_channels);
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun exit:
550*4882a593Smuzhiyun iwl_free_resp(&cmd);
551*4882a593Smuzhiyun return resp_cp;
552*4882a593Smuzhiyun }
553*4882a593Smuzhiyun
iwl_mvm_init_mcc(struct iwl_mvm * mvm)554*4882a593Smuzhiyun int iwl_mvm_init_mcc(struct iwl_mvm *mvm)
555*4882a593Smuzhiyun {
556*4882a593Smuzhiyun bool tlv_lar;
557*4882a593Smuzhiyun bool nvm_lar;
558*4882a593Smuzhiyun int retval;
559*4882a593Smuzhiyun struct ieee80211_regdomain *regd;
560*4882a593Smuzhiyun char mcc[3];
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun if (mvm->cfg->nvm_type == IWL_NVM_EXT) {
563*4882a593Smuzhiyun tlv_lar = fw_has_capa(&mvm->fw->ucode_capa,
564*4882a593Smuzhiyun IWL_UCODE_TLV_CAPA_LAR_SUPPORT);
565*4882a593Smuzhiyun nvm_lar = mvm->nvm_data->lar_enabled;
566*4882a593Smuzhiyun if (tlv_lar != nvm_lar)
567*4882a593Smuzhiyun IWL_INFO(mvm,
568*4882a593Smuzhiyun "Conflict between TLV & NVM regarding enabling LAR (TLV = %s NVM =%s)\n",
569*4882a593Smuzhiyun tlv_lar ? "enabled" : "disabled",
570*4882a593Smuzhiyun nvm_lar ? "enabled" : "disabled");
571*4882a593Smuzhiyun }
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun if (!iwl_mvm_is_lar_supported(mvm))
574*4882a593Smuzhiyun return 0;
575*4882a593Smuzhiyun
576*4882a593Smuzhiyun /*
577*4882a593Smuzhiyun * try to replay the last set MCC to FW. If it doesn't exist,
578*4882a593Smuzhiyun * queue an update to cfg80211 to retrieve the default alpha2 from FW.
579*4882a593Smuzhiyun */
580*4882a593Smuzhiyun retval = iwl_mvm_init_fw_regd(mvm);
581*4882a593Smuzhiyun if (retval != -ENOENT)
582*4882a593Smuzhiyun return retval;
583*4882a593Smuzhiyun
584*4882a593Smuzhiyun /*
585*4882a593Smuzhiyun * Driver regulatory hint for initial update, this also informs the
586*4882a593Smuzhiyun * firmware we support wifi location updates.
587*4882a593Smuzhiyun * Disallow scans that might crash the FW while the LAR regdomain
588*4882a593Smuzhiyun * is not set.
589*4882a593Smuzhiyun */
590*4882a593Smuzhiyun mvm->lar_regdom_set = false;
591*4882a593Smuzhiyun
592*4882a593Smuzhiyun regd = iwl_mvm_get_current_regdomain(mvm, NULL);
593*4882a593Smuzhiyun if (IS_ERR_OR_NULL(regd))
594*4882a593Smuzhiyun return -EIO;
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun if (iwl_mvm_is_wifi_mcc_supported(mvm) &&
597*4882a593Smuzhiyun !iwl_acpi_get_mcc(mvm->dev, mcc)) {
598*4882a593Smuzhiyun kfree(regd);
599*4882a593Smuzhiyun regd = iwl_mvm_get_regdomain(mvm->hw->wiphy, mcc,
600*4882a593Smuzhiyun MCC_SOURCE_BIOS, NULL);
601*4882a593Smuzhiyun if (IS_ERR_OR_NULL(regd))
602*4882a593Smuzhiyun return -EIO;
603*4882a593Smuzhiyun }
604*4882a593Smuzhiyun
605*4882a593Smuzhiyun retval = regulatory_set_wiphy_regd_sync_rtnl(mvm->hw->wiphy, regd);
606*4882a593Smuzhiyun kfree(regd);
607*4882a593Smuzhiyun return retval;
608*4882a593Smuzhiyun }
609*4882a593Smuzhiyun
iwl_mvm_rx_chub_update_mcc(struct iwl_mvm * mvm,struct iwl_rx_cmd_buffer * rxb)610*4882a593Smuzhiyun void iwl_mvm_rx_chub_update_mcc(struct iwl_mvm *mvm,
611*4882a593Smuzhiyun struct iwl_rx_cmd_buffer *rxb)
612*4882a593Smuzhiyun {
613*4882a593Smuzhiyun struct iwl_rx_packet *pkt = rxb_addr(rxb);
614*4882a593Smuzhiyun struct iwl_mcc_chub_notif *notif = (void *)pkt->data;
615*4882a593Smuzhiyun enum iwl_mcc_source src;
616*4882a593Smuzhiyun char mcc[3];
617*4882a593Smuzhiyun struct ieee80211_regdomain *regd;
618*4882a593Smuzhiyun int wgds_tbl_idx;
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun lockdep_assert_held(&mvm->mutex);
621*4882a593Smuzhiyun
622*4882a593Smuzhiyun if (iwl_mvm_is_vif_assoc(mvm) && notif->source_id == MCC_SOURCE_WIFI) {
623*4882a593Smuzhiyun IWL_DEBUG_LAR(mvm, "Ignore mcc update while associated\n");
624*4882a593Smuzhiyun return;
625*4882a593Smuzhiyun }
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun if (WARN_ON_ONCE(!iwl_mvm_is_lar_supported(mvm)))
628*4882a593Smuzhiyun return;
629*4882a593Smuzhiyun
630*4882a593Smuzhiyun mcc[0] = le16_to_cpu(notif->mcc) >> 8;
631*4882a593Smuzhiyun mcc[1] = le16_to_cpu(notif->mcc) & 0xff;
632*4882a593Smuzhiyun mcc[2] = '\0';
633*4882a593Smuzhiyun src = notif->source_id;
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun IWL_DEBUG_LAR(mvm,
636*4882a593Smuzhiyun "RX: received chub update mcc cmd (mcc '%s' src %d)\n",
637*4882a593Smuzhiyun mcc, src);
638*4882a593Smuzhiyun regd = iwl_mvm_get_regdomain(mvm->hw->wiphy, mcc, src, NULL);
639*4882a593Smuzhiyun if (IS_ERR_OR_NULL(regd))
640*4882a593Smuzhiyun return;
641*4882a593Smuzhiyun
642*4882a593Smuzhiyun wgds_tbl_idx = iwl_mvm_get_sar_geo_profile(mvm);
643*4882a593Smuzhiyun if (wgds_tbl_idx < 0)
644*4882a593Smuzhiyun IWL_DEBUG_INFO(mvm, "SAR WGDS is disabled (%d)\n",
645*4882a593Smuzhiyun wgds_tbl_idx);
646*4882a593Smuzhiyun else
647*4882a593Smuzhiyun IWL_DEBUG_INFO(mvm, "SAR WGDS: geo profile %d is configured\n",
648*4882a593Smuzhiyun wgds_tbl_idx);
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun regulatory_set_wiphy_regd(mvm->hw->wiphy, regd);
651*4882a593Smuzhiyun kfree(regd);
652*4882a593Smuzhiyun }
653