xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/intel/iwlwifi/iwl-context-info.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /******************************************************************************
2*4882a593Smuzhiyun  *
3*4882a593Smuzhiyun  * This file is provided under a dual BSD/GPLv2 license.  When using or
4*4882a593Smuzhiyun  * redistributing this file, you may do so under either license.
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * GPL LICENSE SUMMARY
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * Copyright(c) 2017 Intel Deutschland GmbH
9*4882a593Smuzhiyun  * Copyright(c) 2018 - 2020 Intel Corporation
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or modify
12*4882a593Smuzhiyun  * it under the terms of version 2 of the GNU General Public License as
13*4882a593Smuzhiyun  * published by the Free Software Foundation.
14*4882a593Smuzhiyun  *
15*4882a593Smuzhiyun  * This program is distributed in the hope that it will be useful, but
16*4882a593Smuzhiyun  * WITHOUT ANY WARRANTY; without even the implied warranty of
17*4882a593Smuzhiyun  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18*4882a593Smuzhiyun  * General Public License for more details.
19*4882a593Smuzhiyun  *
20*4882a593Smuzhiyun  * BSD LICENSE
21*4882a593Smuzhiyun  *
22*4882a593Smuzhiyun  * Copyright(c) 2017 Intel Deutschland GmbH
23*4882a593Smuzhiyun  * Copyright(c) 2018 - 2020 Intel Corporation
24*4882a593Smuzhiyun  * All rights reserved.
25*4882a593Smuzhiyun  *
26*4882a593Smuzhiyun  * Redistribution and use in source and binary forms, with or without
27*4882a593Smuzhiyun  * modification, are permitted provided that the following conditions
28*4882a593Smuzhiyun  * are met:
29*4882a593Smuzhiyun  *
30*4882a593Smuzhiyun  *  * Redistributions of source code must retain the above copyright
31*4882a593Smuzhiyun  *    notice, this list of conditions and the following disclaimer.
32*4882a593Smuzhiyun  *  * Redistributions in binary form must reproduce the above copyright
33*4882a593Smuzhiyun  *    notice, this list of conditions and the following disclaimer in
34*4882a593Smuzhiyun  *    the documentation and/or other materials provided with the
35*4882a593Smuzhiyun  *    distribution.
36*4882a593Smuzhiyun  *  * Neither the name Intel Corporation nor the names of its
37*4882a593Smuzhiyun  *    contributors may be used to endorse or promote products derived
38*4882a593Smuzhiyun  *    from this software without specific prior written permission.
39*4882a593Smuzhiyun  *
40*4882a593Smuzhiyun  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
41*4882a593Smuzhiyun  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
42*4882a593Smuzhiyun  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
43*4882a593Smuzhiyun  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
44*4882a593Smuzhiyun  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
45*4882a593Smuzhiyun  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
46*4882a593Smuzhiyun  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
47*4882a593Smuzhiyun  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
48*4882a593Smuzhiyun  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
49*4882a593Smuzhiyun  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
50*4882a593Smuzhiyun  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51*4882a593Smuzhiyun  *
52*4882a593Smuzhiyun  *****************************************************************************/
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun #ifndef __iwl_context_info_file_h__
55*4882a593Smuzhiyun #define __iwl_context_info_file_h__
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun /* maximmum number of DRAM map entries supported by FW */
58*4882a593Smuzhiyun #define IWL_MAX_DRAM_ENTRY	64
59*4882a593Smuzhiyun #define CSR_CTXT_INFO_BA	0x40
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun /**
62*4882a593Smuzhiyun  * enum iwl_context_info_flags - Context information control flags
63*4882a593Smuzhiyun  * @IWL_CTXT_INFO_AUTO_FUNC_INIT: If set, FW will not wait before interrupting
64*4882a593Smuzhiyun  *	the init done for driver command that configures several system modes
65*4882a593Smuzhiyun  * @IWL_CTXT_INFO_EARLY_DEBUG: enable early debug
66*4882a593Smuzhiyun  * @IWL_CTXT_INFO_ENABLE_CDMP: enable core dump
67*4882a593Smuzhiyun  * @IWL_CTXT_INFO_RB_CB_SIZE: mask of the RBD Cyclic Buffer Size
68*4882a593Smuzhiyun  *	exponent, the actual size is 2**value, valid sizes are 8-2048.
69*4882a593Smuzhiyun  *	The value is four bits long. Maximum valid exponent is 12
70*4882a593Smuzhiyun  * @IWL_CTXT_INFO_TFD_FORMAT_LONG: use long TFD Format (the
71*4882a593Smuzhiyun  *	default is short format - not supported by the driver)
72*4882a593Smuzhiyun  * @IWL_CTXT_INFO_RB_SIZE: RB size mask
73*4882a593Smuzhiyun  *	(values are IWL_CTXT_INFO_RB_SIZE_*K)
74*4882a593Smuzhiyun  * @IWL_CTXT_INFO_RB_SIZE_1K: Value for 1K RB size
75*4882a593Smuzhiyun  * @IWL_CTXT_INFO_RB_SIZE_2K: Value for 2K RB size
76*4882a593Smuzhiyun  * @IWL_CTXT_INFO_RB_SIZE_4K: Value for 4K RB size
77*4882a593Smuzhiyun  * @IWL_CTXT_INFO_RB_SIZE_8K: Value for 8K RB size
78*4882a593Smuzhiyun  * @IWL_CTXT_INFO_RB_SIZE_12K: Value for 12K RB size
79*4882a593Smuzhiyun  * @IWL_CTXT_INFO_RB_SIZE_16K: Value for 16K RB size
80*4882a593Smuzhiyun  * @IWL_CTXT_INFO_RB_SIZE_20K: Value for 20K RB size
81*4882a593Smuzhiyun  * @IWL_CTXT_INFO_RB_SIZE_24K: Value for 24K RB size
82*4882a593Smuzhiyun  * @IWL_CTXT_INFO_RB_SIZE_28K: Value for 28K RB size
83*4882a593Smuzhiyun  * @IWL_CTXT_INFO_RB_SIZE_32K: Value for 32K RB size
84*4882a593Smuzhiyun  */
85*4882a593Smuzhiyun enum iwl_context_info_flags {
86*4882a593Smuzhiyun 	IWL_CTXT_INFO_AUTO_FUNC_INIT	= 0x0001,
87*4882a593Smuzhiyun 	IWL_CTXT_INFO_EARLY_DEBUG	= 0x0002,
88*4882a593Smuzhiyun 	IWL_CTXT_INFO_ENABLE_CDMP	= 0x0004,
89*4882a593Smuzhiyun 	IWL_CTXT_INFO_RB_CB_SIZE	= 0x00f0,
90*4882a593Smuzhiyun 	IWL_CTXT_INFO_TFD_FORMAT_LONG	= 0x0100,
91*4882a593Smuzhiyun 	IWL_CTXT_INFO_RB_SIZE		= 0x1e00,
92*4882a593Smuzhiyun 	IWL_CTXT_INFO_RB_SIZE_1K	= 0x1,
93*4882a593Smuzhiyun 	IWL_CTXT_INFO_RB_SIZE_2K	= 0x2,
94*4882a593Smuzhiyun 	IWL_CTXT_INFO_RB_SIZE_4K	= 0x4,
95*4882a593Smuzhiyun 	IWL_CTXT_INFO_RB_SIZE_8K	= 0x8,
96*4882a593Smuzhiyun 	IWL_CTXT_INFO_RB_SIZE_12K	= 0x9,
97*4882a593Smuzhiyun 	IWL_CTXT_INFO_RB_SIZE_16K	= 0xa,
98*4882a593Smuzhiyun 	IWL_CTXT_INFO_RB_SIZE_20K	= 0xb,
99*4882a593Smuzhiyun 	IWL_CTXT_INFO_RB_SIZE_24K	= 0xc,
100*4882a593Smuzhiyun 	IWL_CTXT_INFO_RB_SIZE_28K	= 0xd,
101*4882a593Smuzhiyun 	IWL_CTXT_INFO_RB_SIZE_32K	= 0xe,
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun /*
105*4882a593Smuzhiyun  * struct iwl_context_info_version - version structure
106*4882a593Smuzhiyun  * @mac_id: SKU and revision id
107*4882a593Smuzhiyun  * @version: context information version id
108*4882a593Smuzhiyun  * @size: the size of the context information in DWs
109*4882a593Smuzhiyun  */
110*4882a593Smuzhiyun struct iwl_context_info_version {
111*4882a593Smuzhiyun 	__le16 mac_id;
112*4882a593Smuzhiyun 	__le16 version;
113*4882a593Smuzhiyun 	__le16 size;
114*4882a593Smuzhiyun 	__le16 reserved;
115*4882a593Smuzhiyun } __packed;
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun /*
118*4882a593Smuzhiyun  * struct iwl_context_info_control - version structure
119*4882a593Smuzhiyun  * @control_flags: context information flags see &enum iwl_context_info_flags
120*4882a593Smuzhiyun  */
121*4882a593Smuzhiyun struct iwl_context_info_control {
122*4882a593Smuzhiyun 	__le32 control_flags;
123*4882a593Smuzhiyun 	__le32 reserved;
124*4882a593Smuzhiyun } __packed;
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun /*
127*4882a593Smuzhiyun  * struct iwl_context_info_dram - images DRAM map
128*4882a593Smuzhiyun  * each entry in the map represents a DRAM chunk of up to 32 KB
129*4882a593Smuzhiyun  * @umac_img: UMAC image DRAM map
130*4882a593Smuzhiyun  * @lmac_img: LMAC image DRAM map
131*4882a593Smuzhiyun  * @virtual_img: paged image DRAM map
132*4882a593Smuzhiyun  */
133*4882a593Smuzhiyun struct iwl_context_info_dram {
134*4882a593Smuzhiyun 	__le64 umac_img[IWL_MAX_DRAM_ENTRY];
135*4882a593Smuzhiyun 	__le64 lmac_img[IWL_MAX_DRAM_ENTRY];
136*4882a593Smuzhiyun 	__le64 virtual_img[IWL_MAX_DRAM_ENTRY];
137*4882a593Smuzhiyun } __packed;
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun /*
140*4882a593Smuzhiyun  * struct iwl_context_info_rbd_cfg - RBDs configuration
141*4882a593Smuzhiyun  * @free_rbd_addr: default queue free RB CB base address
142*4882a593Smuzhiyun  * @used_rbd_addr: default queue used RB CB base address
143*4882a593Smuzhiyun  * @status_wr_ptr: default queue used RB status write pointer
144*4882a593Smuzhiyun  */
145*4882a593Smuzhiyun struct iwl_context_info_rbd_cfg {
146*4882a593Smuzhiyun 	__le64 free_rbd_addr;
147*4882a593Smuzhiyun 	__le64 used_rbd_addr;
148*4882a593Smuzhiyun 	__le64 status_wr_ptr;
149*4882a593Smuzhiyun } __packed;
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun /*
152*4882a593Smuzhiyun  * struct iwl_context_info_hcmd_cfg  - command queue configuration
153*4882a593Smuzhiyun  * @cmd_queue_addr: address of command queue
154*4882a593Smuzhiyun  * @cmd_queue_size: number of entries
155*4882a593Smuzhiyun  */
156*4882a593Smuzhiyun struct iwl_context_info_hcmd_cfg {
157*4882a593Smuzhiyun 	__le64 cmd_queue_addr;
158*4882a593Smuzhiyun 	u8 cmd_queue_size;
159*4882a593Smuzhiyun 	u8 reserved[7];
160*4882a593Smuzhiyun } __packed;
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun /*
163*4882a593Smuzhiyun  * struct iwl_context_info_dump_cfg - Core Dump configuration
164*4882a593Smuzhiyun  * @core_dump_addr: core dump (debug DRAM address) start address
165*4882a593Smuzhiyun  * @core_dump_size: size, in DWs
166*4882a593Smuzhiyun  */
167*4882a593Smuzhiyun struct iwl_context_info_dump_cfg {
168*4882a593Smuzhiyun 	__le64 core_dump_addr;
169*4882a593Smuzhiyun 	__le32 core_dump_size;
170*4882a593Smuzhiyun 	__le32 reserved;
171*4882a593Smuzhiyun } __packed;
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun /*
174*4882a593Smuzhiyun  * struct iwl_context_info_pnvm_cfg - platform NVM data configuration
175*4882a593Smuzhiyun  * @platform_nvm_addr: Platform NVM data start address
176*4882a593Smuzhiyun  * @platform_nvm_size: size in DWs
177*4882a593Smuzhiyun  */
178*4882a593Smuzhiyun struct iwl_context_info_pnvm_cfg {
179*4882a593Smuzhiyun 	__le64 platform_nvm_addr;
180*4882a593Smuzhiyun 	__le32 platform_nvm_size;
181*4882a593Smuzhiyun 	__le32 reserved;
182*4882a593Smuzhiyun } __packed;
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun /*
185*4882a593Smuzhiyun  * struct iwl_context_info_early_dbg_cfg - early debug configuration for
186*4882a593Smuzhiyun  *	dumping DRAM addresses
187*4882a593Smuzhiyun  * @early_debug_addr: early debug start address
188*4882a593Smuzhiyun  * @early_debug_size: size in DWs
189*4882a593Smuzhiyun  */
190*4882a593Smuzhiyun struct iwl_context_info_early_dbg_cfg {
191*4882a593Smuzhiyun 	__le64 early_debug_addr;
192*4882a593Smuzhiyun 	__le32 early_debug_size;
193*4882a593Smuzhiyun 	__le32 reserved;
194*4882a593Smuzhiyun } __packed;
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun /*
197*4882a593Smuzhiyun  * struct iwl_context_info - device INIT configuration
198*4882a593Smuzhiyun  * @version: version information of context info and HW
199*4882a593Smuzhiyun  * @control: control flags of FH configurations
200*4882a593Smuzhiyun  * @rbd_cfg: default RX queue configuration
201*4882a593Smuzhiyun  * @hcmd_cfg: command queue configuration
202*4882a593Smuzhiyun  * @dump_cfg: core dump data
203*4882a593Smuzhiyun  * @edbg_cfg: early debug configuration
204*4882a593Smuzhiyun  * @pnvm_cfg: platform nvm configuration
205*4882a593Smuzhiyun  * @dram: firmware image addresses in DRAM
206*4882a593Smuzhiyun  */
207*4882a593Smuzhiyun struct iwl_context_info {
208*4882a593Smuzhiyun 	struct iwl_context_info_version version;
209*4882a593Smuzhiyun 	struct iwl_context_info_control control;
210*4882a593Smuzhiyun 	__le64 reserved0;
211*4882a593Smuzhiyun 	struct iwl_context_info_rbd_cfg rbd_cfg;
212*4882a593Smuzhiyun 	struct iwl_context_info_hcmd_cfg hcmd_cfg;
213*4882a593Smuzhiyun 	__le32 reserved1[4];
214*4882a593Smuzhiyun 	struct iwl_context_info_dump_cfg dump_cfg;
215*4882a593Smuzhiyun 	struct iwl_context_info_early_dbg_cfg edbg_cfg;
216*4882a593Smuzhiyun 	struct iwl_context_info_pnvm_cfg pnvm_cfg;
217*4882a593Smuzhiyun 	__le32 reserved2[16];
218*4882a593Smuzhiyun 	struct iwl_context_info_dram dram;
219*4882a593Smuzhiyun 	__le32 reserved3[16];
220*4882a593Smuzhiyun } __packed;
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun int iwl_pcie_ctxt_info_init(struct iwl_trans *trans, const struct fw_img *fw);
223*4882a593Smuzhiyun void iwl_pcie_ctxt_info_free(struct iwl_trans *trans);
224*4882a593Smuzhiyun void iwl_pcie_ctxt_info_free_paging(struct iwl_trans *trans);
225*4882a593Smuzhiyun int iwl_pcie_init_fw_sec(struct iwl_trans *trans,
226*4882a593Smuzhiyun 			 const struct fw_img *fw,
227*4882a593Smuzhiyun 			 struct iwl_context_info_dram *ctxt_dram);
228*4882a593Smuzhiyun int iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans *trans,
229*4882a593Smuzhiyun 				 const void *data, u32 len,
230*4882a593Smuzhiyun 				 struct iwl_dram_data *dram);
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun #endif /* __iwl_context_info_file_h__ */
233