xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/intel/iwlwifi/iwl-config.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /******************************************************************************
2*4882a593Smuzhiyun  *
3*4882a593Smuzhiyun  * This file is provided under a dual BSD/GPLv2 license.  When using or
4*4882a593Smuzhiyun  * redistributing this file, you may do so under either license.
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * GPL LICENSE SUMMARY
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * Copyright (C) 2016 - 2017 Intel Deutschland GmbH
9*4882a593Smuzhiyun  * Copyright(c) 2007 - 2014, 2018 - 2020 Intel Corporation
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or modify
12*4882a593Smuzhiyun  * it under the terms of version 2 of the GNU General Public License as
13*4882a593Smuzhiyun  * published by the Free Software Foundation.
14*4882a593Smuzhiyun  *
15*4882a593Smuzhiyun  * This program is distributed in the hope that it will be useful, but
16*4882a593Smuzhiyun  * WITHOUT ANY WARRANTY; without even the implied warranty of
17*4882a593Smuzhiyun  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18*4882a593Smuzhiyun  * General Public License for more details.
19*4882a593Smuzhiyun  *
20*4882a593Smuzhiyun  * The full GNU General Public License is included in this distribution
21*4882a593Smuzhiyun  * in the file called COPYING.
22*4882a593Smuzhiyun  *
23*4882a593Smuzhiyun  * Contact Information:
24*4882a593Smuzhiyun  *  Intel Linux Wireless <linuxwifi@intel.com>
25*4882a593Smuzhiyun  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26*4882a593Smuzhiyun  *
27*4882a593Smuzhiyun  * BSD LICENSE
28*4882a593Smuzhiyun  *
29*4882a593Smuzhiyun  * Copyright (C) 2016 - 2017 Intel Deutschland GmbH
30*4882a593Smuzhiyun  * Copyright(c) 2005 - 2014, 2018 - 2020 Intel Corporation
31*4882a593Smuzhiyun  * All rights reserved.
32*4882a593Smuzhiyun  *
33*4882a593Smuzhiyun  * Redistribution and use in source and binary forms, with or without
34*4882a593Smuzhiyun  * modification, are permitted provided that the following conditions
35*4882a593Smuzhiyun  * are met:
36*4882a593Smuzhiyun  *
37*4882a593Smuzhiyun  *  * Redistributions of source code must retain the above copyright
38*4882a593Smuzhiyun  *    notice, this list of conditions and the following disclaimer.
39*4882a593Smuzhiyun  *  * Redistributions in binary form must reproduce the above copyright
40*4882a593Smuzhiyun  *    notice, this list of conditions and the following disclaimer in
41*4882a593Smuzhiyun  *    the documentation and/or other materials provided with the
42*4882a593Smuzhiyun  *    distribution.
43*4882a593Smuzhiyun  *  * Neither the name Intel Corporation nor the names of its
44*4882a593Smuzhiyun  *    contributors may be used to endorse or promote products derived
45*4882a593Smuzhiyun  *    from this software without specific prior written permission.
46*4882a593Smuzhiyun  *
47*4882a593Smuzhiyun  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
48*4882a593Smuzhiyun  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
49*4882a593Smuzhiyun  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
50*4882a593Smuzhiyun  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
51*4882a593Smuzhiyun  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
52*4882a593Smuzhiyun  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
53*4882a593Smuzhiyun  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
54*4882a593Smuzhiyun  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
55*4882a593Smuzhiyun  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
56*4882a593Smuzhiyun  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
57*4882a593Smuzhiyun  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
58*4882a593Smuzhiyun  *
59*4882a593Smuzhiyun  *****************************************************************************/
60*4882a593Smuzhiyun #ifndef __IWL_CONFIG_H__
61*4882a593Smuzhiyun #define __IWL_CONFIG_H__
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun #include <linux/types.h>
64*4882a593Smuzhiyun #include <linux/netdevice.h>
65*4882a593Smuzhiyun #include <linux/ieee80211.h>
66*4882a593Smuzhiyun #include <linux/nl80211.h>
67*4882a593Smuzhiyun #include "iwl-csr.h"
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun enum iwl_device_family {
70*4882a593Smuzhiyun 	IWL_DEVICE_FAMILY_UNDEFINED,
71*4882a593Smuzhiyun 	IWL_DEVICE_FAMILY_1000,
72*4882a593Smuzhiyun 	IWL_DEVICE_FAMILY_100,
73*4882a593Smuzhiyun 	IWL_DEVICE_FAMILY_2000,
74*4882a593Smuzhiyun 	IWL_DEVICE_FAMILY_2030,
75*4882a593Smuzhiyun 	IWL_DEVICE_FAMILY_105,
76*4882a593Smuzhiyun 	IWL_DEVICE_FAMILY_135,
77*4882a593Smuzhiyun 	IWL_DEVICE_FAMILY_5000,
78*4882a593Smuzhiyun 	IWL_DEVICE_FAMILY_5150,
79*4882a593Smuzhiyun 	IWL_DEVICE_FAMILY_6000,
80*4882a593Smuzhiyun 	IWL_DEVICE_FAMILY_6000i,
81*4882a593Smuzhiyun 	IWL_DEVICE_FAMILY_6005,
82*4882a593Smuzhiyun 	IWL_DEVICE_FAMILY_6030,
83*4882a593Smuzhiyun 	IWL_DEVICE_FAMILY_6050,
84*4882a593Smuzhiyun 	IWL_DEVICE_FAMILY_6150,
85*4882a593Smuzhiyun 	IWL_DEVICE_FAMILY_7000,
86*4882a593Smuzhiyun 	IWL_DEVICE_FAMILY_8000,
87*4882a593Smuzhiyun 	IWL_DEVICE_FAMILY_9000,
88*4882a593Smuzhiyun 	IWL_DEVICE_FAMILY_22000,
89*4882a593Smuzhiyun 	IWL_DEVICE_FAMILY_AX210,
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun /*
93*4882a593Smuzhiyun  * LED mode
94*4882a593Smuzhiyun  *    IWL_LED_DEFAULT:  use device default
95*4882a593Smuzhiyun  *    IWL_LED_RF_STATE: turn LED on/off based on RF state
96*4882a593Smuzhiyun  *			LED ON  = RF ON
97*4882a593Smuzhiyun  *			LED OFF = RF OFF
98*4882a593Smuzhiyun  *    IWL_LED_BLINK:    adjust led blink rate based on blink table
99*4882a593Smuzhiyun  *    IWL_LED_DISABLE:	led disabled
100*4882a593Smuzhiyun  */
101*4882a593Smuzhiyun enum iwl_led_mode {
102*4882a593Smuzhiyun 	IWL_LED_DEFAULT,
103*4882a593Smuzhiyun 	IWL_LED_RF_STATE,
104*4882a593Smuzhiyun 	IWL_LED_BLINK,
105*4882a593Smuzhiyun 	IWL_LED_DISABLE,
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun /**
109*4882a593Smuzhiyun  * enum iwl_nvm_type - nvm formats
110*4882a593Smuzhiyun  * @IWL_NVM: the regular format
111*4882a593Smuzhiyun  * @IWL_NVM_EXT: extended NVM format
112*4882a593Smuzhiyun  * @IWL_NVM_SDP: NVM format used by 3168 series
113*4882a593Smuzhiyun  */
114*4882a593Smuzhiyun enum iwl_nvm_type {
115*4882a593Smuzhiyun 	IWL_NVM,
116*4882a593Smuzhiyun 	IWL_NVM_EXT,
117*4882a593Smuzhiyun 	IWL_NVM_SDP,
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun /*
121*4882a593Smuzhiyun  * This is the threshold value of plcp error rate per 100mSecs.  It is
122*4882a593Smuzhiyun  * used to set and check for the validity of plcp_delta.
123*4882a593Smuzhiyun  */
124*4882a593Smuzhiyun #define IWL_MAX_PLCP_ERR_THRESHOLD_MIN		1
125*4882a593Smuzhiyun #define IWL_MAX_PLCP_ERR_THRESHOLD_DEF		50
126*4882a593Smuzhiyun #define IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF	100
127*4882a593Smuzhiyun #define IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF	200
128*4882a593Smuzhiyun #define IWL_MAX_PLCP_ERR_THRESHOLD_MAX		255
129*4882a593Smuzhiyun #define IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE	0
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun /* TX queue watchdog timeouts in mSecs */
132*4882a593Smuzhiyun #define IWL_WATCHDOG_DISABLED	0
133*4882a593Smuzhiyun #define IWL_DEF_WD_TIMEOUT	2500
134*4882a593Smuzhiyun #define IWL_LONG_WD_TIMEOUT	10000
135*4882a593Smuzhiyun #define IWL_MAX_WD_TIMEOUT	120000
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun #define IWL_DEFAULT_MAX_TX_POWER 22
138*4882a593Smuzhiyun #define IWL_TX_CSUM_NETIF_FLAGS (NETIF_F_IPV6_CSUM | NETIF_F_IP_CSUM |\
139*4882a593Smuzhiyun 				 NETIF_F_TSO | NETIF_F_TSO6)
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun /* Antenna presence definitions */
142*4882a593Smuzhiyun #define	ANT_NONE	0x0
143*4882a593Smuzhiyun #define	ANT_INVALID	0xff
144*4882a593Smuzhiyun #define	ANT_A		BIT(0)
145*4882a593Smuzhiyun #define	ANT_B		BIT(1)
146*4882a593Smuzhiyun #define ANT_C		BIT(2)
147*4882a593Smuzhiyun #define	ANT_AB		(ANT_A | ANT_B)
148*4882a593Smuzhiyun #define	ANT_AC		(ANT_A | ANT_C)
149*4882a593Smuzhiyun #define ANT_BC		(ANT_B | ANT_C)
150*4882a593Smuzhiyun #define ANT_ABC		(ANT_A | ANT_B | ANT_C)
151*4882a593Smuzhiyun #define MAX_ANT_NUM 3
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun 
num_of_ant(u8 mask)154*4882a593Smuzhiyun static inline u8 num_of_ant(u8 mask)
155*4882a593Smuzhiyun {
156*4882a593Smuzhiyun 	return  !!((mask) & ANT_A) +
157*4882a593Smuzhiyun 		!!((mask) & ANT_B) +
158*4882a593Smuzhiyun 		!!((mask) & ANT_C);
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun /**
162*4882a593Smuzhiyun  * struct iwl_base_params - params not likely to change within a device family
163*4882a593Smuzhiyun  * @max_ll_items: max number of OTP blocks
164*4882a593Smuzhiyun  * @shadow_ram_support: shadow support for OTP memory
165*4882a593Smuzhiyun  * @led_compensation: compensate on the led on/off time per HW according
166*4882a593Smuzhiyun  *	to the deviation to achieve the desired led frequency.
167*4882a593Smuzhiyun  *	The detail algorithm is described in iwl-led.c
168*4882a593Smuzhiyun  * @wd_timeout: TX queues watchdog timeout
169*4882a593Smuzhiyun  * @max_event_log_size: size of event log buffer size for ucode event logging
170*4882a593Smuzhiyun  * @shadow_reg_enable: HW shadow register support
171*4882a593Smuzhiyun  * @apmg_wake_up_wa: should the MAC access REQ be asserted when a command
172*4882a593Smuzhiyun  *	is in flight. This is due to a HW bug in 7260, 3160 and 7265.
173*4882a593Smuzhiyun  * @scd_chain_ext_wa: should the chain extension feature in SCD be disabled.
174*4882a593Smuzhiyun  * @max_tfd_queue_size: max number of entries in tfd queue.
175*4882a593Smuzhiyun  */
176*4882a593Smuzhiyun struct iwl_base_params {
177*4882a593Smuzhiyun 	unsigned int wd_timeout;
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 	u16 eeprom_size;
180*4882a593Smuzhiyun 	u16 max_event_log_size;
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	u8 pll_cfg:1, /* for iwl_pcie_apm_init() */
183*4882a593Smuzhiyun 	   shadow_ram_support:1,
184*4882a593Smuzhiyun 	   shadow_reg_enable:1,
185*4882a593Smuzhiyun 	   pcie_l1_allowed:1,
186*4882a593Smuzhiyun 	   apmg_wake_up_wa:1,
187*4882a593Smuzhiyun 	   scd_chain_ext_wa:1;
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 	u16 num_of_queues;	/* def: HW dependent */
190*4882a593Smuzhiyun 	u32 max_tfd_queue_size;	/* def: HW dependent */
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun 	u8 max_ll_items;
193*4882a593Smuzhiyun 	u8 led_compensation;
194*4882a593Smuzhiyun };
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun /*
197*4882a593Smuzhiyun  * @stbc: support Tx STBC and 1*SS Rx STBC
198*4882a593Smuzhiyun  * @ldpc: support Tx/Rx with LDPC
199*4882a593Smuzhiyun  * @use_rts_for_aggregation: use rts/cts protection for HT traffic
200*4882a593Smuzhiyun  * @ht40_bands: bitmap of bands (using %NL80211_BAND_*) that support HT40
201*4882a593Smuzhiyun  */
202*4882a593Smuzhiyun struct iwl_ht_params {
203*4882a593Smuzhiyun 	u8 ht_greenfield_support:1,
204*4882a593Smuzhiyun 	   stbc:1,
205*4882a593Smuzhiyun 	   ldpc:1,
206*4882a593Smuzhiyun 	   use_rts_for_aggregation:1;
207*4882a593Smuzhiyun 	u8 ht40_bands;
208*4882a593Smuzhiyun };
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun /*
211*4882a593Smuzhiyun  * Tx-backoff threshold
212*4882a593Smuzhiyun  * @temperature: The threshold in Celsius
213*4882a593Smuzhiyun  * @backoff: The tx-backoff in uSec
214*4882a593Smuzhiyun  */
215*4882a593Smuzhiyun struct iwl_tt_tx_backoff {
216*4882a593Smuzhiyun 	s32 temperature;
217*4882a593Smuzhiyun 	u32 backoff;
218*4882a593Smuzhiyun };
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun #define TT_TX_BACKOFF_SIZE 6
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun /**
223*4882a593Smuzhiyun  * struct iwl_tt_params - thermal throttling parameters
224*4882a593Smuzhiyun  * @ct_kill_entry: CT Kill entry threshold
225*4882a593Smuzhiyun  * @ct_kill_exit: CT Kill exit threshold
226*4882a593Smuzhiyun  * @ct_kill_duration: The time  intervals (in uSec) in which the driver needs
227*4882a593Smuzhiyun  *	to checks whether to exit CT Kill.
228*4882a593Smuzhiyun  * @dynamic_smps_entry: Dynamic SMPS entry threshold
229*4882a593Smuzhiyun  * @dynamic_smps_exit: Dynamic SMPS exit threshold
230*4882a593Smuzhiyun  * @tx_protection_entry: TX protection entry threshold
231*4882a593Smuzhiyun  * @tx_protection_exit: TX protection exit threshold
232*4882a593Smuzhiyun  * @tx_backoff: Array of thresholds for tx-backoff , in ascending order.
233*4882a593Smuzhiyun  * @support_ct_kill: Support CT Kill?
234*4882a593Smuzhiyun  * @support_dynamic_smps: Support dynamic SMPS?
235*4882a593Smuzhiyun  * @support_tx_protection: Support tx protection?
236*4882a593Smuzhiyun  * @support_tx_backoff: Support tx-backoff?
237*4882a593Smuzhiyun  */
238*4882a593Smuzhiyun struct iwl_tt_params {
239*4882a593Smuzhiyun 	u32 ct_kill_entry;
240*4882a593Smuzhiyun 	u32 ct_kill_exit;
241*4882a593Smuzhiyun 	u32 ct_kill_duration;
242*4882a593Smuzhiyun 	u32 dynamic_smps_entry;
243*4882a593Smuzhiyun 	u32 dynamic_smps_exit;
244*4882a593Smuzhiyun 	u32 tx_protection_entry;
245*4882a593Smuzhiyun 	u32 tx_protection_exit;
246*4882a593Smuzhiyun 	struct iwl_tt_tx_backoff tx_backoff[TT_TX_BACKOFF_SIZE];
247*4882a593Smuzhiyun 	u8 support_ct_kill:1,
248*4882a593Smuzhiyun 	   support_dynamic_smps:1,
249*4882a593Smuzhiyun 	   support_tx_protection:1,
250*4882a593Smuzhiyun 	   support_tx_backoff:1;
251*4882a593Smuzhiyun };
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun /*
254*4882a593Smuzhiyun  * information on how to parse the EEPROM
255*4882a593Smuzhiyun  */
256*4882a593Smuzhiyun #define EEPROM_REG_BAND_1_CHANNELS		0x08
257*4882a593Smuzhiyun #define EEPROM_REG_BAND_2_CHANNELS		0x26
258*4882a593Smuzhiyun #define EEPROM_REG_BAND_3_CHANNELS		0x42
259*4882a593Smuzhiyun #define EEPROM_REG_BAND_4_CHANNELS		0x5C
260*4882a593Smuzhiyun #define EEPROM_REG_BAND_5_CHANNELS		0x74
261*4882a593Smuzhiyun #define EEPROM_REG_BAND_24_HT40_CHANNELS	0x82
262*4882a593Smuzhiyun #define EEPROM_REG_BAND_52_HT40_CHANNELS	0x92
263*4882a593Smuzhiyun #define EEPROM_6000_REG_BAND_24_HT40_CHANNELS	0x80
264*4882a593Smuzhiyun #define EEPROM_REGULATORY_BAND_NO_HT40		0
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun /* lower blocks contain EEPROM image and calibration data */
267*4882a593Smuzhiyun #define OTP_LOW_IMAGE_SIZE_2K		(2 * 512 * sizeof(u16))  /*  2 KB */
268*4882a593Smuzhiyun #define OTP_LOW_IMAGE_SIZE_16K		(16 * 512 * sizeof(u16)) /* 16 KB */
269*4882a593Smuzhiyun #define OTP_LOW_IMAGE_SIZE_32K		(32 * 512 * sizeof(u16)) /* 32 KB */
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun struct iwl_eeprom_params {
272*4882a593Smuzhiyun 	const u8 regulatory_bands[7];
273*4882a593Smuzhiyun 	bool enhanced_txpower;
274*4882a593Smuzhiyun };
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun /* Tx-backoff power threshold
277*4882a593Smuzhiyun  * @pwr: The power limit in mw
278*4882a593Smuzhiyun  * @backoff: The tx-backoff in uSec
279*4882a593Smuzhiyun  */
280*4882a593Smuzhiyun struct iwl_pwr_tx_backoff {
281*4882a593Smuzhiyun 	u32 pwr;
282*4882a593Smuzhiyun 	u32 backoff;
283*4882a593Smuzhiyun };
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun enum iwl_cfg_trans_ltr_delay {
286*4882a593Smuzhiyun 	IWL_CFG_TRANS_LTR_DELAY_NONE	= 0,
287*4882a593Smuzhiyun 	IWL_CFG_TRANS_LTR_DELAY_200US	= 1,
288*4882a593Smuzhiyun 	IWL_CFG_TRANS_LTR_DELAY_2500US	= 2,
289*4882a593Smuzhiyun 	IWL_CFG_TRANS_LTR_DELAY_1820US	= 3,
290*4882a593Smuzhiyun };
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun /**
293*4882a593Smuzhiyun  * struct iwl_cfg_trans - information needed to start the trans
294*4882a593Smuzhiyun  *
295*4882a593Smuzhiyun  * These values are specific to the device ID and do not change when
296*4882a593Smuzhiyun  * multiple configs are used for a single device ID.  They values are
297*4882a593Smuzhiyun  * used, among other things, to boot the NIC so that the HW REV or
298*4882a593Smuzhiyun  * RFID can be read before deciding the remaining parameters to use.
299*4882a593Smuzhiyun  *
300*4882a593Smuzhiyun  * @base_params: pointer to basic parameters
301*4882a593Smuzhiyun  * @csr: csr flags and addresses that are different across devices
302*4882a593Smuzhiyun  * @device_family: the device family
303*4882a593Smuzhiyun  * @umac_prph_offset: offset to add to UMAC periphery address
304*4882a593Smuzhiyun  * @xtal_latency: power up latency to get the xtal stabilized
305*4882a593Smuzhiyun  * @extra_phy_cfg_flags: extra configuration flags to pass to the PHY
306*4882a593Smuzhiyun  * @rf_id: need to read rf_id to determine the firmware image
307*4882a593Smuzhiyun  * @use_tfh: use TFH
308*4882a593Smuzhiyun  * @gen2: 22000 and on transport operation
309*4882a593Smuzhiyun  * @mq_rx_supported: multi-queue rx support
310*4882a593Smuzhiyun  * @integrated: discrete or integrated
311*4882a593Smuzhiyun  * @low_latency_xtal: use the low latency xtal if supported
312*4882a593Smuzhiyun  * @ltr_delay: LTR delay parameter, &enum iwl_cfg_trans_ltr_delay.
313*4882a593Smuzhiyun  */
314*4882a593Smuzhiyun struct iwl_cfg_trans_params {
315*4882a593Smuzhiyun 	const struct iwl_base_params *base_params;
316*4882a593Smuzhiyun 	enum iwl_device_family device_family;
317*4882a593Smuzhiyun 	u32 umac_prph_offset;
318*4882a593Smuzhiyun 	u32 xtal_latency;
319*4882a593Smuzhiyun 	u32 extra_phy_cfg_flags;
320*4882a593Smuzhiyun 	u32 rf_id:1,
321*4882a593Smuzhiyun 	    use_tfh:1,
322*4882a593Smuzhiyun 	    gen2:1,
323*4882a593Smuzhiyun 	    mq_rx_supported:1,
324*4882a593Smuzhiyun 	    integrated:1,
325*4882a593Smuzhiyun 	    low_latency_xtal:1,
326*4882a593Smuzhiyun 	    bisr_workaround:1,
327*4882a593Smuzhiyun 	    ltr_delay:2;
328*4882a593Smuzhiyun };
329*4882a593Smuzhiyun 
330*4882a593Smuzhiyun /**
331*4882a593Smuzhiyun  * struct iwl_fw_mon_reg - FW monitor register info
332*4882a593Smuzhiyun  * @addr: register address
333*4882a593Smuzhiyun  * @mask: register mask
334*4882a593Smuzhiyun  */
335*4882a593Smuzhiyun struct iwl_fw_mon_reg {
336*4882a593Smuzhiyun 	u32 addr;
337*4882a593Smuzhiyun 	u32 mask;
338*4882a593Smuzhiyun };
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun /**
341*4882a593Smuzhiyun  * struct iwl_fw_mon_regs - FW monitor registers
342*4882a593Smuzhiyun  * @write_ptr: write pointer register
343*4882a593Smuzhiyun  * @cycle_cnt: cycle count register
344*4882a593Smuzhiyun  * @cur_frag: current fragment in use
345*4882a593Smuzhiyun  */
346*4882a593Smuzhiyun struct iwl_fw_mon_regs {
347*4882a593Smuzhiyun 	struct iwl_fw_mon_reg write_ptr;
348*4882a593Smuzhiyun 	struct iwl_fw_mon_reg cycle_cnt;
349*4882a593Smuzhiyun 	struct iwl_fw_mon_reg cur_frag;
350*4882a593Smuzhiyun };
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun /**
353*4882a593Smuzhiyun  * struct iwl_cfg
354*4882a593Smuzhiyun  * @trans: the trans-specific configuration part
355*4882a593Smuzhiyun  * @name: Official name of the device
356*4882a593Smuzhiyun  * @fw_name_pre: Firmware filename prefix. The api version and extension
357*4882a593Smuzhiyun  *	(.ucode) will be added to filename before loading from disk. The
358*4882a593Smuzhiyun  *	filename is constructed as fw_name_pre<api>.ucode.
359*4882a593Smuzhiyun  * @ucode_api_max: Highest version of uCode API supported by driver.
360*4882a593Smuzhiyun  * @ucode_api_min: Lowest version of uCode API supported by driver.
361*4882a593Smuzhiyun  * @max_inst_size: The maximal length of the fw inst section (only DVM)
362*4882a593Smuzhiyun  * @max_data_size: The maximal length of the fw data section (only DVM)
363*4882a593Smuzhiyun  * @valid_tx_ant: valid transmit antenna
364*4882a593Smuzhiyun  * @valid_rx_ant: valid receive antenna
365*4882a593Smuzhiyun  * @non_shared_ant: the antenna that is for WiFi only
366*4882a593Smuzhiyun  * @nvm_ver: NVM version
367*4882a593Smuzhiyun  * @nvm_calib_ver: NVM calibration version
368*4882a593Smuzhiyun  * @lib: pointer to the lib ops
369*4882a593Smuzhiyun  * @ht_params: point to ht parameters
370*4882a593Smuzhiyun  * @led_mode: 0=blinking, 1=On(RF On)/Off(RF Off)
371*4882a593Smuzhiyun  * @rx_with_siso_diversity: 1x1 device with rx antenna diversity
372*4882a593Smuzhiyun  * @tx_with_siso_diversity: 1x1 device with tx antenna diversity
373*4882a593Smuzhiyun  * @internal_wimax_coex: internal wifi/wimax combo device
374*4882a593Smuzhiyun  * @high_temp: Is this NIC is designated to be in high temperature.
375*4882a593Smuzhiyun  * @host_interrupt_operation_mode: device needs host interrupt operation
376*4882a593Smuzhiyun  *	mode set
377*4882a593Smuzhiyun  * @nvm_hw_section_num: the ID of the HW NVM section
378*4882a593Smuzhiyun  * @mac_addr_from_csr: read HW address from CSR registers
379*4882a593Smuzhiyun  * @features: hw features, any combination of feature_passlist
380*4882a593Smuzhiyun  * @pwr_tx_backoffs: translation table between power limits and backoffs
381*4882a593Smuzhiyun  * @max_tx_agg_size: max TX aggregation size of the ADDBA request/response
382*4882a593Smuzhiyun  * @max_ht_ampdu_factor: the exponent of the max length of A-MPDU that the
383*4882a593Smuzhiyun  *	station can receive in HT
384*4882a593Smuzhiyun  * @max_vht_ampdu_exponent: the exponent of the max length of A-MPDU that the
385*4882a593Smuzhiyun  *	station can receive in VHT
386*4882a593Smuzhiyun  * @dccm_offset: offset from which DCCM begins
387*4882a593Smuzhiyun  * @dccm_len: length of DCCM (including runtime stack CCM)
388*4882a593Smuzhiyun  * @dccm2_offset: offset from which the second DCCM begins
389*4882a593Smuzhiyun  * @dccm2_len: length of the second DCCM
390*4882a593Smuzhiyun  * @smem_offset: offset from which the SMEM begins
391*4882a593Smuzhiyun  * @smem_len: the length of SMEM
392*4882a593Smuzhiyun  * @vht_mu_mimo_supported: VHT MU-MIMO support
393*4882a593Smuzhiyun  * @cdb: CDB support
394*4882a593Smuzhiyun  * @nvm_type: see &enum iwl_nvm_type
395*4882a593Smuzhiyun  * @d3_debug_data_base_addr: base address where D3 debug data is stored
396*4882a593Smuzhiyun  * @d3_debug_data_length: length of the D3 debug data
397*4882a593Smuzhiyun  * @bisr_workaround: BISR hardware workaround (for 22260 series devices)
398*4882a593Smuzhiyun  * @min_txq_size: minimum number of slots required in a TX queue
399*4882a593Smuzhiyun  * @uhb_supported: ultra high band channels supported
400*4882a593Smuzhiyun  * @min_256_ba_txq_size: minimum number of slots required in a TX queue which
401*4882a593Smuzhiyun  *	supports 256 BA aggregation
402*4882a593Smuzhiyun  * @num_rbds: number of receive buffer descriptors to use
403*4882a593Smuzhiyun  *	(only used for multi-queue capable devices)
404*4882a593Smuzhiyun  *
405*4882a593Smuzhiyun  * We enable the driver to be backward compatible wrt. hardware features.
406*4882a593Smuzhiyun  * API differences in uCode shouldn't be handled here but through TLVs
407*4882a593Smuzhiyun  * and/or the uCode API version instead.
408*4882a593Smuzhiyun  */
409*4882a593Smuzhiyun struct iwl_cfg {
410*4882a593Smuzhiyun 	struct iwl_cfg_trans_params trans;
411*4882a593Smuzhiyun 	/* params specific to an individual device within a device family */
412*4882a593Smuzhiyun 	const char *name;
413*4882a593Smuzhiyun 	const char *fw_name_pre;
414*4882a593Smuzhiyun 	/* params likely to change within a device family */
415*4882a593Smuzhiyun 	const struct iwl_ht_params *ht_params;
416*4882a593Smuzhiyun 	const struct iwl_eeprom_params *eeprom_params;
417*4882a593Smuzhiyun 	const struct iwl_pwr_tx_backoff *pwr_tx_backoffs;
418*4882a593Smuzhiyun 	const char *default_nvm_file_C_step;
419*4882a593Smuzhiyun 	const struct iwl_tt_params *thermal_params;
420*4882a593Smuzhiyun 	enum iwl_led_mode led_mode;
421*4882a593Smuzhiyun 	enum iwl_nvm_type nvm_type;
422*4882a593Smuzhiyun 	u32 max_data_size;
423*4882a593Smuzhiyun 	u32 max_inst_size;
424*4882a593Smuzhiyun 	netdev_features_t features;
425*4882a593Smuzhiyun 	u32 dccm_offset;
426*4882a593Smuzhiyun 	u32 dccm_len;
427*4882a593Smuzhiyun 	u32 dccm2_offset;
428*4882a593Smuzhiyun 	u32 dccm2_len;
429*4882a593Smuzhiyun 	u32 smem_offset;
430*4882a593Smuzhiyun 	u32 smem_len;
431*4882a593Smuzhiyun 	u16 nvm_ver;
432*4882a593Smuzhiyun 	u16 nvm_calib_ver;
433*4882a593Smuzhiyun 	u32 rx_with_siso_diversity:1,
434*4882a593Smuzhiyun 	    tx_with_siso_diversity:1,
435*4882a593Smuzhiyun 	    bt_shared_single_ant:1,
436*4882a593Smuzhiyun 	    internal_wimax_coex:1,
437*4882a593Smuzhiyun 	    host_interrupt_operation_mode:1,
438*4882a593Smuzhiyun 	    high_temp:1,
439*4882a593Smuzhiyun 	    mac_addr_from_csr:1,
440*4882a593Smuzhiyun 	    lp_xtal_workaround:1,
441*4882a593Smuzhiyun 	    disable_dummy_notification:1,
442*4882a593Smuzhiyun 	    apmg_not_supported:1,
443*4882a593Smuzhiyun 	    vht_mu_mimo_supported:1,
444*4882a593Smuzhiyun 	    cdb:1,
445*4882a593Smuzhiyun 	    dbgc_supported:1,
446*4882a593Smuzhiyun 	    uhb_supported:1;
447*4882a593Smuzhiyun 	u8 valid_tx_ant;
448*4882a593Smuzhiyun 	u8 valid_rx_ant;
449*4882a593Smuzhiyun 	u8 non_shared_ant;
450*4882a593Smuzhiyun 	u8 nvm_hw_section_num;
451*4882a593Smuzhiyun 	u8 max_tx_agg_size;
452*4882a593Smuzhiyun 	u8 max_ht_ampdu_exponent;
453*4882a593Smuzhiyun 	u8 max_vht_ampdu_exponent;
454*4882a593Smuzhiyun 	u8 ucode_api_max;
455*4882a593Smuzhiyun 	u8 ucode_api_min;
456*4882a593Smuzhiyun 	u16 num_rbds;
457*4882a593Smuzhiyun 	u32 min_umac_error_event_table;
458*4882a593Smuzhiyun 	u32 d3_debug_data_base_addr;
459*4882a593Smuzhiyun 	u32 d3_debug_data_length;
460*4882a593Smuzhiyun 	u32 min_txq_size;
461*4882a593Smuzhiyun 	u32 gp2_reg_addr;
462*4882a593Smuzhiyun 	u32 min_256_ba_txq_size;
463*4882a593Smuzhiyun 	const struct iwl_fw_mon_regs mon_dram_regs;
464*4882a593Smuzhiyun 	const struct iwl_fw_mon_regs mon_smem_regs;
465*4882a593Smuzhiyun };
466*4882a593Smuzhiyun 
467*4882a593Smuzhiyun #define IWL_CFG_ANY (~0)
468*4882a593Smuzhiyun 
469*4882a593Smuzhiyun #define IWL_CFG_MAC_TYPE_PU		0x31
470*4882a593Smuzhiyun #define IWL_CFG_MAC_TYPE_PNJ		0x32
471*4882a593Smuzhiyun #define IWL_CFG_MAC_TYPE_TH		0x32
472*4882a593Smuzhiyun #define IWL_CFG_MAC_TYPE_QU		0x33
473*4882a593Smuzhiyun #define IWL_CFG_MAC_TYPE_QUZ		0x35
474*4882a593Smuzhiyun #define IWL_CFG_MAC_TYPE_QNJ		0x36
475*4882a593Smuzhiyun #define IWL_CFG_MAC_TYPE_SNJ		0x42
476*4882a593Smuzhiyun #define IWL_CFG_MAC_TYPE_MA		0x44
477*4882a593Smuzhiyun 
478*4882a593Smuzhiyun #define IWL_CFG_RF_TYPE_TH		0x105
479*4882a593Smuzhiyun #define IWL_CFG_RF_TYPE_TH1		0x108
480*4882a593Smuzhiyun #define IWL_CFG_RF_TYPE_JF2		0x105
481*4882a593Smuzhiyun #define IWL_CFG_RF_TYPE_JF1		0x108
482*4882a593Smuzhiyun #define IWL_CFG_RF_TYPE_HR2		0x10A
483*4882a593Smuzhiyun #define IWL_CFG_RF_TYPE_HR1		0x10C
484*4882a593Smuzhiyun #define IWL_CFG_RF_TYPE_GF		0x10D
485*4882a593Smuzhiyun #define IWL_CFG_RF_TYPE_MR		0x110
486*4882a593Smuzhiyun 
487*4882a593Smuzhiyun #define IWL_CFG_RF_ID_TH		0x1
488*4882a593Smuzhiyun #define IWL_CFG_RF_ID_TH1		0x1
489*4882a593Smuzhiyun #define IWL_CFG_RF_ID_JF		0x3
490*4882a593Smuzhiyun #define IWL_CFG_RF_ID_JF1		0x6
491*4882a593Smuzhiyun #define IWL_CFG_RF_ID_JF1_DIV		0xA
492*4882a593Smuzhiyun #define IWL_CFG_RF_ID_HR		0x7
493*4882a593Smuzhiyun #define IWL_CFG_RF_ID_HR1		0x4
494*4882a593Smuzhiyun 
495*4882a593Smuzhiyun #define IWL_CFG_NO_160			0x1
496*4882a593Smuzhiyun #define IWL_CFG_160			0x0
497*4882a593Smuzhiyun 
498*4882a593Smuzhiyun #define IWL_CFG_CORES_BT		0x0
499*4882a593Smuzhiyun #define IWL_CFG_CORES_BT_GNSS		0x5
500*4882a593Smuzhiyun 
501*4882a593Smuzhiyun #define IWL_SUBDEVICE_RF_ID(subdevice)	((u16)((subdevice) & 0x00F0) >> 4)
502*4882a593Smuzhiyun #define IWL_SUBDEVICE_NO_160(subdevice)	((u16)((subdevice) & 0x0200) >> 9)
503*4882a593Smuzhiyun #define IWL_SUBDEVICE_CORES(subdevice)	((u16)((subdevice) & 0x1C00) >> 10)
504*4882a593Smuzhiyun 
505*4882a593Smuzhiyun struct iwl_dev_info {
506*4882a593Smuzhiyun 	u16 device;
507*4882a593Smuzhiyun 	u16 subdevice;
508*4882a593Smuzhiyun 	u16 mac_type;
509*4882a593Smuzhiyun 	u16 rf_type;
510*4882a593Smuzhiyun 	u8 mac_step;
511*4882a593Smuzhiyun 	u8 rf_id;
512*4882a593Smuzhiyun 	u8 no_160;
513*4882a593Smuzhiyun 	u8 cores;
514*4882a593Smuzhiyun 	const struct iwl_cfg *cfg;
515*4882a593Smuzhiyun 	const char *name;
516*4882a593Smuzhiyun };
517*4882a593Smuzhiyun 
518*4882a593Smuzhiyun /*
519*4882a593Smuzhiyun  * This list declares the config structures for all devices.
520*4882a593Smuzhiyun  */
521*4882a593Smuzhiyun extern const struct iwl_cfg_trans_params iwl9000_trans_cfg;
522*4882a593Smuzhiyun extern const struct iwl_cfg_trans_params iwl9560_trans_cfg;
523*4882a593Smuzhiyun extern const struct iwl_cfg_trans_params iwl9560_long_latency_trans_cfg;
524*4882a593Smuzhiyun extern const struct iwl_cfg_trans_params iwl9560_shared_clk_trans_cfg;
525*4882a593Smuzhiyun extern const struct iwl_cfg_trans_params iwl_qnj_trans_cfg;
526*4882a593Smuzhiyun extern const struct iwl_cfg_trans_params iwl_qu_trans_cfg;
527*4882a593Smuzhiyun extern const struct iwl_cfg_trans_params iwl_qu_medium_latency_trans_cfg;
528*4882a593Smuzhiyun extern const struct iwl_cfg_trans_params iwl_qu_long_latency_trans_cfg;
529*4882a593Smuzhiyun extern const struct iwl_cfg_trans_params iwl_ax200_trans_cfg;
530*4882a593Smuzhiyun extern const struct iwl_cfg_trans_params iwl_ma_trans_cfg;
531*4882a593Smuzhiyun extern const char iwl9162_name[];
532*4882a593Smuzhiyun extern const char iwl9260_name[];
533*4882a593Smuzhiyun extern const char iwl9260_1_name[];
534*4882a593Smuzhiyun extern const char iwl9270_name[];
535*4882a593Smuzhiyun extern const char iwl9461_name[];
536*4882a593Smuzhiyun extern const char iwl9462_name[];
537*4882a593Smuzhiyun extern const char iwl9560_name[];
538*4882a593Smuzhiyun extern const char iwl9162_160_name[];
539*4882a593Smuzhiyun extern const char iwl9260_160_name[];
540*4882a593Smuzhiyun extern const char iwl9270_160_name[];
541*4882a593Smuzhiyun extern const char iwl9461_160_name[];
542*4882a593Smuzhiyun extern const char iwl9462_160_name[];
543*4882a593Smuzhiyun extern const char iwl9560_160_name[];
544*4882a593Smuzhiyun extern const char iwl9260_killer_1550_name[];
545*4882a593Smuzhiyun extern const char iwl9560_killer_1550i_name[];
546*4882a593Smuzhiyun extern const char iwl9560_killer_1550s_name[];
547*4882a593Smuzhiyun extern const char iwl_ax200_name[];
548*4882a593Smuzhiyun extern const char iwl_ax203_name[];
549*4882a593Smuzhiyun extern const char iwl_ax201_name[];
550*4882a593Smuzhiyun extern const char iwl_ax101_name[];
551*4882a593Smuzhiyun extern const char iwl_ax200_killer_1650w_name[];
552*4882a593Smuzhiyun extern const char iwl_ax200_killer_1650x_name[];
553*4882a593Smuzhiyun extern const char iwl_ax201_killer_1650s_name[];
554*4882a593Smuzhiyun extern const char iwl_ax201_killer_1650i_name[];
555*4882a593Smuzhiyun extern const char iwl_ma_name[];
556*4882a593Smuzhiyun extern const char iwl_ax211_name[];
557*4882a593Smuzhiyun extern const char iwl_ax411_name[];
558*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_IWLDVM)
559*4882a593Smuzhiyun extern const struct iwl_cfg iwl5300_agn_cfg;
560*4882a593Smuzhiyun extern const struct iwl_cfg iwl5100_agn_cfg;
561*4882a593Smuzhiyun extern const struct iwl_cfg iwl5350_agn_cfg;
562*4882a593Smuzhiyun extern const struct iwl_cfg iwl5100_bgn_cfg;
563*4882a593Smuzhiyun extern const struct iwl_cfg iwl5100_abg_cfg;
564*4882a593Smuzhiyun extern const struct iwl_cfg iwl5150_agn_cfg;
565*4882a593Smuzhiyun extern const struct iwl_cfg iwl5150_abg_cfg;
566*4882a593Smuzhiyun extern const struct iwl_cfg iwl6005_2agn_cfg;
567*4882a593Smuzhiyun extern const struct iwl_cfg iwl6005_2abg_cfg;
568*4882a593Smuzhiyun extern const struct iwl_cfg iwl6005_2bg_cfg;
569*4882a593Smuzhiyun extern const struct iwl_cfg iwl6005_2agn_sff_cfg;
570*4882a593Smuzhiyun extern const struct iwl_cfg iwl6005_2agn_d_cfg;
571*4882a593Smuzhiyun extern const struct iwl_cfg iwl6005_2agn_mow1_cfg;
572*4882a593Smuzhiyun extern const struct iwl_cfg iwl6005_2agn_mow2_cfg;
573*4882a593Smuzhiyun extern const struct iwl_cfg iwl1030_bgn_cfg;
574*4882a593Smuzhiyun extern const struct iwl_cfg iwl1030_bg_cfg;
575*4882a593Smuzhiyun extern const struct iwl_cfg iwl6030_2agn_cfg;
576*4882a593Smuzhiyun extern const struct iwl_cfg iwl6030_2abg_cfg;
577*4882a593Smuzhiyun extern const struct iwl_cfg iwl6030_2bgn_cfg;
578*4882a593Smuzhiyun extern const struct iwl_cfg iwl6030_2bg_cfg;
579*4882a593Smuzhiyun extern const struct iwl_cfg iwl6000i_2agn_cfg;
580*4882a593Smuzhiyun extern const struct iwl_cfg iwl6000i_2abg_cfg;
581*4882a593Smuzhiyun extern const struct iwl_cfg iwl6000i_2bg_cfg;
582*4882a593Smuzhiyun extern const struct iwl_cfg iwl6000_3agn_cfg;
583*4882a593Smuzhiyun extern const struct iwl_cfg iwl6050_2agn_cfg;
584*4882a593Smuzhiyun extern const struct iwl_cfg iwl6050_2abg_cfg;
585*4882a593Smuzhiyun extern const struct iwl_cfg iwl6150_bgn_cfg;
586*4882a593Smuzhiyun extern const struct iwl_cfg iwl6150_bg_cfg;
587*4882a593Smuzhiyun extern const struct iwl_cfg iwl1000_bgn_cfg;
588*4882a593Smuzhiyun extern const struct iwl_cfg iwl1000_bg_cfg;
589*4882a593Smuzhiyun extern const struct iwl_cfg iwl100_bgn_cfg;
590*4882a593Smuzhiyun extern const struct iwl_cfg iwl100_bg_cfg;
591*4882a593Smuzhiyun extern const struct iwl_cfg iwl130_bgn_cfg;
592*4882a593Smuzhiyun extern const struct iwl_cfg iwl130_bg_cfg;
593*4882a593Smuzhiyun extern const struct iwl_cfg iwl2000_2bgn_cfg;
594*4882a593Smuzhiyun extern const struct iwl_cfg iwl2000_2bgn_d_cfg;
595*4882a593Smuzhiyun extern const struct iwl_cfg iwl2030_2bgn_cfg;
596*4882a593Smuzhiyun extern const struct iwl_cfg iwl6035_2agn_cfg;
597*4882a593Smuzhiyun extern const struct iwl_cfg iwl6035_2agn_sff_cfg;
598*4882a593Smuzhiyun extern const struct iwl_cfg iwl105_bgn_cfg;
599*4882a593Smuzhiyun extern const struct iwl_cfg iwl105_bgn_d_cfg;
600*4882a593Smuzhiyun extern const struct iwl_cfg iwl135_bgn_cfg;
601*4882a593Smuzhiyun #endif /* CONFIG_IWLDVM */
602*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_IWLMVM)
603*4882a593Smuzhiyun extern const struct iwl_cfg iwl7260_2ac_cfg;
604*4882a593Smuzhiyun extern const struct iwl_cfg iwl7260_2ac_cfg_high_temp;
605*4882a593Smuzhiyun extern const struct iwl_cfg iwl7260_2n_cfg;
606*4882a593Smuzhiyun extern const struct iwl_cfg iwl7260_n_cfg;
607*4882a593Smuzhiyun extern const struct iwl_cfg iwl3160_2ac_cfg;
608*4882a593Smuzhiyun extern const struct iwl_cfg iwl3160_2n_cfg;
609*4882a593Smuzhiyun extern const struct iwl_cfg iwl3160_n_cfg;
610*4882a593Smuzhiyun extern const struct iwl_cfg iwl3165_2ac_cfg;
611*4882a593Smuzhiyun extern const struct iwl_cfg iwl3168_2ac_cfg;
612*4882a593Smuzhiyun extern const struct iwl_cfg iwl7265_2ac_cfg;
613*4882a593Smuzhiyun extern const struct iwl_cfg iwl7265_2n_cfg;
614*4882a593Smuzhiyun extern const struct iwl_cfg iwl7265_n_cfg;
615*4882a593Smuzhiyun extern const struct iwl_cfg iwl7265d_2ac_cfg;
616*4882a593Smuzhiyun extern const struct iwl_cfg iwl7265d_2n_cfg;
617*4882a593Smuzhiyun extern const struct iwl_cfg iwl7265d_n_cfg;
618*4882a593Smuzhiyun extern const struct iwl_cfg iwl8260_2n_cfg;
619*4882a593Smuzhiyun extern const struct iwl_cfg iwl8260_2ac_cfg;
620*4882a593Smuzhiyun extern const struct iwl_cfg iwl8265_2ac_cfg;
621*4882a593Smuzhiyun extern const struct iwl_cfg iwl8275_2ac_cfg;
622*4882a593Smuzhiyun extern const struct iwl_cfg iwl4165_2ac_cfg;
623*4882a593Smuzhiyun extern const struct iwl_cfg iwl9260_2ac_cfg;
624*4882a593Smuzhiyun extern const struct iwl_cfg iwl9560_qu_b0_jf_b0_cfg;
625*4882a593Smuzhiyun extern const struct iwl_cfg iwl9560_qu_c0_jf_b0_cfg;
626*4882a593Smuzhiyun extern const struct iwl_cfg iwl9560_quz_a0_jf_b0_cfg;
627*4882a593Smuzhiyun extern const struct iwl_cfg iwl9560_qnj_b0_jf_b0_cfg;
628*4882a593Smuzhiyun extern const struct iwl_cfg iwl9560_2ac_cfg_soc;
629*4882a593Smuzhiyun extern const struct iwl_cfg iwl_qu_b0_hr1_b0;
630*4882a593Smuzhiyun extern const struct iwl_cfg iwl_qu_c0_hr1_b0;
631*4882a593Smuzhiyun extern const struct iwl_cfg iwl_quz_a0_hr1_b0;
632*4882a593Smuzhiyun extern const struct iwl_cfg iwl_qu_b0_hr_b0;
633*4882a593Smuzhiyun extern const struct iwl_cfg iwl_qu_c0_hr_b0;
634*4882a593Smuzhiyun extern const struct iwl_cfg iwl_ax200_cfg_cc;
635*4882a593Smuzhiyun extern const struct iwl_cfg iwl_ax201_cfg_qu_hr;
636*4882a593Smuzhiyun extern const struct iwl_cfg iwl_ax201_cfg_qu_hr;
637*4882a593Smuzhiyun extern const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0;
638*4882a593Smuzhiyun extern const struct iwl_cfg iwl_ax201_cfg_quz_hr;
639*4882a593Smuzhiyun extern const struct iwl_cfg iwl_ax1650i_cfg_quz_hr;
640*4882a593Smuzhiyun extern const struct iwl_cfg iwl_ax1650s_cfg_quz_hr;
641*4882a593Smuzhiyun extern const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0;
642*4882a593Smuzhiyun extern const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0;
643*4882a593Smuzhiyun extern const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0;
644*4882a593Smuzhiyun extern const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0;
645*4882a593Smuzhiyun extern const struct iwl_cfg killer1650x_2ax_cfg;
646*4882a593Smuzhiyun extern const struct iwl_cfg killer1650w_2ax_cfg;
647*4882a593Smuzhiyun extern const struct iwl_cfg iwl_qnj_b0_hr_b0_cfg;
648*4882a593Smuzhiyun extern const struct iwl_cfg iwlax210_2ax_cfg_so_jf_a0;
649*4882a593Smuzhiyun extern const struct iwl_cfg iwlax210_2ax_cfg_so_hr_a0;
650*4882a593Smuzhiyun extern const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0;
651*4882a593Smuzhiyun extern const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long;
652*4882a593Smuzhiyun extern const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0;
653*4882a593Smuzhiyun extern const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0;
654*4882a593Smuzhiyun extern const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long;
655*4882a593Smuzhiyun extern const struct iwl_cfg iwlax411_2ax_cfg_sosnj_gf4_a0;
656*4882a593Smuzhiyun extern const struct iwl_cfg iwlax211_cfg_snj_gf_a0;
657*4882a593Smuzhiyun extern const struct iwl_cfg iwlax201_cfg_snj_hr_b0;
658*4882a593Smuzhiyun extern const struct iwl_cfg iwl_cfg_ma_a0_gf_a0;
659*4882a593Smuzhiyun extern const struct iwl_cfg iwl_cfg_ma_a0_mr_a0;
660*4882a593Smuzhiyun extern const struct iwl_cfg iwl_cfg_snj_a0_mr_a0;
661*4882a593Smuzhiyun #endif /* CONFIG_IWLMVM */
662*4882a593Smuzhiyun 
663*4882a593Smuzhiyun #endif /* __IWL_CONFIG_H__ */
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