xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/intel/iwlwifi/fw/file.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /******************************************************************************
2*4882a593Smuzhiyun  *
3*4882a593Smuzhiyun  * This file is provided under a dual BSD/GPLv2 license.  When using or
4*4882a593Smuzhiyun  * redistributing this file, you may do so under either license.
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * GPL LICENSE SUMMARY
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
9*4882a593Smuzhiyun  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
10*4882a593Smuzhiyun  * Copyright(c) 2008 - 2014, 2018 - 2020 Intel Corporation
11*4882a593Smuzhiyun  *
12*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or modify
13*4882a593Smuzhiyun  * it under the terms of version 2 of the GNU General Public License as
14*4882a593Smuzhiyun  * published by the Free Software Foundation.
15*4882a593Smuzhiyun  *
16*4882a593Smuzhiyun  * This program is distributed in the hope that it will be useful, but
17*4882a593Smuzhiyun  * WITHOUT ANY WARRANTY; without even the implied warranty of
18*4882a593Smuzhiyun  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
19*4882a593Smuzhiyun  * General Public License for more details.
20*4882a593Smuzhiyun  *
21*4882a593Smuzhiyun  * The full GNU General Public License is included in this distribution
22*4882a593Smuzhiyun  * in the file called COPYING.
23*4882a593Smuzhiyun  *
24*4882a593Smuzhiyun  * Contact Information:
25*4882a593Smuzhiyun  *  Intel Linux Wireless <linuxwifi@intel.com>
26*4882a593Smuzhiyun  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27*4882a593Smuzhiyun  *
28*4882a593Smuzhiyun  * BSD LICENSE
29*4882a593Smuzhiyun  *
30*4882a593Smuzhiyun  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
31*4882a593Smuzhiyun  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
32*4882a593Smuzhiyun  * Copyright(c) 2008 - 2014, 2018 - 2020 Intel Corporation
33*4882a593Smuzhiyun  * All rights reserved.
34*4882a593Smuzhiyun  *
35*4882a593Smuzhiyun  * Redistribution and use in source and binary forms, with or without
36*4882a593Smuzhiyun  * modification, are permitted provided that the following conditions
37*4882a593Smuzhiyun  * are met:
38*4882a593Smuzhiyun  *
39*4882a593Smuzhiyun  *  * Redistributions of source code must retain the above copyright
40*4882a593Smuzhiyun  *    notice, this list of conditions and the following disclaimer.
41*4882a593Smuzhiyun  *  * Redistributions in binary form must reproduce the above copyright
42*4882a593Smuzhiyun  *    notice, this list of conditions and the following disclaimer in
43*4882a593Smuzhiyun  *    the documentation and/or other materials provided with the
44*4882a593Smuzhiyun  *    distribution.
45*4882a593Smuzhiyun  *  * Neither the name Intel Corporation nor the names of its
46*4882a593Smuzhiyun  *    contributors may be used to endorse or promote products derived
47*4882a593Smuzhiyun  *    from this software without specific prior written permission.
48*4882a593Smuzhiyun  *
49*4882a593Smuzhiyun  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
50*4882a593Smuzhiyun  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
51*4882a593Smuzhiyun  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
52*4882a593Smuzhiyun  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
53*4882a593Smuzhiyun  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
54*4882a593Smuzhiyun  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
55*4882a593Smuzhiyun  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
56*4882a593Smuzhiyun  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
57*4882a593Smuzhiyun  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
58*4882a593Smuzhiyun  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
59*4882a593Smuzhiyun  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
60*4882a593Smuzhiyun  *****************************************************************************/
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun #ifndef __iwl_fw_file_h__
63*4882a593Smuzhiyun #define __iwl_fw_file_h__
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun #include <linux/netdevice.h>
66*4882a593Smuzhiyun #include <linux/nl80211.h>
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun /* v1/v2 uCode file layout */
69*4882a593Smuzhiyun struct iwl_ucode_header {
70*4882a593Smuzhiyun 	__le32 ver;	/* major/minor/API/serial */
71*4882a593Smuzhiyun 	union {
72*4882a593Smuzhiyun 		struct {
73*4882a593Smuzhiyun 			__le32 inst_size;	/* bytes of runtime code */
74*4882a593Smuzhiyun 			__le32 data_size;	/* bytes of runtime data */
75*4882a593Smuzhiyun 			__le32 init_size;	/* bytes of init code */
76*4882a593Smuzhiyun 			__le32 init_data_size;	/* bytes of init data */
77*4882a593Smuzhiyun 			__le32 boot_size;	/* bytes of bootstrap code */
78*4882a593Smuzhiyun 			u8 data[0];		/* in same order as sizes */
79*4882a593Smuzhiyun 		} v1;
80*4882a593Smuzhiyun 		struct {
81*4882a593Smuzhiyun 			__le32 build;		/* build number */
82*4882a593Smuzhiyun 			__le32 inst_size;	/* bytes of runtime code */
83*4882a593Smuzhiyun 			__le32 data_size;	/* bytes of runtime data */
84*4882a593Smuzhiyun 			__le32 init_size;	/* bytes of init code */
85*4882a593Smuzhiyun 			__le32 init_data_size;	/* bytes of init data */
86*4882a593Smuzhiyun 			__le32 boot_size;	/* bytes of bootstrap code */
87*4882a593Smuzhiyun 			u8 data[0];		/* in same order as sizes */
88*4882a593Smuzhiyun 		} v2;
89*4882a593Smuzhiyun 	} u;
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun #define IWL_UCODE_TLV_DEBUG_BASE	0x1000005
93*4882a593Smuzhiyun #define IWL_UCODE_TLV_CONST_BASE	0x100
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun /*
96*4882a593Smuzhiyun  * new TLV uCode file layout
97*4882a593Smuzhiyun  *
98*4882a593Smuzhiyun  * The new TLV file format contains TLVs, that each specify
99*4882a593Smuzhiyun  * some piece of data.
100*4882a593Smuzhiyun  */
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun enum iwl_ucode_tlv_type {
103*4882a593Smuzhiyun 	IWL_UCODE_TLV_INVALID		= 0, /* unused */
104*4882a593Smuzhiyun 	IWL_UCODE_TLV_INST		= 1,
105*4882a593Smuzhiyun 	IWL_UCODE_TLV_DATA		= 2,
106*4882a593Smuzhiyun 	IWL_UCODE_TLV_INIT		= 3,
107*4882a593Smuzhiyun 	IWL_UCODE_TLV_INIT_DATA		= 4,
108*4882a593Smuzhiyun 	IWL_UCODE_TLV_BOOT		= 5,
109*4882a593Smuzhiyun 	IWL_UCODE_TLV_PROBE_MAX_LEN	= 6, /* a u32 value */
110*4882a593Smuzhiyun 	IWL_UCODE_TLV_PAN		= 7,
111*4882a593Smuzhiyun 	IWL_UCODE_TLV_RUNT_EVTLOG_PTR	= 8,
112*4882a593Smuzhiyun 	IWL_UCODE_TLV_RUNT_EVTLOG_SIZE	= 9,
113*4882a593Smuzhiyun 	IWL_UCODE_TLV_RUNT_ERRLOG_PTR	= 10,
114*4882a593Smuzhiyun 	IWL_UCODE_TLV_INIT_EVTLOG_PTR	= 11,
115*4882a593Smuzhiyun 	IWL_UCODE_TLV_INIT_EVTLOG_SIZE	= 12,
116*4882a593Smuzhiyun 	IWL_UCODE_TLV_INIT_ERRLOG_PTR	= 13,
117*4882a593Smuzhiyun 	IWL_UCODE_TLV_ENHANCE_SENS_TBL	= 14,
118*4882a593Smuzhiyun 	IWL_UCODE_TLV_PHY_CALIBRATION_SIZE = 15,
119*4882a593Smuzhiyun 	IWL_UCODE_TLV_WOWLAN_INST	= 16,
120*4882a593Smuzhiyun 	IWL_UCODE_TLV_WOWLAN_DATA	= 17,
121*4882a593Smuzhiyun 	IWL_UCODE_TLV_FLAGS		= 18,
122*4882a593Smuzhiyun 	IWL_UCODE_TLV_SEC_RT		= 19,
123*4882a593Smuzhiyun 	IWL_UCODE_TLV_SEC_INIT		= 20,
124*4882a593Smuzhiyun 	IWL_UCODE_TLV_SEC_WOWLAN	= 21,
125*4882a593Smuzhiyun 	IWL_UCODE_TLV_DEF_CALIB		= 22,
126*4882a593Smuzhiyun 	IWL_UCODE_TLV_PHY_SKU		= 23,
127*4882a593Smuzhiyun 	IWL_UCODE_TLV_SECURE_SEC_RT	= 24,
128*4882a593Smuzhiyun 	IWL_UCODE_TLV_SECURE_SEC_INIT	= 25,
129*4882a593Smuzhiyun 	IWL_UCODE_TLV_SECURE_SEC_WOWLAN	= 26,
130*4882a593Smuzhiyun 	IWL_UCODE_TLV_NUM_OF_CPU	= 27,
131*4882a593Smuzhiyun 	IWL_UCODE_TLV_CSCHEME		= 28,
132*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_CHANGES_SET	= 29,
133*4882a593Smuzhiyun 	IWL_UCODE_TLV_ENABLED_CAPABILITIES	= 30,
134*4882a593Smuzhiyun 	IWL_UCODE_TLV_N_SCAN_CHANNELS		= 31,
135*4882a593Smuzhiyun 	IWL_UCODE_TLV_PAGING		= 32,
136*4882a593Smuzhiyun 	IWL_UCODE_TLV_SEC_RT_USNIFFER	= 34,
137*4882a593Smuzhiyun 	/* 35 is unused */
138*4882a593Smuzhiyun 	IWL_UCODE_TLV_FW_VERSION	= 36,
139*4882a593Smuzhiyun 	IWL_UCODE_TLV_FW_DBG_DEST	= 38,
140*4882a593Smuzhiyun 	IWL_UCODE_TLV_FW_DBG_CONF	= 39,
141*4882a593Smuzhiyun 	IWL_UCODE_TLV_FW_DBG_TRIGGER	= 40,
142*4882a593Smuzhiyun 	IWL_UCODE_TLV_CMD_VERSIONS	= 48,
143*4882a593Smuzhiyun 	IWL_UCODE_TLV_FW_GSCAN_CAPA	= 50,
144*4882a593Smuzhiyun 	IWL_UCODE_TLV_FW_MEM_SEG	= 51,
145*4882a593Smuzhiyun 	IWL_UCODE_TLV_IML		= 52,
146*4882a593Smuzhiyun 	IWL_UCODE_TLV_UMAC_DEBUG_ADDRS	= 54,
147*4882a593Smuzhiyun 	IWL_UCODE_TLV_LMAC_DEBUG_ADDRS	= 55,
148*4882a593Smuzhiyun 	IWL_UCODE_TLV_FW_RECOVERY_INFO	= 57,
149*4882a593Smuzhiyun 	IWL_UCODE_TLV_HW_TYPE			= 58,
150*4882a593Smuzhiyun 	IWL_UCODE_TLV_FW_FSEQ_VERSION		= 60,
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	IWL_UCODE_TLV_PNVM_VERSION		= 62,
153*4882a593Smuzhiyun 	IWL_UCODE_TLV_PNVM_SKU			= 64,
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	IWL_UCODE_TLV_FW_NUM_STATIONS		= IWL_UCODE_TLV_CONST_BASE + 0,
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	IWL_UCODE_TLV_TYPE_DEBUG_INFO		= IWL_UCODE_TLV_DEBUG_BASE + 0,
158*4882a593Smuzhiyun 	IWL_UCODE_TLV_TYPE_BUFFER_ALLOCATION	= IWL_UCODE_TLV_DEBUG_BASE + 1,
159*4882a593Smuzhiyun 	IWL_UCODE_TLV_TYPE_HCMD			= IWL_UCODE_TLV_DEBUG_BASE + 2,
160*4882a593Smuzhiyun 	IWL_UCODE_TLV_TYPE_REGIONS		= IWL_UCODE_TLV_DEBUG_BASE + 3,
161*4882a593Smuzhiyun 	IWL_UCODE_TLV_TYPE_TRIGGERS		= IWL_UCODE_TLV_DEBUG_BASE + 4,
162*4882a593Smuzhiyun 	IWL_UCODE_TLV_DEBUG_MAX = IWL_UCODE_TLV_TYPE_TRIGGERS,
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	/* TLVs 0x1000-0x2000 are for internal driver usage */
165*4882a593Smuzhiyun 	IWL_UCODE_TLV_FW_DBG_DUMP_LST	= 0x1000,
166*4882a593Smuzhiyun };
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun struct iwl_ucode_tlv {
169*4882a593Smuzhiyun 	__le32 type;		/* see above */
170*4882a593Smuzhiyun 	__le32 length;		/* not including type/length fields */
171*4882a593Smuzhiyun 	u8 data[0];
172*4882a593Smuzhiyun };
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun #define IWL_TLV_UCODE_MAGIC		0x0a4c5749
175*4882a593Smuzhiyun #define FW_VER_HUMAN_READABLE_SZ	64
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun struct iwl_tlv_ucode_header {
178*4882a593Smuzhiyun 	/*
179*4882a593Smuzhiyun 	 * The TLV style ucode header is distinguished from
180*4882a593Smuzhiyun 	 * the v1/v2 style header by first four bytes being
181*4882a593Smuzhiyun 	 * zero, as such is an invalid combination of
182*4882a593Smuzhiyun 	 * major/minor/API/serial versions.
183*4882a593Smuzhiyun 	 */
184*4882a593Smuzhiyun 	__le32 zero;
185*4882a593Smuzhiyun 	__le32 magic;
186*4882a593Smuzhiyun 	u8 human_readable[FW_VER_HUMAN_READABLE_SZ];
187*4882a593Smuzhiyun 	/* major/minor/API/serial or major in new format */
188*4882a593Smuzhiyun 	__le32 ver;
189*4882a593Smuzhiyun 	__le32 build;
190*4882a593Smuzhiyun 	__le64 ignore;
191*4882a593Smuzhiyun 	/*
192*4882a593Smuzhiyun 	 * The data contained herein has a TLV layout,
193*4882a593Smuzhiyun 	 * see above for the TLV header and types.
194*4882a593Smuzhiyun 	 * Note that each TLV is padded to a length
195*4882a593Smuzhiyun 	 * that is a multiple of 4 for alignment.
196*4882a593Smuzhiyun 	 */
197*4882a593Smuzhiyun 	u8 data[0];
198*4882a593Smuzhiyun };
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun /*
201*4882a593Smuzhiyun  * ucode TLVs
202*4882a593Smuzhiyun  *
203*4882a593Smuzhiyun  * ability to get extension for: flags & capabilities from ucode binaries files
204*4882a593Smuzhiyun  */
205*4882a593Smuzhiyun struct iwl_ucode_api {
206*4882a593Smuzhiyun 	__le32 api_index;
207*4882a593Smuzhiyun 	__le32 api_flags;
208*4882a593Smuzhiyun } __packed;
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun struct iwl_ucode_capa {
211*4882a593Smuzhiyun 	__le32 api_index;
212*4882a593Smuzhiyun 	__le32 api_capa;
213*4882a593Smuzhiyun } __packed;
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun /**
216*4882a593Smuzhiyun  * enum iwl_ucode_tlv_flag - ucode API flags
217*4882a593Smuzhiyun  * @IWL_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously
218*4882a593Smuzhiyun  *	was a separate TLV but moved here to save space.
219*4882a593Smuzhiyun  * @IWL_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behavior on hidden SSID,
220*4882a593Smuzhiyun  *	treats good CRC threshold as a boolean
221*4882a593Smuzhiyun  * @IWL_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w).
222*4882a593Smuzhiyun  * @IWL_UCODE_TLV_FLAGS_UAPSD_SUPPORT: This uCode image supports uAPSD
223*4882a593Smuzhiyun  * @IWL_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of block list instead of 64 in scan
224*4882a593Smuzhiyun  *	offload profile config command.
225*4882a593Smuzhiyun  * @IWL_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six
226*4882a593Smuzhiyun  *	(rather than two) IPv6 addresses
227*4882a593Smuzhiyun  * @IWL_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element
228*4882a593Smuzhiyun  *	from the probe request template.
229*4882a593Smuzhiyun  * @IWL_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version)
230*4882a593Smuzhiyun  * @IWL_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version)
231*4882a593Smuzhiyun  * @IWL_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD
232*4882a593Smuzhiyun  * @IWL_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save
233*4882a593Smuzhiyun  * @IWL_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering.
234*4882a593Smuzhiyun  * @IWL_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS.
235*4882a593Smuzhiyun  */
236*4882a593Smuzhiyun enum iwl_ucode_tlv_flag {
237*4882a593Smuzhiyun 	IWL_UCODE_TLV_FLAGS_PAN			= BIT(0),
238*4882a593Smuzhiyun 	IWL_UCODE_TLV_FLAGS_NEWSCAN		= BIT(1),
239*4882a593Smuzhiyun 	IWL_UCODE_TLV_FLAGS_MFP			= BIT(2),
240*4882a593Smuzhiyun 	IWL_UCODE_TLV_FLAGS_SHORT_BL		= BIT(7),
241*4882a593Smuzhiyun 	IWL_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS	= BIT(10),
242*4882a593Smuzhiyun 	IWL_UCODE_TLV_FLAGS_NO_BASIC_SSID	= BIT(12),
243*4882a593Smuzhiyun 	IWL_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL	= BIT(15),
244*4882a593Smuzhiyun 	IWL_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE	= BIT(16),
245*4882a593Smuzhiyun 	IWL_UCODE_TLV_FLAGS_UAPSD_SUPPORT	= BIT(24),
246*4882a593Smuzhiyun 	IWL_UCODE_TLV_FLAGS_EBS_SUPPORT		= BIT(25),
247*4882a593Smuzhiyun 	IWL_UCODE_TLV_FLAGS_P2P_PS_UAPSD	= BIT(26),
248*4882a593Smuzhiyun 	IWL_UCODE_TLV_FLAGS_BCAST_FILTERING	= BIT(29),
249*4882a593Smuzhiyun };
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun typedef unsigned int __bitwise iwl_ucode_tlv_api_t;
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun /**
254*4882a593Smuzhiyun  * enum iwl_ucode_tlv_api - ucode api
255*4882a593Smuzhiyun  * @IWL_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time
256*4882a593Smuzhiyun  *	longer than the passive one, which is essential for fragmented scan.
257*4882a593Smuzhiyun  * @IWL_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source.
258*4882a593Smuzhiyun  * @IWL_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params
259*4882a593Smuzhiyun  * @IWL_UCODE_TLV_API_NEW_VERSION: new versioning format
260*4882a593Smuzhiyun  * @IWL_UCODE_TLV_API_SCAN_TSF_REPORT: Scan start time reported in scan
261*4882a593Smuzhiyun  *	iteration complete notification, and the timestamp reported for RX
262*4882a593Smuzhiyun  *	received during scan, are reported in TSF of the mac specified in the
263*4882a593Smuzhiyun  *	scan request.
264*4882a593Smuzhiyun  * @IWL_UCODE_TLV_API_TKIP_MIC_KEYS: This ucode supports version 2 of
265*4882a593Smuzhiyun  *	ADD_MODIFY_STA_KEY_API_S_VER_2.
266*4882a593Smuzhiyun  * @IWL_UCODE_TLV_API_STA_TYPE: This ucode supports station type assignement.
267*4882a593Smuzhiyun  * @IWL_UCODE_TLV_API_NAN2_VER2: This ucode supports NAN API version 2
268*4882a593Smuzhiyun  * @IWL_UCODE_TLV_API_NEW_RX_STATS: should new RX STATISTICS API be used
269*4882a593Smuzhiyun  * @IWL_UCODE_TLV_API_QUOTA_LOW_LATENCY: Quota command includes a field
270*4882a593Smuzhiyun  *	indicating low latency direction.
271*4882a593Smuzhiyun  * @IWL_UCODE_TLV_API_DEPRECATE_TTAK: RX status flag TTAK ok (bit 7) is
272*4882a593Smuzhiyun  *	deprecated.
273*4882a593Smuzhiyun  * @IWL_UCODE_TLV_API_ADAPTIVE_DWELL_V2: This ucode supports version 8
274*4882a593Smuzhiyun  *	of scan request: SCAN_REQUEST_CMD_UMAC_API_S_VER_8
275*4882a593Smuzhiyun  * @IWL_UCODE_TLV_API_FRAG_EBS: This ucode supports fragmented EBS
276*4882a593Smuzhiyun  * @IWL_UCODE_TLV_API_REDUCE_TX_POWER: This ucode supports v5 of
277*4882a593Smuzhiyun  *	the REDUCE_TX_POWER_CMD.
278*4882a593Smuzhiyun  * @IWL_UCODE_TLV_API_SHORT_BEACON_NOTIF: This ucode supports the short
279*4882a593Smuzhiyun  *	version of the beacon notification.
280*4882a593Smuzhiyun  * @IWL_UCODE_TLV_API_BEACON_FILTER_V4: This ucode supports v4 of
281*4882a593Smuzhiyun  *	BEACON_FILTER_CONFIG_API_S_VER_4.
282*4882a593Smuzhiyun  * @IWL_UCODE_TLV_API_REGULATORY_NVM_INFO: This ucode supports v4 of
283*4882a593Smuzhiyun  *	REGULATORY_NVM_GET_INFO_RSP_API_S.
284*4882a593Smuzhiyun  * @IWL_UCODE_TLV_API_FTM_NEW_RANGE_REQ: This ucode supports v7 of
285*4882a593Smuzhiyun  *	LOCATION_RANGE_REQ_CMD_API_S and v6 of LOCATION_RANGE_RESP_NTFY_API_S.
286*4882a593Smuzhiyun  * @IWL_UCODE_TLV_API_SCAN_OFFLOAD_CHANS: This ucode supports v2 of
287*4882a593Smuzhiyun  *	SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S and v3 of
288*4882a593Smuzhiyun  *	SCAN_OFFLOAD_PROFILES_QUERY_RSP_S.
289*4882a593Smuzhiyun  * @IWL_UCODE_TLV_API_MBSSID_HE: This ucode supports v2 of
290*4882a593Smuzhiyun  *	STA_CONTEXT_DOT11AX_API_S
291*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_SAR_TABLE_VER: This ucode supports different sar
292*4882a593Smuzhiyun  *	version tables.
293*4882a593Smuzhiyun  * @IWL_UCODE_TLV_API_REDUCED_SCAN_CONFIG: This ucode supports v3 of
294*4882a593Smuzhiyun  *  SCAN_CONFIG_DB_CMD_API_S.
295*4882a593Smuzhiyun  *
296*4882a593Smuzhiyun  * @NUM_IWL_UCODE_TLV_API: number of bits used
297*4882a593Smuzhiyun  */
298*4882a593Smuzhiyun enum iwl_ucode_tlv_api {
299*4882a593Smuzhiyun 	/* API Set 0 */
300*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_FRAGMENTED_SCAN	= (__force iwl_ucode_tlv_api_t)8,
301*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_WIFI_MCC_UPDATE	= (__force iwl_ucode_tlv_api_t)9,
302*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_LQ_SS_PARAMS		= (__force iwl_ucode_tlv_api_t)18,
303*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_NEW_VERSION		= (__force iwl_ucode_tlv_api_t)20,
304*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_SCAN_TSF_REPORT	= (__force iwl_ucode_tlv_api_t)28,
305*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_TKIP_MIC_KEYS		= (__force iwl_ucode_tlv_api_t)29,
306*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_STA_TYPE		= (__force iwl_ucode_tlv_api_t)30,
307*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_NAN2_VER2		= (__force iwl_ucode_tlv_api_t)31,
308*4882a593Smuzhiyun 	/* API Set 1 */
309*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_ADAPTIVE_DWELL	= (__force iwl_ucode_tlv_api_t)32,
310*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_OCE			= (__force iwl_ucode_tlv_api_t)33,
311*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_NEW_BEACON_TEMPLATE	= (__force iwl_ucode_tlv_api_t)34,
312*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_NEW_RX_STATS		= (__force iwl_ucode_tlv_api_t)35,
313*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_WOWLAN_KEY_MATERIAL	= (__force iwl_ucode_tlv_api_t)36,
314*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_QUOTA_LOW_LATENCY	= (__force iwl_ucode_tlv_api_t)38,
315*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_DEPRECATE_TTAK	= (__force iwl_ucode_tlv_api_t)41,
316*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_ADAPTIVE_DWELL_V2	= (__force iwl_ucode_tlv_api_t)42,
317*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_FRAG_EBS		= (__force iwl_ucode_tlv_api_t)44,
318*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_REDUCE_TX_POWER	= (__force iwl_ucode_tlv_api_t)45,
319*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_SHORT_BEACON_NOTIF	= (__force iwl_ucode_tlv_api_t)46,
320*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_BEACON_FILTER_V4      = (__force iwl_ucode_tlv_api_t)47,
321*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_REGULATORY_NVM_INFO   = (__force iwl_ucode_tlv_api_t)48,
322*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_FTM_NEW_RANGE_REQ     = (__force iwl_ucode_tlv_api_t)49,
323*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_SCAN_OFFLOAD_CHANS    = (__force iwl_ucode_tlv_api_t)50,
324*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_MBSSID_HE		= (__force iwl_ucode_tlv_api_t)52,
325*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_WOWLAN_TCP_SYN_WAKE	= (__force iwl_ucode_tlv_api_t)53,
326*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_FTM_RTT_ACCURACY      = (__force iwl_ucode_tlv_api_t)54,
327*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_SAR_TABLE_VER         = (__force iwl_ucode_tlv_api_t)55,
328*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_REDUCED_SCAN_CONFIG   = (__force iwl_ucode_tlv_api_t)56,
329*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_ADWELL_HB_DEF_N_AP	= (__force iwl_ucode_tlv_api_t)57,
330*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_SCAN_EXT_CHAN_VER	= (__force iwl_ucode_tlv_api_t)58,
331*4882a593Smuzhiyun 	IWL_UCODE_TLV_API_BAND_IN_RX_DATA	= (__force iwl_ucode_tlv_api_t)59,
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun 
334*4882a593Smuzhiyun 	NUM_IWL_UCODE_TLV_API
335*4882a593Smuzhiyun #ifdef __CHECKER__
336*4882a593Smuzhiyun 		/* sparse says it cannot increment the previous enum member */
337*4882a593Smuzhiyun 		= 128
338*4882a593Smuzhiyun #endif
339*4882a593Smuzhiyun };
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun typedef unsigned int __bitwise iwl_ucode_tlv_capa_t;
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun /**
344*4882a593Smuzhiyun  * enum iwl_ucode_tlv_capa - ucode capabilities
345*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3
346*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory
347*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan.
348*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer
349*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality
350*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current
351*4882a593Smuzhiyun  *	tx power value into TPC Report action frame and Link Measurement Report
352*4882a593Smuzhiyun  *	action frame
353*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current
354*4882a593Smuzhiyun  *	channel in DS parameter set element in probe requests.
355*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in
356*4882a593Smuzhiyun  *	probe requests.
357*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests
358*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA),
359*4882a593Smuzhiyun  *	which also implies support for the scheduler configuration command
360*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching
361*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image
362*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command
363*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command
364*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload
365*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics
366*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_P2P_SCM_UAPSD: supports U-APSD on p2p interface when it
367*4882a593Smuzhiyun  *	is standalone or with a BSS station interface in the same binding.
368*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running
369*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different
370*4882a593Smuzhiyun  *	sources for the MCC. This TLV bit is a future replacement to
371*4882a593Smuzhiyun  *	IWL_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR
372*4882a593Smuzhiyun  *	is supported.
373*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC
374*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan (no longer used)
375*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT: the firmware supports setting
376*4882a593Smuzhiyun  *	stabilization latency for SoCs.
377*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_STA_PM_NOTIF: firmware will send STA PM notification
378*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_TLC_OFFLOAD: firmware implements rate scaling algorithm
379*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_DYNAMIC_QUOTA: firmware implements quota related
380*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_COEX_SCHEMA_2: firmware implements Coex Schema 2
381*4882a593Smuzhiyun  * IWL_UCODE_TLV_CAPA_CHANNEL_SWITCH_CMD: firmware supports CSA command
382*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS: firmware supports ultra high band
383*4882a593Smuzhiyun  *	(6 GHz).
384*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_CS_MODIFY: firmware supports modify action CSA command
385*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement
386*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts
387*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT
388*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_CSA_AND_TBTT_OFFLOAD: the firmware supports CSA
389*4882a593Smuzhiyun  *	countdown offloading. Beacon notifications are not sent to the host.
390*4882a593Smuzhiyun  *	The fw also offloads TBTT alignment.
391*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what
392*4882a593Smuzhiyun  *	antenna the beacon should be transmitted
393*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon
394*4882a593Smuzhiyun  *	from AP and will send it upon d0i3 exit.
395*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_LAR_SUPPORT_V3: support LAR API V3
396*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill
397*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature
398*4882a593Smuzhiyun  *	thresholds reporting
399*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command
400*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in
401*4882a593Smuzhiyun  *	regular image.
402*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared
403*4882a593Smuzhiyun  *	memory addresses from the firmware.
404*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement
405*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_TX_POWER_ACK: reduced TX power API has larger
406*4882a593Smuzhiyun  *	command size (command version 4) that supports toggling ACK TX
407*4882a593Smuzhiyun  *	power reduction.
408*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_D3_DEBUG: supports debug recording during D3
409*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_MCC_UPDATE_11AX_SUPPORT: MCC response support 11ax
410*4882a593Smuzhiyun  *	capability.
411*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_CSI_REPORTING: firmware is capable of being configured
412*4882a593Smuzhiyun  *	to report the CSI information with (certain) RX frames
413*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_FTM_CALIBRATED: has FTM calibrated and thus supports both
414*4882a593Smuzhiyun  *	initiator and responder
415*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_MLME_OFFLOAD: supports MLME offload
416*4882a593Smuzhiyun  * @IWL_UCODE_TLV_CAPA_PROTECTED_TWT: Supports protection of TWT action frames
417*4882a593Smuzhiyun  *
418*4882a593Smuzhiyun  * @NUM_IWL_UCODE_TLV_CAPA: number of bits used
419*4882a593Smuzhiyun  */
420*4882a593Smuzhiyun enum iwl_ucode_tlv_capa {
421*4882a593Smuzhiyun 	/* set 0 */
422*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_D0I3_SUPPORT			= (__force iwl_ucode_tlv_capa_t)0,
423*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_LAR_SUPPORT			= (__force iwl_ucode_tlv_capa_t)1,
424*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_UMAC_SCAN			= (__force iwl_ucode_tlv_capa_t)2,
425*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_BEAMFORMER			= (__force iwl_ucode_tlv_capa_t)3,
426*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_TDLS_SUPPORT			= (__force iwl_ucode_tlv_capa_t)6,
427*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT	= (__force iwl_ucode_tlv_capa_t)8,
428*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT	= (__force iwl_ucode_tlv_capa_t)9,
429*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT	= (__force iwl_ucode_tlv_capa_t)10,
430*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT		= (__force iwl_ucode_tlv_capa_t)11,
431*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_DQA_SUPPORT			= (__force iwl_ucode_tlv_capa_t)12,
432*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH		= (__force iwl_ucode_tlv_capa_t)13,
433*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG		= (__force iwl_ucode_tlv_capa_t)17,
434*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_HOTSPOT_SUPPORT		= (__force iwl_ucode_tlv_capa_t)18,
435*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT		= (__force iwl_ucode_tlv_capa_t)19,
436*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_CSUM_SUPPORT			= (__force iwl_ucode_tlv_capa_t)21,
437*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_RADIO_BEACON_STATS		= (__force iwl_ucode_tlv_capa_t)22,
438*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_P2P_SCM_UAPSD		= (__force iwl_ucode_tlv_capa_t)26,
439*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_BT_COEX_PLCR			= (__force iwl_ucode_tlv_capa_t)28,
440*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_LAR_MULTI_MCC		= (__force iwl_ucode_tlv_capa_t)29,
441*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_BT_COEX_RRC			= (__force iwl_ucode_tlv_capa_t)30,
442*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_GSCAN_SUPPORT		= (__force iwl_ucode_tlv_capa_t)31,
443*4882a593Smuzhiyun 
444*4882a593Smuzhiyun 	/* set 1 */
445*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT		= (__force iwl_ucode_tlv_capa_t)37,
446*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_STA_PM_NOTIF			= (__force iwl_ucode_tlv_capa_t)38,
447*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_BINDING_CDB_SUPPORT		= (__force iwl_ucode_tlv_capa_t)39,
448*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_CDB_SUPPORT			= (__force iwl_ucode_tlv_capa_t)40,
449*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_D0I3_END_FIRST		= (__force iwl_ucode_tlv_capa_t)41,
450*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_TLC_OFFLOAD                  = (__force iwl_ucode_tlv_capa_t)43,
451*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_DYNAMIC_QUOTA                = (__force iwl_ucode_tlv_capa_t)44,
452*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_COEX_SCHEMA_2		= (__force iwl_ucode_tlv_capa_t)45,
453*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_CHANNEL_SWITCH_CMD		= (__force iwl_ucode_tlv_capa_t)46,
454*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_FTM_CALIBRATED		= (__force iwl_ucode_tlv_capa_t)47,
455*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS		= (__force iwl_ucode_tlv_capa_t)48,
456*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_CS_MODIFY			= (__force iwl_ucode_tlv_capa_t)49,
457*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_SET_LTR_GEN2			= (__force iwl_ucode_tlv_capa_t)50,
458*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_SET_PPAG			= (__force iwl_ucode_tlv_capa_t)52,
459*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_TAS_CFG			= (__force iwl_ucode_tlv_capa_t)53,
460*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_SESSION_PROT_CMD		= (__force iwl_ucode_tlv_capa_t)54,
461*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_PROTECTED_TWT		= (__force iwl_ucode_tlv_capa_t)56,
462*4882a593Smuzhiyun 
463*4882a593Smuzhiyun 	/* set 2 */
464*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE		= (__force iwl_ucode_tlv_capa_t)64,
465*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS		= (__force iwl_ucode_tlv_capa_t)65,
466*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT		= (__force iwl_ucode_tlv_capa_t)67,
467*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT	= (__force iwl_ucode_tlv_capa_t)68,
468*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_CSA_AND_TBTT_OFFLOAD		= (__force iwl_ucode_tlv_capa_t)70,
469*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_BEACON_ANT_SELECTION		= (__force iwl_ucode_tlv_capa_t)71,
470*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_BEACON_STORING		= (__force iwl_ucode_tlv_capa_t)72,
471*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_LAR_SUPPORT_V3		= (__force iwl_ucode_tlv_capa_t)73,
472*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_CT_KILL_BY_FW		= (__force iwl_ucode_tlv_capa_t)74,
473*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT	= (__force iwl_ucode_tlv_capa_t)75,
474*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_CTDP_SUPPORT			= (__force iwl_ucode_tlv_capa_t)76,
475*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_USNIFFER_UNIFIED		= (__force iwl_ucode_tlv_capa_t)77,
476*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG	= (__force iwl_ucode_tlv_capa_t)80,
477*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_LQM_SUPPORT			= (__force iwl_ucode_tlv_capa_t)81,
478*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_TX_POWER_ACK			= (__force iwl_ucode_tlv_capa_t)84,
479*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_D3_DEBUG			= (__force iwl_ucode_tlv_capa_t)87,
480*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_LED_CMD_SUPPORT		= (__force iwl_ucode_tlv_capa_t)88,
481*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_MCC_UPDATE_11AX_SUPPORT	= (__force iwl_ucode_tlv_capa_t)89,
482*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_CSI_REPORTING		= (__force iwl_ucode_tlv_capa_t)90,
483*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_DBG_SUSPEND_RESUME_CMD_SUPP	= (__force iwl_ucode_tlv_capa_t)92,
484*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP	= (__force iwl_ucode_tlv_capa_t)93,
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun 	/* set 3 */
487*4882a593Smuzhiyun 	IWL_UCODE_TLV_CAPA_MLME_OFFLOAD			= (__force iwl_ucode_tlv_capa_t)96,
488*4882a593Smuzhiyun 
489*4882a593Smuzhiyun 	NUM_IWL_UCODE_TLV_CAPA
490*4882a593Smuzhiyun #ifdef __CHECKER__
491*4882a593Smuzhiyun 		/* sparse says it cannot increment the previous enum member */
492*4882a593Smuzhiyun 		= 128
493*4882a593Smuzhiyun #endif
494*4882a593Smuzhiyun };
495*4882a593Smuzhiyun 
496*4882a593Smuzhiyun /* The default calibrate table size if not specified by firmware file */
497*4882a593Smuzhiyun #define IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE	18
498*4882a593Smuzhiyun #define IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE		19
499*4882a593Smuzhiyun #define IWL_MAX_PHY_CALIBRATE_TBL_SIZE			253
500*4882a593Smuzhiyun 
501*4882a593Smuzhiyun /* The default max probe length if not specified by the firmware file */
502*4882a593Smuzhiyun #define IWL_DEFAULT_MAX_PROBE_LENGTH	200
503*4882a593Smuzhiyun 
504*4882a593Smuzhiyun /*
505*4882a593Smuzhiyun  * For 16.0 uCode and above, there is no differentiation between sections,
506*4882a593Smuzhiyun  * just an offset to the HW address.
507*4882a593Smuzhiyun  */
508*4882a593Smuzhiyun #define CPU1_CPU2_SEPARATOR_SECTION	0xFFFFCCCC
509*4882a593Smuzhiyun #define PAGING_SEPARATOR_SECTION	0xAAAABBBB
510*4882a593Smuzhiyun 
511*4882a593Smuzhiyun /* uCode version contains 4 values: Major/Minor/API/Serial */
512*4882a593Smuzhiyun #define IWL_UCODE_MAJOR(ver)	(((ver) & 0xFF000000) >> 24)
513*4882a593Smuzhiyun #define IWL_UCODE_MINOR(ver)	(((ver) & 0x00FF0000) >> 16)
514*4882a593Smuzhiyun #define IWL_UCODE_API(ver)	(((ver) & 0x0000FF00) >> 8)
515*4882a593Smuzhiyun #define IWL_UCODE_SERIAL(ver)	((ver) & 0x000000FF)
516*4882a593Smuzhiyun 
517*4882a593Smuzhiyun /**
518*4882a593Smuzhiyun  * struct iwl_tlv_calib_ctrl - Calibration control struct.
519*4882a593Smuzhiyun  * Sent as part of the phy configuration command.
520*4882a593Smuzhiyun  * @flow_trigger: bitmap for which calibrations to perform according to
521*4882a593Smuzhiyun  *		flow triggers.
522*4882a593Smuzhiyun  * @event_trigger: bitmap for which calibrations to perform according to
523*4882a593Smuzhiyun  *		event triggers.
524*4882a593Smuzhiyun  */
525*4882a593Smuzhiyun struct iwl_tlv_calib_ctrl {
526*4882a593Smuzhiyun 	__le32 flow_trigger;
527*4882a593Smuzhiyun 	__le32 event_trigger;
528*4882a593Smuzhiyun } __packed;
529*4882a593Smuzhiyun 
530*4882a593Smuzhiyun enum iwl_fw_phy_cfg {
531*4882a593Smuzhiyun 	FW_PHY_CFG_RADIO_TYPE_POS = 0,
532*4882a593Smuzhiyun 	FW_PHY_CFG_RADIO_TYPE = 0x3 << FW_PHY_CFG_RADIO_TYPE_POS,
533*4882a593Smuzhiyun 	FW_PHY_CFG_RADIO_STEP_POS = 2,
534*4882a593Smuzhiyun 	FW_PHY_CFG_RADIO_STEP = 0x3 << FW_PHY_CFG_RADIO_STEP_POS,
535*4882a593Smuzhiyun 	FW_PHY_CFG_RADIO_DASH_POS = 4,
536*4882a593Smuzhiyun 	FW_PHY_CFG_RADIO_DASH = 0x3 << FW_PHY_CFG_RADIO_DASH_POS,
537*4882a593Smuzhiyun 	FW_PHY_CFG_TX_CHAIN_POS = 16,
538*4882a593Smuzhiyun 	FW_PHY_CFG_TX_CHAIN = 0xf << FW_PHY_CFG_TX_CHAIN_POS,
539*4882a593Smuzhiyun 	FW_PHY_CFG_RX_CHAIN_POS = 20,
540*4882a593Smuzhiyun 	FW_PHY_CFG_RX_CHAIN = 0xf << FW_PHY_CFG_RX_CHAIN_POS,
541*4882a593Smuzhiyun 	FW_PHY_CFG_CHAIN_SAD_POS = 23,
542*4882a593Smuzhiyun 	FW_PHY_CFG_CHAIN_SAD_ENABLED = 0x1 << FW_PHY_CFG_CHAIN_SAD_POS,
543*4882a593Smuzhiyun 	FW_PHY_CFG_CHAIN_SAD_ANT_A = 0x2 << FW_PHY_CFG_CHAIN_SAD_POS,
544*4882a593Smuzhiyun 	FW_PHY_CFG_CHAIN_SAD_ANT_B = 0x4 << FW_PHY_CFG_CHAIN_SAD_POS,
545*4882a593Smuzhiyun 	FW_PHY_CFG_SHARED_CLK = BIT(31),
546*4882a593Smuzhiyun };
547*4882a593Smuzhiyun 
548*4882a593Smuzhiyun #define IWL_UCODE_MAX_CS		1
549*4882a593Smuzhiyun 
550*4882a593Smuzhiyun /**
551*4882a593Smuzhiyun  * struct iwl_fw_cipher_scheme - a cipher scheme supported by FW.
552*4882a593Smuzhiyun  * @cipher: a cipher suite selector
553*4882a593Smuzhiyun  * @flags: cipher scheme flags (currently reserved for a future use)
554*4882a593Smuzhiyun  * @hdr_len: a size of MPDU security header
555*4882a593Smuzhiyun  * @pn_len: a size of PN
556*4882a593Smuzhiyun  * @pn_off: an offset of pn from the beginning of the security header
557*4882a593Smuzhiyun  * @key_idx_off: an offset of key index byte in the security header
558*4882a593Smuzhiyun  * @key_idx_mask: a bit mask of key_idx bits
559*4882a593Smuzhiyun  * @key_idx_shift: bit shift needed to get key_idx
560*4882a593Smuzhiyun  * @mic_len: mic length in bytes
561*4882a593Smuzhiyun  * @hw_cipher: a HW cipher index used in host commands
562*4882a593Smuzhiyun  */
563*4882a593Smuzhiyun struct iwl_fw_cipher_scheme {
564*4882a593Smuzhiyun 	__le32 cipher;
565*4882a593Smuzhiyun 	u8 flags;
566*4882a593Smuzhiyun 	u8 hdr_len;
567*4882a593Smuzhiyun 	u8 pn_len;
568*4882a593Smuzhiyun 	u8 pn_off;
569*4882a593Smuzhiyun 	u8 key_idx_off;
570*4882a593Smuzhiyun 	u8 key_idx_mask;
571*4882a593Smuzhiyun 	u8 key_idx_shift;
572*4882a593Smuzhiyun 	u8 mic_len;
573*4882a593Smuzhiyun 	u8 hw_cipher;
574*4882a593Smuzhiyun } __packed;
575*4882a593Smuzhiyun 
576*4882a593Smuzhiyun enum iwl_fw_dbg_reg_operator {
577*4882a593Smuzhiyun 	CSR_ASSIGN,
578*4882a593Smuzhiyun 	CSR_SETBIT,
579*4882a593Smuzhiyun 	CSR_CLEARBIT,
580*4882a593Smuzhiyun 
581*4882a593Smuzhiyun 	PRPH_ASSIGN,
582*4882a593Smuzhiyun 	PRPH_SETBIT,
583*4882a593Smuzhiyun 	PRPH_CLEARBIT,
584*4882a593Smuzhiyun 
585*4882a593Smuzhiyun 	INDIRECT_ASSIGN,
586*4882a593Smuzhiyun 	INDIRECT_SETBIT,
587*4882a593Smuzhiyun 	INDIRECT_CLEARBIT,
588*4882a593Smuzhiyun 
589*4882a593Smuzhiyun 	PRPH_BLOCKBIT,
590*4882a593Smuzhiyun };
591*4882a593Smuzhiyun 
592*4882a593Smuzhiyun /**
593*4882a593Smuzhiyun  * struct iwl_fw_dbg_reg_op - an operation on a register
594*4882a593Smuzhiyun  *
595*4882a593Smuzhiyun  * @op: &enum iwl_fw_dbg_reg_operator
596*4882a593Smuzhiyun  * @addr: offset of the register
597*4882a593Smuzhiyun  * @val: value
598*4882a593Smuzhiyun  */
599*4882a593Smuzhiyun struct iwl_fw_dbg_reg_op {
600*4882a593Smuzhiyun 	u8 op;
601*4882a593Smuzhiyun 	u8 reserved[3];
602*4882a593Smuzhiyun 	__le32 addr;
603*4882a593Smuzhiyun 	__le32 val;
604*4882a593Smuzhiyun } __packed;
605*4882a593Smuzhiyun 
606*4882a593Smuzhiyun /**
607*4882a593Smuzhiyun  * enum iwl_fw_dbg_monitor_mode - available monitor recording modes
608*4882a593Smuzhiyun  *
609*4882a593Smuzhiyun  * @SMEM_MODE: monitor stores the data in SMEM
610*4882a593Smuzhiyun  * @EXTERNAL_MODE: monitor stores the data in allocated DRAM
611*4882a593Smuzhiyun  * @MARBH_MODE: monitor stores the data in MARBH buffer
612*4882a593Smuzhiyun  * @MIPI_MODE: monitor outputs the data through the MIPI interface
613*4882a593Smuzhiyun  */
614*4882a593Smuzhiyun enum iwl_fw_dbg_monitor_mode {
615*4882a593Smuzhiyun 	SMEM_MODE = 0,
616*4882a593Smuzhiyun 	EXTERNAL_MODE = 1,
617*4882a593Smuzhiyun 	MARBH_MODE = 2,
618*4882a593Smuzhiyun 	MIPI_MODE = 3,
619*4882a593Smuzhiyun };
620*4882a593Smuzhiyun 
621*4882a593Smuzhiyun /**
622*4882a593Smuzhiyun  * struct iwl_fw_dbg_mem_seg_tlv - configures the debug data memory segments
623*4882a593Smuzhiyun  *
624*4882a593Smuzhiyun  * @data_type: the memory segment type to record
625*4882a593Smuzhiyun  * @ofs: the memory segment offset
626*4882a593Smuzhiyun  * @len: the memory segment length, in bytes
627*4882a593Smuzhiyun  *
628*4882a593Smuzhiyun  * This parses IWL_UCODE_TLV_FW_MEM_SEG
629*4882a593Smuzhiyun  */
630*4882a593Smuzhiyun struct iwl_fw_dbg_mem_seg_tlv {
631*4882a593Smuzhiyun 	__le32 data_type;
632*4882a593Smuzhiyun 	__le32 ofs;
633*4882a593Smuzhiyun 	__le32 len;
634*4882a593Smuzhiyun } __packed;
635*4882a593Smuzhiyun 
636*4882a593Smuzhiyun /**
637*4882a593Smuzhiyun  * struct iwl_fw_dbg_dest_tlv_v1 - configures the destination of the debug data
638*4882a593Smuzhiyun  *
639*4882a593Smuzhiyun  * @version: version of the TLV - currently 0
640*4882a593Smuzhiyun  * @monitor_mode: &enum iwl_fw_dbg_monitor_mode
641*4882a593Smuzhiyun  * @size_power: buffer size will be 2^(size_power + 11)
642*4882a593Smuzhiyun  * @base_reg: addr of the base addr register (PRPH)
643*4882a593Smuzhiyun  * @end_reg:  addr of the end addr register (PRPH)
644*4882a593Smuzhiyun  * @write_ptr_reg: the addr of the reg of the write pointer
645*4882a593Smuzhiyun  * @wrap_count: the addr of the reg of the wrap_count
646*4882a593Smuzhiyun  * @base_shift: shift right of the base addr reg
647*4882a593Smuzhiyun  * @end_shift: shift right of the end addr reg
648*4882a593Smuzhiyun  * @reg_ops: array of registers operations
649*4882a593Smuzhiyun  *
650*4882a593Smuzhiyun  * This parses IWL_UCODE_TLV_FW_DBG_DEST
651*4882a593Smuzhiyun  */
652*4882a593Smuzhiyun struct iwl_fw_dbg_dest_tlv_v1 {
653*4882a593Smuzhiyun 	u8 version;
654*4882a593Smuzhiyun 	u8 monitor_mode;
655*4882a593Smuzhiyun 	u8 size_power;
656*4882a593Smuzhiyun 	u8 reserved;
657*4882a593Smuzhiyun 	__le32 base_reg;
658*4882a593Smuzhiyun 	__le32 end_reg;
659*4882a593Smuzhiyun 	__le32 write_ptr_reg;
660*4882a593Smuzhiyun 	__le32 wrap_count;
661*4882a593Smuzhiyun 	u8 base_shift;
662*4882a593Smuzhiyun 	u8 end_shift;
663*4882a593Smuzhiyun 	struct iwl_fw_dbg_reg_op reg_ops[0];
664*4882a593Smuzhiyun } __packed;
665*4882a593Smuzhiyun 
666*4882a593Smuzhiyun /* Mask of the register for defining the LDBG MAC2SMEM buffer SMEM size */
667*4882a593Smuzhiyun #define IWL_LDBG_M2S_BUF_SIZE_MSK	0x0fff0000
668*4882a593Smuzhiyun /* Mask of the register for defining the LDBG MAC2SMEM SMEM base address */
669*4882a593Smuzhiyun #define IWL_LDBG_M2S_BUF_BA_MSK		0x00000fff
670*4882a593Smuzhiyun /* The smem buffer chunks are in units of 256 bits */
671*4882a593Smuzhiyun #define IWL_M2S_UNIT_SIZE			0x100
672*4882a593Smuzhiyun 
673*4882a593Smuzhiyun struct iwl_fw_dbg_dest_tlv {
674*4882a593Smuzhiyun 	u8 version;
675*4882a593Smuzhiyun 	u8 monitor_mode;
676*4882a593Smuzhiyun 	u8 size_power;
677*4882a593Smuzhiyun 	u8 reserved;
678*4882a593Smuzhiyun 	__le32 cfg_reg;
679*4882a593Smuzhiyun 	__le32 write_ptr_reg;
680*4882a593Smuzhiyun 	__le32 wrap_count;
681*4882a593Smuzhiyun 	u8 base_shift;
682*4882a593Smuzhiyun 	u8 size_shift;
683*4882a593Smuzhiyun 	struct iwl_fw_dbg_reg_op reg_ops[0];
684*4882a593Smuzhiyun } __packed;
685*4882a593Smuzhiyun 
686*4882a593Smuzhiyun struct iwl_fw_dbg_conf_hcmd {
687*4882a593Smuzhiyun 	u8 id;
688*4882a593Smuzhiyun 	u8 reserved;
689*4882a593Smuzhiyun 	__le16 len;
690*4882a593Smuzhiyun 	u8 data[0];
691*4882a593Smuzhiyun } __packed;
692*4882a593Smuzhiyun 
693*4882a593Smuzhiyun /**
694*4882a593Smuzhiyun  * enum iwl_fw_dbg_trigger_mode - triggers functionalities
695*4882a593Smuzhiyun  *
696*4882a593Smuzhiyun  * @IWL_FW_DBG_TRIGGER_START: when trigger occurs re-conf the dbg mechanism
697*4882a593Smuzhiyun  * @IWL_FW_DBG_TRIGGER_STOP: when trigger occurs pull the dbg data
698*4882a593Smuzhiyun  * @IWL_FW_DBG_TRIGGER_MONITOR_ONLY: when trigger occurs trigger is set to
699*4882a593Smuzhiyun  *	collect only monitor data
700*4882a593Smuzhiyun  */
701*4882a593Smuzhiyun enum iwl_fw_dbg_trigger_mode {
702*4882a593Smuzhiyun 	IWL_FW_DBG_TRIGGER_START = BIT(0),
703*4882a593Smuzhiyun 	IWL_FW_DBG_TRIGGER_STOP = BIT(1),
704*4882a593Smuzhiyun 	IWL_FW_DBG_TRIGGER_MONITOR_ONLY = BIT(2),
705*4882a593Smuzhiyun };
706*4882a593Smuzhiyun 
707*4882a593Smuzhiyun /**
708*4882a593Smuzhiyun  * enum iwl_fw_dbg_trigger_flags - the flags supported by wrt triggers
709*4882a593Smuzhiyun  * @IWL_FW_DBG_FORCE_RESTART: force a firmware restart
710*4882a593Smuzhiyun  */
711*4882a593Smuzhiyun enum iwl_fw_dbg_trigger_flags {
712*4882a593Smuzhiyun 	IWL_FW_DBG_FORCE_RESTART = BIT(0),
713*4882a593Smuzhiyun };
714*4882a593Smuzhiyun 
715*4882a593Smuzhiyun /**
716*4882a593Smuzhiyun  * enum iwl_fw_dbg_trigger_vif_type - define the VIF type for a trigger
717*4882a593Smuzhiyun  * @IWL_FW_DBG_CONF_VIF_ANY: any vif type
718*4882a593Smuzhiyun  * @IWL_FW_DBG_CONF_VIF_IBSS: IBSS mode
719*4882a593Smuzhiyun  * @IWL_FW_DBG_CONF_VIF_STATION: BSS mode
720*4882a593Smuzhiyun  * @IWL_FW_DBG_CONF_VIF_AP: AP mode
721*4882a593Smuzhiyun  * @IWL_FW_DBG_CONF_VIF_P2P_CLIENT: P2P Client mode
722*4882a593Smuzhiyun  * @IWL_FW_DBG_CONF_VIF_P2P_GO: P2P GO mode
723*4882a593Smuzhiyun  * @IWL_FW_DBG_CONF_VIF_P2P_DEVICE: P2P device
724*4882a593Smuzhiyun  */
725*4882a593Smuzhiyun enum iwl_fw_dbg_trigger_vif_type {
726*4882a593Smuzhiyun 	IWL_FW_DBG_CONF_VIF_ANY = NL80211_IFTYPE_UNSPECIFIED,
727*4882a593Smuzhiyun 	IWL_FW_DBG_CONF_VIF_IBSS = NL80211_IFTYPE_ADHOC,
728*4882a593Smuzhiyun 	IWL_FW_DBG_CONF_VIF_STATION = NL80211_IFTYPE_STATION,
729*4882a593Smuzhiyun 	IWL_FW_DBG_CONF_VIF_AP = NL80211_IFTYPE_AP,
730*4882a593Smuzhiyun 	IWL_FW_DBG_CONF_VIF_P2P_CLIENT = NL80211_IFTYPE_P2P_CLIENT,
731*4882a593Smuzhiyun 	IWL_FW_DBG_CONF_VIF_P2P_GO = NL80211_IFTYPE_P2P_GO,
732*4882a593Smuzhiyun 	IWL_FW_DBG_CONF_VIF_P2P_DEVICE = NL80211_IFTYPE_P2P_DEVICE,
733*4882a593Smuzhiyun };
734*4882a593Smuzhiyun 
735*4882a593Smuzhiyun /**
736*4882a593Smuzhiyun  * struct iwl_fw_dbg_trigger_tlv - a TLV that describes the trigger
737*4882a593Smuzhiyun  * @id: &enum iwl_fw_dbg_trigger
738*4882a593Smuzhiyun  * @vif_type: &enum iwl_fw_dbg_trigger_vif_type
739*4882a593Smuzhiyun  * @stop_conf_ids: bitmap of configurations this trigger relates to.
740*4882a593Smuzhiyun  *	if the mode is %IWL_FW_DBG_TRIGGER_STOP, then if the bit corresponding
741*4882a593Smuzhiyun  *	to the currently running configuration is set, the data should be
742*4882a593Smuzhiyun  *	collected.
743*4882a593Smuzhiyun  * @stop_delay: how many milliseconds to wait before collecting the data
744*4882a593Smuzhiyun  *	after the STOP trigger fires.
745*4882a593Smuzhiyun  * @mode: &enum iwl_fw_dbg_trigger_mode - can be stop / start of both
746*4882a593Smuzhiyun  * @start_conf_id: if mode is %IWL_FW_DBG_TRIGGER_START, this defines what
747*4882a593Smuzhiyun  *	configuration should be applied when the triggers kicks in.
748*4882a593Smuzhiyun  * @occurrences: number of occurrences. 0 means the trigger will never fire.
749*4882a593Smuzhiyun  * @trig_dis_ms: the time, in milliseconds, after an occurrence of this
750*4882a593Smuzhiyun  *	trigger in which another occurrence should be ignored.
751*4882a593Smuzhiyun  * @flags: &enum iwl_fw_dbg_trigger_flags
752*4882a593Smuzhiyun  */
753*4882a593Smuzhiyun struct iwl_fw_dbg_trigger_tlv {
754*4882a593Smuzhiyun 	__le32 id;
755*4882a593Smuzhiyun 	__le32 vif_type;
756*4882a593Smuzhiyun 	__le32 stop_conf_ids;
757*4882a593Smuzhiyun 	__le32 stop_delay;
758*4882a593Smuzhiyun 	u8 mode;
759*4882a593Smuzhiyun 	u8 start_conf_id;
760*4882a593Smuzhiyun 	__le16 occurrences;
761*4882a593Smuzhiyun 	__le16 trig_dis_ms;
762*4882a593Smuzhiyun 	u8 flags;
763*4882a593Smuzhiyun 	u8 reserved[5];
764*4882a593Smuzhiyun 
765*4882a593Smuzhiyun 	u8 data[0];
766*4882a593Smuzhiyun } __packed;
767*4882a593Smuzhiyun 
768*4882a593Smuzhiyun #define FW_DBG_START_FROM_ALIVE	0
769*4882a593Smuzhiyun #define FW_DBG_CONF_MAX		32
770*4882a593Smuzhiyun #define FW_DBG_INVALID		0xff
771*4882a593Smuzhiyun 
772*4882a593Smuzhiyun /**
773*4882a593Smuzhiyun  * struct iwl_fw_dbg_trigger_missed_bcon - configures trigger for missed beacons
774*4882a593Smuzhiyun  * @stop_consec_missed_bcon: stop recording if threshold is crossed.
775*4882a593Smuzhiyun  * @stop_consec_missed_bcon_since_rx: stop recording if threshold is crossed.
776*4882a593Smuzhiyun  * @start_consec_missed_bcon: start recording if threshold is crossed.
777*4882a593Smuzhiyun  * @start_consec_missed_bcon_since_rx: start recording if threshold is crossed.
778*4882a593Smuzhiyun  * @reserved1: reserved
779*4882a593Smuzhiyun  * @reserved2: reserved
780*4882a593Smuzhiyun  */
781*4882a593Smuzhiyun struct iwl_fw_dbg_trigger_missed_bcon {
782*4882a593Smuzhiyun 	__le32 stop_consec_missed_bcon;
783*4882a593Smuzhiyun 	__le32 stop_consec_missed_bcon_since_rx;
784*4882a593Smuzhiyun 	__le32 reserved2[2];
785*4882a593Smuzhiyun 	__le32 start_consec_missed_bcon;
786*4882a593Smuzhiyun 	__le32 start_consec_missed_bcon_since_rx;
787*4882a593Smuzhiyun 	__le32 reserved1[2];
788*4882a593Smuzhiyun } __packed;
789*4882a593Smuzhiyun 
790*4882a593Smuzhiyun /**
791*4882a593Smuzhiyun  * struct iwl_fw_dbg_trigger_cmd - configures trigger for messages from FW.
792*4882a593Smuzhiyun  * cmds: the list of commands to trigger the collection on
793*4882a593Smuzhiyun  */
794*4882a593Smuzhiyun struct iwl_fw_dbg_trigger_cmd {
795*4882a593Smuzhiyun 	struct cmd {
796*4882a593Smuzhiyun 		u8 cmd_id;
797*4882a593Smuzhiyun 		u8 group_id;
798*4882a593Smuzhiyun 	} __packed cmds[16];
799*4882a593Smuzhiyun } __packed;
800*4882a593Smuzhiyun 
801*4882a593Smuzhiyun /**
802*4882a593Smuzhiyun  * iwl_fw_dbg_trigger_stats - configures trigger for statistics
803*4882a593Smuzhiyun  * @stop_offset: the offset of the value to be monitored
804*4882a593Smuzhiyun  * @stop_threshold: the threshold above which to collect
805*4882a593Smuzhiyun  * @start_offset: the offset of the value to be monitored
806*4882a593Smuzhiyun  * @start_threshold: the threshold above which to start recording
807*4882a593Smuzhiyun  */
808*4882a593Smuzhiyun struct iwl_fw_dbg_trigger_stats {
809*4882a593Smuzhiyun 	__le32 stop_offset;
810*4882a593Smuzhiyun 	__le32 stop_threshold;
811*4882a593Smuzhiyun 	__le32 start_offset;
812*4882a593Smuzhiyun 	__le32 start_threshold;
813*4882a593Smuzhiyun } __packed;
814*4882a593Smuzhiyun 
815*4882a593Smuzhiyun /**
816*4882a593Smuzhiyun  * struct iwl_fw_dbg_trigger_low_rssi - trigger for low beacon RSSI
817*4882a593Smuzhiyun  * @rssi: RSSI value to trigger at
818*4882a593Smuzhiyun  */
819*4882a593Smuzhiyun struct iwl_fw_dbg_trigger_low_rssi {
820*4882a593Smuzhiyun 	__le32 rssi;
821*4882a593Smuzhiyun } __packed;
822*4882a593Smuzhiyun 
823*4882a593Smuzhiyun /**
824*4882a593Smuzhiyun  * struct iwl_fw_dbg_trigger_mlme - configures trigger for mlme events
825*4882a593Smuzhiyun  * @stop_auth_denied: number of denied authentication to collect
826*4882a593Smuzhiyun  * @stop_auth_timeout: number of authentication timeout to collect
827*4882a593Smuzhiyun  * @stop_rx_deauth: number of Rx deauth before to collect
828*4882a593Smuzhiyun  * @stop_tx_deauth: number of Tx deauth before to collect
829*4882a593Smuzhiyun  * @stop_assoc_denied: number of denied association to collect
830*4882a593Smuzhiyun  * @stop_assoc_timeout: number of association timeout to collect
831*4882a593Smuzhiyun  * @stop_connection_loss: number of connection loss to collect
832*4882a593Smuzhiyun  * @start_auth_denied: number of denied authentication to start recording
833*4882a593Smuzhiyun  * @start_auth_timeout: number of authentication timeout to start recording
834*4882a593Smuzhiyun  * @start_rx_deauth: number of Rx deauth to start recording
835*4882a593Smuzhiyun  * @start_tx_deauth: number of Tx deauth to start recording
836*4882a593Smuzhiyun  * @start_assoc_denied: number of denied association to start recording
837*4882a593Smuzhiyun  * @start_assoc_timeout: number of association timeout to start recording
838*4882a593Smuzhiyun  * @start_connection_loss: number of connection loss to start recording
839*4882a593Smuzhiyun  */
840*4882a593Smuzhiyun struct iwl_fw_dbg_trigger_mlme {
841*4882a593Smuzhiyun 	u8 stop_auth_denied;
842*4882a593Smuzhiyun 	u8 stop_auth_timeout;
843*4882a593Smuzhiyun 	u8 stop_rx_deauth;
844*4882a593Smuzhiyun 	u8 stop_tx_deauth;
845*4882a593Smuzhiyun 
846*4882a593Smuzhiyun 	u8 stop_assoc_denied;
847*4882a593Smuzhiyun 	u8 stop_assoc_timeout;
848*4882a593Smuzhiyun 	u8 stop_connection_loss;
849*4882a593Smuzhiyun 	u8 reserved;
850*4882a593Smuzhiyun 
851*4882a593Smuzhiyun 	u8 start_auth_denied;
852*4882a593Smuzhiyun 	u8 start_auth_timeout;
853*4882a593Smuzhiyun 	u8 start_rx_deauth;
854*4882a593Smuzhiyun 	u8 start_tx_deauth;
855*4882a593Smuzhiyun 
856*4882a593Smuzhiyun 	u8 start_assoc_denied;
857*4882a593Smuzhiyun 	u8 start_assoc_timeout;
858*4882a593Smuzhiyun 	u8 start_connection_loss;
859*4882a593Smuzhiyun 	u8 reserved2;
860*4882a593Smuzhiyun } __packed;
861*4882a593Smuzhiyun 
862*4882a593Smuzhiyun /**
863*4882a593Smuzhiyun  * struct iwl_fw_dbg_trigger_txq_timer - configures the Tx queue's timer
864*4882a593Smuzhiyun  * @command_queue: timeout for the command queue in ms
865*4882a593Smuzhiyun  * @bss: timeout for the queues of a BSS (except for TDLS queues) in ms
866*4882a593Smuzhiyun  * @softap: timeout for the queues of a softAP in ms
867*4882a593Smuzhiyun  * @p2p_go: timeout for the queues of a P2P GO in ms
868*4882a593Smuzhiyun  * @p2p_client: timeout for the queues of a P2P client in ms
869*4882a593Smuzhiyun  * @p2p_device: timeout for the queues of a P2P device in ms
870*4882a593Smuzhiyun  * @ibss: timeout for the queues of an IBSS in ms
871*4882a593Smuzhiyun  * @tdls: timeout for the queues of a TDLS station in ms
872*4882a593Smuzhiyun  */
873*4882a593Smuzhiyun struct iwl_fw_dbg_trigger_txq_timer {
874*4882a593Smuzhiyun 	__le32 command_queue;
875*4882a593Smuzhiyun 	__le32 bss;
876*4882a593Smuzhiyun 	__le32 softap;
877*4882a593Smuzhiyun 	__le32 p2p_go;
878*4882a593Smuzhiyun 	__le32 p2p_client;
879*4882a593Smuzhiyun 	__le32 p2p_device;
880*4882a593Smuzhiyun 	__le32 ibss;
881*4882a593Smuzhiyun 	__le32 tdls;
882*4882a593Smuzhiyun 	__le32 reserved[4];
883*4882a593Smuzhiyun } __packed;
884*4882a593Smuzhiyun 
885*4882a593Smuzhiyun /**
886*4882a593Smuzhiyun  * struct iwl_fw_dbg_trigger_time_event - configures a time event trigger
887*4882a593Smuzhiyun  * time_Events: a list of tuples <id, action_bitmap>. The driver will issue a
888*4882a593Smuzhiyun  *	trigger each time a time event notification that relates to time event
889*4882a593Smuzhiyun  *	id with one of the actions in the bitmap is received and
890*4882a593Smuzhiyun  *	BIT(notif->status) is set in status_bitmap.
891*4882a593Smuzhiyun  *
892*4882a593Smuzhiyun  */
893*4882a593Smuzhiyun struct iwl_fw_dbg_trigger_time_event {
894*4882a593Smuzhiyun 	struct {
895*4882a593Smuzhiyun 		__le32 id;
896*4882a593Smuzhiyun 		__le32 action_bitmap;
897*4882a593Smuzhiyun 		__le32 status_bitmap;
898*4882a593Smuzhiyun 	} __packed time_events[16];
899*4882a593Smuzhiyun } __packed;
900*4882a593Smuzhiyun 
901*4882a593Smuzhiyun /**
902*4882a593Smuzhiyun  * struct iwl_fw_dbg_trigger_ba - configures BlockAck related trigger
903*4882a593Smuzhiyun  * rx_ba_start: tid bitmap to configure on what tid the trigger should occur
904*4882a593Smuzhiyun  *	when an Rx BlockAck session is started.
905*4882a593Smuzhiyun  * rx_ba_stop: tid bitmap to configure on what tid the trigger should occur
906*4882a593Smuzhiyun  *	when an Rx BlockAck session is stopped.
907*4882a593Smuzhiyun  * tx_ba_start: tid bitmap to configure on what tid the trigger should occur
908*4882a593Smuzhiyun  *	when a Tx BlockAck session is started.
909*4882a593Smuzhiyun  * tx_ba_stop: tid bitmap to configure on what tid the trigger should occur
910*4882a593Smuzhiyun  *	when a Tx BlockAck session is stopped.
911*4882a593Smuzhiyun  * rx_bar: tid bitmap to configure on what tid the trigger should occur
912*4882a593Smuzhiyun  *	when a BAR is received (for a Tx BlockAck session).
913*4882a593Smuzhiyun  * tx_bar: tid bitmap to configure on what tid the trigger should occur
914*4882a593Smuzhiyun  *	when a BAR is send (for an Rx BlocAck session).
915*4882a593Smuzhiyun  * frame_timeout: tid bitmap to configure on what tid the trigger should occur
916*4882a593Smuzhiyun  *	when a frame times out in the reodering buffer.
917*4882a593Smuzhiyun  */
918*4882a593Smuzhiyun struct iwl_fw_dbg_trigger_ba {
919*4882a593Smuzhiyun 	__le16 rx_ba_start;
920*4882a593Smuzhiyun 	__le16 rx_ba_stop;
921*4882a593Smuzhiyun 	__le16 tx_ba_start;
922*4882a593Smuzhiyun 	__le16 tx_ba_stop;
923*4882a593Smuzhiyun 	__le16 rx_bar;
924*4882a593Smuzhiyun 	__le16 tx_bar;
925*4882a593Smuzhiyun 	__le16 frame_timeout;
926*4882a593Smuzhiyun } __packed;
927*4882a593Smuzhiyun 
928*4882a593Smuzhiyun /**
929*4882a593Smuzhiyun  * struct iwl_fw_dbg_trigger_tdls - configures trigger for TDLS events.
930*4882a593Smuzhiyun  * @action_bitmap: the TDLS action to trigger the collection upon
931*4882a593Smuzhiyun  * @peer_mode: trigger on specific peer or all
932*4882a593Smuzhiyun  * @peer: the TDLS peer to trigger the collection on
933*4882a593Smuzhiyun  */
934*4882a593Smuzhiyun struct iwl_fw_dbg_trigger_tdls {
935*4882a593Smuzhiyun 	u8 action_bitmap;
936*4882a593Smuzhiyun 	u8 peer_mode;
937*4882a593Smuzhiyun 	u8 peer[ETH_ALEN];
938*4882a593Smuzhiyun 	u8 reserved[4];
939*4882a593Smuzhiyun } __packed;
940*4882a593Smuzhiyun 
941*4882a593Smuzhiyun /**
942*4882a593Smuzhiyun  * struct iwl_fw_dbg_trigger_tx_status - configures trigger for tx response
943*4882a593Smuzhiyun  *  status.
944*4882a593Smuzhiyun  * @statuses: the list of statuses to trigger the collection on
945*4882a593Smuzhiyun  */
946*4882a593Smuzhiyun struct iwl_fw_dbg_trigger_tx_status {
947*4882a593Smuzhiyun 	struct tx_status {
948*4882a593Smuzhiyun 		u8 status;
949*4882a593Smuzhiyun 		u8 reserved[3];
950*4882a593Smuzhiyun 	} __packed statuses[16];
951*4882a593Smuzhiyun 	__le32 reserved[2];
952*4882a593Smuzhiyun } __packed;
953*4882a593Smuzhiyun 
954*4882a593Smuzhiyun /**
955*4882a593Smuzhiyun  * struct iwl_fw_dbg_conf_tlv - a TLV that describes a debug configuration.
956*4882a593Smuzhiyun  * @id: conf id
957*4882a593Smuzhiyun  * @usniffer: should the uSniffer image be used
958*4882a593Smuzhiyun  * @num_of_hcmds: how many HCMDs to send are present here
959*4882a593Smuzhiyun  * @hcmd: a variable length host command to be sent to apply the configuration.
960*4882a593Smuzhiyun  *	If there is more than one HCMD to send, they will appear one after the
961*4882a593Smuzhiyun  *	other and be sent in the order that they appear in.
962*4882a593Smuzhiyun  * This parses IWL_UCODE_TLV_FW_DBG_CONF. The user can add up-to
963*4882a593Smuzhiyun  * %FW_DBG_CONF_MAX configuration per run.
964*4882a593Smuzhiyun  */
965*4882a593Smuzhiyun struct iwl_fw_dbg_conf_tlv {
966*4882a593Smuzhiyun 	u8 id;
967*4882a593Smuzhiyun 	u8 usniffer;
968*4882a593Smuzhiyun 	u8 reserved;
969*4882a593Smuzhiyun 	u8 num_of_hcmds;
970*4882a593Smuzhiyun 	struct iwl_fw_dbg_conf_hcmd hcmd;
971*4882a593Smuzhiyun } __packed;
972*4882a593Smuzhiyun 
973*4882a593Smuzhiyun #define IWL_FW_CMD_VER_UNKNOWN 99
974*4882a593Smuzhiyun 
975*4882a593Smuzhiyun /**
976*4882a593Smuzhiyun  * struct iwl_fw_cmd_version - firmware command version entry
977*4882a593Smuzhiyun  * @cmd: command ID
978*4882a593Smuzhiyun  * @group: group ID
979*4882a593Smuzhiyun  * @cmd_ver: command version
980*4882a593Smuzhiyun  * @notif_ver: notification version
981*4882a593Smuzhiyun  */
982*4882a593Smuzhiyun struct iwl_fw_cmd_version {
983*4882a593Smuzhiyun 	u8 cmd;
984*4882a593Smuzhiyun 	u8 group;
985*4882a593Smuzhiyun 	u8 cmd_ver;
986*4882a593Smuzhiyun 	u8 notif_ver;
987*4882a593Smuzhiyun } __packed;
988*4882a593Smuzhiyun 
_iwl_tlv_array_len(const struct iwl_ucode_tlv * tlv,size_t fixed_size,size_t var_size)989*4882a593Smuzhiyun static inline size_t _iwl_tlv_array_len(const struct iwl_ucode_tlv *tlv,
990*4882a593Smuzhiyun 					size_t fixed_size, size_t var_size)
991*4882a593Smuzhiyun {
992*4882a593Smuzhiyun 	size_t var_len = le32_to_cpu(tlv->length) - fixed_size;
993*4882a593Smuzhiyun 
994*4882a593Smuzhiyun 	if (WARN_ON(var_len % var_size))
995*4882a593Smuzhiyun 		return 0;
996*4882a593Smuzhiyun 
997*4882a593Smuzhiyun 	return var_len / var_size;
998*4882a593Smuzhiyun }
999*4882a593Smuzhiyun 
1000*4882a593Smuzhiyun #define iwl_tlv_array_len(_tlv_ptr, _struct_ptr, _memb)			\
1001*4882a593Smuzhiyun 	_iwl_tlv_array_len((_tlv_ptr), sizeof(*(_struct_ptr)),		\
1002*4882a593Smuzhiyun 			   sizeof(_struct_ptr->_memb[0]))
1003*4882a593Smuzhiyun 
1004*4882a593Smuzhiyun #endif  /* __iwl_fw_file_h__ */
1005