xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/intel/iwlwifi/dvm/devices.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /******************************************************************************
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
5*4882a593Smuzhiyun  * Copyright (C) 2019 Intel Corporation
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Contact Information:
8*4882a593Smuzhiyun  *  Intel Linux Wireless <linuxwifi@intel.com>
9*4882a593Smuzhiyun  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  *****************************************************************************/
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include <linux/units.h>
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun /*
16*4882a593Smuzhiyun  * DVM device-specific data & functions
17*4882a593Smuzhiyun  */
18*4882a593Smuzhiyun #include "iwl-io.h"
19*4882a593Smuzhiyun #include "iwl-prph.h"
20*4882a593Smuzhiyun #include "iwl-eeprom-parse.h"
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #include "agn.h"
23*4882a593Smuzhiyun #include "dev.h"
24*4882a593Smuzhiyun #include "commands.h"
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun /*
28*4882a593Smuzhiyun  * 1000 series
29*4882a593Smuzhiyun  * ===========
30*4882a593Smuzhiyun  */
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun /*
33*4882a593Smuzhiyun  * For 1000, use advance thermal throttling critical temperature threshold,
34*4882a593Smuzhiyun  * but legacy thermal management implementation for now.
35*4882a593Smuzhiyun  * This is for the reason of 1000 uCode using advance thermal throttling API
36*4882a593Smuzhiyun  * but not implement ct_kill_exit based on ct_kill exit temperature
37*4882a593Smuzhiyun  * so the thermal throttling will still based on legacy thermal throttling
38*4882a593Smuzhiyun  * management.
39*4882a593Smuzhiyun  * The code here need to be modified once 1000 uCode has the advanced thermal
40*4882a593Smuzhiyun  * throttling algorithm in place
41*4882a593Smuzhiyun  */
iwl1000_set_ct_threshold(struct iwl_priv * priv)42*4882a593Smuzhiyun static void iwl1000_set_ct_threshold(struct iwl_priv *priv)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun 	/* want Celsius */
45*4882a593Smuzhiyun 	priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY;
46*4882a593Smuzhiyun 	priv->hw_params.ct_kill_exit_threshold = CT_KILL_EXIT_THRESHOLD;
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun /* NIC configuration for 1000 series */
iwl1000_nic_config(struct iwl_priv * priv)50*4882a593Smuzhiyun static void iwl1000_nic_config(struct iwl_priv *priv)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun 	/* Setting digital SVR for 1000 card to 1.32V */
53*4882a593Smuzhiyun 	/* locking is acquired in iwl_set_bits_mask_prph() function */
54*4882a593Smuzhiyun 	iwl_set_bits_mask_prph(priv->trans, APMG_DIGITAL_SVR_REG,
55*4882a593Smuzhiyun 				APMG_SVR_DIGITAL_VOLTAGE_1_32,
56*4882a593Smuzhiyun 				~APMG_SVR_VOLTAGE_CONFIG_BIT_MSK);
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun /**
60*4882a593Smuzhiyun  * iwl_beacon_time_mask_low - mask of lower 32 bit of beacon time
61*4882a593Smuzhiyun  * @priv: pointer to iwl_priv data structure
62*4882a593Smuzhiyun  * @tsf_bits: number of bits need to shift for masking)
63*4882a593Smuzhiyun  */
iwl_beacon_time_mask_low(struct iwl_priv * priv,u16 tsf_bits)64*4882a593Smuzhiyun static inline u32 iwl_beacon_time_mask_low(struct iwl_priv *priv,
65*4882a593Smuzhiyun 					   u16 tsf_bits)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun 	return (1 << tsf_bits) - 1;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun /**
71*4882a593Smuzhiyun  * iwl_beacon_time_mask_high - mask of higher 32 bit of beacon time
72*4882a593Smuzhiyun  * @priv: pointer to iwl_priv data structure
73*4882a593Smuzhiyun  * @tsf_bits: number of bits need to shift for masking)
74*4882a593Smuzhiyun  */
iwl_beacon_time_mask_high(struct iwl_priv * priv,u16 tsf_bits)75*4882a593Smuzhiyun static inline u32 iwl_beacon_time_mask_high(struct iwl_priv *priv,
76*4882a593Smuzhiyun 					    u16 tsf_bits)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun 	return ((1 << (32 - tsf_bits)) - 1) << tsf_bits;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun /*
82*4882a593Smuzhiyun  * extended beacon time format
83*4882a593Smuzhiyun  * time in usec will be changed into a 32-bit value in extended:internal format
84*4882a593Smuzhiyun  * the extended part is the beacon counts
85*4882a593Smuzhiyun  * the internal part is the time in usec within one beacon interval
86*4882a593Smuzhiyun  */
iwl_usecs_to_beacons(struct iwl_priv * priv,u32 usec,u32 beacon_interval)87*4882a593Smuzhiyun static u32 iwl_usecs_to_beacons(struct iwl_priv *priv, u32 usec,
88*4882a593Smuzhiyun 				u32 beacon_interval)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun 	u32 quot;
91*4882a593Smuzhiyun 	u32 rem;
92*4882a593Smuzhiyun 	u32 interval = beacon_interval * TIME_UNIT;
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	if (!interval || !usec)
95*4882a593Smuzhiyun 		return 0;
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	quot = (usec / interval) &
98*4882a593Smuzhiyun 		(iwl_beacon_time_mask_high(priv, IWLAGN_EXT_BEACON_TIME_POS) >>
99*4882a593Smuzhiyun 		IWLAGN_EXT_BEACON_TIME_POS);
100*4882a593Smuzhiyun 	rem = (usec % interval) & iwl_beacon_time_mask_low(priv,
101*4882a593Smuzhiyun 				   IWLAGN_EXT_BEACON_TIME_POS);
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun 	return (quot << IWLAGN_EXT_BEACON_TIME_POS) + rem;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun /* base is usually what we get from ucode with each received frame,
107*4882a593Smuzhiyun  * the same as HW timer counter counting down
108*4882a593Smuzhiyun  */
iwl_add_beacon_time(struct iwl_priv * priv,u32 base,u32 addon,u32 beacon_interval)109*4882a593Smuzhiyun static __le32 iwl_add_beacon_time(struct iwl_priv *priv, u32 base,
110*4882a593Smuzhiyun 			   u32 addon, u32 beacon_interval)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun 	u32 base_low = base & iwl_beacon_time_mask_low(priv,
113*4882a593Smuzhiyun 				IWLAGN_EXT_BEACON_TIME_POS);
114*4882a593Smuzhiyun 	u32 addon_low = addon & iwl_beacon_time_mask_low(priv,
115*4882a593Smuzhiyun 				IWLAGN_EXT_BEACON_TIME_POS);
116*4882a593Smuzhiyun 	u32 interval = beacon_interval * TIME_UNIT;
117*4882a593Smuzhiyun 	u32 res = (base & iwl_beacon_time_mask_high(priv,
118*4882a593Smuzhiyun 				IWLAGN_EXT_BEACON_TIME_POS)) +
119*4882a593Smuzhiyun 				(addon & iwl_beacon_time_mask_high(priv,
120*4882a593Smuzhiyun 				IWLAGN_EXT_BEACON_TIME_POS));
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	if (base_low > addon_low)
123*4882a593Smuzhiyun 		res += base_low - addon_low;
124*4882a593Smuzhiyun 	else if (base_low < addon_low) {
125*4882a593Smuzhiyun 		res += interval + base_low - addon_low;
126*4882a593Smuzhiyun 		res += (1 << IWLAGN_EXT_BEACON_TIME_POS);
127*4882a593Smuzhiyun 	} else
128*4882a593Smuzhiyun 		res += (1 << IWLAGN_EXT_BEACON_TIME_POS);
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	return cpu_to_le32(res);
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun static const struct iwl_sensitivity_ranges iwl1000_sensitivity = {
134*4882a593Smuzhiyun 	.min_nrg_cck = 95,
135*4882a593Smuzhiyun 	.auto_corr_min_ofdm = 90,
136*4882a593Smuzhiyun 	.auto_corr_min_ofdm_mrc = 170,
137*4882a593Smuzhiyun 	.auto_corr_min_ofdm_x1 = 120,
138*4882a593Smuzhiyun 	.auto_corr_min_ofdm_mrc_x1 = 240,
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	.auto_corr_max_ofdm = 120,
141*4882a593Smuzhiyun 	.auto_corr_max_ofdm_mrc = 210,
142*4882a593Smuzhiyun 	.auto_corr_max_ofdm_x1 = 155,
143*4882a593Smuzhiyun 	.auto_corr_max_ofdm_mrc_x1 = 290,
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 	.auto_corr_min_cck = 125,
146*4882a593Smuzhiyun 	.auto_corr_max_cck = 200,
147*4882a593Smuzhiyun 	.auto_corr_min_cck_mrc = 170,
148*4882a593Smuzhiyun 	.auto_corr_max_cck_mrc = 400,
149*4882a593Smuzhiyun 	.nrg_th_cck = 95,
150*4882a593Smuzhiyun 	.nrg_th_ofdm = 95,
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	.barker_corr_th_min = 190,
153*4882a593Smuzhiyun 	.barker_corr_th_min_mrc = 390,
154*4882a593Smuzhiyun 	.nrg_th_cca = 62,
155*4882a593Smuzhiyun };
156*4882a593Smuzhiyun 
iwl1000_hw_set_hw_params(struct iwl_priv * priv)157*4882a593Smuzhiyun static void iwl1000_hw_set_hw_params(struct iwl_priv *priv)
158*4882a593Smuzhiyun {
159*4882a593Smuzhiyun 	iwl1000_set_ct_threshold(priv);
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	/* Set initial sensitivity parameters */
162*4882a593Smuzhiyun 	priv->hw_params.sens = &iwl1000_sensitivity;
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun const struct iwl_dvm_cfg iwl_dvm_1000_cfg = {
166*4882a593Smuzhiyun 	.set_hw_params = iwl1000_hw_set_hw_params,
167*4882a593Smuzhiyun 	.nic_config = iwl1000_nic_config,
168*4882a593Smuzhiyun 	.temperature = iwlagn_temperature,
169*4882a593Smuzhiyun 	.support_ct_kill_exit = true,
170*4882a593Smuzhiyun 	.plcp_delta_threshold = IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF,
171*4882a593Smuzhiyun 	.chain_noise_scale = 1000,
172*4882a593Smuzhiyun };
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun /*
176*4882a593Smuzhiyun  * 2000 series
177*4882a593Smuzhiyun  * ===========
178*4882a593Smuzhiyun  */
179*4882a593Smuzhiyun 
iwl2000_set_ct_threshold(struct iwl_priv * priv)180*4882a593Smuzhiyun static void iwl2000_set_ct_threshold(struct iwl_priv *priv)
181*4882a593Smuzhiyun {
182*4882a593Smuzhiyun 	/* want Celsius */
183*4882a593Smuzhiyun 	priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
184*4882a593Smuzhiyun 	priv->hw_params.ct_kill_exit_threshold = CT_KILL_EXIT_THRESHOLD;
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun /* NIC configuration for 2000 series */
iwl2000_nic_config(struct iwl_priv * priv)188*4882a593Smuzhiyun static void iwl2000_nic_config(struct iwl_priv *priv)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun 	iwl_set_bit(priv->trans, CSR_GP_DRIVER_REG,
191*4882a593Smuzhiyun 		    CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER);
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun static const struct iwl_sensitivity_ranges iwl2000_sensitivity = {
195*4882a593Smuzhiyun 	.min_nrg_cck = 97,
196*4882a593Smuzhiyun 	.auto_corr_min_ofdm = 80,
197*4882a593Smuzhiyun 	.auto_corr_min_ofdm_mrc = 128,
198*4882a593Smuzhiyun 	.auto_corr_min_ofdm_x1 = 105,
199*4882a593Smuzhiyun 	.auto_corr_min_ofdm_mrc_x1 = 192,
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun 	.auto_corr_max_ofdm = 145,
202*4882a593Smuzhiyun 	.auto_corr_max_ofdm_mrc = 232,
203*4882a593Smuzhiyun 	.auto_corr_max_ofdm_x1 = 110,
204*4882a593Smuzhiyun 	.auto_corr_max_ofdm_mrc_x1 = 232,
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun 	.auto_corr_min_cck = 125,
207*4882a593Smuzhiyun 	.auto_corr_max_cck = 175,
208*4882a593Smuzhiyun 	.auto_corr_min_cck_mrc = 160,
209*4882a593Smuzhiyun 	.auto_corr_max_cck_mrc = 310,
210*4882a593Smuzhiyun 	.nrg_th_cck = 97,
211*4882a593Smuzhiyun 	.nrg_th_ofdm = 100,
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun 	.barker_corr_th_min = 190,
214*4882a593Smuzhiyun 	.barker_corr_th_min_mrc = 390,
215*4882a593Smuzhiyun 	.nrg_th_cca = 62,
216*4882a593Smuzhiyun };
217*4882a593Smuzhiyun 
iwl2000_hw_set_hw_params(struct iwl_priv * priv)218*4882a593Smuzhiyun static void iwl2000_hw_set_hw_params(struct iwl_priv *priv)
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun 	iwl2000_set_ct_threshold(priv);
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	/* Set initial sensitivity parameters */
223*4882a593Smuzhiyun 	priv->hw_params.sens = &iwl2000_sensitivity;
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun const struct iwl_dvm_cfg iwl_dvm_2000_cfg = {
227*4882a593Smuzhiyun 	.set_hw_params = iwl2000_hw_set_hw_params,
228*4882a593Smuzhiyun 	.nic_config = iwl2000_nic_config,
229*4882a593Smuzhiyun 	.temperature = iwlagn_temperature,
230*4882a593Smuzhiyun 	.adv_thermal_throttle = true,
231*4882a593Smuzhiyun 	.support_ct_kill_exit = true,
232*4882a593Smuzhiyun 	.plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
233*4882a593Smuzhiyun 	.chain_noise_scale = 1000,
234*4882a593Smuzhiyun 	.hd_v2 = true,
235*4882a593Smuzhiyun 	.need_temp_offset_calib = true,
236*4882a593Smuzhiyun 	.temp_offset_v2 = true,
237*4882a593Smuzhiyun };
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun const struct iwl_dvm_cfg iwl_dvm_105_cfg = {
240*4882a593Smuzhiyun 	.set_hw_params = iwl2000_hw_set_hw_params,
241*4882a593Smuzhiyun 	.nic_config = iwl2000_nic_config,
242*4882a593Smuzhiyun 	.temperature = iwlagn_temperature,
243*4882a593Smuzhiyun 	.adv_thermal_throttle = true,
244*4882a593Smuzhiyun 	.support_ct_kill_exit = true,
245*4882a593Smuzhiyun 	.plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
246*4882a593Smuzhiyun 	.chain_noise_scale = 1000,
247*4882a593Smuzhiyun 	.hd_v2 = true,
248*4882a593Smuzhiyun 	.need_temp_offset_calib = true,
249*4882a593Smuzhiyun 	.temp_offset_v2 = true,
250*4882a593Smuzhiyun 	.adv_pm = true,
251*4882a593Smuzhiyun };
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun static const struct iwl_dvm_bt_params iwl2030_bt_params = {
254*4882a593Smuzhiyun 	/* Due to bluetooth, we transmit 2.4 GHz probes only on antenna A */
255*4882a593Smuzhiyun 	.advanced_bt_coexist = true,
256*4882a593Smuzhiyun 	.agg_time_limit = BT_AGG_THRESHOLD_DEF,
257*4882a593Smuzhiyun 	.bt_init_traffic_load = IWL_BT_COEX_TRAFFIC_LOAD_NONE,
258*4882a593Smuzhiyun 	.bt_prio_boost = IWLAGN_BT_PRIO_BOOST_DEFAULT32,
259*4882a593Smuzhiyun 	.bt_sco_disable = true,
260*4882a593Smuzhiyun 	.bt_session_2 = true,
261*4882a593Smuzhiyun };
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun const struct iwl_dvm_cfg iwl_dvm_2030_cfg = {
264*4882a593Smuzhiyun 	.set_hw_params = iwl2000_hw_set_hw_params,
265*4882a593Smuzhiyun 	.nic_config = iwl2000_nic_config,
266*4882a593Smuzhiyun 	.temperature = iwlagn_temperature,
267*4882a593Smuzhiyun 	.adv_thermal_throttle = true,
268*4882a593Smuzhiyun 	.support_ct_kill_exit = true,
269*4882a593Smuzhiyun 	.plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
270*4882a593Smuzhiyun 	.chain_noise_scale = 1000,
271*4882a593Smuzhiyun 	.hd_v2 = true,
272*4882a593Smuzhiyun 	.bt_params = &iwl2030_bt_params,
273*4882a593Smuzhiyun 	.need_temp_offset_calib = true,
274*4882a593Smuzhiyun 	.temp_offset_v2 = true,
275*4882a593Smuzhiyun 	.adv_pm = true,
276*4882a593Smuzhiyun };
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun /*
279*4882a593Smuzhiyun  * 5000 series
280*4882a593Smuzhiyun  * ===========
281*4882a593Smuzhiyun  */
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun /* NIC configuration for 5000 series */
284*4882a593Smuzhiyun static const struct iwl_sensitivity_ranges iwl5000_sensitivity = {
285*4882a593Smuzhiyun 	.min_nrg_cck = 100,
286*4882a593Smuzhiyun 	.auto_corr_min_ofdm = 90,
287*4882a593Smuzhiyun 	.auto_corr_min_ofdm_mrc = 170,
288*4882a593Smuzhiyun 	.auto_corr_min_ofdm_x1 = 105,
289*4882a593Smuzhiyun 	.auto_corr_min_ofdm_mrc_x1 = 220,
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 	.auto_corr_max_ofdm = 120,
292*4882a593Smuzhiyun 	.auto_corr_max_ofdm_mrc = 210,
293*4882a593Smuzhiyun 	.auto_corr_max_ofdm_x1 = 120,
294*4882a593Smuzhiyun 	.auto_corr_max_ofdm_mrc_x1 = 240,
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun 	.auto_corr_min_cck = 125,
297*4882a593Smuzhiyun 	.auto_corr_max_cck = 200,
298*4882a593Smuzhiyun 	.auto_corr_min_cck_mrc = 200,
299*4882a593Smuzhiyun 	.auto_corr_max_cck_mrc = 400,
300*4882a593Smuzhiyun 	.nrg_th_cck = 100,
301*4882a593Smuzhiyun 	.nrg_th_ofdm = 100,
302*4882a593Smuzhiyun 
303*4882a593Smuzhiyun 	.barker_corr_th_min = 190,
304*4882a593Smuzhiyun 	.barker_corr_th_min_mrc = 390,
305*4882a593Smuzhiyun 	.nrg_th_cca = 62,
306*4882a593Smuzhiyun };
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun static const struct iwl_sensitivity_ranges iwl5150_sensitivity = {
309*4882a593Smuzhiyun 	.min_nrg_cck = 95,
310*4882a593Smuzhiyun 	.auto_corr_min_ofdm = 90,
311*4882a593Smuzhiyun 	.auto_corr_min_ofdm_mrc = 170,
312*4882a593Smuzhiyun 	.auto_corr_min_ofdm_x1 = 105,
313*4882a593Smuzhiyun 	.auto_corr_min_ofdm_mrc_x1 = 220,
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun 	.auto_corr_max_ofdm = 120,
316*4882a593Smuzhiyun 	.auto_corr_max_ofdm_mrc = 210,
317*4882a593Smuzhiyun 	/* max = min for performance bug in 5150 DSP */
318*4882a593Smuzhiyun 	.auto_corr_max_ofdm_x1 = 105,
319*4882a593Smuzhiyun 	.auto_corr_max_ofdm_mrc_x1 = 220,
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun 	.auto_corr_min_cck = 125,
322*4882a593Smuzhiyun 	.auto_corr_max_cck = 200,
323*4882a593Smuzhiyun 	.auto_corr_min_cck_mrc = 170,
324*4882a593Smuzhiyun 	.auto_corr_max_cck_mrc = 400,
325*4882a593Smuzhiyun 	.nrg_th_cck = 95,
326*4882a593Smuzhiyun 	.nrg_th_ofdm = 95,
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun 	.barker_corr_th_min = 190,
329*4882a593Smuzhiyun 	.barker_corr_th_min_mrc = 390,
330*4882a593Smuzhiyun 	.nrg_th_cca = 62,
331*4882a593Smuzhiyun };
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun #define IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF	(-5)
334*4882a593Smuzhiyun 
iwl_temp_calib_to_offset(struct iwl_priv * priv)335*4882a593Smuzhiyun static s32 iwl_temp_calib_to_offset(struct iwl_priv *priv)
336*4882a593Smuzhiyun {
337*4882a593Smuzhiyun 	u16 temperature, voltage;
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun 	temperature = le16_to_cpu(priv->nvm_data->kelvin_temperature);
340*4882a593Smuzhiyun 	voltage = le16_to_cpu(priv->nvm_data->kelvin_voltage);
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun 	/* offset = temp - volt / coeff */
343*4882a593Smuzhiyun 	return (s32)(temperature -
344*4882a593Smuzhiyun 			voltage / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF);
345*4882a593Smuzhiyun }
346*4882a593Smuzhiyun 
iwl5150_set_ct_threshold(struct iwl_priv * priv)347*4882a593Smuzhiyun static void iwl5150_set_ct_threshold(struct iwl_priv *priv)
348*4882a593Smuzhiyun {
349*4882a593Smuzhiyun 	const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF;
350*4882a593Smuzhiyun 	s32 threshold = (s32)celsius_to_kelvin(CT_KILL_THRESHOLD_LEGACY) -
351*4882a593Smuzhiyun 			iwl_temp_calib_to_offset(priv);
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun 	priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef;
354*4882a593Smuzhiyun }
355*4882a593Smuzhiyun 
iwl5000_set_ct_threshold(struct iwl_priv * priv)356*4882a593Smuzhiyun static void iwl5000_set_ct_threshold(struct iwl_priv *priv)
357*4882a593Smuzhiyun {
358*4882a593Smuzhiyun 	/* want Celsius */
359*4882a593Smuzhiyun 	priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY;
360*4882a593Smuzhiyun }
361*4882a593Smuzhiyun 
iwl5000_hw_set_hw_params(struct iwl_priv * priv)362*4882a593Smuzhiyun static void iwl5000_hw_set_hw_params(struct iwl_priv *priv)
363*4882a593Smuzhiyun {
364*4882a593Smuzhiyun 	iwl5000_set_ct_threshold(priv);
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun 	/* Set initial sensitivity parameters */
367*4882a593Smuzhiyun 	priv->hw_params.sens = &iwl5000_sensitivity;
368*4882a593Smuzhiyun }
369*4882a593Smuzhiyun 
iwl5150_hw_set_hw_params(struct iwl_priv * priv)370*4882a593Smuzhiyun static void iwl5150_hw_set_hw_params(struct iwl_priv *priv)
371*4882a593Smuzhiyun {
372*4882a593Smuzhiyun 	iwl5150_set_ct_threshold(priv);
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun 	/* Set initial sensitivity parameters */
375*4882a593Smuzhiyun 	priv->hw_params.sens = &iwl5150_sensitivity;
376*4882a593Smuzhiyun }
377*4882a593Smuzhiyun 
iwl5150_temperature(struct iwl_priv * priv)378*4882a593Smuzhiyun static void iwl5150_temperature(struct iwl_priv *priv)
379*4882a593Smuzhiyun {
380*4882a593Smuzhiyun 	u32 vt = 0;
381*4882a593Smuzhiyun 	s32 offset =  iwl_temp_calib_to_offset(priv);
382*4882a593Smuzhiyun 
383*4882a593Smuzhiyun 	vt = le32_to_cpu(priv->statistics.common.temperature);
384*4882a593Smuzhiyun 	vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset;
385*4882a593Smuzhiyun 	/* now vt hold the temperature in Kelvin */
386*4882a593Smuzhiyun 	priv->temperature = kelvin_to_celsius(vt);
387*4882a593Smuzhiyun 	iwl_tt_handler(priv);
388*4882a593Smuzhiyun }
389*4882a593Smuzhiyun 
iwl5000_hw_channel_switch(struct iwl_priv * priv,struct ieee80211_channel_switch * ch_switch)390*4882a593Smuzhiyun static int iwl5000_hw_channel_switch(struct iwl_priv *priv,
391*4882a593Smuzhiyun 				     struct ieee80211_channel_switch *ch_switch)
392*4882a593Smuzhiyun {
393*4882a593Smuzhiyun 	/*
394*4882a593Smuzhiyun 	 * MULTI-FIXME
395*4882a593Smuzhiyun 	 * See iwlagn_mac_channel_switch.
396*4882a593Smuzhiyun 	 */
397*4882a593Smuzhiyun 	struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
398*4882a593Smuzhiyun 	struct iwl5000_channel_switch_cmd cmd;
399*4882a593Smuzhiyun 	u32 switch_time_in_usec, ucode_switch_time;
400*4882a593Smuzhiyun 	u16 ch;
401*4882a593Smuzhiyun 	u32 tsf_low;
402*4882a593Smuzhiyun 	u8 switch_count;
403*4882a593Smuzhiyun 	u16 beacon_interval = le16_to_cpu(ctx->timing.beacon_interval);
404*4882a593Smuzhiyun 	struct ieee80211_vif *vif = ctx->vif;
405*4882a593Smuzhiyun 	struct iwl_host_cmd hcmd = {
406*4882a593Smuzhiyun 		.id = REPLY_CHANNEL_SWITCH,
407*4882a593Smuzhiyun 		.len = { sizeof(cmd), },
408*4882a593Smuzhiyun 		.data = { &cmd, },
409*4882a593Smuzhiyun 	};
410*4882a593Smuzhiyun 
411*4882a593Smuzhiyun 	cmd.band = priv->band == NL80211_BAND_2GHZ;
412*4882a593Smuzhiyun 	ch = ch_switch->chandef.chan->hw_value;
413*4882a593Smuzhiyun 	IWL_DEBUG_11H(priv, "channel switch from %d to %d\n",
414*4882a593Smuzhiyun 		      ctx->active.channel, ch);
415*4882a593Smuzhiyun 	cmd.channel = cpu_to_le16(ch);
416*4882a593Smuzhiyun 	cmd.rxon_flags = ctx->staging.flags;
417*4882a593Smuzhiyun 	cmd.rxon_filter_flags = ctx->staging.filter_flags;
418*4882a593Smuzhiyun 	switch_count = ch_switch->count;
419*4882a593Smuzhiyun 	tsf_low = ch_switch->timestamp & 0x0ffffffff;
420*4882a593Smuzhiyun 	/*
421*4882a593Smuzhiyun 	 * calculate the ucode channel switch time
422*4882a593Smuzhiyun 	 * adding TSF as one of the factor for when to switch
423*4882a593Smuzhiyun 	 */
424*4882a593Smuzhiyun 	if ((priv->ucode_beacon_time > tsf_low) && beacon_interval) {
425*4882a593Smuzhiyun 		if (switch_count > ((priv->ucode_beacon_time - tsf_low) /
426*4882a593Smuzhiyun 		    beacon_interval)) {
427*4882a593Smuzhiyun 			switch_count -= (priv->ucode_beacon_time -
428*4882a593Smuzhiyun 				tsf_low) / beacon_interval;
429*4882a593Smuzhiyun 		} else
430*4882a593Smuzhiyun 			switch_count = 0;
431*4882a593Smuzhiyun 	}
432*4882a593Smuzhiyun 	if (switch_count <= 1)
433*4882a593Smuzhiyun 		cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
434*4882a593Smuzhiyun 	else {
435*4882a593Smuzhiyun 		switch_time_in_usec =
436*4882a593Smuzhiyun 			vif->bss_conf.beacon_int * switch_count * TIME_UNIT;
437*4882a593Smuzhiyun 		ucode_switch_time = iwl_usecs_to_beacons(priv,
438*4882a593Smuzhiyun 							 switch_time_in_usec,
439*4882a593Smuzhiyun 							 beacon_interval);
440*4882a593Smuzhiyun 		cmd.switch_time = iwl_add_beacon_time(priv,
441*4882a593Smuzhiyun 						      priv->ucode_beacon_time,
442*4882a593Smuzhiyun 						      ucode_switch_time,
443*4882a593Smuzhiyun 						      beacon_interval);
444*4882a593Smuzhiyun 	}
445*4882a593Smuzhiyun 	IWL_DEBUG_11H(priv, "uCode time for the switch is 0x%x\n",
446*4882a593Smuzhiyun 		      cmd.switch_time);
447*4882a593Smuzhiyun 	cmd.expect_beacon =
448*4882a593Smuzhiyun 		ch_switch->chandef.chan->flags & IEEE80211_CHAN_RADAR;
449*4882a593Smuzhiyun 
450*4882a593Smuzhiyun 	return iwl_dvm_send_cmd(priv, &hcmd);
451*4882a593Smuzhiyun }
452*4882a593Smuzhiyun 
453*4882a593Smuzhiyun const struct iwl_dvm_cfg iwl_dvm_5000_cfg = {
454*4882a593Smuzhiyun 	.set_hw_params = iwl5000_hw_set_hw_params,
455*4882a593Smuzhiyun 	.set_channel_switch = iwl5000_hw_channel_switch,
456*4882a593Smuzhiyun 	.temperature = iwlagn_temperature,
457*4882a593Smuzhiyun 	.plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
458*4882a593Smuzhiyun 	.chain_noise_scale = 1000,
459*4882a593Smuzhiyun 	.no_idle_support = true,
460*4882a593Smuzhiyun };
461*4882a593Smuzhiyun 
462*4882a593Smuzhiyun const struct iwl_dvm_cfg iwl_dvm_5150_cfg = {
463*4882a593Smuzhiyun 	.set_hw_params = iwl5150_hw_set_hw_params,
464*4882a593Smuzhiyun 	.set_channel_switch = iwl5000_hw_channel_switch,
465*4882a593Smuzhiyun 	.temperature = iwl5150_temperature,
466*4882a593Smuzhiyun 	.plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
467*4882a593Smuzhiyun 	.chain_noise_scale = 1000,
468*4882a593Smuzhiyun 	.no_idle_support = true,
469*4882a593Smuzhiyun 	.no_xtal_calib = true,
470*4882a593Smuzhiyun };
471*4882a593Smuzhiyun 
472*4882a593Smuzhiyun 
473*4882a593Smuzhiyun 
474*4882a593Smuzhiyun /*
475*4882a593Smuzhiyun  * 6000 series
476*4882a593Smuzhiyun  * ===========
477*4882a593Smuzhiyun  */
478*4882a593Smuzhiyun 
iwl6000_set_ct_threshold(struct iwl_priv * priv)479*4882a593Smuzhiyun static void iwl6000_set_ct_threshold(struct iwl_priv *priv)
480*4882a593Smuzhiyun {
481*4882a593Smuzhiyun 	/* want Celsius */
482*4882a593Smuzhiyun 	priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
483*4882a593Smuzhiyun 	priv->hw_params.ct_kill_exit_threshold = CT_KILL_EXIT_THRESHOLD;
484*4882a593Smuzhiyun }
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun /* NIC configuration for 6000 series */
iwl6000_nic_config(struct iwl_priv * priv)487*4882a593Smuzhiyun static void iwl6000_nic_config(struct iwl_priv *priv)
488*4882a593Smuzhiyun {
489*4882a593Smuzhiyun 	switch (priv->trans->trans_cfg->device_family) {
490*4882a593Smuzhiyun 	case IWL_DEVICE_FAMILY_6005:
491*4882a593Smuzhiyun 	case IWL_DEVICE_FAMILY_6030:
492*4882a593Smuzhiyun 	case IWL_DEVICE_FAMILY_6000:
493*4882a593Smuzhiyun 		break;
494*4882a593Smuzhiyun 	case IWL_DEVICE_FAMILY_6000i:
495*4882a593Smuzhiyun 		/* 2x2 IPA phy type */
496*4882a593Smuzhiyun 		iwl_write32(priv->trans, CSR_GP_DRIVER_REG,
497*4882a593Smuzhiyun 			     CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA);
498*4882a593Smuzhiyun 		break;
499*4882a593Smuzhiyun 	case IWL_DEVICE_FAMILY_6050:
500*4882a593Smuzhiyun 		/* Indicate calibration version to uCode. */
501*4882a593Smuzhiyun 		if (priv->nvm_data->calib_version >= 6)
502*4882a593Smuzhiyun 			iwl_set_bit(priv->trans, CSR_GP_DRIVER_REG,
503*4882a593Smuzhiyun 					CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6);
504*4882a593Smuzhiyun 		break;
505*4882a593Smuzhiyun 	case IWL_DEVICE_FAMILY_6150:
506*4882a593Smuzhiyun 		/* Indicate calibration version to uCode. */
507*4882a593Smuzhiyun 		if (priv->nvm_data->calib_version >= 6)
508*4882a593Smuzhiyun 			iwl_set_bit(priv->trans, CSR_GP_DRIVER_REG,
509*4882a593Smuzhiyun 					CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6);
510*4882a593Smuzhiyun 		iwl_set_bit(priv->trans, CSR_GP_DRIVER_REG,
511*4882a593Smuzhiyun 			    CSR_GP_DRIVER_REG_BIT_6050_1x2);
512*4882a593Smuzhiyun 		break;
513*4882a593Smuzhiyun 	default:
514*4882a593Smuzhiyun 		WARN_ON(1);
515*4882a593Smuzhiyun 	}
516*4882a593Smuzhiyun }
517*4882a593Smuzhiyun 
518*4882a593Smuzhiyun static const struct iwl_sensitivity_ranges iwl6000_sensitivity = {
519*4882a593Smuzhiyun 	.min_nrg_cck = 110,
520*4882a593Smuzhiyun 	.auto_corr_min_ofdm = 80,
521*4882a593Smuzhiyun 	.auto_corr_min_ofdm_mrc = 128,
522*4882a593Smuzhiyun 	.auto_corr_min_ofdm_x1 = 105,
523*4882a593Smuzhiyun 	.auto_corr_min_ofdm_mrc_x1 = 192,
524*4882a593Smuzhiyun 
525*4882a593Smuzhiyun 	.auto_corr_max_ofdm = 145,
526*4882a593Smuzhiyun 	.auto_corr_max_ofdm_mrc = 232,
527*4882a593Smuzhiyun 	.auto_corr_max_ofdm_x1 = 110,
528*4882a593Smuzhiyun 	.auto_corr_max_ofdm_mrc_x1 = 232,
529*4882a593Smuzhiyun 
530*4882a593Smuzhiyun 	.auto_corr_min_cck = 125,
531*4882a593Smuzhiyun 	.auto_corr_max_cck = 175,
532*4882a593Smuzhiyun 	.auto_corr_min_cck_mrc = 160,
533*4882a593Smuzhiyun 	.auto_corr_max_cck_mrc = 310,
534*4882a593Smuzhiyun 	.nrg_th_cck = 110,
535*4882a593Smuzhiyun 	.nrg_th_ofdm = 110,
536*4882a593Smuzhiyun 
537*4882a593Smuzhiyun 	.barker_corr_th_min = 190,
538*4882a593Smuzhiyun 	.barker_corr_th_min_mrc = 336,
539*4882a593Smuzhiyun 	.nrg_th_cca = 62,
540*4882a593Smuzhiyun };
541*4882a593Smuzhiyun 
iwl6000_hw_set_hw_params(struct iwl_priv * priv)542*4882a593Smuzhiyun static void iwl6000_hw_set_hw_params(struct iwl_priv *priv)
543*4882a593Smuzhiyun {
544*4882a593Smuzhiyun 	iwl6000_set_ct_threshold(priv);
545*4882a593Smuzhiyun 
546*4882a593Smuzhiyun 	/* Set initial sensitivity parameters */
547*4882a593Smuzhiyun 	priv->hw_params.sens = &iwl6000_sensitivity;
548*4882a593Smuzhiyun 
549*4882a593Smuzhiyun }
550*4882a593Smuzhiyun 
iwl6000_hw_channel_switch(struct iwl_priv * priv,struct ieee80211_channel_switch * ch_switch)551*4882a593Smuzhiyun static int iwl6000_hw_channel_switch(struct iwl_priv *priv,
552*4882a593Smuzhiyun 				     struct ieee80211_channel_switch *ch_switch)
553*4882a593Smuzhiyun {
554*4882a593Smuzhiyun 	/*
555*4882a593Smuzhiyun 	 * MULTI-FIXME
556*4882a593Smuzhiyun 	 * See iwlagn_mac_channel_switch.
557*4882a593Smuzhiyun 	 */
558*4882a593Smuzhiyun 	struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
559*4882a593Smuzhiyun 	struct iwl6000_channel_switch_cmd *cmd;
560*4882a593Smuzhiyun 	u32 switch_time_in_usec, ucode_switch_time;
561*4882a593Smuzhiyun 	u16 ch;
562*4882a593Smuzhiyun 	u32 tsf_low;
563*4882a593Smuzhiyun 	u8 switch_count;
564*4882a593Smuzhiyun 	u16 beacon_interval = le16_to_cpu(ctx->timing.beacon_interval);
565*4882a593Smuzhiyun 	struct ieee80211_vif *vif = ctx->vif;
566*4882a593Smuzhiyun 	struct iwl_host_cmd hcmd = {
567*4882a593Smuzhiyun 		.id = REPLY_CHANNEL_SWITCH,
568*4882a593Smuzhiyun 		.len = { sizeof(*cmd), },
569*4882a593Smuzhiyun 		.dataflags[0] = IWL_HCMD_DFL_NOCOPY,
570*4882a593Smuzhiyun 	};
571*4882a593Smuzhiyun 	int err;
572*4882a593Smuzhiyun 
573*4882a593Smuzhiyun 	cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
574*4882a593Smuzhiyun 	if (!cmd)
575*4882a593Smuzhiyun 		return -ENOMEM;
576*4882a593Smuzhiyun 
577*4882a593Smuzhiyun 	hcmd.data[0] = cmd;
578*4882a593Smuzhiyun 
579*4882a593Smuzhiyun 	cmd->band = priv->band == NL80211_BAND_2GHZ;
580*4882a593Smuzhiyun 	ch = ch_switch->chandef.chan->hw_value;
581*4882a593Smuzhiyun 	IWL_DEBUG_11H(priv, "channel switch from %u to %u\n",
582*4882a593Smuzhiyun 		      ctx->active.channel, ch);
583*4882a593Smuzhiyun 	cmd->channel = cpu_to_le16(ch);
584*4882a593Smuzhiyun 	cmd->rxon_flags = ctx->staging.flags;
585*4882a593Smuzhiyun 	cmd->rxon_filter_flags = ctx->staging.filter_flags;
586*4882a593Smuzhiyun 	switch_count = ch_switch->count;
587*4882a593Smuzhiyun 	tsf_low = ch_switch->timestamp & 0x0ffffffff;
588*4882a593Smuzhiyun 	/*
589*4882a593Smuzhiyun 	 * calculate the ucode channel switch time
590*4882a593Smuzhiyun 	 * adding TSF as one of the factor for when to switch
591*4882a593Smuzhiyun 	 */
592*4882a593Smuzhiyun 	if ((priv->ucode_beacon_time > tsf_low) && beacon_interval) {
593*4882a593Smuzhiyun 		if (switch_count > ((priv->ucode_beacon_time - tsf_low) /
594*4882a593Smuzhiyun 		    beacon_interval)) {
595*4882a593Smuzhiyun 			switch_count -= (priv->ucode_beacon_time -
596*4882a593Smuzhiyun 				tsf_low) / beacon_interval;
597*4882a593Smuzhiyun 		} else
598*4882a593Smuzhiyun 			switch_count = 0;
599*4882a593Smuzhiyun 	}
600*4882a593Smuzhiyun 	if (switch_count <= 1)
601*4882a593Smuzhiyun 		cmd->switch_time = cpu_to_le32(priv->ucode_beacon_time);
602*4882a593Smuzhiyun 	else {
603*4882a593Smuzhiyun 		switch_time_in_usec =
604*4882a593Smuzhiyun 			vif->bss_conf.beacon_int * switch_count * TIME_UNIT;
605*4882a593Smuzhiyun 		ucode_switch_time = iwl_usecs_to_beacons(priv,
606*4882a593Smuzhiyun 							 switch_time_in_usec,
607*4882a593Smuzhiyun 							 beacon_interval);
608*4882a593Smuzhiyun 		cmd->switch_time = iwl_add_beacon_time(priv,
609*4882a593Smuzhiyun 						       priv->ucode_beacon_time,
610*4882a593Smuzhiyun 						       ucode_switch_time,
611*4882a593Smuzhiyun 						       beacon_interval);
612*4882a593Smuzhiyun 	}
613*4882a593Smuzhiyun 	IWL_DEBUG_11H(priv, "uCode time for the switch is 0x%x\n",
614*4882a593Smuzhiyun 		      cmd->switch_time);
615*4882a593Smuzhiyun 	cmd->expect_beacon =
616*4882a593Smuzhiyun 		ch_switch->chandef.chan->flags & IEEE80211_CHAN_RADAR;
617*4882a593Smuzhiyun 
618*4882a593Smuzhiyun 	err = iwl_dvm_send_cmd(priv, &hcmd);
619*4882a593Smuzhiyun 	kfree(cmd);
620*4882a593Smuzhiyun 	return err;
621*4882a593Smuzhiyun }
622*4882a593Smuzhiyun 
623*4882a593Smuzhiyun const struct iwl_dvm_cfg iwl_dvm_6000_cfg = {
624*4882a593Smuzhiyun 	.set_hw_params = iwl6000_hw_set_hw_params,
625*4882a593Smuzhiyun 	.set_channel_switch = iwl6000_hw_channel_switch,
626*4882a593Smuzhiyun 	.nic_config = iwl6000_nic_config,
627*4882a593Smuzhiyun 	.temperature = iwlagn_temperature,
628*4882a593Smuzhiyun 	.adv_thermal_throttle = true,
629*4882a593Smuzhiyun 	.support_ct_kill_exit = true,
630*4882a593Smuzhiyun 	.plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
631*4882a593Smuzhiyun 	.chain_noise_scale = 1000,
632*4882a593Smuzhiyun };
633*4882a593Smuzhiyun 
634*4882a593Smuzhiyun const struct iwl_dvm_cfg iwl_dvm_6005_cfg = {
635*4882a593Smuzhiyun 	.set_hw_params = iwl6000_hw_set_hw_params,
636*4882a593Smuzhiyun 	.set_channel_switch = iwl6000_hw_channel_switch,
637*4882a593Smuzhiyun 	.nic_config = iwl6000_nic_config,
638*4882a593Smuzhiyun 	.temperature = iwlagn_temperature,
639*4882a593Smuzhiyun 	.adv_thermal_throttle = true,
640*4882a593Smuzhiyun 	.support_ct_kill_exit = true,
641*4882a593Smuzhiyun 	.plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
642*4882a593Smuzhiyun 	.chain_noise_scale = 1000,
643*4882a593Smuzhiyun 	.need_temp_offset_calib = true,
644*4882a593Smuzhiyun };
645*4882a593Smuzhiyun 
646*4882a593Smuzhiyun const struct iwl_dvm_cfg iwl_dvm_6050_cfg = {
647*4882a593Smuzhiyun 	.set_hw_params = iwl6000_hw_set_hw_params,
648*4882a593Smuzhiyun 	.set_channel_switch = iwl6000_hw_channel_switch,
649*4882a593Smuzhiyun 	.nic_config = iwl6000_nic_config,
650*4882a593Smuzhiyun 	.temperature = iwlagn_temperature,
651*4882a593Smuzhiyun 	.adv_thermal_throttle = true,
652*4882a593Smuzhiyun 	.support_ct_kill_exit = true,
653*4882a593Smuzhiyun 	.plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
654*4882a593Smuzhiyun 	.chain_noise_scale = 1500,
655*4882a593Smuzhiyun };
656*4882a593Smuzhiyun 
657*4882a593Smuzhiyun static const struct iwl_dvm_bt_params iwl6000_bt_params = {
658*4882a593Smuzhiyun 	/* Due to bluetooth, we transmit 2.4 GHz probes only on antenna A */
659*4882a593Smuzhiyun 	.advanced_bt_coexist = true,
660*4882a593Smuzhiyun 	.agg_time_limit = BT_AGG_THRESHOLD_DEF,
661*4882a593Smuzhiyun 	.bt_init_traffic_load = IWL_BT_COEX_TRAFFIC_LOAD_NONE,
662*4882a593Smuzhiyun 	.bt_prio_boost = IWLAGN_BT_PRIO_BOOST_DEFAULT,
663*4882a593Smuzhiyun 	.bt_sco_disable = true,
664*4882a593Smuzhiyun };
665*4882a593Smuzhiyun 
666*4882a593Smuzhiyun const struct iwl_dvm_cfg iwl_dvm_6030_cfg = {
667*4882a593Smuzhiyun 	.set_hw_params = iwl6000_hw_set_hw_params,
668*4882a593Smuzhiyun 	.set_channel_switch = iwl6000_hw_channel_switch,
669*4882a593Smuzhiyun 	.nic_config = iwl6000_nic_config,
670*4882a593Smuzhiyun 	.temperature = iwlagn_temperature,
671*4882a593Smuzhiyun 	.adv_thermal_throttle = true,
672*4882a593Smuzhiyun 	.support_ct_kill_exit = true,
673*4882a593Smuzhiyun 	.plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
674*4882a593Smuzhiyun 	.chain_noise_scale = 1000,
675*4882a593Smuzhiyun 	.bt_params = &iwl6000_bt_params,
676*4882a593Smuzhiyun 	.need_temp_offset_calib = true,
677*4882a593Smuzhiyun 	.adv_pm = true,
678*4882a593Smuzhiyun };
679