xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/intel/iwlwifi/cfg/22000.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /******************************************************************************
2*4882a593Smuzhiyun  *
3*4882a593Smuzhiyun  * This file is provided under a dual BSD/GPLv2 license.  When using or
4*4882a593Smuzhiyun  * redistributing this file, you may do so under either license.
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * GPL LICENSE SUMMARY
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * Copyright(c) 2015-2017 Intel Deutschland GmbH
9*4882a593Smuzhiyun  * Copyright (C) 2018-2020 Intel Corporation
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or modify
12*4882a593Smuzhiyun  * it under the terms of version 2 of the GNU General Public License as
13*4882a593Smuzhiyun  * published by the Free Software Foundation.
14*4882a593Smuzhiyun  *
15*4882a593Smuzhiyun  * This program is distributed in the hope that it will be useful, but
16*4882a593Smuzhiyun  * WITHOUT ANY WARRANTY; without even the implied warranty of
17*4882a593Smuzhiyun  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18*4882a593Smuzhiyun  * General Public License for more details.
19*4882a593Smuzhiyun  *
20*4882a593Smuzhiyun  * BSD LICENSE
21*4882a593Smuzhiyun  *
22*4882a593Smuzhiyun  * Copyright(c) 2015-2017 Intel Deutschland GmbH
23*4882a593Smuzhiyun  * Copyright (C) 2018-2020 Intel Corporation
24*4882a593Smuzhiyun  * All rights reserved.
25*4882a593Smuzhiyun  *
26*4882a593Smuzhiyun  * Redistribution and use in source and binary forms, with or without
27*4882a593Smuzhiyun  * modification, are permitted provided that the following conditions
28*4882a593Smuzhiyun  * are met:
29*4882a593Smuzhiyun  *
30*4882a593Smuzhiyun  *  * Redistributions of source code must retain the above copyright
31*4882a593Smuzhiyun  *    notice, this list of conditions and the following disclaimer.
32*4882a593Smuzhiyun  *  * Redistributions in binary form must reproduce the above copyright
33*4882a593Smuzhiyun  *    notice, this list of conditions and the following disclaimer in
34*4882a593Smuzhiyun  *    the documentation and/or other materials provided with the
35*4882a593Smuzhiyun  *    distribution.
36*4882a593Smuzhiyun  *  * Neither the name Intel Corporation nor the names of its
37*4882a593Smuzhiyun  *    contributors may be used to endorse or promote products derived
38*4882a593Smuzhiyun  *    from this software without specific prior written permission.
39*4882a593Smuzhiyun  *
40*4882a593Smuzhiyun  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
41*4882a593Smuzhiyun  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
42*4882a593Smuzhiyun  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
43*4882a593Smuzhiyun  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
44*4882a593Smuzhiyun  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
45*4882a593Smuzhiyun  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
46*4882a593Smuzhiyun  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
47*4882a593Smuzhiyun  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
48*4882a593Smuzhiyun  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
49*4882a593Smuzhiyun  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
50*4882a593Smuzhiyun  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51*4882a593Smuzhiyun  *
52*4882a593Smuzhiyun  *****************************************************************************/
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun #include <linux/module.h>
55*4882a593Smuzhiyun #include <linux/stringify.h>
56*4882a593Smuzhiyun #include "iwl-config.h"
57*4882a593Smuzhiyun #include "iwl-prph.h"
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun /* Highest firmware API version supported */
60*4882a593Smuzhiyun #define IWL_22000_UCODE_API_MAX	59
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun /* Lowest firmware API version supported */
63*4882a593Smuzhiyun #define IWL_22000_UCODE_API_MIN	39
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun /* NVM versions */
66*4882a593Smuzhiyun #define IWL_22000_NVM_VERSION		0x0a1d
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun /* Memory offsets and lengths */
69*4882a593Smuzhiyun #define IWL_22000_DCCM_OFFSET		0x800000 /* LMAC1 */
70*4882a593Smuzhiyun #define IWL_22000_DCCM_LEN		0x10000 /* LMAC1 */
71*4882a593Smuzhiyun #define IWL_22000_DCCM2_OFFSET		0x880000
72*4882a593Smuzhiyun #define IWL_22000_DCCM2_LEN		0x8000
73*4882a593Smuzhiyun #define IWL_22000_SMEM_OFFSET		0x400000
74*4882a593Smuzhiyun #define IWL_22000_SMEM_LEN		0xD0000
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun #define IWL_QU_B_HR_B_FW_PRE		"iwlwifi-Qu-b0-hr-b0-"
77*4882a593Smuzhiyun #define IWL_QNJ_B_HR_B_FW_PRE		"iwlwifi-QuQnj-b0-hr-b0-"
78*4882a593Smuzhiyun #define IWL_QU_C_HR_B_FW_PRE		"iwlwifi-Qu-c0-hr-b0-"
79*4882a593Smuzhiyun #define IWL_QU_B_JF_B_FW_PRE		"iwlwifi-Qu-b0-jf-b0-"
80*4882a593Smuzhiyun #define IWL_QU_C_JF_B_FW_PRE		"iwlwifi-Qu-c0-jf-b0-"
81*4882a593Smuzhiyun #define IWL_QUZ_A_HR_B_FW_PRE		"iwlwifi-QuZ-a0-hr-b0-"
82*4882a593Smuzhiyun #define IWL_QUZ_A_JF_B_FW_PRE		"iwlwifi-QuZ-a0-jf-b0-"
83*4882a593Smuzhiyun #define IWL_QNJ_B_JF_B_FW_PRE		"iwlwifi-QuQnj-b0-jf-b0-"
84*4882a593Smuzhiyun #define IWL_CC_A_FW_PRE			"iwlwifi-cc-a0-"
85*4882a593Smuzhiyun #define IWL_SO_A_JF_B_FW_PRE		"iwlwifi-so-a0-jf-b0-"
86*4882a593Smuzhiyun #define IWL_SO_A_HR_B_FW_PRE		"iwlwifi-so-a0-hr-b0-"
87*4882a593Smuzhiyun #define IWL_SO_A_GF_A_FW_PRE		"iwlwifi-so-a0-gf-a0-"
88*4882a593Smuzhiyun #define IWL_TY_A_GF_A_FW_PRE		"iwlwifi-ty-a0-gf-a0-"
89*4882a593Smuzhiyun #define IWL_SO_A_GF4_A_FW_PRE		"iwlwifi-so-a0-gf4-a0-"
90*4882a593Smuzhiyun #define IWL_SNJ_A_GF4_A_FW_PRE		"iwlwifi-SoSnj-a0-gf4-a0-"
91*4882a593Smuzhiyun #define IWL_SNJ_A_GF_A_FW_PRE		"iwlwifi-SoSnj-a0-gf-a0-"
92*4882a593Smuzhiyun #define IWL_SNJ_A_HR_B_FW_PRE		"iwlwifi-SoSnj-a0-hr-b0-"
93*4882a593Smuzhiyun #define IWL_MA_A_GF_A_FW_PRE		"iwlwifi-ma-a0-gf-a0-"
94*4882a593Smuzhiyun #define IWL_MA_A_MR_A_FW_PRE		"iwlwifi-ma-a0-mr-a0-"
95*4882a593Smuzhiyun #define IWL_SNJ_A_MR_A_FW_PRE		"iwlwifi-SoSnj-a0-mr-a0-"
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun #define IWL_QU_B_HR_B_MODULE_FIRMWARE(api) \
98*4882a593Smuzhiyun 	IWL_QU_B_HR_B_FW_PRE __stringify(api) ".ucode"
99*4882a593Smuzhiyun #define IWL_QNJ_B_HR_B_MODULE_FIRMWARE(api)	\
100*4882a593Smuzhiyun 	IWL_QNJ_B_HR_B_FW_PRE __stringify(api) ".ucode"
101*4882a593Smuzhiyun #define IWL_QUZ_A_HR_B_MODULE_FIRMWARE(api) \
102*4882a593Smuzhiyun 	IWL_QUZ_A_HR_B_FW_PRE __stringify(api) ".ucode"
103*4882a593Smuzhiyun #define IWL_QUZ_A_JF_B_MODULE_FIRMWARE(api) \
104*4882a593Smuzhiyun 	IWL_QUZ_A_JF_B_FW_PRE __stringify(api) ".ucode"
105*4882a593Smuzhiyun #define IWL_QU_C_HR_B_MODULE_FIRMWARE(api) \
106*4882a593Smuzhiyun 	IWL_QU_C_HR_B_FW_PRE __stringify(api) ".ucode"
107*4882a593Smuzhiyun #define IWL_QU_B_JF_B_MODULE_FIRMWARE(api) \
108*4882a593Smuzhiyun 	IWL_QU_B_JF_B_FW_PRE __stringify(api) ".ucode"
109*4882a593Smuzhiyun #define IWL_QNJ_B_JF_B_MODULE_FIRMWARE(api)		\
110*4882a593Smuzhiyun 	IWL_QNJ_B_JF_B_FW_PRE __stringify(api) ".ucode"
111*4882a593Smuzhiyun #define IWL_CC_A_MODULE_FIRMWARE(api)			\
112*4882a593Smuzhiyun 	IWL_CC_A_FW_PRE __stringify(api) ".ucode"
113*4882a593Smuzhiyun #define IWL_SO_A_JF_B_MODULE_FIRMWARE(api) \
114*4882a593Smuzhiyun 	IWL_SO_A_JF_B_FW_PRE __stringify(api) ".ucode"
115*4882a593Smuzhiyun #define IWL_SO_A_HR_B_MODULE_FIRMWARE(api) \
116*4882a593Smuzhiyun 	IWL_SO_A_HR_B_FW_PRE __stringify(api) ".ucode"
117*4882a593Smuzhiyun #define IWL_SO_A_GF_A_MODULE_FIRMWARE(api) \
118*4882a593Smuzhiyun 	IWL_SO_A_GF_A_FW_PRE __stringify(api) ".ucode"
119*4882a593Smuzhiyun #define IWL_TY_A_GF_A_MODULE_FIRMWARE(api) \
120*4882a593Smuzhiyun 	IWL_TY_A_GF_A_FW_PRE __stringify(api) ".ucode"
121*4882a593Smuzhiyun #define IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(api) \
122*4882a593Smuzhiyun 	IWL_SNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode"
123*4882a593Smuzhiyun #define IWL_SNJ_A_GF_A_MODULE_FIRMWARE(api) \
124*4882a593Smuzhiyun 	IWL_SNJ_A_GF_A_FW_PRE __stringify(api) ".ucode"
125*4882a593Smuzhiyun #define IWL_SNJ_A_HR_B_MODULE_FIRMWARE(api) \
126*4882a593Smuzhiyun 	IWL_SNJ_A_HR_B_FW_PRE __stringify(api) ".ucode"
127*4882a593Smuzhiyun #define IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(api) \
128*4882a593Smuzhiyun 	IWL_MA_A_GF_A_FW_PRE __stringify(api) ".ucode"
129*4882a593Smuzhiyun #define IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(api) \
130*4882a593Smuzhiyun 	IWL_MA_A_MR_A_FW_PRE __stringify(api) ".ucode"
131*4882a593Smuzhiyun #define IWL_SNJ_A_MR_A_MODULE_FIRMWARE(api) \
132*4882a593Smuzhiyun 	IWL_SNJ_A_MR_A_FW_PRE __stringify(api) ".ucode"
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun static const struct iwl_base_params iwl_22000_base_params = {
135*4882a593Smuzhiyun 	.eeprom_size = OTP_LOW_IMAGE_SIZE_32K,
136*4882a593Smuzhiyun 	.num_of_queues = 512,
137*4882a593Smuzhiyun 	.max_tfd_queue_size = 256,
138*4882a593Smuzhiyun 	.shadow_ram_support = true,
139*4882a593Smuzhiyun 	.led_compensation = 57,
140*4882a593Smuzhiyun 	.wd_timeout = IWL_LONG_WD_TIMEOUT,
141*4882a593Smuzhiyun 	.max_event_log_size = 512,
142*4882a593Smuzhiyun 	.shadow_reg_enable = true,
143*4882a593Smuzhiyun 	.pcie_l1_allowed = true,
144*4882a593Smuzhiyun };
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun static const struct iwl_base_params iwl_ax210_base_params = {
147*4882a593Smuzhiyun 	.eeprom_size = OTP_LOW_IMAGE_SIZE_32K,
148*4882a593Smuzhiyun 	.num_of_queues = 512,
149*4882a593Smuzhiyun 	.max_tfd_queue_size = 65536,
150*4882a593Smuzhiyun 	.shadow_ram_support = true,
151*4882a593Smuzhiyun 	.led_compensation = 57,
152*4882a593Smuzhiyun 	.wd_timeout = IWL_LONG_WD_TIMEOUT,
153*4882a593Smuzhiyun 	.max_event_log_size = 512,
154*4882a593Smuzhiyun 	.shadow_reg_enable = true,
155*4882a593Smuzhiyun 	.pcie_l1_allowed = true,
156*4882a593Smuzhiyun };
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun static const struct iwl_ht_params iwl_22000_ht_params = {
159*4882a593Smuzhiyun 	.stbc = true,
160*4882a593Smuzhiyun 	.ldpc = true,
161*4882a593Smuzhiyun 	.ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ),
162*4882a593Smuzhiyun };
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun #define IWL_DEVICE_22000_COMMON						\
165*4882a593Smuzhiyun 	.ucode_api_max = IWL_22000_UCODE_API_MAX,			\
166*4882a593Smuzhiyun 	.ucode_api_min = IWL_22000_UCODE_API_MIN,			\
167*4882a593Smuzhiyun 	.led_mode = IWL_LED_RF_STATE,					\
168*4882a593Smuzhiyun 	.nvm_hw_section_num = 10,					\
169*4882a593Smuzhiyun 	.non_shared_ant = ANT_B,					\
170*4882a593Smuzhiyun 	.dccm_offset = IWL_22000_DCCM_OFFSET,				\
171*4882a593Smuzhiyun 	.dccm_len = IWL_22000_DCCM_LEN,					\
172*4882a593Smuzhiyun 	.dccm2_offset = IWL_22000_DCCM2_OFFSET,				\
173*4882a593Smuzhiyun 	.dccm2_len = IWL_22000_DCCM2_LEN,				\
174*4882a593Smuzhiyun 	.smem_offset = IWL_22000_SMEM_OFFSET,				\
175*4882a593Smuzhiyun 	.smem_len = IWL_22000_SMEM_LEN,					\
176*4882a593Smuzhiyun 	.features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,		\
177*4882a593Smuzhiyun 	.apmg_not_supported = true,					\
178*4882a593Smuzhiyun 	.trans.mq_rx_supported = true,					\
179*4882a593Smuzhiyun 	.vht_mu_mimo_supported = true,					\
180*4882a593Smuzhiyun 	.mac_addr_from_csr = true,					\
181*4882a593Smuzhiyun 	.ht_params = &iwl_22000_ht_params,				\
182*4882a593Smuzhiyun 	.nvm_ver = IWL_22000_NVM_VERSION,				\
183*4882a593Smuzhiyun 	.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K,		\
184*4882a593Smuzhiyun 	.trans.use_tfh = true,						\
185*4882a593Smuzhiyun 	.trans.rf_id = true,						\
186*4882a593Smuzhiyun 	.trans.gen2 = true,						\
187*4882a593Smuzhiyun 	.nvm_type = IWL_NVM_EXT,					\
188*4882a593Smuzhiyun 	.dbgc_supported = true,						\
189*4882a593Smuzhiyun 	.min_umac_error_event_table = 0x400000,				\
190*4882a593Smuzhiyun 	.d3_debug_data_base_addr = 0x401000,				\
191*4882a593Smuzhiyun 	.d3_debug_data_length = 60 * 1024,				\
192*4882a593Smuzhiyun 	.mon_smem_regs = {						\
193*4882a593Smuzhiyun 		.write_ptr = {						\
194*4882a593Smuzhiyun 			.addr = LDBG_M2S_BUF_WPTR,			\
195*4882a593Smuzhiyun 			.mask = LDBG_M2S_BUF_WPTR_VAL_MSK,		\
196*4882a593Smuzhiyun 	},								\
197*4882a593Smuzhiyun 		.cycle_cnt = {						\
198*4882a593Smuzhiyun 			.addr = LDBG_M2S_BUF_WRAP_CNT,			\
199*4882a593Smuzhiyun 			.mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK,		\
200*4882a593Smuzhiyun 		},							\
201*4882a593Smuzhiyun 	}
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun #define IWL_DEVICE_22500						\
204*4882a593Smuzhiyun 	IWL_DEVICE_22000_COMMON,					\
205*4882a593Smuzhiyun 	.trans.device_family = IWL_DEVICE_FAMILY_22000,			\
206*4882a593Smuzhiyun 	.trans.base_params = &iwl_22000_base_params,			\
207*4882a593Smuzhiyun 	.gp2_reg_addr = 0xa02c68,					\
208*4882a593Smuzhiyun 	.mon_dram_regs = {						\
209*4882a593Smuzhiyun 		.write_ptr = {						\
210*4882a593Smuzhiyun 			.addr = MON_BUFF_WRPTR_VER2,			\
211*4882a593Smuzhiyun 			.mask = 0xffffffff,				\
212*4882a593Smuzhiyun 		},							\
213*4882a593Smuzhiyun 		.cycle_cnt = {						\
214*4882a593Smuzhiyun 			.addr = MON_BUFF_CYCLE_CNT_VER2,		\
215*4882a593Smuzhiyun 			.mask = 0xffffffff,				\
216*4882a593Smuzhiyun 		},							\
217*4882a593Smuzhiyun 	}
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun #define IWL_DEVICE_AX210						\
220*4882a593Smuzhiyun 	IWL_DEVICE_22000_COMMON,					\
221*4882a593Smuzhiyun 	.trans.umac_prph_offset = 0x300000,				\
222*4882a593Smuzhiyun 	.trans.device_family = IWL_DEVICE_FAMILY_AX210,			\
223*4882a593Smuzhiyun 	.trans.base_params = &iwl_ax210_base_params,			\
224*4882a593Smuzhiyun 	.min_txq_size = 128,						\
225*4882a593Smuzhiyun 	.gp2_reg_addr = 0xd02c68,					\
226*4882a593Smuzhiyun 	.min_256_ba_txq_size = 1024,					\
227*4882a593Smuzhiyun 	.mon_dram_regs = {						\
228*4882a593Smuzhiyun 		.write_ptr = {						\
229*4882a593Smuzhiyun 			.addr = DBGC_CUR_DBGBUF_STATUS,			\
230*4882a593Smuzhiyun 			.mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK,	\
231*4882a593Smuzhiyun 		},							\
232*4882a593Smuzhiyun 		.cycle_cnt = {						\
233*4882a593Smuzhiyun 			.addr = DBGC_DBGBUF_WRAP_AROUND,		\
234*4882a593Smuzhiyun 			.mask = 0xffffffff,				\
235*4882a593Smuzhiyun 		},							\
236*4882a593Smuzhiyun 		.cur_frag = {						\
237*4882a593Smuzhiyun 			.addr = DBGC_CUR_DBGBUF_STATUS,			\
238*4882a593Smuzhiyun 			.mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK,		\
239*4882a593Smuzhiyun 		},							\
240*4882a593Smuzhiyun 	}
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun const struct iwl_cfg_trans_params iwl_qnj_trans_cfg = {
243*4882a593Smuzhiyun 	.mq_rx_supported = true,
244*4882a593Smuzhiyun 	.use_tfh = true,
245*4882a593Smuzhiyun 	.rf_id = true,
246*4882a593Smuzhiyun 	.gen2 = true,
247*4882a593Smuzhiyun 	.device_family = IWL_DEVICE_FAMILY_22000,
248*4882a593Smuzhiyun 	.base_params = &iwl_22000_base_params,
249*4882a593Smuzhiyun };
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun const struct iwl_cfg_trans_params iwl_qu_trans_cfg = {
252*4882a593Smuzhiyun 	.mq_rx_supported = true,
253*4882a593Smuzhiyun 	.use_tfh = true,
254*4882a593Smuzhiyun 	.rf_id = true,
255*4882a593Smuzhiyun 	.gen2 = true,
256*4882a593Smuzhiyun 	.device_family = IWL_DEVICE_FAMILY_22000,
257*4882a593Smuzhiyun 	.base_params = &iwl_22000_base_params,
258*4882a593Smuzhiyun 	.integrated = true,
259*4882a593Smuzhiyun 	.xtal_latency = 500,
260*4882a593Smuzhiyun 	.ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US,
261*4882a593Smuzhiyun };
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun const struct iwl_cfg_trans_params iwl_qu_medium_latency_trans_cfg = {
264*4882a593Smuzhiyun 	.mq_rx_supported = true,
265*4882a593Smuzhiyun 	.use_tfh = true,
266*4882a593Smuzhiyun 	.rf_id = true,
267*4882a593Smuzhiyun 	.gen2 = true,
268*4882a593Smuzhiyun 	.device_family = IWL_DEVICE_FAMILY_22000,
269*4882a593Smuzhiyun 	.base_params = &iwl_22000_base_params,
270*4882a593Smuzhiyun 	.integrated = true,
271*4882a593Smuzhiyun 	.xtal_latency = 1820,
272*4882a593Smuzhiyun 	.ltr_delay = IWL_CFG_TRANS_LTR_DELAY_1820US,
273*4882a593Smuzhiyun };
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun const struct iwl_cfg_trans_params iwl_qu_long_latency_trans_cfg = {
276*4882a593Smuzhiyun 	.mq_rx_supported = true,
277*4882a593Smuzhiyun 	.use_tfh = true,
278*4882a593Smuzhiyun 	.rf_id = true,
279*4882a593Smuzhiyun 	.gen2 = true,
280*4882a593Smuzhiyun 	.device_family = IWL_DEVICE_FAMILY_22000,
281*4882a593Smuzhiyun 	.base_params = &iwl_22000_base_params,
282*4882a593Smuzhiyun 	.integrated = true,
283*4882a593Smuzhiyun 	.xtal_latency = 12000,
284*4882a593Smuzhiyun 	.low_latency_xtal = true,
285*4882a593Smuzhiyun 	.ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
286*4882a593Smuzhiyun };
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun /*
289*4882a593Smuzhiyun  * If the device doesn't support HE, no need to have that many buffers.
290*4882a593Smuzhiyun  * 22000 devices can split multiple frames into a single RB, so fewer are
291*4882a593Smuzhiyun  * needed; AX210 cannot (but use smaller RBs by default) - these sizes
292*4882a593Smuzhiyun  * were picked according to 8 MSDUs inside 256 A-MSDUs in an A-MPDU, with
293*4882a593Smuzhiyun  * additional overhead to account for processing time.
294*4882a593Smuzhiyun  */
295*4882a593Smuzhiyun #define IWL_NUM_RBDS_NON_HE		512
296*4882a593Smuzhiyun #define IWL_NUM_RBDS_22000_HE		2048
297*4882a593Smuzhiyun #define IWL_NUM_RBDS_AX210_HE		4096
298*4882a593Smuzhiyun 
299*4882a593Smuzhiyun /*
300*4882a593Smuzhiyun  * All JF radio modules are part of the 9000 series, but the MAC part
301*4882a593Smuzhiyun  * looks more like 22000.  That's why this device is here, but called
302*4882a593Smuzhiyun  * 9560 nevertheless.
303*4882a593Smuzhiyun  */
304*4882a593Smuzhiyun const struct iwl_cfg iwl9560_qu_b0_jf_b0_cfg = {
305*4882a593Smuzhiyun 	.fw_name_pre = IWL_QU_B_JF_B_FW_PRE,
306*4882a593Smuzhiyun 	IWL_DEVICE_22500,
307*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_NON_HE,
308*4882a593Smuzhiyun };
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun const struct iwl_cfg iwl9560_qu_c0_jf_b0_cfg = {
311*4882a593Smuzhiyun 	.fw_name_pre = IWL_QU_C_JF_B_FW_PRE,
312*4882a593Smuzhiyun 	IWL_DEVICE_22500,
313*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_NON_HE,
314*4882a593Smuzhiyun };
315*4882a593Smuzhiyun 
316*4882a593Smuzhiyun const struct iwl_cfg iwl9560_quz_a0_jf_b0_cfg = {
317*4882a593Smuzhiyun 	.fw_name_pre = IWL_QUZ_A_JF_B_FW_PRE,
318*4882a593Smuzhiyun 	IWL_DEVICE_22500,
319*4882a593Smuzhiyun 	/*
320*4882a593Smuzhiyun 	 * This device doesn't support receiving BlockAck with a large bitmap
321*4882a593Smuzhiyun 	 * so we need to restrict the size of transmitted aggregation to the
322*4882a593Smuzhiyun 	 * HT size; mac80211 would otherwise pick the HE max (256) by default.
323*4882a593Smuzhiyun 	 */
324*4882a593Smuzhiyun 	.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
325*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_NON_HE,
326*4882a593Smuzhiyun };
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun const struct iwl_cfg iwl9560_qnj_b0_jf_b0_cfg = {
329*4882a593Smuzhiyun 	.fw_name_pre = IWL_QNJ_B_JF_B_FW_PRE,
330*4882a593Smuzhiyun 	IWL_DEVICE_22500,
331*4882a593Smuzhiyun 	/*
332*4882a593Smuzhiyun 	 * This device doesn't support receiving BlockAck with a large bitmap
333*4882a593Smuzhiyun 	 * so we need to restrict the size of transmitted aggregation to the
334*4882a593Smuzhiyun 	 * HT size; mac80211 would otherwise pick the HE max (256) by default.
335*4882a593Smuzhiyun 	 */
336*4882a593Smuzhiyun 	.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
337*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_NON_HE,
338*4882a593Smuzhiyun };
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun const struct iwl_cfg_trans_params iwl_ax200_trans_cfg = {
341*4882a593Smuzhiyun 	.device_family = IWL_DEVICE_FAMILY_22000,
342*4882a593Smuzhiyun 	.base_params = &iwl_22000_base_params,
343*4882a593Smuzhiyun 	.mq_rx_supported = true,
344*4882a593Smuzhiyun 	.use_tfh = true,
345*4882a593Smuzhiyun 	.rf_id = true,
346*4882a593Smuzhiyun 	.gen2 = true,
347*4882a593Smuzhiyun 	.bisr_workaround = 1,
348*4882a593Smuzhiyun };
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun const struct iwl_cfg_trans_params iwl_ma_trans_cfg = {
351*4882a593Smuzhiyun 	.device_family = IWL_DEVICE_FAMILY_AX210,
352*4882a593Smuzhiyun 	.base_params = &iwl_ax210_base_params,
353*4882a593Smuzhiyun 	.mq_rx_supported = true,
354*4882a593Smuzhiyun 	.use_tfh = true,
355*4882a593Smuzhiyun 	.rf_id = true,
356*4882a593Smuzhiyun 	.gen2 = true,
357*4882a593Smuzhiyun 	.integrated = true,
358*4882a593Smuzhiyun 	.umac_prph_offset = 0x300000
359*4882a593Smuzhiyun };
360*4882a593Smuzhiyun 
361*4882a593Smuzhiyun const char iwl_ax101_name[] = "Intel(R) Wi-Fi 6 AX101";
362*4882a593Smuzhiyun const char iwl_ax200_name[] = "Intel(R) Wi-Fi 6 AX200 160MHz";
363*4882a593Smuzhiyun const char iwl_ax201_name[] = "Intel(R) Wi-Fi 6 AX201 160MHz";
364*4882a593Smuzhiyun const char iwl_ax203_name[] = "Intel(R) Wi-Fi 6 AX203";
365*4882a593Smuzhiyun const char iwl_ax211_name[] = "Intel(R) Wi-Fi 6 AX211 160MHz";
366*4882a593Smuzhiyun const char iwl_ax411_name[] = "Intel(R) Wi-Fi 6 AX411 160MHz";
367*4882a593Smuzhiyun const char iwl_ma_name[] = "Intel(R) Wi-Fi 6";
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun const char iwl_ax200_killer_1650w_name[] =
370*4882a593Smuzhiyun 	"Killer(R) Wi-Fi 6 AX1650w 160MHz Wireless Network Adapter (200D2W)";
371*4882a593Smuzhiyun const char iwl_ax200_killer_1650x_name[] =
372*4882a593Smuzhiyun 	"Killer(R) Wi-Fi 6 AX1650x 160MHz Wireless Network Adapter (200NGW)";
373*4882a593Smuzhiyun const char iwl_ax201_killer_1650s_name[] =
374*4882a593Smuzhiyun 	"Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)";
375*4882a593Smuzhiyun const char iwl_ax201_killer_1650i_name[] =
376*4882a593Smuzhiyun 	"Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)";
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun const struct iwl_cfg iwl_qu_b0_hr1_b0 = {
379*4882a593Smuzhiyun 	.fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
380*4882a593Smuzhiyun 	IWL_DEVICE_22500,
381*4882a593Smuzhiyun 	/*
382*4882a593Smuzhiyun 	 * This device doesn't support receiving BlockAck with a large bitmap
383*4882a593Smuzhiyun 	 * so we need to restrict the size of transmitted aggregation to the
384*4882a593Smuzhiyun 	 * HT size; mac80211 would otherwise pick the HE max (256) by default.
385*4882a593Smuzhiyun 	 */
386*4882a593Smuzhiyun 	.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
387*4882a593Smuzhiyun 	.tx_with_siso_diversity = true,
388*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_22000_HE,
389*4882a593Smuzhiyun };
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun const struct iwl_cfg iwl_qu_b0_hr_b0 = {
392*4882a593Smuzhiyun 	.fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
393*4882a593Smuzhiyun 	IWL_DEVICE_22500,
394*4882a593Smuzhiyun 	/*
395*4882a593Smuzhiyun 	 * This device doesn't support receiving BlockAck with a large bitmap
396*4882a593Smuzhiyun 	 * so we need to restrict the size of transmitted aggregation to the
397*4882a593Smuzhiyun 	 * HT size; mac80211 would otherwise pick the HE max (256) by default.
398*4882a593Smuzhiyun 	 */
399*4882a593Smuzhiyun 	.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
400*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_22000_HE,
401*4882a593Smuzhiyun };
402*4882a593Smuzhiyun 
403*4882a593Smuzhiyun const struct iwl_cfg iwl_ax201_cfg_qu_hr = {
404*4882a593Smuzhiyun 	.name = "Intel(R) Wi-Fi 6 AX201 160MHz",
405*4882a593Smuzhiyun 	.fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
406*4882a593Smuzhiyun 	IWL_DEVICE_22500,
407*4882a593Smuzhiyun 	/*
408*4882a593Smuzhiyun 	 * This device doesn't support receiving BlockAck with a large bitmap
409*4882a593Smuzhiyun 	 * so we need to restrict the size of transmitted aggregation to the
410*4882a593Smuzhiyun 	 * HT size; mac80211 would otherwise pick the HE max (256) by default.
411*4882a593Smuzhiyun 	 */
412*4882a593Smuzhiyun 	.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
413*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_22000_HE,
414*4882a593Smuzhiyun };
415*4882a593Smuzhiyun 
416*4882a593Smuzhiyun const struct iwl_cfg iwl_qu_c0_hr1_b0 = {
417*4882a593Smuzhiyun 	.fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
418*4882a593Smuzhiyun 	IWL_DEVICE_22500,
419*4882a593Smuzhiyun 	/*
420*4882a593Smuzhiyun 	 * This device doesn't support receiving BlockAck with a large bitmap
421*4882a593Smuzhiyun 	 * so we need to restrict the size of transmitted aggregation to the
422*4882a593Smuzhiyun 	 * HT size; mac80211 would otherwise pick the HE max (256) by default.
423*4882a593Smuzhiyun 	 */
424*4882a593Smuzhiyun 	.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
425*4882a593Smuzhiyun 	.tx_with_siso_diversity = true,
426*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_22000_HE,
427*4882a593Smuzhiyun };
428*4882a593Smuzhiyun 
429*4882a593Smuzhiyun const struct iwl_cfg iwl_qu_c0_hr_b0 = {
430*4882a593Smuzhiyun 	.fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
431*4882a593Smuzhiyun 	IWL_DEVICE_22500,
432*4882a593Smuzhiyun 	/*
433*4882a593Smuzhiyun 	 * This device doesn't support receiving BlockAck with a large bitmap
434*4882a593Smuzhiyun 	 * so we need to restrict the size of transmitted aggregation to the
435*4882a593Smuzhiyun 	 * HT size; mac80211 would otherwise pick the HE max (256) by default.
436*4882a593Smuzhiyun 	 */
437*4882a593Smuzhiyun 	.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
438*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_22000_HE,
439*4882a593Smuzhiyun };
440*4882a593Smuzhiyun 
441*4882a593Smuzhiyun const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0 = {
442*4882a593Smuzhiyun 	.name = "Intel(R) Wi-Fi 6 AX201 160MHz",
443*4882a593Smuzhiyun 	.fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
444*4882a593Smuzhiyun 	IWL_DEVICE_22500,
445*4882a593Smuzhiyun 	/*
446*4882a593Smuzhiyun 	 * This device doesn't support receiving BlockAck with a large bitmap
447*4882a593Smuzhiyun 	 * so we need to restrict the size of transmitted aggregation to the
448*4882a593Smuzhiyun 	 * HT size; mac80211 would otherwise pick the HE max (256) by default.
449*4882a593Smuzhiyun 	 */
450*4882a593Smuzhiyun 	.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
451*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_22000_HE,
452*4882a593Smuzhiyun };
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun const struct iwl_cfg iwl_quz_a0_hr1_b0 = {
455*4882a593Smuzhiyun 	.fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
456*4882a593Smuzhiyun 	IWL_DEVICE_22500,
457*4882a593Smuzhiyun 	/*
458*4882a593Smuzhiyun 	 * This device doesn't support receiving BlockAck with a large bitmap
459*4882a593Smuzhiyun 	 * so we need to restrict the size of transmitted aggregation to the
460*4882a593Smuzhiyun 	 * HT size; mac80211 would otherwise pick the HE max (256) by default.
461*4882a593Smuzhiyun 	 */
462*4882a593Smuzhiyun 	.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
463*4882a593Smuzhiyun 	.tx_with_siso_diversity = true,
464*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_22000_HE,
465*4882a593Smuzhiyun };
466*4882a593Smuzhiyun 
467*4882a593Smuzhiyun const struct iwl_cfg iwl_ax201_cfg_quz_hr = {
468*4882a593Smuzhiyun 	.name = "Intel(R) Wi-Fi 6 AX201 160MHz",
469*4882a593Smuzhiyun 	.fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
470*4882a593Smuzhiyun 	IWL_DEVICE_22500,
471*4882a593Smuzhiyun 	/*
472*4882a593Smuzhiyun          * This device doesn't support receiving BlockAck with a large bitmap
473*4882a593Smuzhiyun          * so we need to restrict the size of transmitted aggregation to the
474*4882a593Smuzhiyun          * HT size; mac80211 would otherwise pick the HE max (256) by default.
475*4882a593Smuzhiyun          */
476*4882a593Smuzhiyun 	.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
477*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_22000_HE,
478*4882a593Smuzhiyun };
479*4882a593Smuzhiyun 
480*4882a593Smuzhiyun const struct iwl_cfg iwl_ax1650s_cfg_quz_hr = {
481*4882a593Smuzhiyun 	.name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)",
482*4882a593Smuzhiyun 	.fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
483*4882a593Smuzhiyun 	IWL_DEVICE_22500,
484*4882a593Smuzhiyun 	/*
485*4882a593Smuzhiyun          * This device doesn't support receiving BlockAck with a large bitmap
486*4882a593Smuzhiyun          * so we need to restrict the size of transmitted aggregation to the
487*4882a593Smuzhiyun          * HT size; mac80211 would otherwise pick the HE max (256) by default.
488*4882a593Smuzhiyun          */
489*4882a593Smuzhiyun 	.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
490*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_22000_HE,
491*4882a593Smuzhiyun };
492*4882a593Smuzhiyun 
493*4882a593Smuzhiyun const struct iwl_cfg iwl_ax1650i_cfg_quz_hr = {
494*4882a593Smuzhiyun 	.name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)",
495*4882a593Smuzhiyun 	.fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
496*4882a593Smuzhiyun 	IWL_DEVICE_22500,
497*4882a593Smuzhiyun 	/*
498*4882a593Smuzhiyun          * This device doesn't support receiving BlockAck with a large bitmap
499*4882a593Smuzhiyun          * so we need to restrict the size of transmitted aggregation to the
500*4882a593Smuzhiyun          * HT size; mac80211 would otherwise pick the HE max (256) by default.
501*4882a593Smuzhiyun          */
502*4882a593Smuzhiyun 	.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
503*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_22000_HE,
504*4882a593Smuzhiyun };
505*4882a593Smuzhiyun 
506*4882a593Smuzhiyun const struct iwl_cfg iwl_ax200_cfg_cc = {
507*4882a593Smuzhiyun 	.fw_name_pre = IWL_CC_A_FW_PRE,
508*4882a593Smuzhiyun 	IWL_DEVICE_22500,
509*4882a593Smuzhiyun 	/*
510*4882a593Smuzhiyun 	 * This device doesn't support receiving BlockAck with a large bitmap
511*4882a593Smuzhiyun 	 * so we need to restrict the size of transmitted aggregation to the
512*4882a593Smuzhiyun 	 * HT size; mac80211 would otherwise pick the HE max (256) by default.
513*4882a593Smuzhiyun 	 */
514*4882a593Smuzhiyun 	.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
515*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_22000_HE,
516*4882a593Smuzhiyun };
517*4882a593Smuzhiyun 
518*4882a593Smuzhiyun const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0 = {
519*4882a593Smuzhiyun 	.name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)",
520*4882a593Smuzhiyun 	.fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
521*4882a593Smuzhiyun 	IWL_DEVICE_22500,
522*4882a593Smuzhiyun 	/*
523*4882a593Smuzhiyun 	 * This device doesn't support receiving BlockAck with a large bitmap
524*4882a593Smuzhiyun 	 * so we need to restrict the size of transmitted aggregation to the
525*4882a593Smuzhiyun 	 * HT size; mac80211 would otherwise pick the HE max (256) by default.
526*4882a593Smuzhiyun 	 */
527*4882a593Smuzhiyun 	.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
528*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_22000_HE,
529*4882a593Smuzhiyun };
530*4882a593Smuzhiyun 
531*4882a593Smuzhiyun const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0 = {
532*4882a593Smuzhiyun 	.name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)",
533*4882a593Smuzhiyun 	.fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
534*4882a593Smuzhiyun 	IWL_DEVICE_22500,
535*4882a593Smuzhiyun 	/*
536*4882a593Smuzhiyun 	 * This device doesn't support receiving BlockAck with a large bitmap
537*4882a593Smuzhiyun 	 * so we need to restrict the size of transmitted aggregation to the
538*4882a593Smuzhiyun 	 * HT size; mac80211 would otherwise pick the HE max (256) by default.
539*4882a593Smuzhiyun 	 */
540*4882a593Smuzhiyun 	.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
541*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_22000_HE,
542*4882a593Smuzhiyun };
543*4882a593Smuzhiyun 
544*4882a593Smuzhiyun const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0 = {
545*4882a593Smuzhiyun 	.name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)",
546*4882a593Smuzhiyun 	.fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
547*4882a593Smuzhiyun 	IWL_DEVICE_22500,
548*4882a593Smuzhiyun 	/*
549*4882a593Smuzhiyun 	 * This device doesn't support receiving BlockAck with a large bitmap
550*4882a593Smuzhiyun 	 * so we need to restrict the size of transmitted aggregation to the
551*4882a593Smuzhiyun 	 * HT size; mac80211 would otherwise pick the HE max (256) by default.
552*4882a593Smuzhiyun 	 */
553*4882a593Smuzhiyun 	.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
554*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_22000_HE,
555*4882a593Smuzhiyun };
556*4882a593Smuzhiyun 
557*4882a593Smuzhiyun const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0 = {
558*4882a593Smuzhiyun 	.name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)",
559*4882a593Smuzhiyun 	.fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
560*4882a593Smuzhiyun 	IWL_DEVICE_22500,
561*4882a593Smuzhiyun 	/*
562*4882a593Smuzhiyun 	 * This device doesn't support receiving BlockAck with a large bitmap
563*4882a593Smuzhiyun 	 * so we need to restrict the size of transmitted aggregation to the
564*4882a593Smuzhiyun 	 * HT size; mac80211 would otherwise pick the HE max (256) by default.
565*4882a593Smuzhiyun 	 */
566*4882a593Smuzhiyun 	.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
567*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_22000_HE,
568*4882a593Smuzhiyun };
569*4882a593Smuzhiyun 
570*4882a593Smuzhiyun const struct iwl_cfg iwl_qnj_b0_hr_b0_cfg = {
571*4882a593Smuzhiyun 	.fw_name_pre = IWL_QNJ_B_HR_B_FW_PRE,
572*4882a593Smuzhiyun 	IWL_DEVICE_22500,
573*4882a593Smuzhiyun 	/*
574*4882a593Smuzhiyun 	 * This device doesn't support receiving BlockAck with a large bitmap
575*4882a593Smuzhiyun 	 * so we need to restrict the size of transmitted aggregation to the
576*4882a593Smuzhiyun 	 * HT size; mac80211 would otherwise pick the HE max (256) by default.
577*4882a593Smuzhiyun 	 */
578*4882a593Smuzhiyun 	.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
579*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_22000_HE,
580*4882a593Smuzhiyun };
581*4882a593Smuzhiyun 
582*4882a593Smuzhiyun const struct iwl_cfg iwlax210_2ax_cfg_so_jf_a0 = {
583*4882a593Smuzhiyun 	.name = "Intel(R) Wireless-AC 9560 160MHz",
584*4882a593Smuzhiyun 	.fw_name_pre = IWL_SO_A_JF_B_FW_PRE,
585*4882a593Smuzhiyun 	IWL_DEVICE_AX210,
586*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_NON_HE,
587*4882a593Smuzhiyun };
588*4882a593Smuzhiyun 
589*4882a593Smuzhiyun const struct iwl_cfg iwlax210_2ax_cfg_so_hr_a0 = {
590*4882a593Smuzhiyun 	.name = "Intel(R) Wi-Fi 6 AX210 160MHz",
591*4882a593Smuzhiyun 	.fw_name_pre = IWL_SO_A_HR_B_FW_PRE,
592*4882a593Smuzhiyun 	IWL_DEVICE_AX210,
593*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_AX210_HE,
594*4882a593Smuzhiyun };
595*4882a593Smuzhiyun 
596*4882a593Smuzhiyun const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0 = {
597*4882a593Smuzhiyun 	.name = iwl_ax211_name,
598*4882a593Smuzhiyun 	.fw_name_pre = IWL_SO_A_GF_A_FW_PRE,
599*4882a593Smuzhiyun 	.uhb_supported = true,
600*4882a593Smuzhiyun 	IWL_DEVICE_AX210,
601*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_AX210_HE,
602*4882a593Smuzhiyun };
603*4882a593Smuzhiyun 
604*4882a593Smuzhiyun const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long = {
605*4882a593Smuzhiyun 	.name = iwl_ax211_name,
606*4882a593Smuzhiyun 	.fw_name_pre = IWL_SO_A_GF_A_FW_PRE,
607*4882a593Smuzhiyun 	.uhb_supported = true,
608*4882a593Smuzhiyun 	IWL_DEVICE_AX210,
609*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_AX210_HE,
610*4882a593Smuzhiyun 	.trans.xtal_latency = 12000,
611*4882a593Smuzhiyun 	.trans.low_latency_xtal = true,
612*4882a593Smuzhiyun };
613*4882a593Smuzhiyun 
614*4882a593Smuzhiyun const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0 = {
615*4882a593Smuzhiyun 	.name = "Intel(R) Wi-Fi 6 AX210 160MHz",
616*4882a593Smuzhiyun 	.fw_name_pre = IWL_TY_A_GF_A_FW_PRE,
617*4882a593Smuzhiyun 	.uhb_supported = true,
618*4882a593Smuzhiyun 	IWL_DEVICE_AX210,
619*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_AX210_HE,
620*4882a593Smuzhiyun };
621*4882a593Smuzhiyun 
622*4882a593Smuzhiyun const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0 = {
623*4882a593Smuzhiyun 	.name = iwl_ax411_name,
624*4882a593Smuzhiyun 	.fw_name_pre = IWL_SO_A_GF4_A_FW_PRE,
625*4882a593Smuzhiyun 	.uhb_supported = true,
626*4882a593Smuzhiyun 	IWL_DEVICE_AX210,
627*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_AX210_HE,
628*4882a593Smuzhiyun };
629*4882a593Smuzhiyun 
630*4882a593Smuzhiyun const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long = {
631*4882a593Smuzhiyun 	.name = iwl_ax411_name,
632*4882a593Smuzhiyun 	.fw_name_pre = IWL_SO_A_GF4_A_FW_PRE,
633*4882a593Smuzhiyun 	.uhb_supported = true,
634*4882a593Smuzhiyun 	IWL_DEVICE_AX210,
635*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_AX210_HE,
636*4882a593Smuzhiyun 	.trans.xtal_latency = 12000,
637*4882a593Smuzhiyun 	.trans.low_latency_xtal = true,
638*4882a593Smuzhiyun };
639*4882a593Smuzhiyun 
640*4882a593Smuzhiyun const struct iwl_cfg iwlax411_2ax_cfg_sosnj_gf4_a0 = {
641*4882a593Smuzhiyun 	.name = iwl_ax411_name,
642*4882a593Smuzhiyun 	.fw_name_pre = IWL_SNJ_A_GF4_A_FW_PRE,
643*4882a593Smuzhiyun 	.uhb_supported = true,
644*4882a593Smuzhiyun 	IWL_DEVICE_AX210,
645*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_AX210_HE,
646*4882a593Smuzhiyun };
647*4882a593Smuzhiyun 
648*4882a593Smuzhiyun const struct iwl_cfg iwlax211_cfg_snj_gf_a0 = {
649*4882a593Smuzhiyun 	.name = iwl_ax211_name,
650*4882a593Smuzhiyun 	.fw_name_pre = IWL_SNJ_A_GF_A_FW_PRE,
651*4882a593Smuzhiyun 	.uhb_supported = true,
652*4882a593Smuzhiyun 	IWL_DEVICE_AX210,
653*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_AX210_HE,
654*4882a593Smuzhiyun };
655*4882a593Smuzhiyun 
656*4882a593Smuzhiyun const struct iwl_cfg iwlax201_cfg_snj_hr_b0 = {
657*4882a593Smuzhiyun 	.name = iwl_ax201_name,
658*4882a593Smuzhiyun 	.fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
659*4882a593Smuzhiyun 	.uhb_supported = true,
660*4882a593Smuzhiyun 	IWL_DEVICE_AX210,
661*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_AX210_HE,
662*4882a593Smuzhiyun };
663*4882a593Smuzhiyun 
664*4882a593Smuzhiyun const struct iwl_cfg iwl_cfg_ma_a0_gf_a0 = {
665*4882a593Smuzhiyun 	.fw_name_pre = IWL_MA_A_GF_A_FW_PRE,
666*4882a593Smuzhiyun 	.uhb_supported = true,
667*4882a593Smuzhiyun 	IWL_DEVICE_AX210,
668*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_AX210_HE,
669*4882a593Smuzhiyun };
670*4882a593Smuzhiyun 
671*4882a593Smuzhiyun const struct iwl_cfg iwl_cfg_ma_a0_mr_a0 = {
672*4882a593Smuzhiyun 	.fw_name_pre = IWL_MA_A_MR_A_FW_PRE,
673*4882a593Smuzhiyun 	.uhb_supported = true,
674*4882a593Smuzhiyun 	IWL_DEVICE_AX210,
675*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_AX210_HE,
676*4882a593Smuzhiyun };
677*4882a593Smuzhiyun 
678*4882a593Smuzhiyun const struct iwl_cfg iwl_cfg_snj_a0_mr_a0 = {
679*4882a593Smuzhiyun 	.fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE,
680*4882a593Smuzhiyun 	.uhb_supported = true,
681*4882a593Smuzhiyun 	IWL_DEVICE_AX210,
682*4882a593Smuzhiyun 	.num_rbds = IWL_NUM_RBDS_AX210_HE,
683*4882a593Smuzhiyun };
684*4882a593Smuzhiyun 
685*4882a593Smuzhiyun MODULE_FIRMWARE(IWL_QU_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
686*4882a593Smuzhiyun MODULE_FIRMWARE(IWL_QNJ_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
687*4882a593Smuzhiyun MODULE_FIRMWARE(IWL_QU_C_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
688*4882a593Smuzhiyun MODULE_FIRMWARE(IWL_QU_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
689*4882a593Smuzhiyun MODULE_FIRMWARE(IWL_QUZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
690*4882a593Smuzhiyun MODULE_FIRMWARE(IWL_QUZ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
691*4882a593Smuzhiyun MODULE_FIRMWARE(IWL_QNJ_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
692*4882a593Smuzhiyun MODULE_FIRMWARE(IWL_CC_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
693*4882a593Smuzhiyun MODULE_FIRMWARE(IWL_SO_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
694*4882a593Smuzhiyun MODULE_FIRMWARE(IWL_SO_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
695*4882a593Smuzhiyun MODULE_FIRMWARE(IWL_SO_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
696*4882a593Smuzhiyun MODULE_FIRMWARE(IWL_TY_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
697*4882a593Smuzhiyun MODULE_FIRMWARE(IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
698*4882a593Smuzhiyun MODULE_FIRMWARE(IWL_SNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
699*4882a593Smuzhiyun MODULE_FIRMWARE(IWL_SNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
700*4882a593Smuzhiyun MODULE_FIRMWARE(IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
701*4882a593Smuzhiyun MODULE_FIRMWARE(IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
702*4882a593Smuzhiyun MODULE_FIRMWARE(IWL_SNJ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
703