1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /******************************************************************************
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Portions of this file are derived from the ipw3945 project, as well
7*4882a593Smuzhiyun * as portions of the ieee80211 subsystem header files.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Contact Information:
10*4882a593Smuzhiyun * Intel Linux Wireless <ilw@linux.intel.com>
11*4882a593Smuzhiyun * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun *****************************************************************************/
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <linux/kernel.h>
18*4882a593Smuzhiyun #include <linux/module.h>
19*4882a593Smuzhiyun #include <linux/init.h>
20*4882a593Smuzhiyun #include <linux/pci.h>
21*4882a593Smuzhiyun #include <linux/slab.h>
22*4882a593Smuzhiyun #include <linux/dma-mapping.h>
23*4882a593Smuzhiyun #include <linux/delay.h>
24*4882a593Smuzhiyun #include <linux/sched.h>
25*4882a593Smuzhiyun #include <linux/skbuff.h>
26*4882a593Smuzhiyun #include <linux/netdevice.h>
27*4882a593Smuzhiyun #include <linux/firmware.h>
28*4882a593Smuzhiyun #include <linux/etherdevice.h>
29*4882a593Smuzhiyun #include <linux/if_arp.h>
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #include <net/ieee80211_radiotap.h>
32*4882a593Smuzhiyun #include <net/mac80211.h>
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #include <asm/div64.h>
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define DRV_NAME "iwl3945"
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #include "commands.h"
39*4882a593Smuzhiyun #include "common.h"
40*4882a593Smuzhiyun #include "3945.h"
41*4882a593Smuzhiyun #include "iwl-spectrum.h"
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /*
44*4882a593Smuzhiyun * module name, copyright, version, etc.
45*4882a593Smuzhiyun */
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #define DRV_DESCRIPTION \
48*4882a593Smuzhiyun "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun #ifdef CONFIG_IWLEGACY_DEBUG
51*4882a593Smuzhiyun #define VD "d"
52*4882a593Smuzhiyun #else
53*4882a593Smuzhiyun #define VD
54*4882a593Smuzhiyun #endif
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /*
57*4882a593Smuzhiyun * add "s" to indicate spectrum measurement included.
58*4882a593Smuzhiyun * we add it here to be consistent with previous releases in which
59*4882a593Smuzhiyun * this was configurable.
60*4882a593Smuzhiyun */
61*4882a593Smuzhiyun #define DRV_VERSION IWLWIFI_VERSION VD "s"
62*4882a593Smuzhiyun #define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation"
63*4882a593Smuzhiyun #define DRV_AUTHOR "<ilw@linux.intel.com>"
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun MODULE_DESCRIPTION(DRV_DESCRIPTION);
66*4882a593Smuzhiyun MODULE_VERSION(DRV_VERSION);
67*4882a593Smuzhiyun MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
68*4882a593Smuzhiyun MODULE_LICENSE("GPL");
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /* module parameters */
71*4882a593Smuzhiyun struct il_mod_params il3945_mod_params = {
72*4882a593Smuzhiyun .sw_crypto = 1,
73*4882a593Smuzhiyun .restart_fw = 1,
74*4882a593Smuzhiyun .disable_hw_scan = 1,
75*4882a593Smuzhiyun /* the rest are 0 by default */
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /**
79*4882a593Smuzhiyun * il3945_get_antenna_flags - Get antenna flags for RXON command
80*4882a593Smuzhiyun * @il: eeprom and antenna fields are used to determine antenna flags
81*4882a593Smuzhiyun *
82*4882a593Smuzhiyun * il->eeprom39 is used to determine if antenna AUX/MAIN are reversed
83*4882a593Smuzhiyun * il3945_mod_params.antenna specifies the antenna diversity mode:
84*4882a593Smuzhiyun *
85*4882a593Smuzhiyun * IL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
86*4882a593Smuzhiyun * IL_ANTENNA_MAIN - Force MAIN antenna
87*4882a593Smuzhiyun * IL_ANTENNA_AUX - Force AUX antenna
88*4882a593Smuzhiyun */
89*4882a593Smuzhiyun __le32
il3945_get_antenna_flags(const struct il_priv * il)90*4882a593Smuzhiyun il3945_get_antenna_flags(const struct il_priv *il)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun switch (il3945_mod_params.antenna) {
95*4882a593Smuzhiyun case IL_ANTENNA_DIVERSITY:
96*4882a593Smuzhiyun return 0;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun case IL_ANTENNA_MAIN:
99*4882a593Smuzhiyun if (eeprom->antenna_switch_type)
100*4882a593Smuzhiyun return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
101*4882a593Smuzhiyun return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun case IL_ANTENNA_AUX:
104*4882a593Smuzhiyun if (eeprom->antenna_switch_type)
105*4882a593Smuzhiyun return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
106*4882a593Smuzhiyun return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /* bad antenna selector value */
110*4882a593Smuzhiyun IL_ERR("Bad antenna selector value (0x%x)\n",
111*4882a593Smuzhiyun il3945_mod_params.antenna);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun return 0; /* "diversity" is default if error */
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun static int
il3945_set_ccmp_dynamic_key_info(struct il_priv * il,struct ieee80211_key_conf * keyconf,u8 sta_id)117*4882a593Smuzhiyun il3945_set_ccmp_dynamic_key_info(struct il_priv *il,
118*4882a593Smuzhiyun struct ieee80211_key_conf *keyconf, u8 sta_id)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun unsigned long flags;
121*4882a593Smuzhiyun __le16 key_flags = 0;
122*4882a593Smuzhiyun int ret;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
125*4882a593Smuzhiyun key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun if (sta_id == il->hw_params.bcast_id)
128*4882a593Smuzhiyun key_flags |= STA_KEY_MULTICAST_MSK;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
131*4882a593Smuzhiyun keyconf->hw_key_idx = keyconf->keyidx;
132*4882a593Smuzhiyun key_flags &= ~STA_KEY_FLG_INVALID;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun spin_lock_irqsave(&il->sta_lock, flags);
135*4882a593Smuzhiyun il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
136*4882a593Smuzhiyun il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
137*4882a593Smuzhiyun memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun memcpy(il->stations[sta_id].sta.key.key, keyconf->key, keyconf->keylen);
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun if ((il->stations[sta_id].sta.key.
142*4882a593Smuzhiyun key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
143*4882a593Smuzhiyun il->stations[sta_id].sta.key.key_offset =
144*4882a593Smuzhiyun il_get_free_ucode_key_idx(il);
145*4882a593Smuzhiyun /* else, we are overriding an existing key => no need to allocated room
146*4882a593Smuzhiyun * in uCode. */
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
149*4882a593Smuzhiyun "no space for a new key");
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun il->stations[sta_id].sta.key.key_flags = key_flags;
152*4882a593Smuzhiyun il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
153*4882a593Smuzhiyun il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun D_INFO("hwcrypto: modify ucode station key info\n");
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun ret = il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun spin_unlock_irqrestore(&il->sta_lock, flags);
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun return ret;
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun static int
il3945_set_tkip_dynamic_key_info(struct il_priv * il,struct ieee80211_key_conf * keyconf,u8 sta_id)165*4882a593Smuzhiyun il3945_set_tkip_dynamic_key_info(struct il_priv *il,
166*4882a593Smuzhiyun struct ieee80211_key_conf *keyconf, u8 sta_id)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun return -EOPNOTSUPP;
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun static int
il3945_set_wep_dynamic_key_info(struct il_priv * il,struct ieee80211_key_conf * keyconf,u8 sta_id)172*4882a593Smuzhiyun il3945_set_wep_dynamic_key_info(struct il_priv *il,
173*4882a593Smuzhiyun struct ieee80211_key_conf *keyconf, u8 sta_id)
174*4882a593Smuzhiyun {
175*4882a593Smuzhiyun return -EOPNOTSUPP;
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun static int
il3945_clear_sta_key_info(struct il_priv * il,u8 sta_id)179*4882a593Smuzhiyun il3945_clear_sta_key_info(struct il_priv *il, u8 sta_id)
180*4882a593Smuzhiyun {
181*4882a593Smuzhiyun unsigned long flags;
182*4882a593Smuzhiyun struct il_addsta_cmd sta_cmd;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun spin_lock_irqsave(&il->sta_lock, flags);
185*4882a593Smuzhiyun memset(&il->stations[sta_id].keyinfo, 0, sizeof(struct il_hw_key));
186*4882a593Smuzhiyun memset(&il->stations[sta_id].sta.key, 0, sizeof(struct il4965_keyinfo));
187*4882a593Smuzhiyun il->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
188*4882a593Smuzhiyun il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
189*4882a593Smuzhiyun il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
190*4882a593Smuzhiyun memcpy(&sta_cmd, &il->stations[sta_id].sta,
191*4882a593Smuzhiyun sizeof(struct il_addsta_cmd));
192*4882a593Smuzhiyun spin_unlock_irqrestore(&il->sta_lock, flags);
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun D_INFO("hwcrypto: clear ucode station key info\n");
195*4882a593Smuzhiyun return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun static int
il3945_set_dynamic_key(struct il_priv * il,struct ieee80211_key_conf * keyconf,u8 sta_id)199*4882a593Smuzhiyun il3945_set_dynamic_key(struct il_priv *il, struct ieee80211_key_conf *keyconf,
200*4882a593Smuzhiyun u8 sta_id)
201*4882a593Smuzhiyun {
202*4882a593Smuzhiyun int ret = 0;
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun keyconf->hw_key_idx = HW_KEY_DYNAMIC;
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun switch (keyconf->cipher) {
207*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_CCMP:
208*4882a593Smuzhiyun ret = il3945_set_ccmp_dynamic_key_info(il, keyconf, sta_id);
209*4882a593Smuzhiyun break;
210*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_TKIP:
211*4882a593Smuzhiyun ret = il3945_set_tkip_dynamic_key_info(il, keyconf, sta_id);
212*4882a593Smuzhiyun break;
213*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_WEP40:
214*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_WEP104:
215*4882a593Smuzhiyun ret = il3945_set_wep_dynamic_key_info(il, keyconf, sta_id);
216*4882a593Smuzhiyun break;
217*4882a593Smuzhiyun default:
218*4882a593Smuzhiyun IL_ERR("Unknown alg: %s alg=%x\n", __func__, keyconf->cipher);
219*4882a593Smuzhiyun ret = -EINVAL;
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun D_WEP("Set dynamic key: alg=%x len=%d idx=%d sta=%d ret=%d\n",
223*4882a593Smuzhiyun keyconf->cipher, keyconf->keylen, keyconf->keyidx, sta_id, ret);
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun return ret;
226*4882a593Smuzhiyun }
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun static int
il3945_remove_static_key(struct il_priv * il)229*4882a593Smuzhiyun il3945_remove_static_key(struct il_priv *il)
230*4882a593Smuzhiyun {
231*4882a593Smuzhiyun return -EOPNOTSUPP;
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun static int
il3945_set_static_key(struct il_priv * il,struct ieee80211_key_conf * key)235*4882a593Smuzhiyun il3945_set_static_key(struct il_priv *il, struct ieee80211_key_conf *key)
236*4882a593Smuzhiyun {
237*4882a593Smuzhiyun if (key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
238*4882a593Smuzhiyun key->cipher == WLAN_CIPHER_SUITE_WEP104)
239*4882a593Smuzhiyun return -EOPNOTSUPP;
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun IL_ERR("Static key invalid: cipher %x\n", key->cipher);
242*4882a593Smuzhiyun return -EINVAL;
243*4882a593Smuzhiyun }
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun static void
il3945_clear_free_frames(struct il_priv * il)246*4882a593Smuzhiyun il3945_clear_free_frames(struct il_priv *il)
247*4882a593Smuzhiyun {
248*4882a593Smuzhiyun struct list_head *element;
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun D_INFO("%d frames on pre-allocated heap on clear.\n", il->frames_count);
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun while (!list_empty(&il->free_frames)) {
253*4882a593Smuzhiyun element = il->free_frames.next;
254*4882a593Smuzhiyun list_del(element);
255*4882a593Smuzhiyun kfree(list_entry(element, struct il3945_frame, list));
256*4882a593Smuzhiyun il->frames_count--;
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun if (il->frames_count) {
260*4882a593Smuzhiyun IL_WARN("%d frames still in use. Did we lose one?\n",
261*4882a593Smuzhiyun il->frames_count);
262*4882a593Smuzhiyun il->frames_count = 0;
263*4882a593Smuzhiyun }
264*4882a593Smuzhiyun }
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun static struct il3945_frame *
il3945_get_free_frame(struct il_priv * il)267*4882a593Smuzhiyun il3945_get_free_frame(struct il_priv *il)
268*4882a593Smuzhiyun {
269*4882a593Smuzhiyun struct il3945_frame *frame;
270*4882a593Smuzhiyun struct list_head *element;
271*4882a593Smuzhiyun if (list_empty(&il->free_frames)) {
272*4882a593Smuzhiyun frame = kzalloc(sizeof(*frame), GFP_KERNEL);
273*4882a593Smuzhiyun if (!frame) {
274*4882a593Smuzhiyun IL_ERR("Could not allocate frame!\n");
275*4882a593Smuzhiyun return NULL;
276*4882a593Smuzhiyun }
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun il->frames_count++;
279*4882a593Smuzhiyun return frame;
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun element = il->free_frames.next;
283*4882a593Smuzhiyun list_del(element);
284*4882a593Smuzhiyun return list_entry(element, struct il3945_frame, list);
285*4882a593Smuzhiyun }
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun static void
il3945_free_frame(struct il_priv * il,struct il3945_frame * frame)288*4882a593Smuzhiyun il3945_free_frame(struct il_priv *il, struct il3945_frame *frame)
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun memset(frame, 0, sizeof(*frame));
291*4882a593Smuzhiyun list_add(&frame->list, &il->free_frames);
292*4882a593Smuzhiyun }
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun unsigned int
il3945_fill_beacon_frame(struct il_priv * il,struct ieee80211_hdr * hdr,int left)295*4882a593Smuzhiyun il3945_fill_beacon_frame(struct il_priv *il, struct ieee80211_hdr *hdr,
296*4882a593Smuzhiyun int left)
297*4882a593Smuzhiyun {
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun if (!il_is_associated(il) || !il->beacon_skb)
300*4882a593Smuzhiyun return 0;
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun if (il->beacon_skb->len > left)
303*4882a593Smuzhiyun return 0;
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len);
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun return il->beacon_skb->len;
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun static int
il3945_send_beacon_cmd(struct il_priv * il)311*4882a593Smuzhiyun il3945_send_beacon_cmd(struct il_priv *il)
312*4882a593Smuzhiyun {
313*4882a593Smuzhiyun struct il3945_frame *frame;
314*4882a593Smuzhiyun unsigned int frame_size;
315*4882a593Smuzhiyun int rc;
316*4882a593Smuzhiyun u8 rate;
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun frame = il3945_get_free_frame(il);
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun if (!frame) {
321*4882a593Smuzhiyun IL_ERR("Could not obtain free frame buffer for beacon "
322*4882a593Smuzhiyun "command.\n");
323*4882a593Smuzhiyun return -ENOMEM;
324*4882a593Smuzhiyun }
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun rate = il_get_lowest_plcp(il);
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun frame_size = il3945_hw_get_beacon_cmd(il, frame, rate);
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun rc = il_send_cmd_pdu(il, C_TX_BEACON, frame_size, &frame->u.cmd[0]);
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun il3945_free_frame(il, frame);
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun return rc;
335*4882a593Smuzhiyun }
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun static void
il3945_unset_hw_params(struct il_priv * il)338*4882a593Smuzhiyun il3945_unset_hw_params(struct il_priv *il)
339*4882a593Smuzhiyun {
340*4882a593Smuzhiyun if (il->_3945.shared_virt)
341*4882a593Smuzhiyun dma_free_coherent(&il->pci_dev->dev,
342*4882a593Smuzhiyun sizeof(struct il3945_shared),
343*4882a593Smuzhiyun il->_3945.shared_virt, il->_3945.shared_phys);
344*4882a593Smuzhiyun }
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun static void
il3945_build_tx_cmd_hwcrypto(struct il_priv * il,struct ieee80211_tx_info * info,struct il_device_cmd * cmd,struct sk_buff * skb_frag,int sta_id)347*4882a593Smuzhiyun il3945_build_tx_cmd_hwcrypto(struct il_priv *il, struct ieee80211_tx_info *info,
348*4882a593Smuzhiyun struct il_device_cmd *cmd,
349*4882a593Smuzhiyun struct sk_buff *skb_frag, int sta_id)
350*4882a593Smuzhiyun {
351*4882a593Smuzhiyun struct il3945_tx_cmd *tx_cmd = (struct il3945_tx_cmd *)cmd->cmd.payload;
352*4882a593Smuzhiyun struct il_hw_key *keyinfo = &il->stations[sta_id].keyinfo;
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun tx_cmd->sec_ctl = 0;
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun switch (keyinfo->cipher) {
357*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_CCMP:
358*4882a593Smuzhiyun tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
359*4882a593Smuzhiyun memcpy(tx_cmd->key, keyinfo->key, keyinfo->keylen);
360*4882a593Smuzhiyun D_TX("tx_cmd with AES hwcrypto\n");
361*4882a593Smuzhiyun break;
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_TKIP:
364*4882a593Smuzhiyun break;
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_WEP104:
367*4882a593Smuzhiyun tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
368*4882a593Smuzhiyun fallthrough;
369*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_WEP40:
370*4882a593Smuzhiyun tx_cmd->sec_ctl |=
371*4882a593Smuzhiyun TX_CMD_SEC_WEP | (info->control.hw_key->
372*4882a593Smuzhiyun hw_key_idx & TX_CMD_SEC_MSK) <<
373*4882a593Smuzhiyun TX_CMD_SEC_SHIFT;
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun memcpy(&tx_cmd->key[3], keyinfo->key, keyinfo->keylen);
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun D_TX("Configuring packet for WEP encryption " "with key %d\n",
378*4882a593Smuzhiyun info->control.hw_key->hw_key_idx);
379*4882a593Smuzhiyun break;
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun default:
382*4882a593Smuzhiyun IL_ERR("Unknown encode cipher %x\n", keyinfo->cipher);
383*4882a593Smuzhiyun break;
384*4882a593Smuzhiyun }
385*4882a593Smuzhiyun }
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun /*
388*4882a593Smuzhiyun * handle build C_TX command notification.
389*4882a593Smuzhiyun */
390*4882a593Smuzhiyun static void
il3945_build_tx_cmd_basic(struct il_priv * il,struct il_device_cmd * cmd,struct ieee80211_tx_info * info,struct ieee80211_hdr * hdr,u8 std_id)391*4882a593Smuzhiyun il3945_build_tx_cmd_basic(struct il_priv *il, struct il_device_cmd *cmd,
392*4882a593Smuzhiyun struct ieee80211_tx_info *info,
393*4882a593Smuzhiyun struct ieee80211_hdr *hdr, u8 std_id)
394*4882a593Smuzhiyun {
395*4882a593Smuzhiyun struct il3945_tx_cmd *tx_cmd = (struct il3945_tx_cmd *)cmd->cmd.payload;
396*4882a593Smuzhiyun __le32 tx_flags = tx_cmd->tx_flags;
397*4882a593Smuzhiyun __le16 fc = hdr->frame_control;
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
400*4882a593Smuzhiyun if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
401*4882a593Smuzhiyun tx_flags |= TX_CMD_FLG_ACK_MSK;
402*4882a593Smuzhiyun if (ieee80211_is_mgmt(fc))
403*4882a593Smuzhiyun tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
404*4882a593Smuzhiyun if (ieee80211_is_probe_resp(fc) &&
405*4882a593Smuzhiyun !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
406*4882a593Smuzhiyun tx_flags |= TX_CMD_FLG_TSF_MSK;
407*4882a593Smuzhiyun } else {
408*4882a593Smuzhiyun tx_flags &= (~TX_CMD_FLG_ACK_MSK);
409*4882a593Smuzhiyun tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
410*4882a593Smuzhiyun }
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun tx_cmd->sta_id = std_id;
413*4882a593Smuzhiyun if (ieee80211_has_morefrags(fc))
414*4882a593Smuzhiyun tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun if (ieee80211_is_data_qos(fc)) {
417*4882a593Smuzhiyun u8 *qc = ieee80211_get_qos_ctl(hdr);
418*4882a593Smuzhiyun tx_cmd->tid_tspec = qc[0] & 0xf;
419*4882a593Smuzhiyun tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
420*4882a593Smuzhiyun } else {
421*4882a593Smuzhiyun tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
422*4882a593Smuzhiyun }
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun il_tx_cmd_protection(il, info, fc, &tx_flags);
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
427*4882a593Smuzhiyun if (ieee80211_is_mgmt(fc)) {
428*4882a593Smuzhiyun if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
429*4882a593Smuzhiyun tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
430*4882a593Smuzhiyun else
431*4882a593Smuzhiyun tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
432*4882a593Smuzhiyun } else {
433*4882a593Smuzhiyun tx_cmd->timeout.pm_frame_timeout = 0;
434*4882a593Smuzhiyun }
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun tx_cmd->driver_txop = 0;
437*4882a593Smuzhiyun tx_cmd->tx_flags = tx_flags;
438*4882a593Smuzhiyun tx_cmd->next_frame_len = 0;
439*4882a593Smuzhiyun }
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun /*
442*4882a593Smuzhiyun * start C_TX command process
443*4882a593Smuzhiyun */
444*4882a593Smuzhiyun static int
il3945_tx_skb(struct il_priv * il,struct ieee80211_sta * sta,struct sk_buff * skb)445*4882a593Smuzhiyun il3945_tx_skb(struct il_priv *il,
446*4882a593Smuzhiyun struct ieee80211_sta *sta,
447*4882a593Smuzhiyun struct sk_buff *skb)
448*4882a593Smuzhiyun {
449*4882a593Smuzhiyun struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
450*4882a593Smuzhiyun struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
451*4882a593Smuzhiyun struct il3945_tx_cmd *tx_cmd;
452*4882a593Smuzhiyun struct il_tx_queue *txq = NULL;
453*4882a593Smuzhiyun struct il_queue *q = NULL;
454*4882a593Smuzhiyun struct il_device_cmd *out_cmd;
455*4882a593Smuzhiyun struct il_cmd_meta *out_meta;
456*4882a593Smuzhiyun dma_addr_t phys_addr;
457*4882a593Smuzhiyun dma_addr_t txcmd_phys;
458*4882a593Smuzhiyun int txq_id = skb_get_queue_mapping(skb);
459*4882a593Smuzhiyun u16 len, idx, hdr_len;
460*4882a593Smuzhiyun u16 firstlen, secondlen;
461*4882a593Smuzhiyun u8 sta_id;
462*4882a593Smuzhiyun u8 tid = 0;
463*4882a593Smuzhiyun __le16 fc;
464*4882a593Smuzhiyun u8 wait_write_ptr = 0;
465*4882a593Smuzhiyun unsigned long flags;
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun spin_lock_irqsave(&il->lock, flags);
468*4882a593Smuzhiyun if (il_is_rfkill(il)) {
469*4882a593Smuzhiyun D_DROP("Dropping - RF KILL\n");
470*4882a593Smuzhiyun goto drop_unlock;
471*4882a593Smuzhiyun }
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun if ((ieee80211_get_tx_rate(il->hw, info)->hw_value & 0xFF) ==
474*4882a593Smuzhiyun IL_INVALID_RATE) {
475*4882a593Smuzhiyun IL_ERR("ERROR: No TX rate available.\n");
476*4882a593Smuzhiyun goto drop_unlock;
477*4882a593Smuzhiyun }
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun fc = hdr->frame_control;
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun #ifdef CONFIG_IWLEGACY_DEBUG
482*4882a593Smuzhiyun if (ieee80211_is_auth(fc))
483*4882a593Smuzhiyun D_TX("Sending AUTH frame\n");
484*4882a593Smuzhiyun else if (ieee80211_is_assoc_req(fc))
485*4882a593Smuzhiyun D_TX("Sending ASSOC frame\n");
486*4882a593Smuzhiyun else if (ieee80211_is_reassoc_req(fc))
487*4882a593Smuzhiyun D_TX("Sending REASSOC frame\n");
488*4882a593Smuzhiyun #endif
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun spin_unlock_irqrestore(&il->lock, flags);
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun hdr_len = ieee80211_hdrlen(fc);
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun /* Find idx into station table for destination station */
495*4882a593Smuzhiyun sta_id = il_sta_id_or_broadcast(il, sta);
496*4882a593Smuzhiyun if (sta_id == IL_INVALID_STATION) {
497*4882a593Smuzhiyun D_DROP("Dropping - INVALID STATION: %pM\n", hdr->addr1);
498*4882a593Smuzhiyun goto drop;
499*4882a593Smuzhiyun }
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun D_RATE("station Id %d\n", sta_id);
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun if (ieee80211_is_data_qos(fc)) {
504*4882a593Smuzhiyun u8 *qc = ieee80211_get_qos_ctl(hdr);
505*4882a593Smuzhiyun tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
506*4882a593Smuzhiyun if (unlikely(tid >= MAX_TID_COUNT))
507*4882a593Smuzhiyun goto drop;
508*4882a593Smuzhiyun }
509*4882a593Smuzhiyun
510*4882a593Smuzhiyun /* Descriptor for chosen Tx queue */
511*4882a593Smuzhiyun txq = &il->txq[txq_id];
512*4882a593Smuzhiyun q = &txq->q;
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun if ((il_queue_space(q) < q->high_mark))
515*4882a593Smuzhiyun goto drop;
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun spin_lock_irqsave(&il->lock, flags);
518*4882a593Smuzhiyun
519*4882a593Smuzhiyun idx = il_get_cmd_idx(q, q->write_ptr, 0);
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun txq->skbs[q->write_ptr] = skb;
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun /* Init first empty entry in queue's array of Tx/cmd buffers */
524*4882a593Smuzhiyun out_cmd = txq->cmd[idx];
525*4882a593Smuzhiyun out_meta = &txq->meta[idx];
526*4882a593Smuzhiyun tx_cmd = (struct il3945_tx_cmd *)out_cmd->cmd.payload;
527*4882a593Smuzhiyun memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
528*4882a593Smuzhiyun memset(tx_cmd, 0, sizeof(*tx_cmd));
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun /*
531*4882a593Smuzhiyun * Set up the Tx-command (not MAC!) header.
532*4882a593Smuzhiyun * Store the chosen Tx queue and TFD idx within the sequence field;
533*4882a593Smuzhiyun * after Tx, uCode's Tx response will return this value so driver can
534*4882a593Smuzhiyun * locate the frame within the tx queue and do post-tx processing.
535*4882a593Smuzhiyun */
536*4882a593Smuzhiyun out_cmd->hdr.cmd = C_TX;
537*4882a593Smuzhiyun out_cmd->hdr.sequence =
538*4882a593Smuzhiyun cpu_to_le16((u16)
539*4882a593Smuzhiyun (QUEUE_TO_SEQ(txq_id) | IDX_TO_SEQ(q->write_ptr)));
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun /* Copy MAC header from skb into command buffer */
542*4882a593Smuzhiyun memcpy(tx_cmd->hdr, hdr, hdr_len);
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun if (info->control.hw_key)
545*4882a593Smuzhiyun il3945_build_tx_cmd_hwcrypto(il, info, out_cmd, skb, sta_id);
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun /* TODO need this for burst mode later on */
548*4882a593Smuzhiyun il3945_build_tx_cmd_basic(il, out_cmd, info, hdr, sta_id);
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun il3945_hw_build_tx_cmd_rate(il, out_cmd, info, hdr, sta_id);
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun /* Total # bytes to be transmitted */
553*4882a593Smuzhiyun tx_cmd->len = cpu_to_le16((u16) skb->len);
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
556*4882a593Smuzhiyun tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun /*
559*4882a593Smuzhiyun * Use the first empty entry in this queue's command buffer array
560*4882a593Smuzhiyun * to contain the Tx command and MAC header concatenated together
561*4882a593Smuzhiyun * (payload data will be in another buffer).
562*4882a593Smuzhiyun * Size of this varies, due to varying MAC header length.
563*4882a593Smuzhiyun * If end is not dword aligned, we'll have 2 extra bytes at the end
564*4882a593Smuzhiyun * of the MAC header (device reads on dword boundaries).
565*4882a593Smuzhiyun * We'll tell device about this padding later.
566*4882a593Smuzhiyun */
567*4882a593Smuzhiyun len =
568*4882a593Smuzhiyun sizeof(struct il3945_tx_cmd) + sizeof(struct il_cmd_header) +
569*4882a593Smuzhiyun hdr_len;
570*4882a593Smuzhiyun firstlen = (len + 3) & ~3;
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun /* Physical address of this Tx command's header (not MAC header!),
573*4882a593Smuzhiyun * within command buffer array. */
574*4882a593Smuzhiyun txcmd_phys =
575*4882a593Smuzhiyun pci_map_single(il->pci_dev, &out_cmd->hdr, firstlen,
576*4882a593Smuzhiyun PCI_DMA_TODEVICE);
577*4882a593Smuzhiyun if (unlikely(pci_dma_mapping_error(il->pci_dev, txcmd_phys)))
578*4882a593Smuzhiyun goto drop_unlock;
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun /* Set up TFD's 2nd entry to point directly to remainder of skb,
581*4882a593Smuzhiyun * if any (802.11 null frames have no payload). */
582*4882a593Smuzhiyun secondlen = skb->len - hdr_len;
583*4882a593Smuzhiyun if (secondlen > 0) {
584*4882a593Smuzhiyun phys_addr =
585*4882a593Smuzhiyun pci_map_single(il->pci_dev, skb->data + hdr_len, secondlen,
586*4882a593Smuzhiyun PCI_DMA_TODEVICE);
587*4882a593Smuzhiyun if (unlikely(pci_dma_mapping_error(il->pci_dev, phys_addr)))
588*4882a593Smuzhiyun goto drop_unlock;
589*4882a593Smuzhiyun }
590*4882a593Smuzhiyun
591*4882a593Smuzhiyun /* Add buffer containing Tx command and MAC(!) header to TFD's
592*4882a593Smuzhiyun * first entry */
593*4882a593Smuzhiyun il->ops->txq_attach_buf_to_tfd(il, txq, txcmd_phys, firstlen, 1, 0);
594*4882a593Smuzhiyun dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
595*4882a593Smuzhiyun dma_unmap_len_set(out_meta, len, firstlen);
596*4882a593Smuzhiyun if (secondlen > 0)
597*4882a593Smuzhiyun il->ops->txq_attach_buf_to_tfd(il, txq, phys_addr, secondlen, 0,
598*4882a593Smuzhiyun U32_PAD(secondlen));
599*4882a593Smuzhiyun
600*4882a593Smuzhiyun if (!ieee80211_has_morefrags(hdr->frame_control)) {
601*4882a593Smuzhiyun txq->need_update = 1;
602*4882a593Smuzhiyun } else {
603*4882a593Smuzhiyun wait_write_ptr = 1;
604*4882a593Smuzhiyun txq->need_update = 0;
605*4882a593Smuzhiyun }
606*4882a593Smuzhiyun
607*4882a593Smuzhiyun il_update_stats(il, true, fc, skb->len);
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun D_TX("sequence nr = 0X%x\n", le16_to_cpu(out_cmd->hdr.sequence));
610*4882a593Smuzhiyun D_TX("tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
611*4882a593Smuzhiyun il_print_hex_dump(il, IL_DL_TX, tx_cmd, sizeof(*tx_cmd));
612*4882a593Smuzhiyun il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd->hdr,
613*4882a593Smuzhiyun ieee80211_hdrlen(fc));
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun /* Tell device the write idx *just past* this latest filled TFD */
616*4882a593Smuzhiyun q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
617*4882a593Smuzhiyun il_txq_update_write_ptr(il, txq);
618*4882a593Smuzhiyun spin_unlock_irqrestore(&il->lock, flags);
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun if (il_queue_space(q) < q->high_mark && il->mac80211_registered) {
621*4882a593Smuzhiyun if (wait_write_ptr) {
622*4882a593Smuzhiyun spin_lock_irqsave(&il->lock, flags);
623*4882a593Smuzhiyun txq->need_update = 1;
624*4882a593Smuzhiyun il_txq_update_write_ptr(il, txq);
625*4882a593Smuzhiyun spin_unlock_irqrestore(&il->lock, flags);
626*4882a593Smuzhiyun }
627*4882a593Smuzhiyun
628*4882a593Smuzhiyun il_stop_queue(il, txq);
629*4882a593Smuzhiyun }
630*4882a593Smuzhiyun
631*4882a593Smuzhiyun return 0;
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun drop_unlock:
634*4882a593Smuzhiyun spin_unlock_irqrestore(&il->lock, flags);
635*4882a593Smuzhiyun drop:
636*4882a593Smuzhiyun return -1;
637*4882a593Smuzhiyun }
638*4882a593Smuzhiyun
639*4882a593Smuzhiyun static int
il3945_get_measurement(struct il_priv * il,struct ieee80211_measurement_params * params,u8 type)640*4882a593Smuzhiyun il3945_get_measurement(struct il_priv *il,
641*4882a593Smuzhiyun struct ieee80211_measurement_params *params, u8 type)
642*4882a593Smuzhiyun {
643*4882a593Smuzhiyun struct il_spectrum_cmd spectrum;
644*4882a593Smuzhiyun struct il_rx_pkt *pkt;
645*4882a593Smuzhiyun struct il_host_cmd cmd = {
646*4882a593Smuzhiyun .id = C_SPECTRUM_MEASUREMENT,
647*4882a593Smuzhiyun .data = (void *)&spectrum,
648*4882a593Smuzhiyun .flags = CMD_WANT_SKB,
649*4882a593Smuzhiyun };
650*4882a593Smuzhiyun u32 add_time = le64_to_cpu(params->start_time);
651*4882a593Smuzhiyun int rc;
652*4882a593Smuzhiyun int spectrum_resp_status;
653*4882a593Smuzhiyun int duration = le16_to_cpu(params->duration);
654*4882a593Smuzhiyun
655*4882a593Smuzhiyun if (il_is_associated(il))
656*4882a593Smuzhiyun add_time =
657*4882a593Smuzhiyun il_usecs_to_beacons(il,
658*4882a593Smuzhiyun le64_to_cpu(params->start_time) -
659*4882a593Smuzhiyun il->_3945.last_tsf,
660*4882a593Smuzhiyun le16_to_cpu(il->timing.beacon_interval));
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun memset(&spectrum, 0, sizeof(spectrum));
663*4882a593Smuzhiyun
664*4882a593Smuzhiyun spectrum.channel_count = cpu_to_le16(1);
665*4882a593Smuzhiyun spectrum.flags =
666*4882a593Smuzhiyun RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
667*4882a593Smuzhiyun spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
668*4882a593Smuzhiyun cmd.len = sizeof(spectrum);
669*4882a593Smuzhiyun spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
670*4882a593Smuzhiyun
671*4882a593Smuzhiyun if (il_is_associated(il))
672*4882a593Smuzhiyun spectrum.start_time =
673*4882a593Smuzhiyun il_add_beacon_time(il, il->_3945.last_beacon_time, add_time,
674*4882a593Smuzhiyun le16_to_cpu(il->timing.beacon_interval));
675*4882a593Smuzhiyun else
676*4882a593Smuzhiyun spectrum.start_time = 0;
677*4882a593Smuzhiyun
678*4882a593Smuzhiyun spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
679*4882a593Smuzhiyun spectrum.channels[0].channel = params->channel;
680*4882a593Smuzhiyun spectrum.channels[0].type = type;
681*4882a593Smuzhiyun if (il->active.flags & RXON_FLG_BAND_24G_MSK)
682*4882a593Smuzhiyun spectrum.flags |=
683*4882a593Smuzhiyun RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK |
684*4882a593Smuzhiyun RXON_FLG_TGG_PROTECT_MSK;
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun rc = il_send_cmd_sync(il, &cmd);
687*4882a593Smuzhiyun if (rc)
688*4882a593Smuzhiyun return rc;
689*4882a593Smuzhiyun
690*4882a593Smuzhiyun pkt = (struct il_rx_pkt *)cmd.reply_page;
691*4882a593Smuzhiyun if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
692*4882a593Smuzhiyun IL_ERR("Bad return from N_RX_ON_ASSOC command\n");
693*4882a593Smuzhiyun rc = -EIO;
694*4882a593Smuzhiyun }
695*4882a593Smuzhiyun
696*4882a593Smuzhiyun spectrum_resp_status = le16_to_cpu(pkt->u.spectrum.status);
697*4882a593Smuzhiyun switch (spectrum_resp_status) {
698*4882a593Smuzhiyun case 0: /* Command will be handled */
699*4882a593Smuzhiyun if (pkt->u.spectrum.id != 0xff) {
700*4882a593Smuzhiyun D_INFO("Replaced existing measurement: %d\n",
701*4882a593Smuzhiyun pkt->u.spectrum.id);
702*4882a593Smuzhiyun il->measurement_status &= ~MEASUREMENT_READY;
703*4882a593Smuzhiyun }
704*4882a593Smuzhiyun il->measurement_status |= MEASUREMENT_ACTIVE;
705*4882a593Smuzhiyun rc = 0;
706*4882a593Smuzhiyun break;
707*4882a593Smuzhiyun
708*4882a593Smuzhiyun case 1: /* Command will not be handled */
709*4882a593Smuzhiyun rc = -EAGAIN;
710*4882a593Smuzhiyun break;
711*4882a593Smuzhiyun }
712*4882a593Smuzhiyun
713*4882a593Smuzhiyun il_free_pages(il, cmd.reply_page);
714*4882a593Smuzhiyun
715*4882a593Smuzhiyun return rc;
716*4882a593Smuzhiyun }
717*4882a593Smuzhiyun
718*4882a593Smuzhiyun static void
il3945_hdl_alive(struct il_priv * il,struct il_rx_buf * rxb)719*4882a593Smuzhiyun il3945_hdl_alive(struct il_priv *il, struct il_rx_buf *rxb)
720*4882a593Smuzhiyun {
721*4882a593Smuzhiyun struct il_rx_pkt *pkt = rxb_addr(rxb);
722*4882a593Smuzhiyun struct il_alive_resp *palive;
723*4882a593Smuzhiyun struct delayed_work *pwork;
724*4882a593Smuzhiyun
725*4882a593Smuzhiyun palive = &pkt->u.alive_frame;
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun D_INFO("Alive ucode status 0x%08X revision " "0x%01X 0x%01X\n",
728*4882a593Smuzhiyun palive->is_valid, palive->ver_type, palive->ver_subtype);
729*4882a593Smuzhiyun
730*4882a593Smuzhiyun if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
731*4882a593Smuzhiyun D_INFO("Initialization Alive received.\n");
732*4882a593Smuzhiyun memcpy(&il->card_alive_init, &pkt->u.alive_frame,
733*4882a593Smuzhiyun sizeof(struct il_alive_resp));
734*4882a593Smuzhiyun pwork = &il->init_alive_start;
735*4882a593Smuzhiyun } else {
736*4882a593Smuzhiyun D_INFO("Runtime Alive received.\n");
737*4882a593Smuzhiyun memcpy(&il->card_alive, &pkt->u.alive_frame,
738*4882a593Smuzhiyun sizeof(struct il_alive_resp));
739*4882a593Smuzhiyun pwork = &il->alive_start;
740*4882a593Smuzhiyun il3945_disable_events(il);
741*4882a593Smuzhiyun }
742*4882a593Smuzhiyun
743*4882a593Smuzhiyun /* We delay the ALIVE response by 5ms to
744*4882a593Smuzhiyun * give the HW RF Kill time to activate... */
745*4882a593Smuzhiyun if (palive->is_valid == UCODE_VALID_OK)
746*4882a593Smuzhiyun queue_delayed_work(il->workqueue, pwork, msecs_to_jiffies(5));
747*4882a593Smuzhiyun else
748*4882a593Smuzhiyun IL_WARN("uCode did not respond OK.\n");
749*4882a593Smuzhiyun }
750*4882a593Smuzhiyun
751*4882a593Smuzhiyun static void
il3945_hdl_add_sta(struct il_priv * il,struct il_rx_buf * rxb)752*4882a593Smuzhiyun il3945_hdl_add_sta(struct il_priv *il, struct il_rx_buf *rxb)
753*4882a593Smuzhiyun {
754*4882a593Smuzhiyun #ifdef CONFIG_IWLEGACY_DEBUG
755*4882a593Smuzhiyun struct il_rx_pkt *pkt = rxb_addr(rxb);
756*4882a593Smuzhiyun #endif
757*4882a593Smuzhiyun
758*4882a593Smuzhiyun D_RX("Received C_ADD_STA: 0x%02X\n", pkt->u.status);
759*4882a593Smuzhiyun }
760*4882a593Smuzhiyun
761*4882a593Smuzhiyun static void
il3945_hdl_beacon(struct il_priv * il,struct il_rx_buf * rxb)762*4882a593Smuzhiyun il3945_hdl_beacon(struct il_priv *il, struct il_rx_buf *rxb)
763*4882a593Smuzhiyun {
764*4882a593Smuzhiyun struct il_rx_pkt *pkt = rxb_addr(rxb);
765*4882a593Smuzhiyun struct il3945_beacon_notif *beacon = &(pkt->u.beacon_status);
766*4882a593Smuzhiyun #ifdef CONFIG_IWLEGACY_DEBUG
767*4882a593Smuzhiyun u8 rate = beacon->beacon_notify_hdr.rate;
768*4882a593Smuzhiyun
769*4882a593Smuzhiyun D_RX("beacon status %x retries %d iss %d " "tsf %d %d rate %d\n",
770*4882a593Smuzhiyun le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
771*4882a593Smuzhiyun beacon->beacon_notify_hdr.failure_frame,
772*4882a593Smuzhiyun le32_to_cpu(beacon->ibss_mgr_status),
773*4882a593Smuzhiyun le32_to_cpu(beacon->high_tsf), le32_to_cpu(beacon->low_tsf), rate);
774*4882a593Smuzhiyun #endif
775*4882a593Smuzhiyun
776*4882a593Smuzhiyun il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
777*4882a593Smuzhiyun
778*4882a593Smuzhiyun }
779*4882a593Smuzhiyun
780*4882a593Smuzhiyun /* Handle notification from uCode that card's power state is changing
781*4882a593Smuzhiyun * due to software, hardware, or critical temperature RFKILL */
782*4882a593Smuzhiyun static void
il3945_hdl_card_state(struct il_priv * il,struct il_rx_buf * rxb)783*4882a593Smuzhiyun il3945_hdl_card_state(struct il_priv *il, struct il_rx_buf *rxb)
784*4882a593Smuzhiyun {
785*4882a593Smuzhiyun struct il_rx_pkt *pkt = rxb_addr(rxb);
786*4882a593Smuzhiyun u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
787*4882a593Smuzhiyun unsigned long status = il->status;
788*4882a593Smuzhiyun
789*4882a593Smuzhiyun IL_WARN("Card state received: HW:%s SW:%s\n",
790*4882a593Smuzhiyun (flags & HW_CARD_DISABLED) ? "Kill" : "On",
791*4882a593Smuzhiyun (flags & SW_CARD_DISABLED) ? "Kill" : "On");
792*4882a593Smuzhiyun
793*4882a593Smuzhiyun _il_wr(il, CSR_UCODE_DRV_GP1_SET, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
794*4882a593Smuzhiyun
795*4882a593Smuzhiyun if (flags & HW_CARD_DISABLED)
796*4882a593Smuzhiyun set_bit(S_RFKILL, &il->status);
797*4882a593Smuzhiyun else
798*4882a593Smuzhiyun clear_bit(S_RFKILL, &il->status);
799*4882a593Smuzhiyun
800*4882a593Smuzhiyun il_scan_cancel(il);
801*4882a593Smuzhiyun
802*4882a593Smuzhiyun if ((test_bit(S_RFKILL, &status) !=
803*4882a593Smuzhiyun test_bit(S_RFKILL, &il->status)))
804*4882a593Smuzhiyun wiphy_rfkill_set_hw_state(il->hw->wiphy,
805*4882a593Smuzhiyun test_bit(S_RFKILL, &il->status));
806*4882a593Smuzhiyun else
807*4882a593Smuzhiyun wake_up(&il->wait_command_queue);
808*4882a593Smuzhiyun }
809*4882a593Smuzhiyun
810*4882a593Smuzhiyun /*
811*4882a593Smuzhiyun * il3945_setup_handlers - Initialize Rx handler callbacks
812*4882a593Smuzhiyun *
813*4882a593Smuzhiyun * Setup the RX handlers for each of the reply types sent from the uCode
814*4882a593Smuzhiyun * to the host.
815*4882a593Smuzhiyun *
816*4882a593Smuzhiyun * This function chains into the hardware specific files for them to setup
817*4882a593Smuzhiyun * any hardware specific handlers as well.
818*4882a593Smuzhiyun */
819*4882a593Smuzhiyun static void
il3945_setup_handlers(struct il_priv * il)820*4882a593Smuzhiyun il3945_setup_handlers(struct il_priv *il)
821*4882a593Smuzhiyun {
822*4882a593Smuzhiyun il->handlers[N_ALIVE] = il3945_hdl_alive;
823*4882a593Smuzhiyun il->handlers[C_ADD_STA] = il3945_hdl_add_sta;
824*4882a593Smuzhiyun il->handlers[N_ERROR] = il_hdl_error;
825*4882a593Smuzhiyun il->handlers[N_CHANNEL_SWITCH] = il_hdl_csa;
826*4882a593Smuzhiyun il->handlers[N_SPECTRUM_MEASUREMENT] = il_hdl_spectrum_measurement;
827*4882a593Smuzhiyun il->handlers[N_PM_SLEEP] = il_hdl_pm_sleep;
828*4882a593Smuzhiyun il->handlers[N_PM_DEBUG_STATS] = il_hdl_pm_debug_stats;
829*4882a593Smuzhiyun il->handlers[N_BEACON] = il3945_hdl_beacon;
830*4882a593Smuzhiyun
831*4882a593Smuzhiyun /*
832*4882a593Smuzhiyun * The same handler is used for both the REPLY to a discrete
833*4882a593Smuzhiyun * stats request from the host as well as for the periodic
834*4882a593Smuzhiyun * stats notifications (after received beacons) from the uCode.
835*4882a593Smuzhiyun */
836*4882a593Smuzhiyun il->handlers[C_STATS] = il3945_hdl_c_stats;
837*4882a593Smuzhiyun il->handlers[N_STATS] = il3945_hdl_stats;
838*4882a593Smuzhiyun
839*4882a593Smuzhiyun il_setup_rx_scan_handlers(il);
840*4882a593Smuzhiyun il->handlers[N_CARD_STATE] = il3945_hdl_card_state;
841*4882a593Smuzhiyun
842*4882a593Smuzhiyun /* Set up hardware specific Rx handlers */
843*4882a593Smuzhiyun il3945_hw_handler_setup(il);
844*4882a593Smuzhiyun }
845*4882a593Smuzhiyun
846*4882a593Smuzhiyun /************************** RX-FUNCTIONS ****************************/
847*4882a593Smuzhiyun /*
848*4882a593Smuzhiyun * Rx theory of operation
849*4882a593Smuzhiyun *
850*4882a593Smuzhiyun * The host allocates 32 DMA target addresses and passes the host address
851*4882a593Smuzhiyun * to the firmware at register IL_RFDS_TBL_LOWER + N * RFD_SIZE where N is
852*4882a593Smuzhiyun * 0 to 31
853*4882a593Smuzhiyun *
854*4882a593Smuzhiyun * Rx Queue Indexes
855*4882a593Smuzhiyun * The host/firmware share two idx registers for managing the Rx buffers.
856*4882a593Smuzhiyun *
857*4882a593Smuzhiyun * The READ idx maps to the first position that the firmware may be writing
858*4882a593Smuzhiyun * to -- the driver can read up to (but not including) this position and get
859*4882a593Smuzhiyun * good data.
860*4882a593Smuzhiyun * The READ idx is managed by the firmware once the card is enabled.
861*4882a593Smuzhiyun *
862*4882a593Smuzhiyun * The WRITE idx maps to the last position the driver has read from -- the
863*4882a593Smuzhiyun * position preceding WRITE is the last slot the firmware can place a packet.
864*4882a593Smuzhiyun *
865*4882a593Smuzhiyun * The queue is empty (no good data) if WRITE = READ - 1, and is full if
866*4882a593Smuzhiyun * WRITE = READ.
867*4882a593Smuzhiyun *
868*4882a593Smuzhiyun * During initialization, the host sets up the READ queue position to the first
869*4882a593Smuzhiyun * IDX position, and WRITE to the last (READ - 1 wrapped)
870*4882a593Smuzhiyun *
871*4882a593Smuzhiyun * When the firmware places a packet in a buffer, it will advance the READ idx
872*4882a593Smuzhiyun * and fire the RX interrupt. The driver can then query the READ idx and
873*4882a593Smuzhiyun * process as many packets as possible, moving the WRITE idx forward as it
874*4882a593Smuzhiyun * resets the Rx queue buffers with new memory.
875*4882a593Smuzhiyun *
876*4882a593Smuzhiyun * The management in the driver is as follows:
877*4882a593Smuzhiyun * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
878*4882a593Smuzhiyun * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
879*4882a593Smuzhiyun * to replenish the iwl->rxq->rx_free.
880*4882a593Smuzhiyun * + In il3945_rx_replenish (scheduled) if 'processed' != 'read' then the
881*4882a593Smuzhiyun * iwl->rxq is replenished and the READ IDX is updated (updating the
882*4882a593Smuzhiyun * 'processed' and 'read' driver idxes as well)
883*4882a593Smuzhiyun * + A received packet is processed and handed to the kernel network stack,
884*4882a593Smuzhiyun * detached from the iwl->rxq. The driver 'processed' idx is updated.
885*4882a593Smuzhiyun * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
886*4882a593Smuzhiyun * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
887*4882a593Smuzhiyun * IDX is not incremented and iwl->status(RX_STALLED) is set. If there
888*4882a593Smuzhiyun * were enough free buffers and RX_STALLED is set it is cleared.
889*4882a593Smuzhiyun *
890*4882a593Smuzhiyun *
891*4882a593Smuzhiyun * Driver sequence:
892*4882a593Smuzhiyun *
893*4882a593Smuzhiyun * il3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
894*4882a593Smuzhiyun * il3945_rx_queue_restock
895*4882a593Smuzhiyun * il3945_rx_queue_restock() Moves available buffers from rx_free into Rx
896*4882a593Smuzhiyun * queue, updates firmware pointers, and updates
897*4882a593Smuzhiyun * the WRITE idx. If insufficient rx_free buffers
898*4882a593Smuzhiyun * are available, schedules il3945_rx_replenish
899*4882a593Smuzhiyun *
900*4882a593Smuzhiyun * -- enable interrupts --
901*4882a593Smuzhiyun * ISR - il3945_rx() Detach il_rx_bufs from pool up to the
902*4882a593Smuzhiyun * READ IDX, detaching the SKB from the pool.
903*4882a593Smuzhiyun * Moves the packet buffer from queue to rx_used.
904*4882a593Smuzhiyun * Calls il3945_rx_queue_restock to refill any empty
905*4882a593Smuzhiyun * slots.
906*4882a593Smuzhiyun * ...
907*4882a593Smuzhiyun *
908*4882a593Smuzhiyun */
909*4882a593Smuzhiyun
910*4882a593Smuzhiyun /*
911*4882a593Smuzhiyun * il3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
912*4882a593Smuzhiyun */
913*4882a593Smuzhiyun static inline __le32
il3945_dma_addr2rbd_ptr(struct il_priv * il,dma_addr_t dma_addr)914*4882a593Smuzhiyun il3945_dma_addr2rbd_ptr(struct il_priv *il, dma_addr_t dma_addr)
915*4882a593Smuzhiyun {
916*4882a593Smuzhiyun return cpu_to_le32((u32) dma_addr);
917*4882a593Smuzhiyun }
918*4882a593Smuzhiyun
919*4882a593Smuzhiyun /*
920*4882a593Smuzhiyun * il3945_rx_queue_restock - refill RX queue from pre-allocated pool
921*4882a593Smuzhiyun *
922*4882a593Smuzhiyun * If there are slots in the RX queue that need to be restocked,
923*4882a593Smuzhiyun * and we have free pre-allocated buffers, fill the ranks as much
924*4882a593Smuzhiyun * as we can, pulling from rx_free.
925*4882a593Smuzhiyun *
926*4882a593Smuzhiyun * This moves the 'write' idx forward to catch up with 'processed', and
927*4882a593Smuzhiyun * also updates the memory address in the firmware to reference the new
928*4882a593Smuzhiyun * target buffer.
929*4882a593Smuzhiyun */
930*4882a593Smuzhiyun static void
il3945_rx_queue_restock(struct il_priv * il)931*4882a593Smuzhiyun il3945_rx_queue_restock(struct il_priv *il)
932*4882a593Smuzhiyun {
933*4882a593Smuzhiyun struct il_rx_queue *rxq = &il->rxq;
934*4882a593Smuzhiyun struct list_head *element;
935*4882a593Smuzhiyun struct il_rx_buf *rxb;
936*4882a593Smuzhiyun unsigned long flags;
937*4882a593Smuzhiyun
938*4882a593Smuzhiyun spin_lock_irqsave(&rxq->lock, flags);
939*4882a593Smuzhiyun while (il_rx_queue_space(rxq) > 0 && rxq->free_count) {
940*4882a593Smuzhiyun /* Get next free Rx buffer, remove from free list */
941*4882a593Smuzhiyun element = rxq->rx_free.next;
942*4882a593Smuzhiyun rxb = list_entry(element, struct il_rx_buf, list);
943*4882a593Smuzhiyun list_del(element);
944*4882a593Smuzhiyun
945*4882a593Smuzhiyun /* Point to Rx buffer via next RBD in circular buffer */
946*4882a593Smuzhiyun rxq->bd[rxq->write] =
947*4882a593Smuzhiyun il3945_dma_addr2rbd_ptr(il, rxb->page_dma);
948*4882a593Smuzhiyun rxq->queue[rxq->write] = rxb;
949*4882a593Smuzhiyun rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
950*4882a593Smuzhiyun rxq->free_count--;
951*4882a593Smuzhiyun }
952*4882a593Smuzhiyun spin_unlock_irqrestore(&rxq->lock, flags);
953*4882a593Smuzhiyun /* If the pre-allocated buffer pool is dropping low, schedule to
954*4882a593Smuzhiyun * refill it */
955*4882a593Smuzhiyun if (rxq->free_count <= RX_LOW_WATERMARK)
956*4882a593Smuzhiyun queue_work(il->workqueue, &il->rx_replenish);
957*4882a593Smuzhiyun
958*4882a593Smuzhiyun /* If we've added more space for the firmware to place data, tell it.
959*4882a593Smuzhiyun * Increment device's write pointer in multiples of 8. */
960*4882a593Smuzhiyun if (rxq->write_actual != (rxq->write & ~0x7) ||
961*4882a593Smuzhiyun abs(rxq->write - rxq->read) > 7) {
962*4882a593Smuzhiyun spin_lock_irqsave(&rxq->lock, flags);
963*4882a593Smuzhiyun rxq->need_update = 1;
964*4882a593Smuzhiyun spin_unlock_irqrestore(&rxq->lock, flags);
965*4882a593Smuzhiyun il_rx_queue_update_write_ptr(il, rxq);
966*4882a593Smuzhiyun }
967*4882a593Smuzhiyun }
968*4882a593Smuzhiyun
969*4882a593Smuzhiyun /*
970*4882a593Smuzhiyun * il3945_rx_replenish - Move all used packet from rx_used to rx_free
971*4882a593Smuzhiyun *
972*4882a593Smuzhiyun * When moving to rx_free an SKB is allocated for the slot.
973*4882a593Smuzhiyun *
974*4882a593Smuzhiyun * Also restock the Rx queue via il3945_rx_queue_restock.
975*4882a593Smuzhiyun * This is called as a scheduled work item (except for during initialization)
976*4882a593Smuzhiyun */
977*4882a593Smuzhiyun static void
il3945_rx_allocate(struct il_priv * il,gfp_t priority)978*4882a593Smuzhiyun il3945_rx_allocate(struct il_priv *il, gfp_t priority)
979*4882a593Smuzhiyun {
980*4882a593Smuzhiyun struct il_rx_queue *rxq = &il->rxq;
981*4882a593Smuzhiyun struct list_head *element;
982*4882a593Smuzhiyun struct il_rx_buf *rxb;
983*4882a593Smuzhiyun struct page *page;
984*4882a593Smuzhiyun dma_addr_t page_dma;
985*4882a593Smuzhiyun unsigned long flags;
986*4882a593Smuzhiyun gfp_t gfp_mask = priority;
987*4882a593Smuzhiyun
988*4882a593Smuzhiyun while (1) {
989*4882a593Smuzhiyun spin_lock_irqsave(&rxq->lock, flags);
990*4882a593Smuzhiyun if (list_empty(&rxq->rx_used)) {
991*4882a593Smuzhiyun spin_unlock_irqrestore(&rxq->lock, flags);
992*4882a593Smuzhiyun return;
993*4882a593Smuzhiyun }
994*4882a593Smuzhiyun spin_unlock_irqrestore(&rxq->lock, flags);
995*4882a593Smuzhiyun
996*4882a593Smuzhiyun if (rxq->free_count > RX_LOW_WATERMARK)
997*4882a593Smuzhiyun gfp_mask |= __GFP_NOWARN;
998*4882a593Smuzhiyun
999*4882a593Smuzhiyun if (il->hw_params.rx_page_order > 0)
1000*4882a593Smuzhiyun gfp_mask |= __GFP_COMP;
1001*4882a593Smuzhiyun
1002*4882a593Smuzhiyun /* Alloc a new receive buffer */
1003*4882a593Smuzhiyun page = alloc_pages(gfp_mask, il->hw_params.rx_page_order);
1004*4882a593Smuzhiyun if (!page) {
1005*4882a593Smuzhiyun if (net_ratelimit())
1006*4882a593Smuzhiyun D_INFO("Failed to allocate SKB buffer.\n");
1007*4882a593Smuzhiyun if (rxq->free_count <= RX_LOW_WATERMARK &&
1008*4882a593Smuzhiyun net_ratelimit())
1009*4882a593Smuzhiyun IL_ERR("Failed to allocate SKB buffer with %0x."
1010*4882a593Smuzhiyun "Only %u free buffers remaining.\n",
1011*4882a593Smuzhiyun priority, rxq->free_count);
1012*4882a593Smuzhiyun /* We don't reschedule replenish work here -- we will
1013*4882a593Smuzhiyun * call the restock method and if it still needs
1014*4882a593Smuzhiyun * more buffers it will schedule replenish */
1015*4882a593Smuzhiyun break;
1016*4882a593Smuzhiyun }
1017*4882a593Smuzhiyun
1018*4882a593Smuzhiyun /* Get physical address of RB/SKB */
1019*4882a593Smuzhiyun page_dma =
1020*4882a593Smuzhiyun pci_map_page(il->pci_dev, page, 0,
1021*4882a593Smuzhiyun PAGE_SIZE << il->hw_params.rx_page_order,
1022*4882a593Smuzhiyun PCI_DMA_FROMDEVICE);
1023*4882a593Smuzhiyun
1024*4882a593Smuzhiyun if (unlikely(pci_dma_mapping_error(il->pci_dev, page_dma))) {
1025*4882a593Smuzhiyun __free_pages(page, il->hw_params.rx_page_order);
1026*4882a593Smuzhiyun break;
1027*4882a593Smuzhiyun }
1028*4882a593Smuzhiyun
1029*4882a593Smuzhiyun spin_lock_irqsave(&rxq->lock, flags);
1030*4882a593Smuzhiyun
1031*4882a593Smuzhiyun if (list_empty(&rxq->rx_used)) {
1032*4882a593Smuzhiyun spin_unlock_irqrestore(&rxq->lock, flags);
1033*4882a593Smuzhiyun pci_unmap_page(il->pci_dev, page_dma,
1034*4882a593Smuzhiyun PAGE_SIZE << il->hw_params.rx_page_order,
1035*4882a593Smuzhiyun PCI_DMA_FROMDEVICE);
1036*4882a593Smuzhiyun __free_pages(page, il->hw_params.rx_page_order);
1037*4882a593Smuzhiyun return;
1038*4882a593Smuzhiyun }
1039*4882a593Smuzhiyun
1040*4882a593Smuzhiyun element = rxq->rx_used.next;
1041*4882a593Smuzhiyun rxb = list_entry(element, struct il_rx_buf, list);
1042*4882a593Smuzhiyun list_del(element);
1043*4882a593Smuzhiyun
1044*4882a593Smuzhiyun rxb->page = page;
1045*4882a593Smuzhiyun rxb->page_dma = page_dma;
1046*4882a593Smuzhiyun list_add_tail(&rxb->list, &rxq->rx_free);
1047*4882a593Smuzhiyun rxq->free_count++;
1048*4882a593Smuzhiyun il->alloc_rxb_page++;
1049*4882a593Smuzhiyun
1050*4882a593Smuzhiyun spin_unlock_irqrestore(&rxq->lock, flags);
1051*4882a593Smuzhiyun }
1052*4882a593Smuzhiyun }
1053*4882a593Smuzhiyun
1054*4882a593Smuzhiyun void
il3945_rx_queue_reset(struct il_priv * il,struct il_rx_queue * rxq)1055*4882a593Smuzhiyun il3945_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq)
1056*4882a593Smuzhiyun {
1057*4882a593Smuzhiyun unsigned long flags;
1058*4882a593Smuzhiyun int i;
1059*4882a593Smuzhiyun spin_lock_irqsave(&rxq->lock, flags);
1060*4882a593Smuzhiyun INIT_LIST_HEAD(&rxq->rx_free);
1061*4882a593Smuzhiyun INIT_LIST_HEAD(&rxq->rx_used);
1062*4882a593Smuzhiyun /* Fill the rx_used queue with _all_ of the Rx buffers */
1063*4882a593Smuzhiyun for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
1064*4882a593Smuzhiyun /* In the reset function, these buffers may have been allocated
1065*4882a593Smuzhiyun * to an SKB, so we need to unmap and free potential storage */
1066*4882a593Smuzhiyun if (rxq->pool[i].page != NULL) {
1067*4882a593Smuzhiyun pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
1068*4882a593Smuzhiyun PAGE_SIZE << il->hw_params.rx_page_order,
1069*4882a593Smuzhiyun PCI_DMA_FROMDEVICE);
1070*4882a593Smuzhiyun __il_free_pages(il, rxq->pool[i].page);
1071*4882a593Smuzhiyun rxq->pool[i].page = NULL;
1072*4882a593Smuzhiyun }
1073*4882a593Smuzhiyun list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
1074*4882a593Smuzhiyun }
1075*4882a593Smuzhiyun
1076*4882a593Smuzhiyun /* Set us so that we have processed and used all buffers, but have
1077*4882a593Smuzhiyun * not restocked the Rx queue with fresh buffers */
1078*4882a593Smuzhiyun rxq->read = rxq->write = 0;
1079*4882a593Smuzhiyun rxq->write_actual = 0;
1080*4882a593Smuzhiyun rxq->free_count = 0;
1081*4882a593Smuzhiyun spin_unlock_irqrestore(&rxq->lock, flags);
1082*4882a593Smuzhiyun }
1083*4882a593Smuzhiyun
1084*4882a593Smuzhiyun void
il3945_rx_replenish(void * data)1085*4882a593Smuzhiyun il3945_rx_replenish(void *data)
1086*4882a593Smuzhiyun {
1087*4882a593Smuzhiyun struct il_priv *il = data;
1088*4882a593Smuzhiyun unsigned long flags;
1089*4882a593Smuzhiyun
1090*4882a593Smuzhiyun il3945_rx_allocate(il, GFP_KERNEL);
1091*4882a593Smuzhiyun
1092*4882a593Smuzhiyun spin_lock_irqsave(&il->lock, flags);
1093*4882a593Smuzhiyun il3945_rx_queue_restock(il);
1094*4882a593Smuzhiyun spin_unlock_irqrestore(&il->lock, flags);
1095*4882a593Smuzhiyun }
1096*4882a593Smuzhiyun
1097*4882a593Smuzhiyun static void
il3945_rx_replenish_now(struct il_priv * il)1098*4882a593Smuzhiyun il3945_rx_replenish_now(struct il_priv *il)
1099*4882a593Smuzhiyun {
1100*4882a593Smuzhiyun il3945_rx_allocate(il, GFP_ATOMIC);
1101*4882a593Smuzhiyun
1102*4882a593Smuzhiyun il3945_rx_queue_restock(il);
1103*4882a593Smuzhiyun }
1104*4882a593Smuzhiyun
1105*4882a593Smuzhiyun /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
1106*4882a593Smuzhiyun * If an SKB has been detached, the POOL needs to have its SKB set to NULL
1107*4882a593Smuzhiyun * This free routine walks the list of POOL entries and if SKB is set to
1108*4882a593Smuzhiyun * non NULL it is unmapped and freed
1109*4882a593Smuzhiyun */
1110*4882a593Smuzhiyun static void
il3945_rx_queue_free(struct il_priv * il,struct il_rx_queue * rxq)1111*4882a593Smuzhiyun il3945_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq)
1112*4882a593Smuzhiyun {
1113*4882a593Smuzhiyun int i;
1114*4882a593Smuzhiyun for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
1115*4882a593Smuzhiyun if (rxq->pool[i].page != NULL) {
1116*4882a593Smuzhiyun pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
1117*4882a593Smuzhiyun PAGE_SIZE << il->hw_params.rx_page_order,
1118*4882a593Smuzhiyun PCI_DMA_FROMDEVICE);
1119*4882a593Smuzhiyun __il_free_pages(il, rxq->pool[i].page);
1120*4882a593Smuzhiyun rxq->pool[i].page = NULL;
1121*4882a593Smuzhiyun }
1122*4882a593Smuzhiyun }
1123*4882a593Smuzhiyun
1124*4882a593Smuzhiyun dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
1125*4882a593Smuzhiyun rxq->bd_dma);
1126*4882a593Smuzhiyun dma_free_coherent(&il->pci_dev->dev, sizeof(struct il_rb_status),
1127*4882a593Smuzhiyun rxq->rb_stts, rxq->rb_stts_dma);
1128*4882a593Smuzhiyun rxq->bd = NULL;
1129*4882a593Smuzhiyun rxq->rb_stts = NULL;
1130*4882a593Smuzhiyun }
1131*4882a593Smuzhiyun
1132*4882a593Smuzhiyun /* Convert linear signal-to-noise ratio into dB */
1133*4882a593Smuzhiyun static u8 ratio2dB[100] = {
1134*4882a593Smuzhiyun /* 0 1 2 3 4 5 6 7 8 9 */
1135*4882a593Smuzhiyun 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
1136*4882a593Smuzhiyun 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
1137*4882a593Smuzhiyun 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
1138*4882a593Smuzhiyun 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
1139*4882a593Smuzhiyun 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
1140*4882a593Smuzhiyun 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
1141*4882a593Smuzhiyun 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
1142*4882a593Smuzhiyun 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
1143*4882a593Smuzhiyun 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
1144*4882a593Smuzhiyun 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
1145*4882a593Smuzhiyun };
1146*4882a593Smuzhiyun
1147*4882a593Smuzhiyun /* Calculates a relative dB value from a ratio of linear
1148*4882a593Smuzhiyun * (i.e. not dB) signal levels.
1149*4882a593Smuzhiyun * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
1150*4882a593Smuzhiyun int
il3945_calc_db_from_ratio(int sig_ratio)1151*4882a593Smuzhiyun il3945_calc_db_from_ratio(int sig_ratio)
1152*4882a593Smuzhiyun {
1153*4882a593Smuzhiyun /* 1000:1 or higher just report as 60 dB */
1154*4882a593Smuzhiyun if (sig_ratio >= 1000)
1155*4882a593Smuzhiyun return 60;
1156*4882a593Smuzhiyun
1157*4882a593Smuzhiyun /* 100:1 or higher, divide by 10 and use table,
1158*4882a593Smuzhiyun * add 20 dB to make up for divide by 10 */
1159*4882a593Smuzhiyun if (sig_ratio >= 100)
1160*4882a593Smuzhiyun return 20 + (int)ratio2dB[sig_ratio / 10];
1161*4882a593Smuzhiyun
1162*4882a593Smuzhiyun /* We shouldn't see this */
1163*4882a593Smuzhiyun if (sig_ratio < 1)
1164*4882a593Smuzhiyun return 0;
1165*4882a593Smuzhiyun
1166*4882a593Smuzhiyun /* Use table for ratios 1:1 - 99:1 */
1167*4882a593Smuzhiyun return (int)ratio2dB[sig_ratio];
1168*4882a593Smuzhiyun }
1169*4882a593Smuzhiyun
1170*4882a593Smuzhiyun /*
1171*4882a593Smuzhiyun * il3945_rx_handle - Main entry function for receiving responses from uCode
1172*4882a593Smuzhiyun *
1173*4882a593Smuzhiyun * Uses the il->handlers callback function array to invoke
1174*4882a593Smuzhiyun * the appropriate handlers, including command responses,
1175*4882a593Smuzhiyun * frame-received notifications, and other notifications.
1176*4882a593Smuzhiyun */
1177*4882a593Smuzhiyun static void
il3945_rx_handle(struct il_priv * il)1178*4882a593Smuzhiyun il3945_rx_handle(struct il_priv *il)
1179*4882a593Smuzhiyun {
1180*4882a593Smuzhiyun struct il_rx_buf *rxb;
1181*4882a593Smuzhiyun struct il_rx_pkt *pkt;
1182*4882a593Smuzhiyun struct il_rx_queue *rxq = &il->rxq;
1183*4882a593Smuzhiyun u32 r, i;
1184*4882a593Smuzhiyun int reclaim;
1185*4882a593Smuzhiyun unsigned long flags;
1186*4882a593Smuzhiyun u8 fill_rx = 0;
1187*4882a593Smuzhiyun u32 count = 8;
1188*4882a593Smuzhiyun int total_empty = 0;
1189*4882a593Smuzhiyun
1190*4882a593Smuzhiyun /* uCode's read idx (stored in shared DRAM) indicates the last Rx
1191*4882a593Smuzhiyun * buffer that the driver may process (last buffer filled by ucode). */
1192*4882a593Smuzhiyun r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
1193*4882a593Smuzhiyun i = rxq->read;
1194*4882a593Smuzhiyun
1195*4882a593Smuzhiyun /* calculate total frames need to be restock after handling RX */
1196*4882a593Smuzhiyun total_empty = r - rxq->write_actual;
1197*4882a593Smuzhiyun if (total_empty < 0)
1198*4882a593Smuzhiyun total_empty += RX_QUEUE_SIZE;
1199*4882a593Smuzhiyun
1200*4882a593Smuzhiyun if (total_empty > (RX_QUEUE_SIZE / 2))
1201*4882a593Smuzhiyun fill_rx = 1;
1202*4882a593Smuzhiyun /* Rx interrupt, but nothing sent from uCode */
1203*4882a593Smuzhiyun if (i == r)
1204*4882a593Smuzhiyun D_RX("r = %d, i = %d\n", r, i);
1205*4882a593Smuzhiyun
1206*4882a593Smuzhiyun while (i != r) {
1207*4882a593Smuzhiyun int len;
1208*4882a593Smuzhiyun
1209*4882a593Smuzhiyun rxb = rxq->queue[i];
1210*4882a593Smuzhiyun
1211*4882a593Smuzhiyun /* If an RXB doesn't have a Rx queue slot associated with it,
1212*4882a593Smuzhiyun * then a bug has been introduced in the queue refilling
1213*4882a593Smuzhiyun * routines -- catch it here */
1214*4882a593Smuzhiyun BUG_ON(rxb == NULL);
1215*4882a593Smuzhiyun
1216*4882a593Smuzhiyun rxq->queue[i] = NULL;
1217*4882a593Smuzhiyun
1218*4882a593Smuzhiyun pci_unmap_page(il->pci_dev, rxb->page_dma,
1219*4882a593Smuzhiyun PAGE_SIZE << il->hw_params.rx_page_order,
1220*4882a593Smuzhiyun PCI_DMA_FROMDEVICE);
1221*4882a593Smuzhiyun pkt = rxb_addr(rxb);
1222*4882a593Smuzhiyun
1223*4882a593Smuzhiyun len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
1224*4882a593Smuzhiyun len += sizeof(u32); /* account for status word */
1225*4882a593Smuzhiyun
1226*4882a593Smuzhiyun reclaim = il_need_reclaim(il, pkt);
1227*4882a593Smuzhiyun
1228*4882a593Smuzhiyun /* Based on type of command response or notification,
1229*4882a593Smuzhiyun * handle those that need handling via function in
1230*4882a593Smuzhiyun * handlers table. See il3945_setup_handlers() */
1231*4882a593Smuzhiyun if (il->handlers[pkt->hdr.cmd]) {
1232*4882a593Smuzhiyun D_RX("r = %d, i = %d, %s, 0x%02x\n", r, i,
1233*4882a593Smuzhiyun il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
1234*4882a593Smuzhiyun il->isr_stats.handlers[pkt->hdr.cmd]++;
1235*4882a593Smuzhiyun il->handlers[pkt->hdr.cmd] (il, rxb);
1236*4882a593Smuzhiyun } else {
1237*4882a593Smuzhiyun /* No handling needed */
1238*4882a593Smuzhiyun D_RX("r %d i %d No handler needed for %s, 0x%02x\n", r,
1239*4882a593Smuzhiyun i, il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
1240*4882a593Smuzhiyun }
1241*4882a593Smuzhiyun
1242*4882a593Smuzhiyun /*
1243*4882a593Smuzhiyun * XXX: After here, we should always check rxb->page
1244*4882a593Smuzhiyun * against NULL before touching it or its virtual
1245*4882a593Smuzhiyun * memory (pkt). Because some handler might have
1246*4882a593Smuzhiyun * already taken or freed the pages.
1247*4882a593Smuzhiyun */
1248*4882a593Smuzhiyun
1249*4882a593Smuzhiyun if (reclaim) {
1250*4882a593Smuzhiyun /* Invoke any callbacks, transfer the buffer to caller,
1251*4882a593Smuzhiyun * and fire off the (possibly) blocking il_send_cmd()
1252*4882a593Smuzhiyun * as we reclaim the driver command queue */
1253*4882a593Smuzhiyun if (rxb->page)
1254*4882a593Smuzhiyun il_tx_cmd_complete(il, rxb);
1255*4882a593Smuzhiyun else
1256*4882a593Smuzhiyun IL_WARN("Claim null rxb?\n");
1257*4882a593Smuzhiyun }
1258*4882a593Smuzhiyun
1259*4882a593Smuzhiyun /* Reuse the page if possible. For notification packets and
1260*4882a593Smuzhiyun * SKBs that fail to Rx correctly, add them back into the
1261*4882a593Smuzhiyun * rx_free list for reuse later. */
1262*4882a593Smuzhiyun spin_lock_irqsave(&rxq->lock, flags);
1263*4882a593Smuzhiyun if (rxb->page != NULL) {
1264*4882a593Smuzhiyun rxb->page_dma =
1265*4882a593Smuzhiyun pci_map_page(il->pci_dev, rxb->page, 0,
1266*4882a593Smuzhiyun PAGE_SIZE << il->hw_params.
1267*4882a593Smuzhiyun rx_page_order, PCI_DMA_FROMDEVICE);
1268*4882a593Smuzhiyun if (unlikely(pci_dma_mapping_error(il->pci_dev,
1269*4882a593Smuzhiyun rxb->page_dma))) {
1270*4882a593Smuzhiyun __il_free_pages(il, rxb->page);
1271*4882a593Smuzhiyun rxb->page = NULL;
1272*4882a593Smuzhiyun list_add_tail(&rxb->list, &rxq->rx_used);
1273*4882a593Smuzhiyun } else {
1274*4882a593Smuzhiyun list_add_tail(&rxb->list, &rxq->rx_free);
1275*4882a593Smuzhiyun rxq->free_count++;
1276*4882a593Smuzhiyun }
1277*4882a593Smuzhiyun } else
1278*4882a593Smuzhiyun list_add_tail(&rxb->list, &rxq->rx_used);
1279*4882a593Smuzhiyun
1280*4882a593Smuzhiyun spin_unlock_irqrestore(&rxq->lock, flags);
1281*4882a593Smuzhiyun
1282*4882a593Smuzhiyun i = (i + 1) & RX_QUEUE_MASK;
1283*4882a593Smuzhiyun /* If there are a lot of unused frames,
1284*4882a593Smuzhiyun * restock the Rx queue so ucode won't assert. */
1285*4882a593Smuzhiyun if (fill_rx) {
1286*4882a593Smuzhiyun count++;
1287*4882a593Smuzhiyun if (count >= 8) {
1288*4882a593Smuzhiyun rxq->read = i;
1289*4882a593Smuzhiyun il3945_rx_replenish_now(il);
1290*4882a593Smuzhiyun count = 0;
1291*4882a593Smuzhiyun }
1292*4882a593Smuzhiyun }
1293*4882a593Smuzhiyun }
1294*4882a593Smuzhiyun
1295*4882a593Smuzhiyun /* Backtrack one entry */
1296*4882a593Smuzhiyun rxq->read = i;
1297*4882a593Smuzhiyun if (fill_rx)
1298*4882a593Smuzhiyun il3945_rx_replenish_now(il);
1299*4882a593Smuzhiyun else
1300*4882a593Smuzhiyun il3945_rx_queue_restock(il);
1301*4882a593Smuzhiyun }
1302*4882a593Smuzhiyun
1303*4882a593Smuzhiyun /* call this function to flush any scheduled tasklet */
1304*4882a593Smuzhiyun static inline void
il3945_synchronize_irq(struct il_priv * il)1305*4882a593Smuzhiyun il3945_synchronize_irq(struct il_priv *il)
1306*4882a593Smuzhiyun {
1307*4882a593Smuzhiyun /* wait to make sure we flush pending tasklet */
1308*4882a593Smuzhiyun synchronize_irq(il->pci_dev->irq);
1309*4882a593Smuzhiyun tasklet_kill(&il->irq_tasklet);
1310*4882a593Smuzhiyun }
1311*4882a593Smuzhiyun
1312*4882a593Smuzhiyun static const char *
il3945_desc_lookup(int i)1313*4882a593Smuzhiyun il3945_desc_lookup(int i)
1314*4882a593Smuzhiyun {
1315*4882a593Smuzhiyun switch (i) {
1316*4882a593Smuzhiyun case 1:
1317*4882a593Smuzhiyun return "FAIL";
1318*4882a593Smuzhiyun case 2:
1319*4882a593Smuzhiyun return "BAD_PARAM";
1320*4882a593Smuzhiyun case 3:
1321*4882a593Smuzhiyun return "BAD_CHECKSUM";
1322*4882a593Smuzhiyun case 4:
1323*4882a593Smuzhiyun return "NMI_INTERRUPT";
1324*4882a593Smuzhiyun case 5:
1325*4882a593Smuzhiyun return "SYSASSERT";
1326*4882a593Smuzhiyun case 6:
1327*4882a593Smuzhiyun return "FATAL_ERROR";
1328*4882a593Smuzhiyun }
1329*4882a593Smuzhiyun
1330*4882a593Smuzhiyun return "UNKNOWN";
1331*4882a593Smuzhiyun }
1332*4882a593Smuzhiyun
1333*4882a593Smuzhiyun #define ERROR_START_OFFSET (1 * sizeof(u32))
1334*4882a593Smuzhiyun #define ERROR_ELEM_SIZE (7 * sizeof(u32))
1335*4882a593Smuzhiyun
1336*4882a593Smuzhiyun void
il3945_dump_nic_error_log(struct il_priv * il)1337*4882a593Smuzhiyun il3945_dump_nic_error_log(struct il_priv *il)
1338*4882a593Smuzhiyun {
1339*4882a593Smuzhiyun u32 i;
1340*4882a593Smuzhiyun u32 desc, time, count, base, data1;
1341*4882a593Smuzhiyun u32 blink1, blink2, ilink1, ilink2;
1342*4882a593Smuzhiyun
1343*4882a593Smuzhiyun base = le32_to_cpu(il->card_alive.error_event_table_ptr);
1344*4882a593Smuzhiyun
1345*4882a593Smuzhiyun if (!il3945_hw_valid_rtc_data_addr(base)) {
1346*4882a593Smuzhiyun IL_ERR("Not valid error log pointer 0x%08X\n", base);
1347*4882a593Smuzhiyun return;
1348*4882a593Smuzhiyun }
1349*4882a593Smuzhiyun
1350*4882a593Smuzhiyun count = il_read_targ_mem(il, base);
1351*4882a593Smuzhiyun
1352*4882a593Smuzhiyun if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1353*4882a593Smuzhiyun IL_ERR("Start IWL Error Log Dump:\n");
1354*4882a593Smuzhiyun IL_ERR("Status: 0x%08lX, count: %d\n", il->status, count);
1355*4882a593Smuzhiyun }
1356*4882a593Smuzhiyun
1357*4882a593Smuzhiyun IL_ERR("Desc Time asrtPC blink2 "
1358*4882a593Smuzhiyun "ilink1 nmiPC Line\n");
1359*4882a593Smuzhiyun for (i = ERROR_START_OFFSET;
1360*4882a593Smuzhiyun i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
1361*4882a593Smuzhiyun i += ERROR_ELEM_SIZE) {
1362*4882a593Smuzhiyun desc = il_read_targ_mem(il, base + i);
1363*4882a593Smuzhiyun time = il_read_targ_mem(il, base + i + 1 * sizeof(u32));
1364*4882a593Smuzhiyun blink1 = il_read_targ_mem(il, base + i + 2 * sizeof(u32));
1365*4882a593Smuzhiyun blink2 = il_read_targ_mem(il, base + i + 3 * sizeof(u32));
1366*4882a593Smuzhiyun ilink1 = il_read_targ_mem(il, base + i + 4 * sizeof(u32));
1367*4882a593Smuzhiyun ilink2 = il_read_targ_mem(il, base + i + 5 * sizeof(u32));
1368*4882a593Smuzhiyun data1 = il_read_targ_mem(il, base + i + 6 * sizeof(u32));
1369*4882a593Smuzhiyun
1370*4882a593Smuzhiyun IL_ERR("%-13s (0x%X) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
1371*4882a593Smuzhiyun il3945_desc_lookup(desc), desc, time, blink1, blink2,
1372*4882a593Smuzhiyun ilink1, ilink2, data1);
1373*4882a593Smuzhiyun }
1374*4882a593Smuzhiyun }
1375*4882a593Smuzhiyun
1376*4882a593Smuzhiyun static void
il3945_irq_tasklet(struct tasklet_struct * t)1377*4882a593Smuzhiyun il3945_irq_tasklet(struct tasklet_struct *t)
1378*4882a593Smuzhiyun {
1379*4882a593Smuzhiyun struct il_priv *il = from_tasklet(il, t, irq_tasklet);
1380*4882a593Smuzhiyun u32 inta, handled = 0;
1381*4882a593Smuzhiyun u32 inta_fh;
1382*4882a593Smuzhiyun unsigned long flags;
1383*4882a593Smuzhiyun #ifdef CONFIG_IWLEGACY_DEBUG
1384*4882a593Smuzhiyun u32 inta_mask;
1385*4882a593Smuzhiyun #endif
1386*4882a593Smuzhiyun
1387*4882a593Smuzhiyun spin_lock_irqsave(&il->lock, flags);
1388*4882a593Smuzhiyun
1389*4882a593Smuzhiyun /* Ack/clear/reset pending uCode interrupts.
1390*4882a593Smuzhiyun * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1391*4882a593Smuzhiyun * and will clear only when CSR_FH_INT_STATUS gets cleared. */
1392*4882a593Smuzhiyun inta = _il_rd(il, CSR_INT);
1393*4882a593Smuzhiyun _il_wr(il, CSR_INT, inta);
1394*4882a593Smuzhiyun
1395*4882a593Smuzhiyun /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1396*4882a593Smuzhiyun * Any new interrupts that happen after this, either while we're
1397*4882a593Smuzhiyun * in this tasklet, or later, will show up in next ISR/tasklet. */
1398*4882a593Smuzhiyun inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
1399*4882a593Smuzhiyun _il_wr(il, CSR_FH_INT_STATUS, inta_fh);
1400*4882a593Smuzhiyun
1401*4882a593Smuzhiyun #ifdef CONFIG_IWLEGACY_DEBUG
1402*4882a593Smuzhiyun if (il_get_debug_level(il) & IL_DL_ISR) {
1403*4882a593Smuzhiyun /* just for debug */
1404*4882a593Smuzhiyun inta_mask = _il_rd(il, CSR_INT_MASK);
1405*4882a593Smuzhiyun D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta,
1406*4882a593Smuzhiyun inta_mask, inta_fh);
1407*4882a593Smuzhiyun }
1408*4882a593Smuzhiyun #endif
1409*4882a593Smuzhiyun
1410*4882a593Smuzhiyun spin_unlock_irqrestore(&il->lock, flags);
1411*4882a593Smuzhiyun
1412*4882a593Smuzhiyun /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1413*4882a593Smuzhiyun * atomic, make sure that inta covers all the interrupts that
1414*4882a593Smuzhiyun * we've discovered, even if FH interrupt came in just after
1415*4882a593Smuzhiyun * reading CSR_INT. */
1416*4882a593Smuzhiyun if (inta_fh & CSR39_FH_INT_RX_MASK)
1417*4882a593Smuzhiyun inta |= CSR_INT_BIT_FH_RX;
1418*4882a593Smuzhiyun if (inta_fh & CSR39_FH_INT_TX_MASK)
1419*4882a593Smuzhiyun inta |= CSR_INT_BIT_FH_TX;
1420*4882a593Smuzhiyun
1421*4882a593Smuzhiyun /* Now service all interrupt bits discovered above. */
1422*4882a593Smuzhiyun if (inta & CSR_INT_BIT_HW_ERR) {
1423*4882a593Smuzhiyun IL_ERR("Hardware error detected. Restarting.\n");
1424*4882a593Smuzhiyun
1425*4882a593Smuzhiyun /* Tell the device to stop sending interrupts */
1426*4882a593Smuzhiyun il_disable_interrupts(il);
1427*4882a593Smuzhiyun
1428*4882a593Smuzhiyun il->isr_stats.hw++;
1429*4882a593Smuzhiyun il_irq_handle_error(il);
1430*4882a593Smuzhiyun
1431*4882a593Smuzhiyun handled |= CSR_INT_BIT_HW_ERR;
1432*4882a593Smuzhiyun
1433*4882a593Smuzhiyun return;
1434*4882a593Smuzhiyun }
1435*4882a593Smuzhiyun #ifdef CONFIG_IWLEGACY_DEBUG
1436*4882a593Smuzhiyun if (il_get_debug_level(il) & (IL_DL_ISR)) {
1437*4882a593Smuzhiyun /* NIC fires this, but we don't use it, redundant with WAKEUP */
1438*4882a593Smuzhiyun if (inta & CSR_INT_BIT_SCD) {
1439*4882a593Smuzhiyun D_ISR("Scheduler finished to transmit "
1440*4882a593Smuzhiyun "the frame/frames.\n");
1441*4882a593Smuzhiyun il->isr_stats.sch++;
1442*4882a593Smuzhiyun }
1443*4882a593Smuzhiyun
1444*4882a593Smuzhiyun /* Alive notification via Rx interrupt will do the real work */
1445*4882a593Smuzhiyun if (inta & CSR_INT_BIT_ALIVE) {
1446*4882a593Smuzhiyun D_ISR("Alive interrupt\n");
1447*4882a593Smuzhiyun il->isr_stats.alive++;
1448*4882a593Smuzhiyun }
1449*4882a593Smuzhiyun }
1450*4882a593Smuzhiyun #endif
1451*4882a593Smuzhiyun /* Safely ignore these bits for debug checks below */
1452*4882a593Smuzhiyun inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1453*4882a593Smuzhiyun
1454*4882a593Smuzhiyun /* Error detected by uCode */
1455*4882a593Smuzhiyun if (inta & CSR_INT_BIT_SW_ERR) {
1456*4882a593Smuzhiyun IL_ERR("Microcode SW error detected. " "Restarting 0x%X.\n",
1457*4882a593Smuzhiyun inta);
1458*4882a593Smuzhiyun il->isr_stats.sw++;
1459*4882a593Smuzhiyun il_irq_handle_error(il);
1460*4882a593Smuzhiyun handled |= CSR_INT_BIT_SW_ERR;
1461*4882a593Smuzhiyun }
1462*4882a593Smuzhiyun
1463*4882a593Smuzhiyun /* uCode wakes up after power-down sleep */
1464*4882a593Smuzhiyun if (inta & CSR_INT_BIT_WAKEUP) {
1465*4882a593Smuzhiyun D_ISR("Wakeup interrupt\n");
1466*4882a593Smuzhiyun il_rx_queue_update_write_ptr(il, &il->rxq);
1467*4882a593Smuzhiyun
1468*4882a593Smuzhiyun spin_lock_irqsave(&il->lock, flags);
1469*4882a593Smuzhiyun il_txq_update_write_ptr(il, &il->txq[0]);
1470*4882a593Smuzhiyun il_txq_update_write_ptr(il, &il->txq[1]);
1471*4882a593Smuzhiyun il_txq_update_write_ptr(il, &il->txq[2]);
1472*4882a593Smuzhiyun il_txq_update_write_ptr(il, &il->txq[3]);
1473*4882a593Smuzhiyun il_txq_update_write_ptr(il, &il->txq[4]);
1474*4882a593Smuzhiyun spin_unlock_irqrestore(&il->lock, flags);
1475*4882a593Smuzhiyun
1476*4882a593Smuzhiyun il->isr_stats.wakeup++;
1477*4882a593Smuzhiyun handled |= CSR_INT_BIT_WAKEUP;
1478*4882a593Smuzhiyun }
1479*4882a593Smuzhiyun
1480*4882a593Smuzhiyun /* All uCode command responses, including Tx command responses,
1481*4882a593Smuzhiyun * Rx "responses" (frame-received notification), and other
1482*4882a593Smuzhiyun * notifications from uCode come through here*/
1483*4882a593Smuzhiyun if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1484*4882a593Smuzhiyun il3945_rx_handle(il);
1485*4882a593Smuzhiyun il->isr_stats.rx++;
1486*4882a593Smuzhiyun handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1487*4882a593Smuzhiyun }
1488*4882a593Smuzhiyun
1489*4882a593Smuzhiyun if (inta & CSR_INT_BIT_FH_TX) {
1490*4882a593Smuzhiyun D_ISR("Tx interrupt\n");
1491*4882a593Smuzhiyun il->isr_stats.tx++;
1492*4882a593Smuzhiyun
1493*4882a593Smuzhiyun _il_wr(il, CSR_FH_INT_STATUS, (1 << 6));
1494*4882a593Smuzhiyun il_wr(il, FH39_TCSR_CREDIT(FH39_SRVC_CHNL), 0x0);
1495*4882a593Smuzhiyun handled |= CSR_INT_BIT_FH_TX;
1496*4882a593Smuzhiyun }
1497*4882a593Smuzhiyun
1498*4882a593Smuzhiyun if (inta & ~handled) {
1499*4882a593Smuzhiyun IL_ERR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
1500*4882a593Smuzhiyun il->isr_stats.unhandled++;
1501*4882a593Smuzhiyun }
1502*4882a593Smuzhiyun
1503*4882a593Smuzhiyun if (inta & ~il->inta_mask) {
1504*4882a593Smuzhiyun IL_WARN("Disabled INTA bits 0x%08x were pending\n",
1505*4882a593Smuzhiyun inta & ~il->inta_mask);
1506*4882a593Smuzhiyun IL_WARN(" with inta_fh = 0x%08x\n", inta_fh);
1507*4882a593Smuzhiyun }
1508*4882a593Smuzhiyun
1509*4882a593Smuzhiyun /* Re-enable all interrupts */
1510*4882a593Smuzhiyun /* only Re-enable if disabled by irq */
1511*4882a593Smuzhiyun if (test_bit(S_INT_ENABLED, &il->status))
1512*4882a593Smuzhiyun il_enable_interrupts(il);
1513*4882a593Smuzhiyun
1514*4882a593Smuzhiyun #ifdef CONFIG_IWLEGACY_DEBUG
1515*4882a593Smuzhiyun if (il_get_debug_level(il) & (IL_DL_ISR)) {
1516*4882a593Smuzhiyun inta = _il_rd(il, CSR_INT);
1517*4882a593Smuzhiyun inta_mask = _il_rd(il, CSR_INT_MASK);
1518*4882a593Smuzhiyun inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
1519*4882a593Smuzhiyun D_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1520*4882a593Smuzhiyun "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1521*4882a593Smuzhiyun }
1522*4882a593Smuzhiyun #endif
1523*4882a593Smuzhiyun }
1524*4882a593Smuzhiyun
1525*4882a593Smuzhiyun static int
il3945_get_channels_for_scan(struct il_priv * il,enum nl80211_band band,u8 is_active,u8 n_probes,struct il3945_scan_channel * scan_ch,struct ieee80211_vif * vif)1526*4882a593Smuzhiyun il3945_get_channels_for_scan(struct il_priv *il, enum nl80211_band band,
1527*4882a593Smuzhiyun u8 is_active, u8 n_probes,
1528*4882a593Smuzhiyun struct il3945_scan_channel *scan_ch,
1529*4882a593Smuzhiyun struct ieee80211_vif *vif)
1530*4882a593Smuzhiyun {
1531*4882a593Smuzhiyun struct ieee80211_channel *chan;
1532*4882a593Smuzhiyun const struct ieee80211_supported_band *sband;
1533*4882a593Smuzhiyun const struct il_channel_info *ch_info;
1534*4882a593Smuzhiyun u16 passive_dwell = 0;
1535*4882a593Smuzhiyun u16 active_dwell = 0;
1536*4882a593Smuzhiyun int added, i;
1537*4882a593Smuzhiyun
1538*4882a593Smuzhiyun sband = il_get_hw_mode(il, band);
1539*4882a593Smuzhiyun if (!sband)
1540*4882a593Smuzhiyun return 0;
1541*4882a593Smuzhiyun
1542*4882a593Smuzhiyun active_dwell = il_get_active_dwell_time(il, band, n_probes);
1543*4882a593Smuzhiyun passive_dwell = il_get_passive_dwell_time(il, band, vif);
1544*4882a593Smuzhiyun
1545*4882a593Smuzhiyun if (passive_dwell <= active_dwell)
1546*4882a593Smuzhiyun passive_dwell = active_dwell + 1;
1547*4882a593Smuzhiyun
1548*4882a593Smuzhiyun for (i = 0, added = 0; i < il->scan_request->n_channels; i++) {
1549*4882a593Smuzhiyun chan = il->scan_request->channels[i];
1550*4882a593Smuzhiyun
1551*4882a593Smuzhiyun if (chan->band != band)
1552*4882a593Smuzhiyun continue;
1553*4882a593Smuzhiyun
1554*4882a593Smuzhiyun scan_ch->channel = chan->hw_value;
1555*4882a593Smuzhiyun
1556*4882a593Smuzhiyun ch_info = il_get_channel_info(il, band, scan_ch->channel);
1557*4882a593Smuzhiyun if (!il_is_channel_valid(ch_info)) {
1558*4882a593Smuzhiyun D_SCAN("Channel %d is INVALID for this band.\n",
1559*4882a593Smuzhiyun scan_ch->channel);
1560*4882a593Smuzhiyun continue;
1561*4882a593Smuzhiyun }
1562*4882a593Smuzhiyun
1563*4882a593Smuzhiyun scan_ch->active_dwell = cpu_to_le16(active_dwell);
1564*4882a593Smuzhiyun scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1565*4882a593Smuzhiyun /* If passive , set up for auto-switch
1566*4882a593Smuzhiyun * and use long active_dwell time.
1567*4882a593Smuzhiyun */
1568*4882a593Smuzhiyun if (!is_active || il_is_channel_passive(ch_info) ||
1569*4882a593Smuzhiyun (chan->flags & IEEE80211_CHAN_NO_IR)) {
1570*4882a593Smuzhiyun scan_ch->type = 0; /* passive */
1571*4882a593Smuzhiyun if (IL_UCODE_API(il->ucode_ver) == 1)
1572*4882a593Smuzhiyun scan_ch->active_dwell =
1573*4882a593Smuzhiyun cpu_to_le16(passive_dwell - 1);
1574*4882a593Smuzhiyun } else {
1575*4882a593Smuzhiyun scan_ch->type = 1; /* active */
1576*4882a593Smuzhiyun }
1577*4882a593Smuzhiyun
1578*4882a593Smuzhiyun /* Set direct probe bits. These may be used both for active
1579*4882a593Smuzhiyun * scan channels (probes gets sent right away),
1580*4882a593Smuzhiyun * or for passive channels (probes get se sent only after
1581*4882a593Smuzhiyun * hearing clear Rx packet).*/
1582*4882a593Smuzhiyun if (IL_UCODE_API(il->ucode_ver) >= 2) {
1583*4882a593Smuzhiyun if (n_probes)
1584*4882a593Smuzhiyun scan_ch->type |= IL39_SCAN_PROBE_MASK(n_probes);
1585*4882a593Smuzhiyun } else {
1586*4882a593Smuzhiyun /* uCode v1 does not allow setting direct probe bits on
1587*4882a593Smuzhiyun * passive channel. */
1588*4882a593Smuzhiyun if ((scan_ch->type & 1) && n_probes)
1589*4882a593Smuzhiyun scan_ch->type |= IL39_SCAN_PROBE_MASK(n_probes);
1590*4882a593Smuzhiyun }
1591*4882a593Smuzhiyun
1592*4882a593Smuzhiyun /* Set txpower levels to defaults */
1593*4882a593Smuzhiyun scan_ch->tpc.dsp_atten = 110;
1594*4882a593Smuzhiyun /* scan_pwr_info->tpc.dsp_atten; */
1595*4882a593Smuzhiyun
1596*4882a593Smuzhiyun /*scan_pwr_info->tpc.tx_gain; */
1597*4882a593Smuzhiyun if (band == NL80211_BAND_5GHZ)
1598*4882a593Smuzhiyun scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
1599*4882a593Smuzhiyun else {
1600*4882a593Smuzhiyun scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
1601*4882a593Smuzhiyun /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1602*4882a593Smuzhiyun * power level:
1603*4882a593Smuzhiyun * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
1604*4882a593Smuzhiyun */
1605*4882a593Smuzhiyun }
1606*4882a593Smuzhiyun
1607*4882a593Smuzhiyun D_SCAN("Scanning %d [%s %d]\n", scan_ch->channel,
1608*4882a593Smuzhiyun (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
1609*4882a593Smuzhiyun (scan_ch->type & 1) ? active_dwell : passive_dwell);
1610*4882a593Smuzhiyun
1611*4882a593Smuzhiyun scan_ch++;
1612*4882a593Smuzhiyun added++;
1613*4882a593Smuzhiyun }
1614*4882a593Smuzhiyun
1615*4882a593Smuzhiyun D_SCAN("total channels to scan %d\n", added);
1616*4882a593Smuzhiyun return added;
1617*4882a593Smuzhiyun }
1618*4882a593Smuzhiyun
1619*4882a593Smuzhiyun static void
il3945_init_hw_rates(struct il_priv * il,struct ieee80211_rate * rates)1620*4882a593Smuzhiyun il3945_init_hw_rates(struct il_priv *il, struct ieee80211_rate *rates)
1621*4882a593Smuzhiyun {
1622*4882a593Smuzhiyun int i;
1623*4882a593Smuzhiyun
1624*4882a593Smuzhiyun for (i = 0; i < RATE_COUNT_LEGACY; i++) {
1625*4882a593Smuzhiyun rates[i].bitrate = il3945_rates[i].ieee * 5;
1626*4882a593Smuzhiyun rates[i].hw_value = i; /* Rate scaling will work on idxes */
1627*4882a593Smuzhiyun rates[i].hw_value_short = i;
1628*4882a593Smuzhiyun rates[i].flags = 0;
1629*4882a593Smuzhiyun if (i > IL39_LAST_OFDM_RATE || i < IL_FIRST_OFDM_RATE) {
1630*4882a593Smuzhiyun /*
1631*4882a593Smuzhiyun * If CCK != 1M then set short preamble rate flag.
1632*4882a593Smuzhiyun */
1633*4882a593Smuzhiyun rates[i].flags |=
1634*4882a593Smuzhiyun (il3945_rates[i].plcp ==
1635*4882a593Smuzhiyun 10) ? 0 : IEEE80211_RATE_SHORT_PREAMBLE;
1636*4882a593Smuzhiyun }
1637*4882a593Smuzhiyun }
1638*4882a593Smuzhiyun }
1639*4882a593Smuzhiyun
1640*4882a593Smuzhiyun /******************************************************************************
1641*4882a593Smuzhiyun *
1642*4882a593Smuzhiyun * uCode download functions
1643*4882a593Smuzhiyun *
1644*4882a593Smuzhiyun ******************************************************************************/
1645*4882a593Smuzhiyun
1646*4882a593Smuzhiyun static void
il3945_dealloc_ucode_pci(struct il_priv * il)1647*4882a593Smuzhiyun il3945_dealloc_ucode_pci(struct il_priv *il)
1648*4882a593Smuzhiyun {
1649*4882a593Smuzhiyun il_free_fw_desc(il->pci_dev, &il->ucode_code);
1650*4882a593Smuzhiyun il_free_fw_desc(il->pci_dev, &il->ucode_data);
1651*4882a593Smuzhiyun il_free_fw_desc(il->pci_dev, &il->ucode_data_backup);
1652*4882a593Smuzhiyun il_free_fw_desc(il->pci_dev, &il->ucode_init);
1653*4882a593Smuzhiyun il_free_fw_desc(il->pci_dev, &il->ucode_init_data);
1654*4882a593Smuzhiyun il_free_fw_desc(il->pci_dev, &il->ucode_boot);
1655*4882a593Smuzhiyun }
1656*4882a593Smuzhiyun
1657*4882a593Smuzhiyun /*
1658*4882a593Smuzhiyun * il3945_verify_inst_full - verify runtime uCode image in card vs. host,
1659*4882a593Smuzhiyun * looking at all data.
1660*4882a593Smuzhiyun */
1661*4882a593Smuzhiyun static int
il3945_verify_inst_full(struct il_priv * il,__le32 * image,u32 len)1662*4882a593Smuzhiyun il3945_verify_inst_full(struct il_priv *il, __le32 * image, u32 len)
1663*4882a593Smuzhiyun {
1664*4882a593Smuzhiyun u32 val;
1665*4882a593Smuzhiyun u32 save_len = len;
1666*4882a593Smuzhiyun int rc = 0;
1667*4882a593Smuzhiyun u32 errcnt;
1668*4882a593Smuzhiyun
1669*4882a593Smuzhiyun D_INFO("ucode inst image size is %u\n", len);
1670*4882a593Smuzhiyun
1671*4882a593Smuzhiyun il_wr(il, HBUS_TARG_MEM_RADDR, IL39_RTC_INST_LOWER_BOUND);
1672*4882a593Smuzhiyun
1673*4882a593Smuzhiyun errcnt = 0;
1674*4882a593Smuzhiyun for (; len > 0; len -= sizeof(u32), image++) {
1675*4882a593Smuzhiyun /* read data comes through single port, auto-incr addr */
1676*4882a593Smuzhiyun /* NOTE: Use the debugless read so we don't flood kernel log
1677*4882a593Smuzhiyun * if IL_DL_IO is set */
1678*4882a593Smuzhiyun val = _il_rd(il, HBUS_TARG_MEM_RDAT);
1679*4882a593Smuzhiyun if (val != le32_to_cpu(*image)) {
1680*4882a593Smuzhiyun IL_ERR("uCode INST section is invalid at "
1681*4882a593Smuzhiyun "offset 0x%x, is 0x%x, s/b 0x%x\n",
1682*4882a593Smuzhiyun save_len - len, val, le32_to_cpu(*image));
1683*4882a593Smuzhiyun rc = -EIO;
1684*4882a593Smuzhiyun errcnt++;
1685*4882a593Smuzhiyun if (errcnt >= 20)
1686*4882a593Smuzhiyun break;
1687*4882a593Smuzhiyun }
1688*4882a593Smuzhiyun }
1689*4882a593Smuzhiyun
1690*4882a593Smuzhiyun if (!errcnt)
1691*4882a593Smuzhiyun D_INFO("ucode image in INSTRUCTION memory is good\n");
1692*4882a593Smuzhiyun
1693*4882a593Smuzhiyun return rc;
1694*4882a593Smuzhiyun }
1695*4882a593Smuzhiyun
1696*4882a593Smuzhiyun /*
1697*4882a593Smuzhiyun * il3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
1698*4882a593Smuzhiyun * using sample data 100 bytes apart. If these sample points are good,
1699*4882a593Smuzhiyun * it's a pretty good bet that everything between them is good, too.
1700*4882a593Smuzhiyun */
1701*4882a593Smuzhiyun static int
il3945_verify_inst_sparse(struct il_priv * il,__le32 * image,u32 len)1702*4882a593Smuzhiyun il3945_verify_inst_sparse(struct il_priv *il, __le32 * image, u32 len)
1703*4882a593Smuzhiyun {
1704*4882a593Smuzhiyun u32 val;
1705*4882a593Smuzhiyun int rc = 0;
1706*4882a593Smuzhiyun u32 errcnt = 0;
1707*4882a593Smuzhiyun u32 i;
1708*4882a593Smuzhiyun
1709*4882a593Smuzhiyun D_INFO("ucode inst image size is %u\n", len);
1710*4882a593Smuzhiyun
1711*4882a593Smuzhiyun for (i = 0; i < len; i += 100, image += 100 / sizeof(u32)) {
1712*4882a593Smuzhiyun /* read data comes through single port, auto-incr addr */
1713*4882a593Smuzhiyun /* NOTE: Use the debugless read so we don't flood kernel log
1714*4882a593Smuzhiyun * if IL_DL_IO is set */
1715*4882a593Smuzhiyun il_wr(il, HBUS_TARG_MEM_RADDR, i + IL39_RTC_INST_LOWER_BOUND);
1716*4882a593Smuzhiyun val = _il_rd(il, HBUS_TARG_MEM_RDAT);
1717*4882a593Smuzhiyun if (val != le32_to_cpu(*image)) {
1718*4882a593Smuzhiyun #if 0 /* Enable this if you want to see details */
1719*4882a593Smuzhiyun IL_ERR("uCode INST section is invalid at "
1720*4882a593Smuzhiyun "offset 0x%x, is 0x%x, s/b 0x%x\n", i, val,
1721*4882a593Smuzhiyun *image);
1722*4882a593Smuzhiyun #endif
1723*4882a593Smuzhiyun rc = -EIO;
1724*4882a593Smuzhiyun errcnt++;
1725*4882a593Smuzhiyun if (errcnt >= 3)
1726*4882a593Smuzhiyun break;
1727*4882a593Smuzhiyun }
1728*4882a593Smuzhiyun }
1729*4882a593Smuzhiyun
1730*4882a593Smuzhiyun return rc;
1731*4882a593Smuzhiyun }
1732*4882a593Smuzhiyun
1733*4882a593Smuzhiyun /*
1734*4882a593Smuzhiyun * il3945_verify_ucode - determine which instruction image is in SRAM,
1735*4882a593Smuzhiyun * and verify its contents
1736*4882a593Smuzhiyun */
1737*4882a593Smuzhiyun static int
il3945_verify_ucode(struct il_priv * il)1738*4882a593Smuzhiyun il3945_verify_ucode(struct il_priv *il)
1739*4882a593Smuzhiyun {
1740*4882a593Smuzhiyun __le32 *image;
1741*4882a593Smuzhiyun u32 len;
1742*4882a593Smuzhiyun int rc = 0;
1743*4882a593Smuzhiyun
1744*4882a593Smuzhiyun /* Try bootstrap */
1745*4882a593Smuzhiyun image = (__le32 *) il->ucode_boot.v_addr;
1746*4882a593Smuzhiyun len = il->ucode_boot.len;
1747*4882a593Smuzhiyun rc = il3945_verify_inst_sparse(il, image, len);
1748*4882a593Smuzhiyun if (rc == 0) {
1749*4882a593Smuzhiyun D_INFO("Bootstrap uCode is good in inst SRAM\n");
1750*4882a593Smuzhiyun return 0;
1751*4882a593Smuzhiyun }
1752*4882a593Smuzhiyun
1753*4882a593Smuzhiyun /* Try initialize */
1754*4882a593Smuzhiyun image = (__le32 *) il->ucode_init.v_addr;
1755*4882a593Smuzhiyun len = il->ucode_init.len;
1756*4882a593Smuzhiyun rc = il3945_verify_inst_sparse(il, image, len);
1757*4882a593Smuzhiyun if (rc == 0) {
1758*4882a593Smuzhiyun D_INFO("Initialize uCode is good in inst SRAM\n");
1759*4882a593Smuzhiyun return 0;
1760*4882a593Smuzhiyun }
1761*4882a593Smuzhiyun
1762*4882a593Smuzhiyun /* Try runtime/protocol */
1763*4882a593Smuzhiyun image = (__le32 *) il->ucode_code.v_addr;
1764*4882a593Smuzhiyun len = il->ucode_code.len;
1765*4882a593Smuzhiyun rc = il3945_verify_inst_sparse(il, image, len);
1766*4882a593Smuzhiyun if (rc == 0) {
1767*4882a593Smuzhiyun D_INFO("Runtime uCode is good in inst SRAM\n");
1768*4882a593Smuzhiyun return 0;
1769*4882a593Smuzhiyun }
1770*4882a593Smuzhiyun
1771*4882a593Smuzhiyun IL_ERR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
1772*4882a593Smuzhiyun
1773*4882a593Smuzhiyun /* Since nothing seems to match, show first several data entries in
1774*4882a593Smuzhiyun * instruction SRAM, so maybe visual inspection will give a clue.
1775*4882a593Smuzhiyun * Selection of bootstrap image (vs. other images) is arbitrary. */
1776*4882a593Smuzhiyun image = (__le32 *) il->ucode_boot.v_addr;
1777*4882a593Smuzhiyun len = il->ucode_boot.len;
1778*4882a593Smuzhiyun rc = il3945_verify_inst_full(il, image, len);
1779*4882a593Smuzhiyun
1780*4882a593Smuzhiyun return rc;
1781*4882a593Smuzhiyun }
1782*4882a593Smuzhiyun
1783*4882a593Smuzhiyun static void
il3945_nic_start(struct il_priv * il)1784*4882a593Smuzhiyun il3945_nic_start(struct il_priv *il)
1785*4882a593Smuzhiyun {
1786*4882a593Smuzhiyun /* Remove all resets to allow NIC to operate */
1787*4882a593Smuzhiyun _il_wr(il, CSR_RESET, 0);
1788*4882a593Smuzhiyun }
1789*4882a593Smuzhiyun
1790*4882a593Smuzhiyun #define IL3945_UCODE_GET(item) \
1791*4882a593Smuzhiyun static u32 il3945_ucode_get_##item(const struct il_ucode_header *ucode)\
1792*4882a593Smuzhiyun { \
1793*4882a593Smuzhiyun return le32_to_cpu(ucode->v1.item); \
1794*4882a593Smuzhiyun }
1795*4882a593Smuzhiyun
1796*4882a593Smuzhiyun static u32
il3945_ucode_get_header_size(u32 api_ver)1797*4882a593Smuzhiyun il3945_ucode_get_header_size(u32 api_ver)
1798*4882a593Smuzhiyun {
1799*4882a593Smuzhiyun return 24;
1800*4882a593Smuzhiyun }
1801*4882a593Smuzhiyun
1802*4882a593Smuzhiyun static u8 *
il3945_ucode_get_data(const struct il_ucode_header * ucode)1803*4882a593Smuzhiyun il3945_ucode_get_data(const struct il_ucode_header *ucode)
1804*4882a593Smuzhiyun {
1805*4882a593Smuzhiyun return (u8 *) ucode->v1.data;
1806*4882a593Smuzhiyun }
1807*4882a593Smuzhiyun
1808*4882a593Smuzhiyun IL3945_UCODE_GET(inst_size);
1809*4882a593Smuzhiyun IL3945_UCODE_GET(data_size);
1810*4882a593Smuzhiyun IL3945_UCODE_GET(init_size);
1811*4882a593Smuzhiyun IL3945_UCODE_GET(init_data_size);
1812*4882a593Smuzhiyun IL3945_UCODE_GET(boot_size);
1813*4882a593Smuzhiyun
1814*4882a593Smuzhiyun /*
1815*4882a593Smuzhiyun * il3945_read_ucode - Read uCode images from disk file.
1816*4882a593Smuzhiyun *
1817*4882a593Smuzhiyun * Copy into buffers for card to fetch via bus-mastering
1818*4882a593Smuzhiyun */
1819*4882a593Smuzhiyun static int
il3945_read_ucode(struct il_priv * il)1820*4882a593Smuzhiyun il3945_read_ucode(struct il_priv *il)
1821*4882a593Smuzhiyun {
1822*4882a593Smuzhiyun const struct il_ucode_header *ucode;
1823*4882a593Smuzhiyun int ret = -EINVAL, idx;
1824*4882a593Smuzhiyun const struct firmware *ucode_raw;
1825*4882a593Smuzhiyun /* firmware file name contains uCode/driver compatibility version */
1826*4882a593Smuzhiyun const char *name_pre = il->cfg->fw_name_pre;
1827*4882a593Smuzhiyun const unsigned int api_max = il->cfg->ucode_api_max;
1828*4882a593Smuzhiyun const unsigned int api_min = il->cfg->ucode_api_min;
1829*4882a593Smuzhiyun char buf[25];
1830*4882a593Smuzhiyun u8 *src;
1831*4882a593Smuzhiyun size_t len;
1832*4882a593Smuzhiyun u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
1833*4882a593Smuzhiyun
1834*4882a593Smuzhiyun /* Ask kernel firmware_class module to get the boot firmware off disk.
1835*4882a593Smuzhiyun * request_firmware() is synchronous, file is in memory on return. */
1836*4882a593Smuzhiyun for (idx = api_max; idx >= api_min; idx--) {
1837*4882a593Smuzhiyun sprintf(buf, "%s%u%s", name_pre, idx, ".ucode");
1838*4882a593Smuzhiyun ret = request_firmware(&ucode_raw, buf, &il->pci_dev->dev);
1839*4882a593Smuzhiyun if (ret < 0) {
1840*4882a593Smuzhiyun IL_ERR("%s firmware file req failed: %d\n", buf, ret);
1841*4882a593Smuzhiyun if (ret == -ENOENT)
1842*4882a593Smuzhiyun continue;
1843*4882a593Smuzhiyun else
1844*4882a593Smuzhiyun goto error;
1845*4882a593Smuzhiyun } else {
1846*4882a593Smuzhiyun if (idx < api_max)
1847*4882a593Smuzhiyun IL_ERR("Loaded firmware %s, "
1848*4882a593Smuzhiyun "which is deprecated. "
1849*4882a593Smuzhiyun " Please use API v%u instead.\n", buf,
1850*4882a593Smuzhiyun api_max);
1851*4882a593Smuzhiyun D_INFO("Got firmware '%s' file "
1852*4882a593Smuzhiyun "(%zd bytes) from disk\n", buf, ucode_raw->size);
1853*4882a593Smuzhiyun break;
1854*4882a593Smuzhiyun }
1855*4882a593Smuzhiyun }
1856*4882a593Smuzhiyun
1857*4882a593Smuzhiyun if (ret < 0)
1858*4882a593Smuzhiyun goto error;
1859*4882a593Smuzhiyun
1860*4882a593Smuzhiyun /* Make sure that we got at least our header! */
1861*4882a593Smuzhiyun if (ucode_raw->size < il3945_ucode_get_header_size(1)) {
1862*4882a593Smuzhiyun IL_ERR("File size way too small!\n");
1863*4882a593Smuzhiyun ret = -EINVAL;
1864*4882a593Smuzhiyun goto err_release;
1865*4882a593Smuzhiyun }
1866*4882a593Smuzhiyun
1867*4882a593Smuzhiyun /* Data from ucode file: header followed by uCode images */
1868*4882a593Smuzhiyun ucode = (struct il_ucode_header *)ucode_raw->data;
1869*4882a593Smuzhiyun
1870*4882a593Smuzhiyun il->ucode_ver = le32_to_cpu(ucode->ver);
1871*4882a593Smuzhiyun api_ver = IL_UCODE_API(il->ucode_ver);
1872*4882a593Smuzhiyun inst_size = il3945_ucode_get_inst_size(ucode);
1873*4882a593Smuzhiyun data_size = il3945_ucode_get_data_size(ucode);
1874*4882a593Smuzhiyun init_size = il3945_ucode_get_init_size(ucode);
1875*4882a593Smuzhiyun init_data_size = il3945_ucode_get_init_data_size(ucode);
1876*4882a593Smuzhiyun boot_size = il3945_ucode_get_boot_size(ucode);
1877*4882a593Smuzhiyun src = il3945_ucode_get_data(ucode);
1878*4882a593Smuzhiyun
1879*4882a593Smuzhiyun /* api_ver should match the api version forming part of the
1880*4882a593Smuzhiyun * firmware filename ... but we don't check for that and only rely
1881*4882a593Smuzhiyun * on the API version read from firmware header from here on forward */
1882*4882a593Smuzhiyun
1883*4882a593Smuzhiyun if (api_ver < api_min || api_ver > api_max) {
1884*4882a593Smuzhiyun IL_ERR("Driver unable to support your firmware API. "
1885*4882a593Smuzhiyun "Driver supports v%u, firmware is v%u.\n", api_max,
1886*4882a593Smuzhiyun api_ver);
1887*4882a593Smuzhiyun il->ucode_ver = 0;
1888*4882a593Smuzhiyun ret = -EINVAL;
1889*4882a593Smuzhiyun goto err_release;
1890*4882a593Smuzhiyun }
1891*4882a593Smuzhiyun if (api_ver != api_max)
1892*4882a593Smuzhiyun IL_ERR("Firmware has old API version. Expected %u, "
1893*4882a593Smuzhiyun "got %u. New firmware can be obtained "
1894*4882a593Smuzhiyun "from http://www.intellinuxwireless.org.\n", api_max,
1895*4882a593Smuzhiyun api_ver);
1896*4882a593Smuzhiyun
1897*4882a593Smuzhiyun IL_INFO("loaded firmware version %u.%u.%u.%u\n",
1898*4882a593Smuzhiyun IL_UCODE_MAJOR(il->ucode_ver), IL_UCODE_MINOR(il->ucode_ver),
1899*4882a593Smuzhiyun IL_UCODE_API(il->ucode_ver), IL_UCODE_SERIAL(il->ucode_ver));
1900*4882a593Smuzhiyun
1901*4882a593Smuzhiyun snprintf(il->hw->wiphy->fw_version, sizeof(il->hw->wiphy->fw_version),
1902*4882a593Smuzhiyun "%u.%u.%u.%u", IL_UCODE_MAJOR(il->ucode_ver),
1903*4882a593Smuzhiyun IL_UCODE_MINOR(il->ucode_ver), IL_UCODE_API(il->ucode_ver),
1904*4882a593Smuzhiyun IL_UCODE_SERIAL(il->ucode_ver));
1905*4882a593Smuzhiyun
1906*4882a593Smuzhiyun D_INFO("f/w package hdr ucode version raw = 0x%x\n", il->ucode_ver);
1907*4882a593Smuzhiyun D_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
1908*4882a593Smuzhiyun D_INFO("f/w package hdr runtime data size = %u\n", data_size);
1909*4882a593Smuzhiyun D_INFO("f/w package hdr init inst size = %u\n", init_size);
1910*4882a593Smuzhiyun D_INFO("f/w package hdr init data size = %u\n", init_data_size);
1911*4882a593Smuzhiyun D_INFO("f/w package hdr boot inst size = %u\n", boot_size);
1912*4882a593Smuzhiyun
1913*4882a593Smuzhiyun /* Verify size of file vs. image size info in file's header */
1914*4882a593Smuzhiyun if (ucode_raw->size !=
1915*4882a593Smuzhiyun il3945_ucode_get_header_size(api_ver) + inst_size + data_size +
1916*4882a593Smuzhiyun init_size + init_data_size + boot_size) {
1917*4882a593Smuzhiyun
1918*4882a593Smuzhiyun D_INFO("uCode file size %zd does not match expected size\n",
1919*4882a593Smuzhiyun ucode_raw->size);
1920*4882a593Smuzhiyun ret = -EINVAL;
1921*4882a593Smuzhiyun goto err_release;
1922*4882a593Smuzhiyun }
1923*4882a593Smuzhiyun
1924*4882a593Smuzhiyun /* Verify that uCode images will fit in card's SRAM */
1925*4882a593Smuzhiyun if (inst_size > IL39_MAX_INST_SIZE) {
1926*4882a593Smuzhiyun D_INFO("uCode instr len %d too large to fit in\n", inst_size);
1927*4882a593Smuzhiyun ret = -EINVAL;
1928*4882a593Smuzhiyun goto err_release;
1929*4882a593Smuzhiyun }
1930*4882a593Smuzhiyun
1931*4882a593Smuzhiyun if (data_size > IL39_MAX_DATA_SIZE) {
1932*4882a593Smuzhiyun D_INFO("uCode data len %d too large to fit in\n", data_size);
1933*4882a593Smuzhiyun ret = -EINVAL;
1934*4882a593Smuzhiyun goto err_release;
1935*4882a593Smuzhiyun }
1936*4882a593Smuzhiyun if (init_size > IL39_MAX_INST_SIZE) {
1937*4882a593Smuzhiyun D_INFO("uCode init instr len %d too large to fit in\n",
1938*4882a593Smuzhiyun init_size);
1939*4882a593Smuzhiyun ret = -EINVAL;
1940*4882a593Smuzhiyun goto err_release;
1941*4882a593Smuzhiyun }
1942*4882a593Smuzhiyun if (init_data_size > IL39_MAX_DATA_SIZE) {
1943*4882a593Smuzhiyun D_INFO("uCode init data len %d too large to fit in\n",
1944*4882a593Smuzhiyun init_data_size);
1945*4882a593Smuzhiyun ret = -EINVAL;
1946*4882a593Smuzhiyun goto err_release;
1947*4882a593Smuzhiyun }
1948*4882a593Smuzhiyun if (boot_size > IL39_MAX_BSM_SIZE) {
1949*4882a593Smuzhiyun D_INFO("uCode boot instr len %d too large to fit in\n",
1950*4882a593Smuzhiyun boot_size);
1951*4882a593Smuzhiyun ret = -EINVAL;
1952*4882a593Smuzhiyun goto err_release;
1953*4882a593Smuzhiyun }
1954*4882a593Smuzhiyun
1955*4882a593Smuzhiyun /* Allocate ucode buffers for card's bus-master loading ... */
1956*4882a593Smuzhiyun
1957*4882a593Smuzhiyun /* Runtime instructions and 2 copies of data:
1958*4882a593Smuzhiyun * 1) unmodified from disk
1959*4882a593Smuzhiyun * 2) backup cache for save/restore during power-downs */
1960*4882a593Smuzhiyun il->ucode_code.len = inst_size;
1961*4882a593Smuzhiyun il_alloc_fw_desc(il->pci_dev, &il->ucode_code);
1962*4882a593Smuzhiyun
1963*4882a593Smuzhiyun il->ucode_data.len = data_size;
1964*4882a593Smuzhiyun il_alloc_fw_desc(il->pci_dev, &il->ucode_data);
1965*4882a593Smuzhiyun
1966*4882a593Smuzhiyun il->ucode_data_backup.len = data_size;
1967*4882a593Smuzhiyun il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup);
1968*4882a593Smuzhiyun
1969*4882a593Smuzhiyun if (!il->ucode_code.v_addr || !il->ucode_data.v_addr ||
1970*4882a593Smuzhiyun !il->ucode_data_backup.v_addr)
1971*4882a593Smuzhiyun goto err_pci_alloc;
1972*4882a593Smuzhiyun
1973*4882a593Smuzhiyun /* Initialization instructions and data */
1974*4882a593Smuzhiyun if (init_size && init_data_size) {
1975*4882a593Smuzhiyun il->ucode_init.len = init_size;
1976*4882a593Smuzhiyun il_alloc_fw_desc(il->pci_dev, &il->ucode_init);
1977*4882a593Smuzhiyun
1978*4882a593Smuzhiyun il->ucode_init_data.len = init_data_size;
1979*4882a593Smuzhiyun il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data);
1980*4882a593Smuzhiyun
1981*4882a593Smuzhiyun if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr)
1982*4882a593Smuzhiyun goto err_pci_alloc;
1983*4882a593Smuzhiyun }
1984*4882a593Smuzhiyun
1985*4882a593Smuzhiyun /* Bootstrap (instructions only, no data) */
1986*4882a593Smuzhiyun if (boot_size) {
1987*4882a593Smuzhiyun il->ucode_boot.len = boot_size;
1988*4882a593Smuzhiyun il_alloc_fw_desc(il->pci_dev, &il->ucode_boot);
1989*4882a593Smuzhiyun
1990*4882a593Smuzhiyun if (!il->ucode_boot.v_addr)
1991*4882a593Smuzhiyun goto err_pci_alloc;
1992*4882a593Smuzhiyun }
1993*4882a593Smuzhiyun
1994*4882a593Smuzhiyun /* Copy images into buffers for card's bus-master reads ... */
1995*4882a593Smuzhiyun
1996*4882a593Smuzhiyun /* Runtime instructions (first block of data in file) */
1997*4882a593Smuzhiyun len = inst_size;
1998*4882a593Smuzhiyun D_INFO("Copying (but not loading) uCode instr len %zd\n", len);
1999*4882a593Smuzhiyun memcpy(il->ucode_code.v_addr, src, len);
2000*4882a593Smuzhiyun src += len;
2001*4882a593Smuzhiyun
2002*4882a593Smuzhiyun D_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
2003*4882a593Smuzhiyun il->ucode_code.v_addr, (u32) il->ucode_code.p_addr);
2004*4882a593Smuzhiyun
2005*4882a593Smuzhiyun /* Runtime data (2nd block)
2006*4882a593Smuzhiyun * NOTE: Copy into backup buffer will be done in il3945_up() */
2007*4882a593Smuzhiyun len = data_size;
2008*4882a593Smuzhiyun D_INFO("Copying (but not loading) uCode data len %zd\n", len);
2009*4882a593Smuzhiyun memcpy(il->ucode_data.v_addr, src, len);
2010*4882a593Smuzhiyun memcpy(il->ucode_data_backup.v_addr, src, len);
2011*4882a593Smuzhiyun src += len;
2012*4882a593Smuzhiyun
2013*4882a593Smuzhiyun /* Initialization instructions (3rd block) */
2014*4882a593Smuzhiyun if (init_size) {
2015*4882a593Smuzhiyun len = init_size;
2016*4882a593Smuzhiyun D_INFO("Copying (but not loading) init instr len %zd\n", len);
2017*4882a593Smuzhiyun memcpy(il->ucode_init.v_addr, src, len);
2018*4882a593Smuzhiyun src += len;
2019*4882a593Smuzhiyun }
2020*4882a593Smuzhiyun
2021*4882a593Smuzhiyun /* Initialization data (4th block) */
2022*4882a593Smuzhiyun if (init_data_size) {
2023*4882a593Smuzhiyun len = init_data_size;
2024*4882a593Smuzhiyun D_INFO("Copying (but not loading) init data len %zd\n", len);
2025*4882a593Smuzhiyun memcpy(il->ucode_init_data.v_addr, src, len);
2026*4882a593Smuzhiyun src += len;
2027*4882a593Smuzhiyun }
2028*4882a593Smuzhiyun
2029*4882a593Smuzhiyun /* Bootstrap instructions (5th block) */
2030*4882a593Smuzhiyun len = boot_size;
2031*4882a593Smuzhiyun D_INFO("Copying (but not loading) boot instr len %zd\n", len);
2032*4882a593Smuzhiyun memcpy(il->ucode_boot.v_addr, src, len);
2033*4882a593Smuzhiyun
2034*4882a593Smuzhiyun /* We have our copies now, allow OS release its copies */
2035*4882a593Smuzhiyun release_firmware(ucode_raw);
2036*4882a593Smuzhiyun return 0;
2037*4882a593Smuzhiyun
2038*4882a593Smuzhiyun err_pci_alloc:
2039*4882a593Smuzhiyun IL_ERR("failed to allocate pci memory\n");
2040*4882a593Smuzhiyun ret = -ENOMEM;
2041*4882a593Smuzhiyun il3945_dealloc_ucode_pci(il);
2042*4882a593Smuzhiyun
2043*4882a593Smuzhiyun err_release:
2044*4882a593Smuzhiyun release_firmware(ucode_raw);
2045*4882a593Smuzhiyun
2046*4882a593Smuzhiyun error:
2047*4882a593Smuzhiyun return ret;
2048*4882a593Smuzhiyun }
2049*4882a593Smuzhiyun
2050*4882a593Smuzhiyun /*
2051*4882a593Smuzhiyun * il3945_set_ucode_ptrs - Set uCode address location
2052*4882a593Smuzhiyun *
2053*4882a593Smuzhiyun * Tell initialization uCode where to find runtime uCode.
2054*4882a593Smuzhiyun *
2055*4882a593Smuzhiyun * BSM registers initially contain pointers to initialization uCode.
2056*4882a593Smuzhiyun * We need to replace them to load runtime uCode inst and data,
2057*4882a593Smuzhiyun * and to save runtime data when powering down.
2058*4882a593Smuzhiyun */
2059*4882a593Smuzhiyun static int
il3945_set_ucode_ptrs(struct il_priv * il)2060*4882a593Smuzhiyun il3945_set_ucode_ptrs(struct il_priv *il)
2061*4882a593Smuzhiyun {
2062*4882a593Smuzhiyun dma_addr_t pinst;
2063*4882a593Smuzhiyun dma_addr_t pdata;
2064*4882a593Smuzhiyun
2065*4882a593Smuzhiyun /* bits 31:0 for 3945 */
2066*4882a593Smuzhiyun pinst = il->ucode_code.p_addr;
2067*4882a593Smuzhiyun pdata = il->ucode_data_backup.p_addr;
2068*4882a593Smuzhiyun
2069*4882a593Smuzhiyun /* Tell bootstrap uCode where to find image to load */
2070*4882a593Smuzhiyun il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
2071*4882a593Smuzhiyun il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
2072*4882a593Smuzhiyun il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, il->ucode_data.len);
2073*4882a593Smuzhiyun
2074*4882a593Smuzhiyun /* Inst byte count must be last to set up, bit 31 signals uCode
2075*4882a593Smuzhiyun * that all new ptr/size info is in place */
2076*4882a593Smuzhiyun il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG,
2077*4882a593Smuzhiyun il->ucode_code.len | BSM_DRAM_INST_LOAD);
2078*4882a593Smuzhiyun
2079*4882a593Smuzhiyun D_INFO("Runtime uCode pointers are set.\n");
2080*4882a593Smuzhiyun
2081*4882a593Smuzhiyun return 0;
2082*4882a593Smuzhiyun }
2083*4882a593Smuzhiyun
2084*4882a593Smuzhiyun /*
2085*4882a593Smuzhiyun * il3945_init_alive_start - Called after N_ALIVE notification received
2086*4882a593Smuzhiyun *
2087*4882a593Smuzhiyun * Called after N_ALIVE notification received from "initialize" uCode.
2088*4882a593Smuzhiyun *
2089*4882a593Smuzhiyun * Tell "initialize" uCode to go ahead and load the runtime uCode.
2090*4882a593Smuzhiyun */
2091*4882a593Smuzhiyun static void
il3945_init_alive_start(struct il_priv * il)2092*4882a593Smuzhiyun il3945_init_alive_start(struct il_priv *il)
2093*4882a593Smuzhiyun {
2094*4882a593Smuzhiyun /* Check alive response for "valid" sign from uCode */
2095*4882a593Smuzhiyun if (il->card_alive_init.is_valid != UCODE_VALID_OK) {
2096*4882a593Smuzhiyun /* We had an error bringing up the hardware, so take it
2097*4882a593Smuzhiyun * all the way back down so we can try again */
2098*4882a593Smuzhiyun D_INFO("Initialize Alive failed.\n");
2099*4882a593Smuzhiyun goto restart;
2100*4882a593Smuzhiyun }
2101*4882a593Smuzhiyun
2102*4882a593Smuzhiyun /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
2103*4882a593Smuzhiyun * This is a paranoid check, because we would not have gotten the
2104*4882a593Smuzhiyun * "initialize" alive if code weren't properly loaded. */
2105*4882a593Smuzhiyun if (il3945_verify_ucode(il)) {
2106*4882a593Smuzhiyun /* Runtime instruction load was bad;
2107*4882a593Smuzhiyun * take it all the way back down so we can try again */
2108*4882a593Smuzhiyun D_INFO("Bad \"initialize\" uCode load.\n");
2109*4882a593Smuzhiyun goto restart;
2110*4882a593Smuzhiyun }
2111*4882a593Smuzhiyun
2112*4882a593Smuzhiyun /* Send pointers to protocol/runtime uCode image ... init code will
2113*4882a593Smuzhiyun * load and launch runtime uCode, which will send us another "Alive"
2114*4882a593Smuzhiyun * notification. */
2115*4882a593Smuzhiyun D_INFO("Initialization Alive received.\n");
2116*4882a593Smuzhiyun if (il3945_set_ucode_ptrs(il)) {
2117*4882a593Smuzhiyun /* Runtime instruction load won't happen;
2118*4882a593Smuzhiyun * take it all the way back down so we can try again */
2119*4882a593Smuzhiyun D_INFO("Couldn't set up uCode pointers.\n");
2120*4882a593Smuzhiyun goto restart;
2121*4882a593Smuzhiyun }
2122*4882a593Smuzhiyun return;
2123*4882a593Smuzhiyun
2124*4882a593Smuzhiyun restart:
2125*4882a593Smuzhiyun queue_work(il->workqueue, &il->restart);
2126*4882a593Smuzhiyun }
2127*4882a593Smuzhiyun
2128*4882a593Smuzhiyun /*
2129*4882a593Smuzhiyun * il3945_alive_start - called after N_ALIVE notification received
2130*4882a593Smuzhiyun * from protocol/runtime uCode (initialization uCode's
2131*4882a593Smuzhiyun * Alive gets handled by il3945_init_alive_start()).
2132*4882a593Smuzhiyun */
2133*4882a593Smuzhiyun static void
il3945_alive_start(struct il_priv * il)2134*4882a593Smuzhiyun il3945_alive_start(struct il_priv *il)
2135*4882a593Smuzhiyun {
2136*4882a593Smuzhiyun int thermal_spin = 0;
2137*4882a593Smuzhiyun u32 rfkill;
2138*4882a593Smuzhiyun
2139*4882a593Smuzhiyun D_INFO("Runtime Alive received.\n");
2140*4882a593Smuzhiyun
2141*4882a593Smuzhiyun if (il->card_alive.is_valid != UCODE_VALID_OK) {
2142*4882a593Smuzhiyun /* We had an error bringing up the hardware, so take it
2143*4882a593Smuzhiyun * all the way back down so we can try again */
2144*4882a593Smuzhiyun D_INFO("Alive failed.\n");
2145*4882a593Smuzhiyun goto restart;
2146*4882a593Smuzhiyun }
2147*4882a593Smuzhiyun
2148*4882a593Smuzhiyun /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2149*4882a593Smuzhiyun * This is a paranoid check, because we would not have gotten the
2150*4882a593Smuzhiyun * "runtime" alive if code weren't properly loaded. */
2151*4882a593Smuzhiyun if (il3945_verify_ucode(il)) {
2152*4882a593Smuzhiyun /* Runtime instruction load was bad;
2153*4882a593Smuzhiyun * take it all the way back down so we can try again */
2154*4882a593Smuzhiyun D_INFO("Bad runtime uCode load.\n");
2155*4882a593Smuzhiyun goto restart;
2156*4882a593Smuzhiyun }
2157*4882a593Smuzhiyun
2158*4882a593Smuzhiyun rfkill = il_rd_prph(il, APMG_RFKILL_REG);
2159*4882a593Smuzhiyun D_INFO("RFKILL status: 0x%x\n", rfkill);
2160*4882a593Smuzhiyun
2161*4882a593Smuzhiyun if (rfkill & 0x1) {
2162*4882a593Smuzhiyun clear_bit(S_RFKILL, &il->status);
2163*4882a593Smuzhiyun /* if RFKILL is not on, then wait for thermal
2164*4882a593Smuzhiyun * sensor in adapter to kick in */
2165*4882a593Smuzhiyun while (il3945_hw_get_temperature(il) == 0) {
2166*4882a593Smuzhiyun thermal_spin++;
2167*4882a593Smuzhiyun udelay(10);
2168*4882a593Smuzhiyun }
2169*4882a593Smuzhiyun
2170*4882a593Smuzhiyun if (thermal_spin)
2171*4882a593Smuzhiyun D_INFO("Thermal calibration took %dus\n",
2172*4882a593Smuzhiyun thermal_spin * 10);
2173*4882a593Smuzhiyun } else
2174*4882a593Smuzhiyun set_bit(S_RFKILL, &il->status);
2175*4882a593Smuzhiyun
2176*4882a593Smuzhiyun /* After the ALIVE response, we can send commands to 3945 uCode */
2177*4882a593Smuzhiyun set_bit(S_ALIVE, &il->status);
2178*4882a593Smuzhiyun
2179*4882a593Smuzhiyun /* Enable watchdog to monitor the driver tx queues */
2180*4882a593Smuzhiyun il_setup_watchdog(il);
2181*4882a593Smuzhiyun
2182*4882a593Smuzhiyun if (il_is_rfkill(il))
2183*4882a593Smuzhiyun return;
2184*4882a593Smuzhiyun
2185*4882a593Smuzhiyun ieee80211_wake_queues(il->hw);
2186*4882a593Smuzhiyun
2187*4882a593Smuzhiyun il->active_rate = RATES_MASK_3945;
2188*4882a593Smuzhiyun
2189*4882a593Smuzhiyun il_power_update_mode(il, true);
2190*4882a593Smuzhiyun
2191*4882a593Smuzhiyun if (il_is_associated(il)) {
2192*4882a593Smuzhiyun struct il3945_rxon_cmd *active_rxon =
2193*4882a593Smuzhiyun (struct il3945_rxon_cmd *)(&il->active);
2194*4882a593Smuzhiyun
2195*4882a593Smuzhiyun il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2196*4882a593Smuzhiyun active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2197*4882a593Smuzhiyun } else {
2198*4882a593Smuzhiyun /* Initialize our rx_config data */
2199*4882a593Smuzhiyun il_connection_init_rx_config(il);
2200*4882a593Smuzhiyun }
2201*4882a593Smuzhiyun
2202*4882a593Smuzhiyun /* Configure Bluetooth device coexistence support */
2203*4882a593Smuzhiyun il_send_bt_config(il);
2204*4882a593Smuzhiyun
2205*4882a593Smuzhiyun set_bit(S_READY, &il->status);
2206*4882a593Smuzhiyun
2207*4882a593Smuzhiyun /* Configure the adapter for unassociated operation */
2208*4882a593Smuzhiyun il3945_commit_rxon(il);
2209*4882a593Smuzhiyun
2210*4882a593Smuzhiyun il3945_reg_txpower_periodic(il);
2211*4882a593Smuzhiyun
2212*4882a593Smuzhiyun D_INFO("ALIVE processing complete.\n");
2213*4882a593Smuzhiyun wake_up(&il->wait_command_queue);
2214*4882a593Smuzhiyun
2215*4882a593Smuzhiyun return;
2216*4882a593Smuzhiyun
2217*4882a593Smuzhiyun restart:
2218*4882a593Smuzhiyun queue_work(il->workqueue, &il->restart);
2219*4882a593Smuzhiyun }
2220*4882a593Smuzhiyun
2221*4882a593Smuzhiyun static void il3945_cancel_deferred_work(struct il_priv *il);
2222*4882a593Smuzhiyun
2223*4882a593Smuzhiyun static void
__il3945_down(struct il_priv * il)2224*4882a593Smuzhiyun __il3945_down(struct il_priv *il)
2225*4882a593Smuzhiyun {
2226*4882a593Smuzhiyun unsigned long flags;
2227*4882a593Smuzhiyun int exit_pending;
2228*4882a593Smuzhiyun
2229*4882a593Smuzhiyun D_INFO(DRV_NAME " is going down\n");
2230*4882a593Smuzhiyun
2231*4882a593Smuzhiyun il_scan_cancel_timeout(il, 200);
2232*4882a593Smuzhiyun
2233*4882a593Smuzhiyun exit_pending = test_and_set_bit(S_EXIT_PENDING, &il->status);
2234*4882a593Smuzhiyun
2235*4882a593Smuzhiyun /* Stop TX queues watchdog. We need to have S_EXIT_PENDING bit set
2236*4882a593Smuzhiyun * to prevent rearm timer */
2237*4882a593Smuzhiyun del_timer_sync(&il->watchdog);
2238*4882a593Smuzhiyun
2239*4882a593Smuzhiyun /* Station information will now be cleared in device */
2240*4882a593Smuzhiyun il_clear_ucode_stations(il);
2241*4882a593Smuzhiyun il_dealloc_bcast_stations(il);
2242*4882a593Smuzhiyun il_clear_driver_stations(il);
2243*4882a593Smuzhiyun
2244*4882a593Smuzhiyun /* Unblock any waiting calls */
2245*4882a593Smuzhiyun wake_up_all(&il->wait_command_queue);
2246*4882a593Smuzhiyun
2247*4882a593Smuzhiyun /* Wipe out the EXIT_PENDING status bit if we are not actually
2248*4882a593Smuzhiyun * exiting the module */
2249*4882a593Smuzhiyun if (!exit_pending)
2250*4882a593Smuzhiyun clear_bit(S_EXIT_PENDING, &il->status);
2251*4882a593Smuzhiyun
2252*4882a593Smuzhiyun /* stop and reset the on-board processor */
2253*4882a593Smuzhiyun _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2254*4882a593Smuzhiyun
2255*4882a593Smuzhiyun /* tell the device to stop sending interrupts */
2256*4882a593Smuzhiyun spin_lock_irqsave(&il->lock, flags);
2257*4882a593Smuzhiyun il_disable_interrupts(il);
2258*4882a593Smuzhiyun spin_unlock_irqrestore(&il->lock, flags);
2259*4882a593Smuzhiyun il3945_synchronize_irq(il);
2260*4882a593Smuzhiyun
2261*4882a593Smuzhiyun if (il->mac80211_registered)
2262*4882a593Smuzhiyun ieee80211_stop_queues(il->hw);
2263*4882a593Smuzhiyun
2264*4882a593Smuzhiyun /* If we have not previously called il3945_init() then
2265*4882a593Smuzhiyun * clear all bits but the RF Kill bits and return */
2266*4882a593Smuzhiyun if (!il_is_init(il)) {
2267*4882a593Smuzhiyun il->status =
2268*4882a593Smuzhiyun test_bit(S_RFKILL, &il->status) << S_RFKILL |
2269*4882a593Smuzhiyun test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
2270*4882a593Smuzhiyun test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
2271*4882a593Smuzhiyun goto exit;
2272*4882a593Smuzhiyun }
2273*4882a593Smuzhiyun
2274*4882a593Smuzhiyun /* ...otherwise clear out all the status bits but the RF Kill
2275*4882a593Smuzhiyun * bit and continue taking the NIC down. */
2276*4882a593Smuzhiyun il->status &=
2277*4882a593Smuzhiyun test_bit(S_RFKILL, &il->status) << S_RFKILL |
2278*4882a593Smuzhiyun test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
2279*4882a593Smuzhiyun test_bit(S_FW_ERROR, &il->status) << S_FW_ERROR |
2280*4882a593Smuzhiyun test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
2281*4882a593Smuzhiyun
2282*4882a593Smuzhiyun /*
2283*4882a593Smuzhiyun * We disabled and synchronized interrupt, and priv->mutex is taken, so
2284*4882a593Smuzhiyun * here is the only thread which will program device registers, but
2285*4882a593Smuzhiyun * still have lockdep assertions, so we are taking reg_lock.
2286*4882a593Smuzhiyun */
2287*4882a593Smuzhiyun spin_lock_irq(&il->reg_lock);
2288*4882a593Smuzhiyun /* FIXME: il_grab_nic_access if rfkill is off ? */
2289*4882a593Smuzhiyun
2290*4882a593Smuzhiyun il3945_hw_txq_ctx_stop(il);
2291*4882a593Smuzhiyun il3945_hw_rxq_stop(il);
2292*4882a593Smuzhiyun /* Power-down device's busmaster DMA clocks */
2293*4882a593Smuzhiyun _il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2294*4882a593Smuzhiyun udelay(5);
2295*4882a593Smuzhiyun /* Stop the device, and put it in low power state */
2296*4882a593Smuzhiyun _il_apm_stop(il);
2297*4882a593Smuzhiyun
2298*4882a593Smuzhiyun spin_unlock_irq(&il->reg_lock);
2299*4882a593Smuzhiyun
2300*4882a593Smuzhiyun il3945_hw_txq_ctx_free(il);
2301*4882a593Smuzhiyun exit:
2302*4882a593Smuzhiyun memset(&il->card_alive, 0, sizeof(struct il_alive_resp));
2303*4882a593Smuzhiyun dev_kfree_skb(il->beacon_skb);
2304*4882a593Smuzhiyun il->beacon_skb = NULL;
2305*4882a593Smuzhiyun
2306*4882a593Smuzhiyun /* clear out any free frames */
2307*4882a593Smuzhiyun il3945_clear_free_frames(il);
2308*4882a593Smuzhiyun }
2309*4882a593Smuzhiyun
2310*4882a593Smuzhiyun static void
il3945_down(struct il_priv * il)2311*4882a593Smuzhiyun il3945_down(struct il_priv *il)
2312*4882a593Smuzhiyun {
2313*4882a593Smuzhiyun mutex_lock(&il->mutex);
2314*4882a593Smuzhiyun __il3945_down(il);
2315*4882a593Smuzhiyun mutex_unlock(&il->mutex);
2316*4882a593Smuzhiyun
2317*4882a593Smuzhiyun il3945_cancel_deferred_work(il);
2318*4882a593Smuzhiyun }
2319*4882a593Smuzhiyun
2320*4882a593Smuzhiyun #define MAX_HW_RESTARTS 5
2321*4882a593Smuzhiyun
2322*4882a593Smuzhiyun static int
il3945_alloc_bcast_station(struct il_priv * il)2323*4882a593Smuzhiyun il3945_alloc_bcast_station(struct il_priv *il)
2324*4882a593Smuzhiyun {
2325*4882a593Smuzhiyun unsigned long flags;
2326*4882a593Smuzhiyun u8 sta_id;
2327*4882a593Smuzhiyun
2328*4882a593Smuzhiyun spin_lock_irqsave(&il->sta_lock, flags);
2329*4882a593Smuzhiyun sta_id = il_prep_station(il, il_bcast_addr, false, NULL);
2330*4882a593Smuzhiyun if (sta_id == IL_INVALID_STATION) {
2331*4882a593Smuzhiyun IL_ERR("Unable to prepare broadcast station\n");
2332*4882a593Smuzhiyun spin_unlock_irqrestore(&il->sta_lock, flags);
2333*4882a593Smuzhiyun
2334*4882a593Smuzhiyun return -EINVAL;
2335*4882a593Smuzhiyun }
2336*4882a593Smuzhiyun
2337*4882a593Smuzhiyun il->stations[sta_id].used |= IL_STA_DRIVER_ACTIVE;
2338*4882a593Smuzhiyun il->stations[sta_id].used |= IL_STA_BCAST;
2339*4882a593Smuzhiyun spin_unlock_irqrestore(&il->sta_lock, flags);
2340*4882a593Smuzhiyun
2341*4882a593Smuzhiyun return 0;
2342*4882a593Smuzhiyun }
2343*4882a593Smuzhiyun
2344*4882a593Smuzhiyun static int
__il3945_up(struct il_priv * il)2345*4882a593Smuzhiyun __il3945_up(struct il_priv *il)
2346*4882a593Smuzhiyun {
2347*4882a593Smuzhiyun int rc, i;
2348*4882a593Smuzhiyun
2349*4882a593Smuzhiyun rc = il3945_alloc_bcast_station(il);
2350*4882a593Smuzhiyun if (rc)
2351*4882a593Smuzhiyun return rc;
2352*4882a593Smuzhiyun
2353*4882a593Smuzhiyun if (test_bit(S_EXIT_PENDING, &il->status)) {
2354*4882a593Smuzhiyun IL_WARN("Exit pending; will not bring the NIC up\n");
2355*4882a593Smuzhiyun return -EIO;
2356*4882a593Smuzhiyun }
2357*4882a593Smuzhiyun
2358*4882a593Smuzhiyun if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) {
2359*4882a593Smuzhiyun IL_ERR("ucode not available for device bring up\n");
2360*4882a593Smuzhiyun return -EIO;
2361*4882a593Smuzhiyun }
2362*4882a593Smuzhiyun
2363*4882a593Smuzhiyun /* If platform's RF_KILL switch is NOT set to KILL */
2364*4882a593Smuzhiyun if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2365*4882a593Smuzhiyun clear_bit(S_RFKILL, &il->status);
2366*4882a593Smuzhiyun else {
2367*4882a593Smuzhiyun set_bit(S_RFKILL, &il->status);
2368*4882a593Smuzhiyun return -ERFKILL;
2369*4882a593Smuzhiyun }
2370*4882a593Smuzhiyun
2371*4882a593Smuzhiyun _il_wr(il, CSR_INT, 0xFFFFFFFF);
2372*4882a593Smuzhiyun
2373*4882a593Smuzhiyun rc = il3945_hw_nic_init(il);
2374*4882a593Smuzhiyun if (rc) {
2375*4882a593Smuzhiyun IL_ERR("Unable to int nic\n");
2376*4882a593Smuzhiyun return rc;
2377*4882a593Smuzhiyun }
2378*4882a593Smuzhiyun
2379*4882a593Smuzhiyun /* make sure rfkill handshake bits are cleared */
2380*4882a593Smuzhiyun _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2381*4882a593Smuzhiyun _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2382*4882a593Smuzhiyun
2383*4882a593Smuzhiyun /* clear (again), then enable host interrupts */
2384*4882a593Smuzhiyun _il_wr(il, CSR_INT, 0xFFFFFFFF);
2385*4882a593Smuzhiyun il_enable_interrupts(il);
2386*4882a593Smuzhiyun
2387*4882a593Smuzhiyun /* really make sure rfkill handshake bits are cleared */
2388*4882a593Smuzhiyun _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2389*4882a593Smuzhiyun _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2390*4882a593Smuzhiyun
2391*4882a593Smuzhiyun /* Copy original ucode data image from disk into backup cache.
2392*4882a593Smuzhiyun * This will be used to initialize the on-board processor's
2393*4882a593Smuzhiyun * data SRAM for a clean start when the runtime program first loads. */
2394*4882a593Smuzhiyun memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr,
2395*4882a593Smuzhiyun il->ucode_data.len);
2396*4882a593Smuzhiyun
2397*4882a593Smuzhiyun /* We return success when we resume from suspend and rf_kill is on. */
2398*4882a593Smuzhiyun if (test_bit(S_RFKILL, &il->status))
2399*4882a593Smuzhiyun return 0;
2400*4882a593Smuzhiyun
2401*4882a593Smuzhiyun for (i = 0; i < MAX_HW_RESTARTS; i++) {
2402*4882a593Smuzhiyun
2403*4882a593Smuzhiyun /* load bootstrap state machine,
2404*4882a593Smuzhiyun * load bootstrap program into processor's memory,
2405*4882a593Smuzhiyun * prepare to load the "initialize" uCode */
2406*4882a593Smuzhiyun rc = il->ops->load_ucode(il);
2407*4882a593Smuzhiyun
2408*4882a593Smuzhiyun if (rc) {
2409*4882a593Smuzhiyun IL_ERR("Unable to set up bootstrap uCode: %d\n", rc);
2410*4882a593Smuzhiyun continue;
2411*4882a593Smuzhiyun }
2412*4882a593Smuzhiyun
2413*4882a593Smuzhiyun /* start card; "initialize" will load runtime ucode */
2414*4882a593Smuzhiyun il3945_nic_start(il);
2415*4882a593Smuzhiyun
2416*4882a593Smuzhiyun D_INFO(DRV_NAME " is coming up\n");
2417*4882a593Smuzhiyun
2418*4882a593Smuzhiyun return 0;
2419*4882a593Smuzhiyun }
2420*4882a593Smuzhiyun
2421*4882a593Smuzhiyun set_bit(S_EXIT_PENDING, &il->status);
2422*4882a593Smuzhiyun __il3945_down(il);
2423*4882a593Smuzhiyun clear_bit(S_EXIT_PENDING, &il->status);
2424*4882a593Smuzhiyun
2425*4882a593Smuzhiyun /* tried to restart and config the device for as long as our
2426*4882a593Smuzhiyun * patience could withstand */
2427*4882a593Smuzhiyun IL_ERR("Unable to initialize device after %d attempts.\n", i);
2428*4882a593Smuzhiyun return -EIO;
2429*4882a593Smuzhiyun }
2430*4882a593Smuzhiyun
2431*4882a593Smuzhiyun /*****************************************************************************
2432*4882a593Smuzhiyun *
2433*4882a593Smuzhiyun * Workqueue callbacks
2434*4882a593Smuzhiyun *
2435*4882a593Smuzhiyun *****************************************************************************/
2436*4882a593Smuzhiyun
2437*4882a593Smuzhiyun static void
il3945_bg_init_alive_start(struct work_struct * data)2438*4882a593Smuzhiyun il3945_bg_init_alive_start(struct work_struct *data)
2439*4882a593Smuzhiyun {
2440*4882a593Smuzhiyun struct il_priv *il =
2441*4882a593Smuzhiyun container_of(data, struct il_priv, init_alive_start.work);
2442*4882a593Smuzhiyun
2443*4882a593Smuzhiyun mutex_lock(&il->mutex);
2444*4882a593Smuzhiyun if (test_bit(S_EXIT_PENDING, &il->status))
2445*4882a593Smuzhiyun goto out;
2446*4882a593Smuzhiyun
2447*4882a593Smuzhiyun il3945_init_alive_start(il);
2448*4882a593Smuzhiyun out:
2449*4882a593Smuzhiyun mutex_unlock(&il->mutex);
2450*4882a593Smuzhiyun }
2451*4882a593Smuzhiyun
2452*4882a593Smuzhiyun static void
il3945_bg_alive_start(struct work_struct * data)2453*4882a593Smuzhiyun il3945_bg_alive_start(struct work_struct *data)
2454*4882a593Smuzhiyun {
2455*4882a593Smuzhiyun struct il_priv *il =
2456*4882a593Smuzhiyun container_of(data, struct il_priv, alive_start.work);
2457*4882a593Smuzhiyun
2458*4882a593Smuzhiyun mutex_lock(&il->mutex);
2459*4882a593Smuzhiyun if (test_bit(S_EXIT_PENDING, &il->status) || il->txq == NULL)
2460*4882a593Smuzhiyun goto out;
2461*4882a593Smuzhiyun
2462*4882a593Smuzhiyun il3945_alive_start(il);
2463*4882a593Smuzhiyun out:
2464*4882a593Smuzhiyun mutex_unlock(&il->mutex);
2465*4882a593Smuzhiyun }
2466*4882a593Smuzhiyun
2467*4882a593Smuzhiyun /*
2468*4882a593Smuzhiyun * 3945 cannot interrupt driver when hardware rf kill switch toggles;
2469*4882a593Smuzhiyun * driver must poll CSR_GP_CNTRL_REG register for change. This register
2470*4882a593Smuzhiyun * *is* readable even when device has been SW_RESET into low power mode
2471*4882a593Smuzhiyun * (e.g. during RF KILL).
2472*4882a593Smuzhiyun */
2473*4882a593Smuzhiyun static void
il3945_rfkill_poll(struct work_struct * data)2474*4882a593Smuzhiyun il3945_rfkill_poll(struct work_struct *data)
2475*4882a593Smuzhiyun {
2476*4882a593Smuzhiyun struct il_priv *il =
2477*4882a593Smuzhiyun container_of(data, struct il_priv, _3945.rfkill_poll.work);
2478*4882a593Smuzhiyun bool old_rfkill = test_bit(S_RFKILL, &il->status);
2479*4882a593Smuzhiyun bool new_rfkill =
2480*4882a593Smuzhiyun !(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
2481*4882a593Smuzhiyun
2482*4882a593Smuzhiyun if (new_rfkill != old_rfkill) {
2483*4882a593Smuzhiyun if (new_rfkill)
2484*4882a593Smuzhiyun set_bit(S_RFKILL, &il->status);
2485*4882a593Smuzhiyun else
2486*4882a593Smuzhiyun clear_bit(S_RFKILL, &il->status);
2487*4882a593Smuzhiyun
2488*4882a593Smuzhiyun wiphy_rfkill_set_hw_state(il->hw->wiphy, new_rfkill);
2489*4882a593Smuzhiyun
2490*4882a593Smuzhiyun D_RF_KILL("RF_KILL bit toggled to %s.\n",
2491*4882a593Smuzhiyun new_rfkill ? "disable radio" : "enable radio");
2492*4882a593Smuzhiyun }
2493*4882a593Smuzhiyun
2494*4882a593Smuzhiyun /* Keep this running, even if radio now enabled. This will be
2495*4882a593Smuzhiyun * cancelled in mac_start() if system decides to start again */
2496*4882a593Smuzhiyun queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll,
2497*4882a593Smuzhiyun round_jiffies_relative(2 * HZ));
2498*4882a593Smuzhiyun
2499*4882a593Smuzhiyun }
2500*4882a593Smuzhiyun
2501*4882a593Smuzhiyun int
il3945_request_scan(struct il_priv * il,struct ieee80211_vif * vif)2502*4882a593Smuzhiyun il3945_request_scan(struct il_priv *il, struct ieee80211_vif *vif)
2503*4882a593Smuzhiyun {
2504*4882a593Smuzhiyun struct il_host_cmd cmd = {
2505*4882a593Smuzhiyun .id = C_SCAN,
2506*4882a593Smuzhiyun .len = sizeof(struct il3945_scan_cmd),
2507*4882a593Smuzhiyun .flags = CMD_SIZE_HUGE,
2508*4882a593Smuzhiyun };
2509*4882a593Smuzhiyun struct il3945_scan_cmd *scan;
2510*4882a593Smuzhiyun u8 n_probes = 0;
2511*4882a593Smuzhiyun enum nl80211_band band;
2512*4882a593Smuzhiyun bool is_active = false;
2513*4882a593Smuzhiyun int ret;
2514*4882a593Smuzhiyun u16 len;
2515*4882a593Smuzhiyun
2516*4882a593Smuzhiyun lockdep_assert_held(&il->mutex);
2517*4882a593Smuzhiyun
2518*4882a593Smuzhiyun if (!il->scan_cmd) {
2519*4882a593Smuzhiyun il->scan_cmd =
2520*4882a593Smuzhiyun kmalloc(sizeof(struct il3945_scan_cmd) + IL_MAX_SCAN_SIZE,
2521*4882a593Smuzhiyun GFP_KERNEL);
2522*4882a593Smuzhiyun if (!il->scan_cmd) {
2523*4882a593Smuzhiyun D_SCAN("Fail to allocate scan memory\n");
2524*4882a593Smuzhiyun return -ENOMEM;
2525*4882a593Smuzhiyun }
2526*4882a593Smuzhiyun }
2527*4882a593Smuzhiyun scan = il->scan_cmd;
2528*4882a593Smuzhiyun memset(scan, 0, sizeof(struct il3945_scan_cmd) + IL_MAX_SCAN_SIZE);
2529*4882a593Smuzhiyun
2530*4882a593Smuzhiyun scan->quiet_plcp_th = IL_PLCP_QUIET_THRESH;
2531*4882a593Smuzhiyun scan->quiet_time = IL_ACTIVE_QUIET_TIME;
2532*4882a593Smuzhiyun
2533*4882a593Smuzhiyun if (il_is_associated(il)) {
2534*4882a593Smuzhiyun u16 interval;
2535*4882a593Smuzhiyun u32 extra;
2536*4882a593Smuzhiyun u32 suspend_time = 100;
2537*4882a593Smuzhiyun u32 scan_suspend_time = 100;
2538*4882a593Smuzhiyun
2539*4882a593Smuzhiyun D_INFO("Scanning while associated...\n");
2540*4882a593Smuzhiyun
2541*4882a593Smuzhiyun interval = vif->bss_conf.beacon_int;
2542*4882a593Smuzhiyun
2543*4882a593Smuzhiyun scan->suspend_time = 0;
2544*4882a593Smuzhiyun scan->max_out_time = cpu_to_le32(200 * 1024);
2545*4882a593Smuzhiyun if (!interval)
2546*4882a593Smuzhiyun interval = suspend_time;
2547*4882a593Smuzhiyun /*
2548*4882a593Smuzhiyun * suspend time format:
2549*4882a593Smuzhiyun * 0-19: beacon interval in usec (time before exec.)
2550*4882a593Smuzhiyun * 20-23: 0
2551*4882a593Smuzhiyun * 24-31: number of beacons (suspend between channels)
2552*4882a593Smuzhiyun */
2553*4882a593Smuzhiyun
2554*4882a593Smuzhiyun extra = (suspend_time / interval) << 24;
2555*4882a593Smuzhiyun scan_suspend_time =
2556*4882a593Smuzhiyun 0xFF0FFFFF & (extra | ((suspend_time % interval) * 1024));
2557*4882a593Smuzhiyun
2558*4882a593Smuzhiyun scan->suspend_time = cpu_to_le32(scan_suspend_time);
2559*4882a593Smuzhiyun D_SCAN("suspend_time 0x%X beacon interval %d\n",
2560*4882a593Smuzhiyun scan_suspend_time, interval);
2561*4882a593Smuzhiyun }
2562*4882a593Smuzhiyun
2563*4882a593Smuzhiyun if (il->scan_request->n_ssids) {
2564*4882a593Smuzhiyun int i, p = 0;
2565*4882a593Smuzhiyun D_SCAN("Kicking off active scan\n");
2566*4882a593Smuzhiyun for (i = 0; i < il->scan_request->n_ssids; i++) {
2567*4882a593Smuzhiyun /* always does wildcard anyway */
2568*4882a593Smuzhiyun if (!il->scan_request->ssids[i].ssid_len)
2569*4882a593Smuzhiyun continue;
2570*4882a593Smuzhiyun scan->direct_scan[p].id = WLAN_EID_SSID;
2571*4882a593Smuzhiyun scan->direct_scan[p].len =
2572*4882a593Smuzhiyun il->scan_request->ssids[i].ssid_len;
2573*4882a593Smuzhiyun memcpy(scan->direct_scan[p].ssid,
2574*4882a593Smuzhiyun il->scan_request->ssids[i].ssid,
2575*4882a593Smuzhiyun il->scan_request->ssids[i].ssid_len);
2576*4882a593Smuzhiyun n_probes++;
2577*4882a593Smuzhiyun p++;
2578*4882a593Smuzhiyun }
2579*4882a593Smuzhiyun is_active = true;
2580*4882a593Smuzhiyun } else
2581*4882a593Smuzhiyun D_SCAN("Kicking off passive scan.\n");
2582*4882a593Smuzhiyun
2583*4882a593Smuzhiyun /* We don't build a direct scan probe request; the uCode will do
2584*4882a593Smuzhiyun * that based on the direct_mask added to each channel entry */
2585*4882a593Smuzhiyun scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
2586*4882a593Smuzhiyun scan->tx_cmd.sta_id = il->hw_params.bcast_id;
2587*4882a593Smuzhiyun scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2588*4882a593Smuzhiyun
2589*4882a593Smuzhiyun /* flags + rate selection */
2590*4882a593Smuzhiyun
2591*4882a593Smuzhiyun switch (il->scan_band) {
2592*4882a593Smuzhiyun case NL80211_BAND_2GHZ:
2593*4882a593Smuzhiyun scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
2594*4882a593Smuzhiyun scan->tx_cmd.rate = RATE_1M_PLCP;
2595*4882a593Smuzhiyun band = NL80211_BAND_2GHZ;
2596*4882a593Smuzhiyun break;
2597*4882a593Smuzhiyun case NL80211_BAND_5GHZ:
2598*4882a593Smuzhiyun scan->tx_cmd.rate = RATE_6M_PLCP;
2599*4882a593Smuzhiyun band = NL80211_BAND_5GHZ;
2600*4882a593Smuzhiyun break;
2601*4882a593Smuzhiyun default:
2602*4882a593Smuzhiyun IL_WARN("Invalid scan band\n");
2603*4882a593Smuzhiyun return -EIO;
2604*4882a593Smuzhiyun }
2605*4882a593Smuzhiyun
2606*4882a593Smuzhiyun /*
2607*4882a593Smuzhiyun * If active scaning is requested but a certain channel is marked
2608*4882a593Smuzhiyun * passive, we can do active scanning if we detect transmissions. For
2609*4882a593Smuzhiyun * passive only scanning disable switching to active on any channel.
2610*4882a593Smuzhiyun */
2611*4882a593Smuzhiyun scan->good_CRC_th =
2612*4882a593Smuzhiyun is_active ? IL_GOOD_CRC_TH_DEFAULT : IL_GOOD_CRC_TH_NEVER;
2613*4882a593Smuzhiyun
2614*4882a593Smuzhiyun len =
2615*4882a593Smuzhiyun il_fill_probe_req(il, (struct ieee80211_mgmt *)scan->data,
2616*4882a593Smuzhiyun vif->addr, il->scan_request->ie,
2617*4882a593Smuzhiyun il->scan_request->ie_len,
2618*4882a593Smuzhiyun IL_MAX_SCAN_SIZE - sizeof(*scan));
2619*4882a593Smuzhiyun scan->tx_cmd.len = cpu_to_le16(len);
2620*4882a593Smuzhiyun
2621*4882a593Smuzhiyun /* select Rx antennas */
2622*4882a593Smuzhiyun scan->flags |= il3945_get_antenna_flags(il);
2623*4882a593Smuzhiyun
2624*4882a593Smuzhiyun scan->channel_count =
2625*4882a593Smuzhiyun il3945_get_channels_for_scan(il, band, is_active, n_probes,
2626*4882a593Smuzhiyun (void *)&scan->data[len], vif);
2627*4882a593Smuzhiyun if (scan->channel_count == 0) {
2628*4882a593Smuzhiyun D_SCAN("channel count %d\n", scan->channel_count);
2629*4882a593Smuzhiyun return -EIO;
2630*4882a593Smuzhiyun }
2631*4882a593Smuzhiyun
2632*4882a593Smuzhiyun cmd.len +=
2633*4882a593Smuzhiyun le16_to_cpu(scan->tx_cmd.len) +
2634*4882a593Smuzhiyun scan->channel_count * sizeof(struct il3945_scan_channel);
2635*4882a593Smuzhiyun cmd.data = scan;
2636*4882a593Smuzhiyun scan->len = cpu_to_le16(cmd.len);
2637*4882a593Smuzhiyun
2638*4882a593Smuzhiyun set_bit(S_SCAN_HW, &il->status);
2639*4882a593Smuzhiyun ret = il_send_cmd_sync(il, &cmd);
2640*4882a593Smuzhiyun if (ret)
2641*4882a593Smuzhiyun clear_bit(S_SCAN_HW, &il->status);
2642*4882a593Smuzhiyun return ret;
2643*4882a593Smuzhiyun }
2644*4882a593Smuzhiyun
2645*4882a593Smuzhiyun void
il3945_post_scan(struct il_priv * il)2646*4882a593Smuzhiyun il3945_post_scan(struct il_priv *il)
2647*4882a593Smuzhiyun {
2648*4882a593Smuzhiyun /*
2649*4882a593Smuzhiyun * Since setting the RXON may have been deferred while
2650*4882a593Smuzhiyun * performing the scan, fire one off if needed
2651*4882a593Smuzhiyun */
2652*4882a593Smuzhiyun if (memcmp(&il->staging, &il->active, sizeof(il->staging)))
2653*4882a593Smuzhiyun il3945_commit_rxon(il);
2654*4882a593Smuzhiyun }
2655*4882a593Smuzhiyun
2656*4882a593Smuzhiyun static void
il3945_bg_restart(struct work_struct * data)2657*4882a593Smuzhiyun il3945_bg_restart(struct work_struct *data)
2658*4882a593Smuzhiyun {
2659*4882a593Smuzhiyun struct il_priv *il = container_of(data, struct il_priv, restart);
2660*4882a593Smuzhiyun
2661*4882a593Smuzhiyun if (test_bit(S_EXIT_PENDING, &il->status))
2662*4882a593Smuzhiyun return;
2663*4882a593Smuzhiyun
2664*4882a593Smuzhiyun if (test_and_clear_bit(S_FW_ERROR, &il->status)) {
2665*4882a593Smuzhiyun mutex_lock(&il->mutex);
2666*4882a593Smuzhiyun il->is_open = 0;
2667*4882a593Smuzhiyun mutex_unlock(&il->mutex);
2668*4882a593Smuzhiyun il3945_down(il);
2669*4882a593Smuzhiyun ieee80211_restart_hw(il->hw);
2670*4882a593Smuzhiyun } else {
2671*4882a593Smuzhiyun il3945_down(il);
2672*4882a593Smuzhiyun
2673*4882a593Smuzhiyun mutex_lock(&il->mutex);
2674*4882a593Smuzhiyun if (test_bit(S_EXIT_PENDING, &il->status)) {
2675*4882a593Smuzhiyun mutex_unlock(&il->mutex);
2676*4882a593Smuzhiyun return;
2677*4882a593Smuzhiyun }
2678*4882a593Smuzhiyun
2679*4882a593Smuzhiyun __il3945_up(il);
2680*4882a593Smuzhiyun mutex_unlock(&il->mutex);
2681*4882a593Smuzhiyun }
2682*4882a593Smuzhiyun }
2683*4882a593Smuzhiyun
2684*4882a593Smuzhiyun static void
il3945_bg_rx_replenish(struct work_struct * data)2685*4882a593Smuzhiyun il3945_bg_rx_replenish(struct work_struct *data)
2686*4882a593Smuzhiyun {
2687*4882a593Smuzhiyun struct il_priv *il = container_of(data, struct il_priv, rx_replenish);
2688*4882a593Smuzhiyun
2689*4882a593Smuzhiyun mutex_lock(&il->mutex);
2690*4882a593Smuzhiyun if (test_bit(S_EXIT_PENDING, &il->status))
2691*4882a593Smuzhiyun goto out;
2692*4882a593Smuzhiyun
2693*4882a593Smuzhiyun il3945_rx_replenish(il);
2694*4882a593Smuzhiyun out:
2695*4882a593Smuzhiyun mutex_unlock(&il->mutex);
2696*4882a593Smuzhiyun }
2697*4882a593Smuzhiyun
2698*4882a593Smuzhiyun void
il3945_post_associate(struct il_priv * il)2699*4882a593Smuzhiyun il3945_post_associate(struct il_priv *il)
2700*4882a593Smuzhiyun {
2701*4882a593Smuzhiyun int rc = 0;
2702*4882a593Smuzhiyun
2703*4882a593Smuzhiyun if (!il->vif || !il->is_open)
2704*4882a593Smuzhiyun return;
2705*4882a593Smuzhiyun
2706*4882a593Smuzhiyun D_ASSOC("Associated as %d to: %pM\n", il->vif->bss_conf.aid,
2707*4882a593Smuzhiyun il->active.bssid_addr);
2708*4882a593Smuzhiyun
2709*4882a593Smuzhiyun if (test_bit(S_EXIT_PENDING, &il->status))
2710*4882a593Smuzhiyun return;
2711*4882a593Smuzhiyun
2712*4882a593Smuzhiyun il_scan_cancel_timeout(il, 200);
2713*4882a593Smuzhiyun
2714*4882a593Smuzhiyun il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2715*4882a593Smuzhiyun il3945_commit_rxon(il);
2716*4882a593Smuzhiyun
2717*4882a593Smuzhiyun rc = il_send_rxon_timing(il);
2718*4882a593Smuzhiyun if (rc)
2719*4882a593Smuzhiyun IL_WARN("C_RXON_TIMING failed - " "Attempting to continue.\n");
2720*4882a593Smuzhiyun
2721*4882a593Smuzhiyun il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2722*4882a593Smuzhiyun
2723*4882a593Smuzhiyun il->staging.assoc_id = cpu_to_le16(il->vif->bss_conf.aid);
2724*4882a593Smuzhiyun
2725*4882a593Smuzhiyun D_ASSOC("assoc id %d beacon interval %d\n", il->vif->bss_conf.aid,
2726*4882a593Smuzhiyun il->vif->bss_conf.beacon_int);
2727*4882a593Smuzhiyun
2728*4882a593Smuzhiyun if (il->vif->bss_conf.use_short_preamble)
2729*4882a593Smuzhiyun il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2730*4882a593Smuzhiyun else
2731*4882a593Smuzhiyun il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2732*4882a593Smuzhiyun
2733*4882a593Smuzhiyun if (il->staging.flags & RXON_FLG_BAND_24G_MSK) {
2734*4882a593Smuzhiyun if (il->vif->bss_conf.use_short_slot)
2735*4882a593Smuzhiyun il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
2736*4882a593Smuzhiyun else
2737*4882a593Smuzhiyun il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2738*4882a593Smuzhiyun }
2739*4882a593Smuzhiyun
2740*4882a593Smuzhiyun il3945_commit_rxon(il);
2741*4882a593Smuzhiyun
2742*4882a593Smuzhiyun switch (il->vif->type) {
2743*4882a593Smuzhiyun case NL80211_IFTYPE_STATION:
2744*4882a593Smuzhiyun il3945_rate_scale_init(il->hw, IL_AP_ID);
2745*4882a593Smuzhiyun break;
2746*4882a593Smuzhiyun case NL80211_IFTYPE_ADHOC:
2747*4882a593Smuzhiyun il3945_send_beacon_cmd(il);
2748*4882a593Smuzhiyun break;
2749*4882a593Smuzhiyun default:
2750*4882a593Smuzhiyun IL_ERR("%s Should not be called in %d mode\n", __func__,
2751*4882a593Smuzhiyun il->vif->type);
2752*4882a593Smuzhiyun break;
2753*4882a593Smuzhiyun }
2754*4882a593Smuzhiyun }
2755*4882a593Smuzhiyun
2756*4882a593Smuzhiyun /*****************************************************************************
2757*4882a593Smuzhiyun *
2758*4882a593Smuzhiyun * mac80211 entry point functions
2759*4882a593Smuzhiyun *
2760*4882a593Smuzhiyun *****************************************************************************/
2761*4882a593Smuzhiyun
2762*4882a593Smuzhiyun #define UCODE_READY_TIMEOUT (2 * HZ)
2763*4882a593Smuzhiyun
2764*4882a593Smuzhiyun static int
il3945_mac_start(struct ieee80211_hw * hw)2765*4882a593Smuzhiyun il3945_mac_start(struct ieee80211_hw *hw)
2766*4882a593Smuzhiyun {
2767*4882a593Smuzhiyun struct il_priv *il = hw->priv;
2768*4882a593Smuzhiyun int ret;
2769*4882a593Smuzhiyun
2770*4882a593Smuzhiyun /* we should be verifying the device is ready to be opened */
2771*4882a593Smuzhiyun mutex_lock(&il->mutex);
2772*4882a593Smuzhiyun D_MAC80211("enter\n");
2773*4882a593Smuzhiyun
2774*4882a593Smuzhiyun /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
2775*4882a593Smuzhiyun * ucode filename and max sizes are card-specific. */
2776*4882a593Smuzhiyun
2777*4882a593Smuzhiyun if (!il->ucode_code.len) {
2778*4882a593Smuzhiyun ret = il3945_read_ucode(il);
2779*4882a593Smuzhiyun if (ret) {
2780*4882a593Smuzhiyun IL_ERR("Could not read microcode: %d\n", ret);
2781*4882a593Smuzhiyun mutex_unlock(&il->mutex);
2782*4882a593Smuzhiyun goto out_release_irq;
2783*4882a593Smuzhiyun }
2784*4882a593Smuzhiyun }
2785*4882a593Smuzhiyun
2786*4882a593Smuzhiyun ret = __il3945_up(il);
2787*4882a593Smuzhiyun
2788*4882a593Smuzhiyun mutex_unlock(&il->mutex);
2789*4882a593Smuzhiyun
2790*4882a593Smuzhiyun if (ret)
2791*4882a593Smuzhiyun goto out_release_irq;
2792*4882a593Smuzhiyun
2793*4882a593Smuzhiyun D_INFO("Start UP work.\n");
2794*4882a593Smuzhiyun
2795*4882a593Smuzhiyun /* Wait for START_ALIVE from ucode. Otherwise callbacks from
2796*4882a593Smuzhiyun * mac80211 will not be run successfully. */
2797*4882a593Smuzhiyun ret = wait_event_timeout(il->wait_command_queue,
2798*4882a593Smuzhiyun test_bit(S_READY, &il->status),
2799*4882a593Smuzhiyun UCODE_READY_TIMEOUT);
2800*4882a593Smuzhiyun if (!ret) {
2801*4882a593Smuzhiyun if (!test_bit(S_READY, &il->status)) {
2802*4882a593Smuzhiyun IL_ERR("Wait for START_ALIVE timeout after %dms.\n",
2803*4882a593Smuzhiyun jiffies_to_msecs(UCODE_READY_TIMEOUT));
2804*4882a593Smuzhiyun ret = -ETIMEDOUT;
2805*4882a593Smuzhiyun goto out_release_irq;
2806*4882a593Smuzhiyun }
2807*4882a593Smuzhiyun }
2808*4882a593Smuzhiyun
2809*4882a593Smuzhiyun /* ucode is running and will send rfkill notifications,
2810*4882a593Smuzhiyun * no need to poll the killswitch state anymore */
2811*4882a593Smuzhiyun cancel_delayed_work(&il->_3945.rfkill_poll);
2812*4882a593Smuzhiyun
2813*4882a593Smuzhiyun il->is_open = 1;
2814*4882a593Smuzhiyun D_MAC80211("leave\n");
2815*4882a593Smuzhiyun return 0;
2816*4882a593Smuzhiyun
2817*4882a593Smuzhiyun out_release_irq:
2818*4882a593Smuzhiyun il->is_open = 0;
2819*4882a593Smuzhiyun D_MAC80211("leave - failed\n");
2820*4882a593Smuzhiyun return ret;
2821*4882a593Smuzhiyun }
2822*4882a593Smuzhiyun
2823*4882a593Smuzhiyun static void
il3945_mac_stop(struct ieee80211_hw * hw)2824*4882a593Smuzhiyun il3945_mac_stop(struct ieee80211_hw *hw)
2825*4882a593Smuzhiyun {
2826*4882a593Smuzhiyun struct il_priv *il = hw->priv;
2827*4882a593Smuzhiyun
2828*4882a593Smuzhiyun D_MAC80211("enter\n");
2829*4882a593Smuzhiyun
2830*4882a593Smuzhiyun if (!il->is_open) {
2831*4882a593Smuzhiyun D_MAC80211("leave - skip\n");
2832*4882a593Smuzhiyun return;
2833*4882a593Smuzhiyun }
2834*4882a593Smuzhiyun
2835*4882a593Smuzhiyun il->is_open = 0;
2836*4882a593Smuzhiyun
2837*4882a593Smuzhiyun il3945_down(il);
2838*4882a593Smuzhiyun
2839*4882a593Smuzhiyun flush_workqueue(il->workqueue);
2840*4882a593Smuzhiyun
2841*4882a593Smuzhiyun /* start polling the killswitch state again */
2842*4882a593Smuzhiyun queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll,
2843*4882a593Smuzhiyun round_jiffies_relative(2 * HZ));
2844*4882a593Smuzhiyun
2845*4882a593Smuzhiyun D_MAC80211("leave\n");
2846*4882a593Smuzhiyun }
2847*4882a593Smuzhiyun
2848*4882a593Smuzhiyun static void
il3945_mac_tx(struct ieee80211_hw * hw,struct ieee80211_tx_control * control,struct sk_buff * skb)2849*4882a593Smuzhiyun il3945_mac_tx(struct ieee80211_hw *hw,
2850*4882a593Smuzhiyun struct ieee80211_tx_control *control,
2851*4882a593Smuzhiyun struct sk_buff *skb)
2852*4882a593Smuzhiyun {
2853*4882a593Smuzhiyun struct il_priv *il = hw->priv;
2854*4882a593Smuzhiyun
2855*4882a593Smuzhiyun D_MAC80211("enter\n");
2856*4882a593Smuzhiyun
2857*4882a593Smuzhiyun D_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
2858*4882a593Smuzhiyun ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
2859*4882a593Smuzhiyun
2860*4882a593Smuzhiyun if (il3945_tx_skb(il, control->sta, skb))
2861*4882a593Smuzhiyun dev_kfree_skb_any(skb);
2862*4882a593Smuzhiyun
2863*4882a593Smuzhiyun D_MAC80211("leave\n");
2864*4882a593Smuzhiyun }
2865*4882a593Smuzhiyun
2866*4882a593Smuzhiyun void
il3945_config_ap(struct il_priv * il)2867*4882a593Smuzhiyun il3945_config_ap(struct il_priv *il)
2868*4882a593Smuzhiyun {
2869*4882a593Smuzhiyun struct ieee80211_vif *vif = il->vif;
2870*4882a593Smuzhiyun int rc = 0;
2871*4882a593Smuzhiyun
2872*4882a593Smuzhiyun if (test_bit(S_EXIT_PENDING, &il->status))
2873*4882a593Smuzhiyun return;
2874*4882a593Smuzhiyun
2875*4882a593Smuzhiyun /* The following should be done only at AP bring up */
2876*4882a593Smuzhiyun if (!(il_is_associated(il))) {
2877*4882a593Smuzhiyun
2878*4882a593Smuzhiyun /* RXON - unassoc (to set timing command) */
2879*4882a593Smuzhiyun il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2880*4882a593Smuzhiyun il3945_commit_rxon(il);
2881*4882a593Smuzhiyun
2882*4882a593Smuzhiyun /* RXON Timing */
2883*4882a593Smuzhiyun rc = il_send_rxon_timing(il);
2884*4882a593Smuzhiyun if (rc)
2885*4882a593Smuzhiyun IL_WARN("C_RXON_TIMING failed - "
2886*4882a593Smuzhiyun "Attempting to continue.\n");
2887*4882a593Smuzhiyun
2888*4882a593Smuzhiyun il->staging.assoc_id = 0;
2889*4882a593Smuzhiyun
2890*4882a593Smuzhiyun if (vif->bss_conf.use_short_preamble)
2891*4882a593Smuzhiyun il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2892*4882a593Smuzhiyun else
2893*4882a593Smuzhiyun il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2894*4882a593Smuzhiyun
2895*4882a593Smuzhiyun if (il->staging.flags & RXON_FLG_BAND_24G_MSK) {
2896*4882a593Smuzhiyun if (vif->bss_conf.use_short_slot)
2897*4882a593Smuzhiyun il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
2898*4882a593Smuzhiyun else
2899*4882a593Smuzhiyun il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2900*4882a593Smuzhiyun }
2901*4882a593Smuzhiyun /* restore RXON assoc */
2902*4882a593Smuzhiyun il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2903*4882a593Smuzhiyun il3945_commit_rxon(il);
2904*4882a593Smuzhiyun }
2905*4882a593Smuzhiyun il3945_send_beacon_cmd(il);
2906*4882a593Smuzhiyun }
2907*4882a593Smuzhiyun
2908*4882a593Smuzhiyun static int
il3945_mac_set_key(struct ieee80211_hw * hw,enum set_key_cmd cmd,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct ieee80211_key_conf * key)2909*4882a593Smuzhiyun il3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2910*4882a593Smuzhiyun struct ieee80211_vif *vif, struct ieee80211_sta *sta,
2911*4882a593Smuzhiyun struct ieee80211_key_conf *key)
2912*4882a593Smuzhiyun {
2913*4882a593Smuzhiyun struct il_priv *il = hw->priv;
2914*4882a593Smuzhiyun int ret = 0;
2915*4882a593Smuzhiyun u8 sta_id = IL_INVALID_STATION;
2916*4882a593Smuzhiyun u8 static_key;
2917*4882a593Smuzhiyun
2918*4882a593Smuzhiyun D_MAC80211("enter\n");
2919*4882a593Smuzhiyun
2920*4882a593Smuzhiyun if (il3945_mod_params.sw_crypto) {
2921*4882a593Smuzhiyun D_MAC80211("leave - hwcrypto disabled\n");
2922*4882a593Smuzhiyun return -EOPNOTSUPP;
2923*4882a593Smuzhiyun }
2924*4882a593Smuzhiyun
2925*4882a593Smuzhiyun /*
2926*4882a593Smuzhiyun * To support IBSS RSN, don't program group keys in IBSS, the
2927*4882a593Smuzhiyun * hardware will then not attempt to decrypt the frames.
2928*4882a593Smuzhiyun */
2929*4882a593Smuzhiyun if (vif->type == NL80211_IFTYPE_ADHOC &&
2930*4882a593Smuzhiyun !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
2931*4882a593Smuzhiyun D_MAC80211("leave - IBSS RSN\n");
2932*4882a593Smuzhiyun return -EOPNOTSUPP;
2933*4882a593Smuzhiyun }
2934*4882a593Smuzhiyun
2935*4882a593Smuzhiyun static_key = !il_is_associated(il);
2936*4882a593Smuzhiyun
2937*4882a593Smuzhiyun if (!static_key) {
2938*4882a593Smuzhiyun sta_id = il_sta_id_or_broadcast(il, sta);
2939*4882a593Smuzhiyun if (sta_id == IL_INVALID_STATION) {
2940*4882a593Smuzhiyun D_MAC80211("leave - station not found\n");
2941*4882a593Smuzhiyun return -EINVAL;
2942*4882a593Smuzhiyun }
2943*4882a593Smuzhiyun }
2944*4882a593Smuzhiyun
2945*4882a593Smuzhiyun mutex_lock(&il->mutex);
2946*4882a593Smuzhiyun il_scan_cancel_timeout(il, 100);
2947*4882a593Smuzhiyun
2948*4882a593Smuzhiyun switch (cmd) {
2949*4882a593Smuzhiyun case SET_KEY:
2950*4882a593Smuzhiyun if (static_key)
2951*4882a593Smuzhiyun ret = il3945_set_static_key(il, key);
2952*4882a593Smuzhiyun else
2953*4882a593Smuzhiyun ret = il3945_set_dynamic_key(il, key, sta_id);
2954*4882a593Smuzhiyun D_MAC80211("enable hwcrypto key\n");
2955*4882a593Smuzhiyun break;
2956*4882a593Smuzhiyun case DISABLE_KEY:
2957*4882a593Smuzhiyun if (static_key)
2958*4882a593Smuzhiyun ret = il3945_remove_static_key(il);
2959*4882a593Smuzhiyun else
2960*4882a593Smuzhiyun ret = il3945_clear_sta_key_info(il, sta_id);
2961*4882a593Smuzhiyun D_MAC80211("disable hwcrypto key\n");
2962*4882a593Smuzhiyun break;
2963*4882a593Smuzhiyun default:
2964*4882a593Smuzhiyun ret = -EINVAL;
2965*4882a593Smuzhiyun }
2966*4882a593Smuzhiyun
2967*4882a593Smuzhiyun D_MAC80211("leave ret %d\n", ret);
2968*4882a593Smuzhiyun mutex_unlock(&il->mutex);
2969*4882a593Smuzhiyun
2970*4882a593Smuzhiyun return ret;
2971*4882a593Smuzhiyun }
2972*4882a593Smuzhiyun
2973*4882a593Smuzhiyun static int
il3945_mac_sta_add(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta)2974*4882a593Smuzhiyun il3945_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2975*4882a593Smuzhiyun struct ieee80211_sta *sta)
2976*4882a593Smuzhiyun {
2977*4882a593Smuzhiyun struct il_priv *il = hw->priv;
2978*4882a593Smuzhiyun struct il3945_sta_priv *sta_priv = (void *)sta->drv_priv;
2979*4882a593Smuzhiyun int ret;
2980*4882a593Smuzhiyun bool is_ap = vif->type == NL80211_IFTYPE_STATION;
2981*4882a593Smuzhiyun u8 sta_id;
2982*4882a593Smuzhiyun
2983*4882a593Smuzhiyun mutex_lock(&il->mutex);
2984*4882a593Smuzhiyun D_INFO("station %pM\n", sta->addr);
2985*4882a593Smuzhiyun sta_priv->common.sta_id = IL_INVALID_STATION;
2986*4882a593Smuzhiyun
2987*4882a593Smuzhiyun ret = il_add_station_common(il, sta->addr, is_ap, sta, &sta_id);
2988*4882a593Smuzhiyun if (ret) {
2989*4882a593Smuzhiyun IL_ERR("Unable to add station %pM (%d)\n", sta->addr, ret);
2990*4882a593Smuzhiyun /* Should we return success if return code is EEXIST ? */
2991*4882a593Smuzhiyun mutex_unlock(&il->mutex);
2992*4882a593Smuzhiyun return ret;
2993*4882a593Smuzhiyun }
2994*4882a593Smuzhiyun
2995*4882a593Smuzhiyun sta_priv->common.sta_id = sta_id;
2996*4882a593Smuzhiyun
2997*4882a593Smuzhiyun /* Initialize rate scaling */
2998*4882a593Smuzhiyun D_INFO("Initializing rate scaling for station %pM\n", sta->addr);
2999*4882a593Smuzhiyun il3945_rs_rate_init(il, sta, sta_id);
3000*4882a593Smuzhiyun mutex_unlock(&il->mutex);
3001*4882a593Smuzhiyun
3002*4882a593Smuzhiyun return 0;
3003*4882a593Smuzhiyun }
3004*4882a593Smuzhiyun
3005*4882a593Smuzhiyun static void
il3945_configure_filter(struct ieee80211_hw * hw,unsigned int changed_flags,unsigned int * total_flags,u64 multicast)3006*4882a593Smuzhiyun il3945_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
3007*4882a593Smuzhiyun unsigned int *total_flags, u64 multicast)
3008*4882a593Smuzhiyun {
3009*4882a593Smuzhiyun struct il_priv *il = hw->priv;
3010*4882a593Smuzhiyun __le32 filter_or = 0, filter_nand = 0;
3011*4882a593Smuzhiyun
3012*4882a593Smuzhiyun #define CHK(test, flag) do { \
3013*4882a593Smuzhiyun if (*total_flags & (test)) \
3014*4882a593Smuzhiyun filter_or |= (flag); \
3015*4882a593Smuzhiyun else \
3016*4882a593Smuzhiyun filter_nand |= (flag); \
3017*4882a593Smuzhiyun } while (0)
3018*4882a593Smuzhiyun
3019*4882a593Smuzhiyun D_MAC80211("Enter: changed: 0x%x, total: 0x%x\n", changed_flags,
3020*4882a593Smuzhiyun *total_flags);
3021*4882a593Smuzhiyun
3022*4882a593Smuzhiyun CHK(FIF_OTHER_BSS, RXON_FILTER_PROMISC_MSK);
3023*4882a593Smuzhiyun CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
3024*4882a593Smuzhiyun CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3025*4882a593Smuzhiyun
3026*4882a593Smuzhiyun #undef CHK
3027*4882a593Smuzhiyun
3028*4882a593Smuzhiyun mutex_lock(&il->mutex);
3029*4882a593Smuzhiyun
3030*4882a593Smuzhiyun il->staging.filter_flags &= ~filter_nand;
3031*4882a593Smuzhiyun il->staging.filter_flags |= filter_or;
3032*4882a593Smuzhiyun
3033*4882a593Smuzhiyun /*
3034*4882a593Smuzhiyun * Not committing directly because hardware can perform a scan,
3035*4882a593Smuzhiyun * but even if hw is ready, committing here breaks for some reason,
3036*4882a593Smuzhiyun * we'll eventually commit the filter flags change anyway.
3037*4882a593Smuzhiyun */
3038*4882a593Smuzhiyun
3039*4882a593Smuzhiyun mutex_unlock(&il->mutex);
3040*4882a593Smuzhiyun
3041*4882a593Smuzhiyun /*
3042*4882a593Smuzhiyun * Receiving all multicast frames is always enabled by the
3043*4882a593Smuzhiyun * default flags setup in il_connection_init_rx_config()
3044*4882a593Smuzhiyun * since we currently do not support programming multicast
3045*4882a593Smuzhiyun * filters into the device.
3046*4882a593Smuzhiyun */
3047*4882a593Smuzhiyun *total_flags &=
3048*4882a593Smuzhiyun FIF_OTHER_BSS | FIF_ALLMULTI |
3049*4882a593Smuzhiyun FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3050*4882a593Smuzhiyun }
3051*4882a593Smuzhiyun
3052*4882a593Smuzhiyun /*****************************************************************************
3053*4882a593Smuzhiyun *
3054*4882a593Smuzhiyun * sysfs attributes
3055*4882a593Smuzhiyun *
3056*4882a593Smuzhiyun *****************************************************************************/
3057*4882a593Smuzhiyun
3058*4882a593Smuzhiyun #ifdef CONFIG_IWLEGACY_DEBUG
3059*4882a593Smuzhiyun
3060*4882a593Smuzhiyun /*
3061*4882a593Smuzhiyun * The following adds a new attribute to the sysfs representation
3062*4882a593Smuzhiyun * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
3063*4882a593Smuzhiyun * used for controlling the debug level.
3064*4882a593Smuzhiyun *
3065*4882a593Smuzhiyun * See the level definitions in iwl for details.
3066*4882a593Smuzhiyun *
3067*4882a593Smuzhiyun * The debug_level being managed using sysfs below is a per device debug
3068*4882a593Smuzhiyun * level that is used instead of the global debug level if it (the per
3069*4882a593Smuzhiyun * device debug level) is set.
3070*4882a593Smuzhiyun */
3071*4882a593Smuzhiyun static ssize_t
il3945_show_debug_level(struct device * d,struct device_attribute * attr,char * buf)3072*4882a593Smuzhiyun il3945_show_debug_level(struct device *d, struct device_attribute *attr,
3073*4882a593Smuzhiyun char *buf)
3074*4882a593Smuzhiyun {
3075*4882a593Smuzhiyun struct il_priv *il = dev_get_drvdata(d);
3076*4882a593Smuzhiyun return sprintf(buf, "0x%08X\n", il_get_debug_level(il));
3077*4882a593Smuzhiyun }
3078*4882a593Smuzhiyun
3079*4882a593Smuzhiyun static ssize_t
il3945_store_debug_level(struct device * d,struct device_attribute * attr,const char * buf,size_t count)3080*4882a593Smuzhiyun il3945_store_debug_level(struct device *d, struct device_attribute *attr,
3081*4882a593Smuzhiyun const char *buf, size_t count)
3082*4882a593Smuzhiyun {
3083*4882a593Smuzhiyun struct il_priv *il = dev_get_drvdata(d);
3084*4882a593Smuzhiyun unsigned long val;
3085*4882a593Smuzhiyun int ret;
3086*4882a593Smuzhiyun
3087*4882a593Smuzhiyun ret = kstrtoul(buf, 0, &val);
3088*4882a593Smuzhiyun if (ret)
3089*4882a593Smuzhiyun IL_INFO("%s is not in hex or decimal form.\n", buf);
3090*4882a593Smuzhiyun else
3091*4882a593Smuzhiyun il->debug_level = val;
3092*4882a593Smuzhiyun
3093*4882a593Smuzhiyun return strnlen(buf, count);
3094*4882a593Smuzhiyun }
3095*4882a593Smuzhiyun
3096*4882a593Smuzhiyun static DEVICE_ATTR(debug_level, 0644, il3945_show_debug_level,
3097*4882a593Smuzhiyun il3945_store_debug_level);
3098*4882a593Smuzhiyun
3099*4882a593Smuzhiyun #endif /* CONFIG_IWLEGACY_DEBUG */
3100*4882a593Smuzhiyun
3101*4882a593Smuzhiyun static ssize_t
il3945_show_temperature(struct device * d,struct device_attribute * attr,char * buf)3102*4882a593Smuzhiyun il3945_show_temperature(struct device *d, struct device_attribute *attr,
3103*4882a593Smuzhiyun char *buf)
3104*4882a593Smuzhiyun {
3105*4882a593Smuzhiyun struct il_priv *il = dev_get_drvdata(d);
3106*4882a593Smuzhiyun
3107*4882a593Smuzhiyun if (!il_is_alive(il))
3108*4882a593Smuzhiyun return -EAGAIN;
3109*4882a593Smuzhiyun
3110*4882a593Smuzhiyun return sprintf(buf, "%d\n", il3945_hw_get_temperature(il));
3111*4882a593Smuzhiyun }
3112*4882a593Smuzhiyun
3113*4882a593Smuzhiyun static DEVICE_ATTR(temperature, 0444, il3945_show_temperature, NULL);
3114*4882a593Smuzhiyun
3115*4882a593Smuzhiyun static ssize_t
il3945_show_tx_power(struct device * d,struct device_attribute * attr,char * buf)3116*4882a593Smuzhiyun il3945_show_tx_power(struct device *d, struct device_attribute *attr, char *buf)
3117*4882a593Smuzhiyun {
3118*4882a593Smuzhiyun struct il_priv *il = dev_get_drvdata(d);
3119*4882a593Smuzhiyun return sprintf(buf, "%d\n", il->tx_power_user_lmt);
3120*4882a593Smuzhiyun }
3121*4882a593Smuzhiyun
3122*4882a593Smuzhiyun static ssize_t
il3945_store_tx_power(struct device * d,struct device_attribute * attr,const char * buf,size_t count)3123*4882a593Smuzhiyun il3945_store_tx_power(struct device *d, struct device_attribute *attr,
3124*4882a593Smuzhiyun const char *buf, size_t count)
3125*4882a593Smuzhiyun {
3126*4882a593Smuzhiyun struct il_priv *il = dev_get_drvdata(d);
3127*4882a593Smuzhiyun char *p = (char *)buf;
3128*4882a593Smuzhiyun u32 val;
3129*4882a593Smuzhiyun
3130*4882a593Smuzhiyun val = simple_strtoul(p, &p, 10);
3131*4882a593Smuzhiyun if (p == buf)
3132*4882a593Smuzhiyun IL_INFO(": %s is not in decimal form.\n", buf);
3133*4882a593Smuzhiyun else
3134*4882a593Smuzhiyun il3945_hw_reg_set_txpower(il, val);
3135*4882a593Smuzhiyun
3136*4882a593Smuzhiyun return count;
3137*4882a593Smuzhiyun }
3138*4882a593Smuzhiyun
3139*4882a593Smuzhiyun static DEVICE_ATTR(tx_power, 0644, il3945_show_tx_power, il3945_store_tx_power);
3140*4882a593Smuzhiyun
3141*4882a593Smuzhiyun static ssize_t
il3945_show_flags(struct device * d,struct device_attribute * attr,char * buf)3142*4882a593Smuzhiyun il3945_show_flags(struct device *d, struct device_attribute *attr, char *buf)
3143*4882a593Smuzhiyun {
3144*4882a593Smuzhiyun struct il_priv *il = dev_get_drvdata(d);
3145*4882a593Smuzhiyun
3146*4882a593Smuzhiyun return sprintf(buf, "0x%04X\n", il->active.flags);
3147*4882a593Smuzhiyun }
3148*4882a593Smuzhiyun
3149*4882a593Smuzhiyun static ssize_t
il3945_store_flags(struct device * d,struct device_attribute * attr,const char * buf,size_t count)3150*4882a593Smuzhiyun il3945_store_flags(struct device *d, struct device_attribute *attr,
3151*4882a593Smuzhiyun const char *buf, size_t count)
3152*4882a593Smuzhiyun {
3153*4882a593Smuzhiyun struct il_priv *il = dev_get_drvdata(d);
3154*4882a593Smuzhiyun u32 flags = simple_strtoul(buf, NULL, 0);
3155*4882a593Smuzhiyun
3156*4882a593Smuzhiyun mutex_lock(&il->mutex);
3157*4882a593Smuzhiyun if (le32_to_cpu(il->staging.flags) != flags) {
3158*4882a593Smuzhiyun /* Cancel any currently running scans... */
3159*4882a593Smuzhiyun if (il_scan_cancel_timeout(il, 100))
3160*4882a593Smuzhiyun IL_WARN("Could not cancel scan.\n");
3161*4882a593Smuzhiyun else {
3162*4882a593Smuzhiyun D_INFO("Committing rxon.flags = 0x%04X\n", flags);
3163*4882a593Smuzhiyun il->staging.flags = cpu_to_le32(flags);
3164*4882a593Smuzhiyun il3945_commit_rxon(il);
3165*4882a593Smuzhiyun }
3166*4882a593Smuzhiyun }
3167*4882a593Smuzhiyun mutex_unlock(&il->mutex);
3168*4882a593Smuzhiyun
3169*4882a593Smuzhiyun return count;
3170*4882a593Smuzhiyun }
3171*4882a593Smuzhiyun
3172*4882a593Smuzhiyun static DEVICE_ATTR(flags, 0644, il3945_show_flags, il3945_store_flags);
3173*4882a593Smuzhiyun
3174*4882a593Smuzhiyun static ssize_t
il3945_show_filter_flags(struct device * d,struct device_attribute * attr,char * buf)3175*4882a593Smuzhiyun il3945_show_filter_flags(struct device *d, struct device_attribute *attr,
3176*4882a593Smuzhiyun char *buf)
3177*4882a593Smuzhiyun {
3178*4882a593Smuzhiyun struct il_priv *il = dev_get_drvdata(d);
3179*4882a593Smuzhiyun
3180*4882a593Smuzhiyun return sprintf(buf, "0x%04X\n", le32_to_cpu(il->active.filter_flags));
3181*4882a593Smuzhiyun }
3182*4882a593Smuzhiyun
3183*4882a593Smuzhiyun static ssize_t
il3945_store_filter_flags(struct device * d,struct device_attribute * attr,const char * buf,size_t count)3184*4882a593Smuzhiyun il3945_store_filter_flags(struct device *d, struct device_attribute *attr,
3185*4882a593Smuzhiyun const char *buf, size_t count)
3186*4882a593Smuzhiyun {
3187*4882a593Smuzhiyun struct il_priv *il = dev_get_drvdata(d);
3188*4882a593Smuzhiyun u32 filter_flags = simple_strtoul(buf, NULL, 0);
3189*4882a593Smuzhiyun
3190*4882a593Smuzhiyun mutex_lock(&il->mutex);
3191*4882a593Smuzhiyun if (le32_to_cpu(il->staging.filter_flags) != filter_flags) {
3192*4882a593Smuzhiyun /* Cancel any currently running scans... */
3193*4882a593Smuzhiyun if (il_scan_cancel_timeout(il, 100))
3194*4882a593Smuzhiyun IL_WARN("Could not cancel scan.\n");
3195*4882a593Smuzhiyun else {
3196*4882a593Smuzhiyun D_INFO("Committing rxon.filter_flags = " "0x%04X\n",
3197*4882a593Smuzhiyun filter_flags);
3198*4882a593Smuzhiyun il->staging.filter_flags = cpu_to_le32(filter_flags);
3199*4882a593Smuzhiyun il3945_commit_rxon(il);
3200*4882a593Smuzhiyun }
3201*4882a593Smuzhiyun }
3202*4882a593Smuzhiyun mutex_unlock(&il->mutex);
3203*4882a593Smuzhiyun
3204*4882a593Smuzhiyun return count;
3205*4882a593Smuzhiyun }
3206*4882a593Smuzhiyun
3207*4882a593Smuzhiyun static DEVICE_ATTR(filter_flags, 0644, il3945_show_filter_flags,
3208*4882a593Smuzhiyun il3945_store_filter_flags);
3209*4882a593Smuzhiyun
3210*4882a593Smuzhiyun static ssize_t
il3945_show_measurement(struct device * d,struct device_attribute * attr,char * buf)3211*4882a593Smuzhiyun il3945_show_measurement(struct device *d, struct device_attribute *attr,
3212*4882a593Smuzhiyun char *buf)
3213*4882a593Smuzhiyun {
3214*4882a593Smuzhiyun struct il_priv *il = dev_get_drvdata(d);
3215*4882a593Smuzhiyun struct il_spectrum_notification measure_report;
3216*4882a593Smuzhiyun u32 size = sizeof(measure_report), len = 0, ofs = 0;
3217*4882a593Smuzhiyun u8 *data = (u8 *) &measure_report;
3218*4882a593Smuzhiyun unsigned long flags;
3219*4882a593Smuzhiyun
3220*4882a593Smuzhiyun spin_lock_irqsave(&il->lock, flags);
3221*4882a593Smuzhiyun if (!(il->measurement_status & MEASUREMENT_READY)) {
3222*4882a593Smuzhiyun spin_unlock_irqrestore(&il->lock, flags);
3223*4882a593Smuzhiyun return 0;
3224*4882a593Smuzhiyun }
3225*4882a593Smuzhiyun memcpy(&measure_report, &il->measure_report, size);
3226*4882a593Smuzhiyun il->measurement_status = 0;
3227*4882a593Smuzhiyun spin_unlock_irqrestore(&il->lock, flags);
3228*4882a593Smuzhiyun
3229*4882a593Smuzhiyun while (size && PAGE_SIZE - len) {
3230*4882a593Smuzhiyun hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3231*4882a593Smuzhiyun PAGE_SIZE - len, true);
3232*4882a593Smuzhiyun len = strlen(buf);
3233*4882a593Smuzhiyun if (PAGE_SIZE - len)
3234*4882a593Smuzhiyun buf[len++] = '\n';
3235*4882a593Smuzhiyun
3236*4882a593Smuzhiyun ofs += 16;
3237*4882a593Smuzhiyun size -= min(size, 16U);
3238*4882a593Smuzhiyun }
3239*4882a593Smuzhiyun
3240*4882a593Smuzhiyun return len;
3241*4882a593Smuzhiyun }
3242*4882a593Smuzhiyun
3243*4882a593Smuzhiyun static ssize_t
il3945_store_measurement(struct device * d,struct device_attribute * attr,const char * buf,size_t count)3244*4882a593Smuzhiyun il3945_store_measurement(struct device *d, struct device_attribute *attr,
3245*4882a593Smuzhiyun const char *buf, size_t count)
3246*4882a593Smuzhiyun {
3247*4882a593Smuzhiyun struct il_priv *il = dev_get_drvdata(d);
3248*4882a593Smuzhiyun struct ieee80211_measurement_params params = {
3249*4882a593Smuzhiyun .channel = le16_to_cpu(il->active.channel),
3250*4882a593Smuzhiyun .start_time = cpu_to_le64(il->_3945.last_tsf),
3251*4882a593Smuzhiyun .duration = cpu_to_le16(1),
3252*4882a593Smuzhiyun };
3253*4882a593Smuzhiyun u8 type = IL_MEASURE_BASIC;
3254*4882a593Smuzhiyun u8 buffer[32];
3255*4882a593Smuzhiyun u8 channel;
3256*4882a593Smuzhiyun
3257*4882a593Smuzhiyun if (count) {
3258*4882a593Smuzhiyun char *p = buffer;
3259*4882a593Smuzhiyun strlcpy(buffer, buf, sizeof(buffer));
3260*4882a593Smuzhiyun channel = simple_strtoul(p, NULL, 0);
3261*4882a593Smuzhiyun if (channel)
3262*4882a593Smuzhiyun params.channel = channel;
3263*4882a593Smuzhiyun
3264*4882a593Smuzhiyun p = buffer;
3265*4882a593Smuzhiyun while (*p && *p != ' ')
3266*4882a593Smuzhiyun p++;
3267*4882a593Smuzhiyun if (*p)
3268*4882a593Smuzhiyun type = simple_strtoul(p + 1, NULL, 0);
3269*4882a593Smuzhiyun }
3270*4882a593Smuzhiyun
3271*4882a593Smuzhiyun D_INFO("Invoking measurement of type %d on " "channel %d (for '%s')\n",
3272*4882a593Smuzhiyun type, params.channel, buf);
3273*4882a593Smuzhiyun il3945_get_measurement(il, ¶ms, type);
3274*4882a593Smuzhiyun
3275*4882a593Smuzhiyun return count;
3276*4882a593Smuzhiyun }
3277*4882a593Smuzhiyun
3278*4882a593Smuzhiyun static DEVICE_ATTR(measurement, 0600, il3945_show_measurement,
3279*4882a593Smuzhiyun il3945_store_measurement);
3280*4882a593Smuzhiyun
3281*4882a593Smuzhiyun static ssize_t
il3945_store_retry_rate(struct device * d,struct device_attribute * attr,const char * buf,size_t count)3282*4882a593Smuzhiyun il3945_store_retry_rate(struct device *d, struct device_attribute *attr,
3283*4882a593Smuzhiyun const char *buf, size_t count)
3284*4882a593Smuzhiyun {
3285*4882a593Smuzhiyun struct il_priv *il = dev_get_drvdata(d);
3286*4882a593Smuzhiyun
3287*4882a593Smuzhiyun il->retry_rate = simple_strtoul(buf, NULL, 0);
3288*4882a593Smuzhiyun if (il->retry_rate <= 0)
3289*4882a593Smuzhiyun il->retry_rate = 1;
3290*4882a593Smuzhiyun
3291*4882a593Smuzhiyun return count;
3292*4882a593Smuzhiyun }
3293*4882a593Smuzhiyun
3294*4882a593Smuzhiyun static ssize_t
il3945_show_retry_rate(struct device * d,struct device_attribute * attr,char * buf)3295*4882a593Smuzhiyun il3945_show_retry_rate(struct device *d, struct device_attribute *attr,
3296*4882a593Smuzhiyun char *buf)
3297*4882a593Smuzhiyun {
3298*4882a593Smuzhiyun struct il_priv *il = dev_get_drvdata(d);
3299*4882a593Smuzhiyun return sprintf(buf, "%d", il->retry_rate);
3300*4882a593Smuzhiyun }
3301*4882a593Smuzhiyun
3302*4882a593Smuzhiyun static DEVICE_ATTR(retry_rate, 0600, il3945_show_retry_rate,
3303*4882a593Smuzhiyun il3945_store_retry_rate);
3304*4882a593Smuzhiyun
3305*4882a593Smuzhiyun static ssize_t
il3945_show_channels(struct device * d,struct device_attribute * attr,char * buf)3306*4882a593Smuzhiyun il3945_show_channels(struct device *d, struct device_attribute *attr, char *buf)
3307*4882a593Smuzhiyun {
3308*4882a593Smuzhiyun /* all this shit doesn't belong into sysfs anyway */
3309*4882a593Smuzhiyun return 0;
3310*4882a593Smuzhiyun }
3311*4882a593Smuzhiyun
3312*4882a593Smuzhiyun static DEVICE_ATTR(channels, 0400, il3945_show_channels, NULL);
3313*4882a593Smuzhiyun
3314*4882a593Smuzhiyun static ssize_t
il3945_show_antenna(struct device * d,struct device_attribute * attr,char * buf)3315*4882a593Smuzhiyun il3945_show_antenna(struct device *d, struct device_attribute *attr, char *buf)
3316*4882a593Smuzhiyun {
3317*4882a593Smuzhiyun struct il_priv *il = dev_get_drvdata(d);
3318*4882a593Smuzhiyun
3319*4882a593Smuzhiyun if (!il_is_alive(il))
3320*4882a593Smuzhiyun return -EAGAIN;
3321*4882a593Smuzhiyun
3322*4882a593Smuzhiyun return sprintf(buf, "%d\n", il3945_mod_params.antenna);
3323*4882a593Smuzhiyun }
3324*4882a593Smuzhiyun
3325*4882a593Smuzhiyun static ssize_t
il3945_store_antenna(struct device * d,struct device_attribute * attr,const char * buf,size_t count)3326*4882a593Smuzhiyun il3945_store_antenna(struct device *d, struct device_attribute *attr,
3327*4882a593Smuzhiyun const char *buf, size_t count)
3328*4882a593Smuzhiyun {
3329*4882a593Smuzhiyun struct il_priv *il __maybe_unused = dev_get_drvdata(d);
3330*4882a593Smuzhiyun int ant;
3331*4882a593Smuzhiyun
3332*4882a593Smuzhiyun if (count == 0)
3333*4882a593Smuzhiyun return 0;
3334*4882a593Smuzhiyun
3335*4882a593Smuzhiyun if (sscanf(buf, "%1i", &ant) != 1) {
3336*4882a593Smuzhiyun D_INFO("not in hex or decimal form.\n");
3337*4882a593Smuzhiyun return count;
3338*4882a593Smuzhiyun }
3339*4882a593Smuzhiyun
3340*4882a593Smuzhiyun if (ant >= 0 && ant <= 2) {
3341*4882a593Smuzhiyun D_INFO("Setting antenna select to %d.\n", ant);
3342*4882a593Smuzhiyun il3945_mod_params.antenna = (enum il3945_antenna)ant;
3343*4882a593Smuzhiyun } else
3344*4882a593Smuzhiyun D_INFO("Bad antenna select value %d.\n", ant);
3345*4882a593Smuzhiyun
3346*4882a593Smuzhiyun return count;
3347*4882a593Smuzhiyun }
3348*4882a593Smuzhiyun
3349*4882a593Smuzhiyun static DEVICE_ATTR(antenna, 0644, il3945_show_antenna, il3945_store_antenna);
3350*4882a593Smuzhiyun
3351*4882a593Smuzhiyun static ssize_t
il3945_show_status(struct device * d,struct device_attribute * attr,char * buf)3352*4882a593Smuzhiyun il3945_show_status(struct device *d, struct device_attribute *attr, char *buf)
3353*4882a593Smuzhiyun {
3354*4882a593Smuzhiyun struct il_priv *il = dev_get_drvdata(d);
3355*4882a593Smuzhiyun if (!il_is_alive(il))
3356*4882a593Smuzhiyun return -EAGAIN;
3357*4882a593Smuzhiyun return sprintf(buf, "0x%08x\n", (int)il->status);
3358*4882a593Smuzhiyun }
3359*4882a593Smuzhiyun
3360*4882a593Smuzhiyun static DEVICE_ATTR(status, 0444, il3945_show_status, NULL);
3361*4882a593Smuzhiyun
3362*4882a593Smuzhiyun static ssize_t
il3945_dump_error_log(struct device * d,struct device_attribute * attr,const char * buf,size_t count)3363*4882a593Smuzhiyun il3945_dump_error_log(struct device *d, struct device_attribute *attr,
3364*4882a593Smuzhiyun const char *buf, size_t count)
3365*4882a593Smuzhiyun {
3366*4882a593Smuzhiyun struct il_priv *il = dev_get_drvdata(d);
3367*4882a593Smuzhiyun char *p = (char *)buf;
3368*4882a593Smuzhiyun
3369*4882a593Smuzhiyun if (p[0] == '1')
3370*4882a593Smuzhiyun il3945_dump_nic_error_log(il);
3371*4882a593Smuzhiyun
3372*4882a593Smuzhiyun return strnlen(buf, count);
3373*4882a593Smuzhiyun }
3374*4882a593Smuzhiyun
3375*4882a593Smuzhiyun static DEVICE_ATTR(dump_errors, 0200, NULL, il3945_dump_error_log);
3376*4882a593Smuzhiyun
3377*4882a593Smuzhiyun /*****************************************************************************
3378*4882a593Smuzhiyun *
3379*4882a593Smuzhiyun * driver setup and tear down
3380*4882a593Smuzhiyun *
3381*4882a593Smuzhiyun *****************************************************************************/
3382*4882a593Smuzhiyun
3383*4882a593Smuzhiyun static void
il3945_setup_deferred_work(struct il_priv * il)3384*4882a593Smuzhiyun il3945_setup_deferred_work(struct il_priv *il)
3385*4882a593Smuzhiyun {
3386*4882a593Smuzhiyun il->workqueue = create_singlethread_workqueue(DRV_NAME);
3387*4882a593Smuzhiyun
3388*4882a593Smuzhiyun init_waitqueue_head(&il->wait_command_queue);
3389*4882a593Smuzhiyun
3390*4882a593Smuzhiyun INIT_WORK(&il->restart, il3945_bg_restart);
3391*4882a593Smuzhiyun INIT_WORK(&il->rx_replenish, il3945_bg_rx_replenish);
3392*4882a593Smuzhiyun INIT_DELAYED_WORK(&il->init_alive_start, il3945_bg_init_alive_start);
3393*4882a593Smuzhiyun INIT_DELAYED_WORK(&il->alive_start, il3945_bg_alive_start);
3394*4882a593Smuzhiyun INIT_DELAYED_WORK(&il->_3945.rfkill_poll, il3945_rfkill_poll);
3395*4882a593Smuzhiyun
3396*4882a593Smuzhiyun il_setup_scan_deferred_work(il);
3397*4882a593Smuzhiyun
3398*4882a593Smuzhiyun il3945_hw_setup_deferred_work(il);
3399*4882a593Smuzhiyun
3400*4882a593Smuzhiyun timer_setup(&il->watchdog, il_bg_watchdog, 0);
3401*4882a593Smuzhiyun
3402*4882a593Smuzhiyun tasklet_setup(&il->irq_tasklet, il3945_irq_tasklet);
3403*4882a593Smuzhiyun }
3404*4882a593Smuzhiyun
3405*4882a593Smuzhiyun static void
il3945_cancel_deferred_work(struct il_priv * il)3406*4882a593Smuzhiyun il3945_cancel_deferred_work(struct il_priv *il)
3407*4882a593Smuzhiyun {
3408*4882a593Smuzhiyun il3945_hw_cancel_deferred_work(il);
3409*4882a593Smuzhiyun
3410*4882a593Smuzhiyun cancel_delayed_work_sync(&il->init_alive_start);
3411*4882a593Smuzhiyun cancel_delayed_work(&il->alive_start);
3412*4882a593Smuzhiyun
3413*4882a593Smuzhiyun il_cancel_scan_deferred_work(il);
3414*4882a593Smuzhiyun }
3415*4882a593Smuzhiyun
3416*4882a593Smuzhiyun static struct attribute *il3945_sysfs_entries[] = {
3417*4882a593Smuzhiyun &dev_attr_antenna.attr,
3418*4882a593Smuzhiyun &dev_attr_channels.attr,
3419*4882a593Smuzhiyun &dev_attr_dump_errors.attr,
3420*4882a593Smuzhiyun &dev_attr_flags.attr,
3421*4882a593Smuzhiyun &dev_attr_filter_flags.attr,
3422*4882a593Smuzhiyun &dev_attr_measurement.attr,
3423*4882a593Smuzhiyun &dev_attr_retry_rate.attr,
3424*4882a593Smuzhiyun &dev_attr_status.attr,
3425*4882a593Smuzhiyun &dev_attr_temperature.attr,
3426*4882a593Smuzhiyun &dev_attr_tx_power.attr,
3427*4882a593Smuzhiyun #ifdef CONFIG_IWLEGACY_DEBUG
3428*4882a593Smuzhiyun &dev_attr_debug_level.attr,
3429*4882a593Smuzhiyun #endif
3430*4882a593Smuzhiyun NULL
3431*4882a593Smuzhiyun };
3432*4882a593Smuzhiyun
3433*4882a593Smuzhiyun static const struct attribute_group il3945_attribute_group = {
3434*4882a593Smuzhiyun .name = NULL, /* put in device directory */
3435*4882a593Smuzhiyun .attrs = il3945_sysfs_entries,
3436*4882a593Smuzhiyun };
3437*4882a593Smuzhiyun
3438*4882a593Smuzhiyun static struct ieee80211_ops il3945_mac_ops __ro_after_init = {
3439*4882a593Smuzhiyun .tx = il3945_mac_tx,
3440*4882a593Smuzhiyun .start = il3945_mac_start,
3441*4882a593Smuzhiyun .stop = il3945_mac_stop,
3442*4882a593Smuzhiyun .add_interface = il_mac_add_interface,
3443*4882a593Smuzhiyun .remove_interface = il_mac_remove_interface,
3444*4882a593Smuzhiyun .change_interface = il_mac_change_interface,
3445*4882a593Smuzhiyun .config = il_mac_config,
3446*4882a593Smuzhiyun .configure_filter = il3945_configure_filter,
3447*4882a593Smuzhiyun .set_key = il3945_mac_set_key,
3448*4882a593Smuzhiyun .conf_tx = il_mac_conf_tx,
3449*4882a593Smuzhiyun .reset_tsf = il_mac_reset_tsf,
3450*4882a593Smuzhiyun .bss_info_changed = il_mac_bss_info_changed,
3451*4882a593Smuzhiyun .hw_scan = il_mac_hw_scan,
3452*4882a593Smuzhiyun .sta_add = il3945_mac_sta_add,
3453*4882a593Smuzhiyun .sta_remove = il_mac_sta_remove,
3454*4882a593Smuzhiyun .tx_last_beacon = il_mac_tx_last_beacon,
3455*4882a593Smuzhiyun .flush = il_mac_flush,
3456*4882a593Smuzhiyun };
3457*4882a593Smuzhiyun
3458*4882a593Smuzhiyun static int
il3945_init_drv(struct il_priv * il)3459*4882a593Smuzhiyun il3945_init_drv(struct il_priv *il)
3460*4882a593Smuzhiyun {
3461*4882a593Smuzhiyun int ret;
3462*4882a593Smuzhiyun struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
3463*4882a593Smuzhiyun
3464*4882a593Smuzhiyun il->retry_rate = 1;
3465*4882a593Smuzhiyun il->beacon_skb = NULL;
3466*4882a593Smuzhiyun
3467*4882a593Smuzhiyun spin_lock_init(&il->sta_lock);
3468*4882a593Smuzhiyun spin_lock_init(&il->hcmd_lock);
3469*4882a593Smuzhiyun
3470*4882a593Smuzhiyun INIT_LIST_HEAD(&il->free_frames);
3471*4882a593Smuzhiyun
3472*4882a593Smuzhiyun mutex_init(&il->mutex);
3473*4882a593Smuzhiyun
3474*4882a593Smuzhiyun il->ieee_channels = NULL;
3475*4882a593Smuzhiyun il->ieee_rates = NULL;
3476*4882a593Smuzhiyun il->band = NL80211_BAND_2GHZ;
3477*4882a593Smuzhiyun
3478*4882a593Smuzhiyun il->iw_mode = NL80211_IFTYPE_STATION;
3479*4882a593Smuzhiyun il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF;
3480*4882a593Smuzhiyun
3481*4882a593Smuzhiyun /* initialize force reset */
3482*4882a593Smuzhiyun il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD;
3483*4882a593Smuzhiyun
3484*4882a593Smuzhiyun if (eeprom->version < EEPROM_3945_EEPROM_VERSION) {
3485*4882a593Smuzhiyun IL_WARN("Unsupported EEPROM version: 0x%04X\n",
3486*4882a593Smuzhiyun eeprom->version);
3487*4882a593Smuzhiyun ret = -EINVAL;
3488*4882a593Smuzhiyun goto err;
3489*4882a593Smuzhiyun }
3490*4882a593Smuzhiyun ret = il_init_channel_map(il);
3491*4882a593Smuzhiyun if (ret) {
3492*4882a593Smuzhiyun IL_ERR("initializing regulatory failed: %d\n", ret);
3493*4882a593Smuzhiyun goto err;
3494*4882a593Smuzhiyun }
3495*4882a593Smuzhiyun
3496*4882a593Smuzhiyun /* Set up txpower settings in driver for all channels */
3497*4882a593Smuzhiyun if (il3945_txpower_set_from_eeprom(il)) {
3498*4882a593Smuzhiyun ret = -EIO;
3499*4882a593Smuzhiyun goto err_free_channel_map;
3500*4882a593Smuzhiyun }
3501*4882a593Smuzhiyun
3502*4882a593Smuzhiyun ret = il_init_geos(il);
3503*4882a593Smuzhiyun if (ret) {
3504*4882a593Smuzhiyun IL_ERR("initializing geos failed: %d\n", ret);
3505*4882a593Smuzhiyun goto err_free_channel_map;
3506*4882a593Smuzhiyun }
3507*4882a593Smuzhiyun il3945_init_hw_rates(il, il->ieee_rates);
3508*4882a593Smuzhiyun
3509*4882a593Smuzhiyun return 0;
3510*4882a593Smuzhiyun
3511*4882a593Smuzhiyun err_free_channel_map:
3512*4882a593Smuzhiyun il_free_channel_map(il);
3513*4882a593Smuzhiyun err:
3514*4882a593Smuzhiyun return ret;
3515*4882a593Smuzhiyun }
3516*4882a593Smuzhiyun
3517*4882a593Smuzhiyun #define IL3945_MAX_PROBE_REQUEST 200
3518*4882a593Smuzhiyun
3519*4882a593Smuzhiyun static int
il3945_setup_mac(struct il_priv * il)3520*4882a593Smuzhiyun il3945_setup_mac(struct il_priv *il)
3521*4882a593Smuzhiyun {
3522*4882a593Smuzhiyun int ret;
3523*4882a593Smuzhiyun struct ieee80211_hw *hw = il->hw;
3524*4882a593Smuzhiyun
3525*4882a593Smuzhiyun hw->rate_control_algorithm = "iwl-3945-rs";
3526*4882a593Smuzhiyun hw->sta_data_size = sizeof(struct il3945_sta_priv);
3527*4882a593Smuzhiyun hw->vif_data_size = sizeof(struct il_vif_priv);
3528*4882a593Smuzhiyun
3529*4882a593Smuzhiyun /* Tell mac80211 our characteristics */
3530*4882a593Smuzhiyun ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
3531*4882a593Smuzhiyun ieee80211_hw_set(hw, SUPPORTS_PS);
3532*4882a593Smuzhiyun ieee80211_hw_set(hw, SIGNAL_DBM);
3533*4882a593Smuzhiyun ieee80211_hw_set(hw, SPECTRUM_MGMT);
3534*4882a593Smuzhiyun
3535*4882a593Smuzhiyun hw->wiphy->interface_modes =
3536*4882a593Smuzhiyun BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_ADHOC);
3537*4882a593Smuzhiyun
3538*4882a593Smuzhiyun hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
3539*4882a593Smuzhiyun hw->wiphy->regulatory_flags |= REGULATORY_CUSTOM_REG |
3540*4882a593Smuzhiyun REGULATORY_DISABLE_BEACON_HINTS;
3541*4882a593Smuzhiyun
3542*4882a593Smuzhiyun hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3543*4882a593Smuzhiyun
3544*4882a593Smuzhiyun hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945;
3545*4882a593Smuzhiyun /* we create the 802.11 header and a zero-length SSID element */
3546*4882a593Smuzhiyun hw->wiphy->max_scan_ie_len = IL3945_MAX_PROBE_REQUEST - 24 - 2;
3547*4882a593Smuzhiyun
3548*4882a593Smuzhiyun /* Default value; 4 EDCA QOS priorities */
3549*4882a593Smuzhiyun hw->queues = 4;
3550*4882a593Smuzhiyun
3551*4882a593Smuzhiyun if (il->bands[NL80211_BAND_2GHZ].n_channels)
3552*4882a593Smuzhiyun il->hw->wiphy->bands[NL80211_BAND_2GHZ] =
3553*4882a593Smuzhiyun &il->bands[NL80211_BAND_2GHZ];
3554*4882a593Smuzhiyun
3555*4882a593Smuzhiyun if (il->bands[NL80211_BAND_5GHZ].n_channels)
3556*4882a593Smuzhiyun il->hw->wiphy->bands[NL80211_BAND_5GHZ] =
3557*4882a593Smuzhiyun &il->bands[NL80211_BAND_5GHZ];
3558*4882a593Smuzhiyun
3559*4882a593Smuzhiyun il_leds_init(il);
3560*4882a593Smuzhiyun
3561*4882a593Smuzhiyun wiphy_ext_feature_set(il->hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
3562*4882a593Smuzhiyun
3563*4882a593Smuzhiyun ret = ieee80211_register_hw(il->hw);
3564*4882a593Smuzhiyun if (ret) {
3565*4882a593Smuzhiyun IL_ERR("Failed to register hw (error %d)\n", ret);
3566*4882a593Smuzhiyun return ret;
3567*4882a593Smuzhiyun }
3568*4882a593Smuzhiyun il->mac80211_registered = 1;
3569*4882a593Smuzhiyun
3570*4882a593Smuzhiyun return 0;
3571*4882a593Smuzhiyun }
3572*4882a593Smuzhiyun
3573*4882a593Smuzhiyun static int
il3945_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)3574*4882a593Smuzhiyun il3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3575*4882a593Smuzhiyun {
3576*4882a593Smuzhiyun int err = 0;
3577*4882a593Smuzhiyun struct il_priv *il;
3578*4882a593Smuzhiyun struct ieee80211_hw *hw;
3579*4882a593Smuzhiyun struct il_cfg *cfg = (struct il_cfg *)(ent->driver_data);
3580*4882a593Smuzhiyun struct il3945_eeprom *eeprom;
3581*4882a593Smuzhiyun unsigned long flags;
3582*4882a593Smuzhiyun
3583*4882a593Smuzhiyun /***********************
3584*4882a593Smuzhiyun * 1. Allocating HW data
3585*4882a593Smuzhiyun * ********************/
3586*4882a593Smuzhiyun
3587*4882a593Smuzhiyun hw = ieee80211_alloc_hw(sizeof(struct il_priv), &il3945_mac_ops);
3588*4882a593Smuzhiyun if (!hw) {
3589*4882a593Smuzhiyun err = -ENOMEM;
3590*4882a593Smuzhiyun goto out;
3591*4882a593Smuzhiyun }
3592*4882a593Smuzhiyun il = hw->priv;
3593*4882a593Smuzhiyun il->hw = hw;
3594*4882a593Smuzhiyun SET_IEEE80211_DEV(hw, &pdev->dev);
3595*4882a593Smuzhiyun
3596*4882a593Smuzhiyun il->cmd_queue = IL39_CMD_QUEUE_NUM;
3597*4882a593Smuzhiyun
3598*4882a593Smuzhiyun D_INFO("*** LOAD DRIVER ***\n");
3599*4882a593Smuzhiyun il->cfg = cfg;
3600*4882a593Smuzhiyun il->ops = &il3945_ops;
3601*4882a593Smuzhiyun #ifdef CONFIG_IWLEGACY_DEBUGFS
3602*4882a593Smuzhiyun il->debugfs_ops = &il3945_debugfs_ops;
3603*4882a593Smuzhiyun #endif
3604*4882a593Smuzhiyun il->pci_dev = pdev;
3605*4882a593Smuzhiyun il->inta_mask = CSR_INI_SET_MASK;
3606*4882a593Smuzhiyun
3607*4882a593Smuzhiyun /***************************
3608*4882a593Smuzhiyun * 2. Initializing PCI bus
3609*4882a593Smuzhiyun * *************************/
3610*4882a593Smuzhiyun pci_disable_link_state(pdev,
3611*4882a593Smuzhiyun PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3612*4882a593Smuzhiyun PCIE_LINK_STATE_CLKPM);
3613*4882a593Smuzhiyun
3614*4882a593Smuzhiyun if (pci_enable_device(pdev)) {
3615*4882a593Smuzhiyun err = -ENODEV;
3616*4882a593Smuzhiyun goto out_ieee80211_free_hw;
3617*4882a593Smuzhiyun }
3618*4882a593Smuzhiyun
3619*4882a593Smuzhiyun pci_set_master(pdev);
3620*4882a593Smuzhiyun
3621*4882a593Smuzhiyun err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3622*4882a593Smuzhiyun if (!err)
3623*4882a593Smuzhiyun err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3624*4882a593Smuzhiyun if (err) {
3625*4882a593Smuzhiyun IL_WARN("No suitable DMA available.\n");
3626*4882a593Smuzhiyun goto out_pci_disable_device;
3627*4882a593Smuzhiyun }
3628*4882a593Smuzhiyun
3629*4882a593Smuzhiyun pci_set_drvdata(pdev, il);
3630*4882a593Smuzhiyun err = pci_request_regions(pdev, DRV_NAME);
3631*4882a593Smuzhiyun if (err)
3632*4882a593Smuzhiyun goto out_pci_disable_device;
3633*4882a593Smuzhiyun
3634*4882a593Smuzhiyun /***********************
3635*4882a593Smuzhiyun * 3. Read REV Register
3636*4882a593Smuzhiyun * ********************/
3637*4882a593Smuzhiyun il->hw_base = pci_ioremap_bar(pdev, 0);
3638*4882a593Smuzhiyun if (!il->hw_base) {
3639*4882a593Smuzhiyun err = -ENODEV;
3640*4882a593Smuzhiyun goto out_pci_release_regions;
3641*4882a593Smuzhiyun }
3642*4882a593Smuzhiyun
3643*4882a593Smuzhiyun D_INFO("pci_resource_len = 0x%08llx\n",
3644*4882a593Smuzhiyun (unsigned long long)pci_resource_len(pdev, 0));
3645*4882a593Smuzhiyun D_INFO("pci_resource_base = %p\n", il->hw_base);
3646*4882a593Smuzhiyun
3647*4882a593Smuzhiyun /* We disable the RETRY_TIMEOUT register (0x41) to keep
3648*4882a593Smuzhiyun * PCI Tx retries from interfering with C3 CPU state */
3649*4882a593Smuzhiyun pci_write_config_byte(pdev, 0x41, 0x00);
3650*4882a593Smuzhiyun
3651*4882a593Smuzhiyun /* these spin locks will be used in apm_init and EEPROM access
3652*4882a593Smuzhiyun * we should init now
3653*4882a593Smuzhiyun */
3654*4882a593Smuzhiyun spin_lock_init(&il->reg_lock);
3655*4882a593Smuzhiyun spin_lock_init(&il->lock);
3656*4882a593Smuzhiyun
3657*4882a593Smuzhiyun /*
3658*4882a593Smuzhiyun * stop and reset the on-board processor just in case it is in a
3659*4882a593Smuzhiyun * strange state ... like being left stranded by a primary kernel
3660*4882a593Smuzhiyun * and this is now the kdump kernel trying to start up
3661*4882a593Smuzhiyun */
3662*4882a593Smuzhiyun _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3663*4882a593Smuzhiyun
3664*4882a593Smuzhiyun /***********************
3665*4882a593Smuzhiyun * 4. Read EEPROM
3666*4882a593Smuzhiyun * ********************/
3667*4882a593Smuzhiyun
3668*4882a593Smuzhiyun /* Read the EEPROM */
3669*4882a593Smuzhiyun err = il_eeprom_init(il);
3670*4882a593Smuzhiyun if (err) {
3671*4882a593Smuzhiyun IL_ERR("Unable to init EEPROM\n");
3672*4882a593Smuzhiyun goto out_iounmap;
3673*4882a593Smuzhiyun }
3674*4882a593Smuzhiyun /* MAC Address location in EEPROM same for 3945/4965 */
3675*4882a593Smuzhiyun eeprom = (struct il3945_eeprom *)il->eeprom;
3676*4882a593Smuzhiyun D_INFO("MAC address: %pM\n", eeprom->mac_address);
3677*4882a593Smuzhiyun SET_IEEE80211_PERM_ADDR(il->hw, eeprom->mac_address);
3678*4882a593Smuzhiyun
3679*4882a593Smuzhiyun /***********************
3680*4882a593Smuzhiyun * 5. Setup HW Constants
3681*4882a593Smuzhiyun * ********************/
3682*4882a593Smuzhiyun /* Device-specific setup */
3683*4882a593Smuzhiyun err = il3945_hw_set_hw_params(il);
3684*4882a593Smuzhiyun if (err) {
3685*4882a593Smuzhiyun IL_ERR("failed to set hw settings\n");
3686*4882a593Smuzhiyun goto out_eeprom_free;
3687*4882a593Smuzhiyun }
3688*4882a593Smuzhiyun
3689*4882a593Smuzhiyun /***********************
3690*4882a593Smuzhiyun * 6. Setup il
3691*4882a593Smuzhiyun * ********************/
3692*4882a593Smuzhiyun
3693*4882a593Smuzhiyun err = il3945_init_drv(il);
3694*4882a593Smuzhiyun if (err) {
3695*4882a593Smuzhiyun IL_ERR("initializing driver failed\n");
3696*4882a593Smuzhiyun goto out_unset_hw_params;
3697*4882a593Smuzhiyun }
3698*4882a593Smuzhiyun
3699*4882a593Smuzhiyun IL_INFO("Detected Intel Wireless WiFi Link %s\n", il->cfg->name);
3700*4882a593Smuzhiyun
3701*4882a593Smuzhiyun /***********************
3702*4882a593Smuzhiyun * 7. Setup Services
3703*4882a593Smuzhiyun * ********************/
3704*4882a593Smuzhiyun
3705*4882a593Smuzhiyun spin_lock_irqsave(&il->lock, flags);
3706*4882a593Smuzhiyun il_disable_interrupts(il);
3707*4882a593Smuzhiyun spin_unlock_irqrestore(&il->lock, flags);
3708*4882a593Smuzhiyun
3709*4882a593Smuzhiyun pci_enable_msi(il->pci_dev);
3710*4882a593Smuzhiyun
3711*4882a593Smuzhiyun err = request_irq(il->pci_dev->irq, il_isr, IRQF_SHARED, DRV_NAME, il);
3712*4882a593Smuzhiyun if (err) {
3713*4882a593Smuzhiyun IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq);
3714*4882a593Smuzhiyun goto out_disable_msi;
3715*4882a593Smuzhiyun }
3716*4882a593Smuzhiyun
3717*4882a593Smuzhiyun err = sysfs_create_group(&pdev->dev.kobj, &il3945_attribute_group);
3718*4882a593Smuzhiyun if (err) {
3719*4882a593Smuzhiyun IL_ERR("failed to create sysfs device attributes\n");
3720*4882a593Smuzhiyun goto out_release_irq;
3721*4882a593Smuzhiyun }
3722*4882a593Smuzhiyun
3723*4882a593Smuzhiyun il_set_rxon_channel(il, &il->bands[NL80211_BAND_2GHZ].channels[5]);
3724*4882a593Smuzhiyun il3945_setup_deferred_work(il);
3725*4882a593Smuzhiyun il3945_setup_handlers(il);
3726*4882a593Smuzhiyun il_power_initialize(il);
3727*4882a593Smuzhiyun
3728*4882a593Smuzhiyun /*********************************
3729*4882a593Smuzhiyun * 8. Setup and Register mac80211
3730*4882a593Smuzhiyun * *******************************/
3731*4882a593Smuzhiyun
3732*4882a593Smuzhiyun il_enable_interrupts(il);
3733*4882a593Smuzhiyun
3734*4882a593Smuzhiyun err = il3945_setup_mac(il);
3735*4882a593Smuzhiyun if (err)
3736*4882a593Smuzhiyun goto out_remove_sysfs;
3737*4882a593Smuzhiyun
3738*4882a593Smuzhiyun il_dbgfs_register(il, DRV_NAME);
3739*4882a593Smuzhiyun
3740*4882a593Smuzhiyun /* Start monitoring the killswitch */
3741*4882a593Smuzhiyun queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll, 2 * HZ);
3742*4882a593Smuzhiyun
3743*4882a593Smuzhiyun return 0;
3744*4882a593Smuzhiyun
3745*4882a593Smuzhiyun out_remove_sysfs:
3746*4882a593Smuzhiyun destroy_workqueue(il->workqueue);
3747*4882a593Smuzhiyun il->workqueue = NULL;
3748*4882a593Smuzhiyun sysfs_remove_group(&pdev->dev.kobj, &il3945_attribute_group);
3749*4882a593Smuzhiyun out_release_irq:
3750*4882a593Smuzhiyun free_irq(il->pci_dev->irq, il);
3751*4882a593Smuzhiyun out_disable_msi:
3752*4882a593Smuzhiyun pci_disable_msi(il->pci_dev);
3753*4882a593Smuzhiyun il_free_geos(il);
3754*4882a593Smuzhiyun il_free_channel_map(il);
3755*4882a593Smuzhiyun out_unset_hw_params:
3756*4882a593Smuzhiyun il3945_unset_hw_params(il);
3757*4882a593Smuzhiyun out_eeprom_free:
3758*4882a593Smuzhiyun il_eeprom_free(il);
3759*4882a593Smuzhiyun out_iounmap:
3760*4882a593Smuzhiyun iounmap(il->hw_base);
3761*4882a593Smuzhiyun out_pci_release_regions:
3762*4882a593Smuzhiyun pci_release_regions(pdev);
3763*4882a593Smuzhiyun out_pci_disable_device:
3764*4882a593Smuzhiyun pci_disable_device(pdev);
3765*4882a593Smuzhiyun out_ieee80211_free_hw:
3766*4882a593Smuzhiyun ieee80211_free_hw(il->hw);
3767*4882a593Smuzhiyun out:
3768*4882a593Smuzhiyun return err;
3769*4882a593Smuzhiyun }
3770*4882a593Smuzhiyun
3771*4882a593Smuzhiyun static void
il3945_pci_remove(struct pci_dev * pdev)3772*4882a593Smuzhiyun il3945_pci_remove(struct pci_dev *pdev)
3773*4882a593Smuzhiyun {
3774*4882a593Smuzhiyun struct il_priv *il = pci_get_drvdata(pdev);
3775*4882a593Smuzhiyun unsigned long flags;
3776*4882a593Smuzhiyun
3777*4882a593Smuzhiyun if (!il)
3778*4882a593Smuzhiyun return;
3779*4882a593Smuzhiyun
3780*4882a593Smuzhiyun D_INFO("*** UNLOAD DRIVER ***\n");
3781*4882a593Smuzhiyun
3782*4882a593Smuzhiyun il_dbgfs_unregister(il);
3783*4882a593Smuzhiyun
3784*4882a593Smuzhiyun set_bit(S_EXIT_PENDING, &il->status);
3785*4882a593Smuzhiyun
3786*4882a593Smuzhiyun il_leds_exit(il);
3787*4882a593Smuzhiyun
3788*4882a593Smuzhiyun if (il->mac80211_registered) {
3789*4882a593Smuzhiyun ieee80211_unregister_hw(il->hw);
3790*4882a593Smuzhiyun il->mac80211_registered = 0;
3791*4882a593Smuzhiyun } else {
3792*4882a593Smuzhiyun il3945_down(il);
3793*4882a593Smuzhiyun }
3794*4882a593Smuzhiyun
3795*4882a593Smuzhiyun /*
3796*4882a593Smuzhiyun * Make sure device is reset to low power before unloading driver.
3797*4882a593Smuzhiyun * This may be redundant with il_down(), but there are paths to
3798*4882a593Smuzhiyun * run il_down() without calling apm_ops.stop(), and there are
3799*4882a593Smuzhiyun * paths to avoid running il_down() at all before leaving driver.
3800*4882a593Smuzhiyun * This (inexpensive) call *makes sure* device is reset.
3801*4882a593Smuzhiyun */
3802*4882a593Smuzhiyun il_apm_stop(il);
3803*4882a593Smuzhiyun
3804*4882a593Smuzhiyun /* make sure we flush any pending irq or
3805*4882a593Smuzhiyun * tasklet for the driver
3806*4882a593Smuzhiyun */
3807*4882a593Smuzhiyun spin_lock_irqsave(&il->lock, flags);
3808*4882a593Smuzhiyun il_disable_interrupts(il);
3809*4882a593Smuzhiyun spin_unlock_irqrestore(&il->lock, flags);
3810*4882a593Smuzhiyun
3811*4882a593Smuzhiyun il3945_synchronize_irq(il);
3812*4882a593Smuzhiyun
3813*4882a593Smuzhiyun sysfs_remove_group(&pdev->dev.kobj, &il3945_attribute_group);
3814*4882a593Smuzhiyun
3815*4882a593Smuzhiyun cancel_delayed_work_sync(&il->_3945.rfkill_poll);
3816*4882a593Smuzhiyun
3817*4882a593Smuzhiyun il3945_dealloc_ucode_pci(il);
3818*4882a593Smuzhiyun
3819*4882a593Smuzhiyun if (il->rxq.bd)
3820*4882a593Smuzhiyun il3945_rx_queue_free(il, &il->rxq);
3821*4882a593Smuzhiyun il3945_hw_txq_ctx_free(il);
3822*4882a593Smuzhiyun
3823*4882a593Smuzhiyun il3945_unset_hw_params(il);
3824*4882a593Smuzhiyun
3825*4882a593Smuzhiyun /*netif_stop_queue(dev); */
3826*4882a593Smuzhiyun flush_workqueue(il->workqueue);
3827*4882a593Smuzhiyun
3828*4882a593Smuzhiyun /* ieee80211_unregister_hw calls il3945_mac_stop, which flushes
3829*4882a593Smuzhiyun * il->workqueue... so we can't take down the workqueue
3830*4882a593Smuzhiyun * until now... */
3831*4882a593Smuzhiyun destroy_workqueue(il->workqueue);
3832*4882a593Smuzhiyun il->workqueue = NULL;
3833*4882a593Smuzhiyun
3834*4882a593Smuzhiyun free_irq(pdev->irq, il);
3835*4882a593Smuzhiyun pci_disable_msi(pdev);
3836*4882a593Smuzhiyun
3837*4882a593Smuzhiyun iounmap(il->hw_base);
3838*4882a593Smuzhiyun pci_release_regions(pdev);
3839*4882a593Smuzhiyun pci_disable_device(pdev);
3840*4882a593Smuzhiyun
3841*4882a593Smuzhiyun il_free_channel_map(il);
3842*4882a593Smuzhiyun il_free_geos(il);
3843*4882a593Smuzhiyun kfree(il->scan_cmd);
3844*4882a593Smuzhiyun dev_kfree_skb(il->beacon_skb);
3845*4882a593Smuzhiyun ieee80211_free_hw(il->hw);
3846*4882a593Smuzhiyun }
3847*4882a593Smuzhiyun
3848*4882a593Smuzhiyun /*****************************************************************************
3849*4882a593Smuzhiyun *
3850*4882a593Smuzhiyun * driver and module entry point
3851*4882a593Smuzhiyun *
3852*4882a593Smuzhiyun *****************************************************************************/
3853*4882a593Smuzhiyun
3854*4882a593Smuzhiyun static struct pci_driver il3945_driver = {
3855*4882a593Smuzhiyun .name = DRV_NAME,
3856*4882a593Smuzhiyun .id_table = il3945_hw_card_ids,
3857*4882a593Smuzhiyun .probe = il3945_pci_probe,
3858*4882a593Smuzhiyun .remove = il3945_pci_remove,
3859*4882a593Smuzhiyun .driver.pm = IL_LEGACY_PM_OPS,
3860*4882a593Smuzhiyun };
3861*4882a593Smuzhiyun
3862*4882a593Smuzhiyun static int __init
il3945_init(void)3863*4882a593Smuzhiyun il3945_init(void)
3864*4882a593Smuzhiyun {
3865*4882a593Smuzhiyun
3866*4882a593Smuzhiyun int ret;
3867*4882a593Smuzhiyun pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
3868*4882a593Smuzhiyun pr_info(DRV_COPYRIGHT "\n");
3869*4882a593Smuzhiyun
3870*4882a593Smuzhiyun /*
3871*4882a593Smuzhiyun * Disabling hardware scan means that mac80211 will perform scans
3872*4882a593Smuzhiyun * "the hard way", rather than using device's scan.
3873*4882a593Smuzhiyun */
3874*4882a593Smuzhiyun if (il3945_mod_params.disable_hw_scan) {
3875*4882a593Smuzhiyun pr_info("hw_scan is disabled\n");
3876*4882a593Smuzhiyun il3945_mac_ops.hw_scan = NULL;
3877*4882a593Smuzhiyun }
3878*4882a593Smuzhiyun
3879*4882a593Smuzhiyun ret = il3945_rate_control_register();
3880*4882a593Smuzhiyun if (ret) {
3881*4882a593Smuzhiyun pr_err("Unable to register rate control algorithm: %d\n", ret);
3882*4882a593Smuzhiyun return ret;
3883*4882a593Smuzhiyun }
3884*4882a593Smuzhiyun
3885*4882a593Smuzhiyun ret = pci_register_driver(&il3945_driver);
3886*4882a593Smuzhiyun if (ret) {
3887*4882a593Smuzhiyun pr_err("Unable to initialize PCI module\n");
3888*4882a593Smuzhiyun goto error_register;
3889*4882a593Smuzhiyun }
3890*4882a593Smuzhiyun
3891*4882a593Smuzhiyun return ret;
3892*4882a593Smuzhiyun
3893*4882a593Smuzhiyun error_register:
3894*4882a593Smuzhiyun il3945_rate_control_unregister();
3895*4882a593Smuzhiyun return ret;
3896*4882a593Smuzhiyun }
3897*4882a593Smuzhiyun
3898*4882a593Smuzhiyun static void __exit
il3945_exit(void)3899*4882a593Smuzhiyun il3945_exit(void)
3900*4882a593Smuzhiyun {
3901*4882a593Smuzhiyun pci_unregister_driver(&il3945_driver);
3902*4882a593Smuzhiyun il3945_rate_control_unregister();
3903*4882a593Smuzhiyun }
3904*4882a593Smuzhiyun
3905*4882a593Smuzhiyun MODULE_FIRMWARE(IL3945_MODULE_FIRMWARE(IL3945_UCODE_API_MAX));
3906*4882a593Smuzhiyun
3907*4882a593Smuzhiyun module_param_named(antenna, il3945_mod_params.antenna, int, 0444);
3908*4882a593Smuzhiyun MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
3909*4882a593Smuzhiyun module_param_named(swcrypto, il3945_mod_params.sw_crypto, int, 0444);
3910*4882a593Smuzhiyun MODULE_PARM_DESC(swcrypto, "using software crypto (default 1 [software])");
3911*4882a593Smuzhiyun module_param_named(disable_hw_scan, il3945_mod_params.disable_hw_scan, int,
3912*4882a593Smuzhiyun 0444);
3913*4882a593Smuzhiyun MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 1)");
3914*4882a593Smuzhiyun #ifdef CONFIG_IWLEGACY_DEBUG
3915*4882a593Smuzhiyun module_param_named(debug, il_debug_level, uint, 0644);
3916*4882a593Smuzhiyun MODULE_PARM_DESC(debug, "debug output mask");
3917*4882a593Smuzhiyun #endif
3918*4882a593Smuzhiyun module_param_named(fw_restart, il3945_mod_params.restart_fw, int, 0444);
3919*4882a593Smuzhiyun MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
3920*4882a593Smuzhiyun
3921*4882a593Smuzhiyun module_exit(il3945_exit);
3922*4882a593Smuzhiyun module_init(il3945_init);
3923