1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2011 Broadcom Corporation
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Permission to use, copy, modify, and/or distribute this software for any
5*4882a593Smuzhiyun * purpose with or without fee is hereby granted, provided that the above
6*4882a593Smuzhiyun * copyright notice and this permission notice appear in all copies.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9*4882a593Smuzhiyun * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10*4882a593Smuzhiyun * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11*4882a593Smuzhiyun * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12*4882a593Smuzhiyun * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13*4882a593Smuzhiyun * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14*4882a593Smuzhiyun * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15*4882a593Smuzhiyun */
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <linux/delay.h>
18*4882a593Smuzhiyun #include <linux/io.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include <brcm_hw_ids.h>
21*4882a593Smuzhiyun #include <chipcommon.h>
22*4882a593Smuzhiyun #include <brcmu_utils.h>
23*4882a593Smuzhiyun #include "pub.h"
24*4882a593Smuzhiyun #include "aiutils.h"
25*4882a593Smuzhiyun #include "pmu.h"
26*4882a593Smuzhiyun #include "soc.h"
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /*
29*4882a593Smuzhiyun * external LPO crystal frequency
30*4882a593Smuzhiyun */
31*4882a593Smuzhiyun #define EXT_ILP_HZ 32768
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /*
34*4882a593Smuzhiyun * Duration for ILP clock frequency measurment in milliseconds
35*4882a593Smuzhiyun *
36*4882a593Smuzhiyun * remark: 1000 must be an integer multiple of this duration
37*4882a593Smuzhiyun */
38*4882a593Smuzhiyun #define ILP_CALC_DUR 10
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /* Fields in pmucontrol */
41*4882a593Smuzhiyun #define PCTL_ILP_DIV_MASK 0xffff0000
42*4882a593Smuzhiyun #define PCTL_ILP_DIV_SHIFT 16
43*4882a593Smuzhiyun #define PCTL_PLL_PLLCTL_UPD 0x00000400 /* rev 2 */
44*4882a593Smuzhiyun #define PCTL_NOILP_ON_WAIT 0x00000200 /* rev 1 */
45*4882a593Smuzhiyun #define PCTL_HT_REQ_EN 0x00000100
46*4882a593Smuzhiyun #define PCTL_ALP_REQ_EN 0x00000080
47*4882a593Smuzhiyun #define PCTL_XTALFREQ_MASK 0x0000007c
48*4882a593Smuzhiyun #define PCTL_XTALFREQ_SHIFT 2
49*4882a593Smuzhiyun #define PCTL_ILP_DIV_EN 0x00000002
50*4882a593Smuzhiyun #define PCTL_LPO_SEL 0x00000001
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /* ILP clock */
53*4882a593Smuzhiyun #define ILP_CLOCK 32000
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /* ALP clock on pre-PMU chips */
56*4882a593Smuzhiyun #define ALP_CLOCK 20000000
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* pmustatus */
59*4882a593Smuzhiyun #define PST_EXTLPOAVAIL 0x0100
60*4882a593Smuzhiyun #define PST_WDRESET 0x0080
61*4882a593Smuzhiyun #define PST_INTPEND 0x0040
62*4882a593Smuzhiyun #define PST_SBCLKST 0x0030
63*4882a593Smuzhiyun #define PST_SBCLKST_ILP 0x0010
64*4882a593Smuzhiyun #define PST_SBCLKST_ALP 0x0020
65*4882a593Smuzhiyun #define PST_SBCLKST_HT 0x0030
66*4882a593Smuzhiyun #define PST_ALPAVAIL 0x0008
67*4882a593Smuzhiyun #define PST_HTAVAIL 0x0004
68*4882a593Smuzhiyun #define PST_RESINIT 0x0003
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /* PMU resource bit position */
71*4882a593Smuzhiyun #define PMURES_BIT(bit) (1 << (bit))
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /* PMU corerev and chip specific PLL controls.
74*4882a593Smuzhiyun * PMU<rev>_PLL<num>_XX where <rev> is PMU corerev and <num> is an arbitrary
75*4882a593Smuzhiyun * number to differentiate different PLLs controlled by the same PMU rev.
76*4882a593Smuzhiyun */
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /* pmu XtalFreqRatio */
79*4882a593Smuzhiyun #define PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF
80*4882a593Smuzhiyun #define PMU_XTALFREQ_REG_MEASURE_MASK 0x80000000
81*4882a593Smuzhiyun #define PMU_XTALFREQ_REG_MEASURE_SHIFT 31
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /* 4313 resources */
84*4882a593Smuzhiyun #define RES4313_BB_PU_RSRC 0
85*4882a593Smuzhiyun #define RES4313_ILP_REQ_RSRC 1
86*4882a593Smuzhiyun #define RES4313_XTAL_PU_RSRC 2
87*4882a593Smuzhiyun #define RES4313_ALP_AVAIL_RSRC 3
88*4882a593Smuzhiyun #define RES4313_RADIO_PU_RSRC 4
89*4882a593Smuzhiyun #define RES4313_BG_PU_RSRC 5
90*4882a593Smuzhiyun #define RES4313_VREG1P4_PU_RSRC 6
91*4882a593Smuzhiyun #define RES4313_AFE_PWRSW_RSRC 7
92*4882a593Smuzhiyun #define RES4313_RX_PWRSW_RSRC 8
93*4882a593Smuzhiyun #define RES4313_TX_PWRSW_RSRC 9
94*4882a593Smuzhiyun #define RES4313_BB_PWRSW_RSRC 10
95*4882a593Smuzhiyun #define RES4313_SYNTH_PWRSW_RSRC 11
96*4882a593Smuzhiyun #define RES4313_MISC_PWRSW_RSRC 12
97*4882a593Smuzhiyun #define RES4313_BB_PLL_PWRSW_RSRC 13
98*4882a593Smuzhiyun #define RES4313_HT_AVAIL_RSRC 14
99*4882a593Smuzhiyun #define RES4313_MACPHY_CLK_AVAIL_RSRC 15
100*4882a593Smuzhiyun
si_pmu_fast_pwrup_delay(struct si_pub * sih)101*4882a593Smuzhiyun u16 si_pmu_fast_pwrup_delay(struct si_pub *sih)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun uint delay = PMU_MAX_TRANSITION_DLY;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun switch (ai_get_chip_id(sih)) {
106*4882a593Smuzhiyun case BCMA_CHIP_ID_BCM43224:
107*4882a593Smuzhiyun case BCMA_CHIP_ID_BCM43225:
108*4882a593Smuzhiyun case BCMA_CHIP_ID_BCM4313:
109*4882a593Smuzhiyun delay = 3700;
110*4882a593Smuzhiyun break;
111*4882a593Smuzhiyun default:
112*4882a593Smuzhiyun break;
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun return (u16) delay;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
si_pmu_measure_alpclk(struct si_pub * sih)118*4882a593Smuzhiyun u32 si_pmu_measure_alpclk(struct si_pub *sih)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun struct si_info *sii = container_of(sih, struct si_info, pub);
121*4882a593Smuzhiyun struct bcma_device *core;
122*4882a593Smuzhiyun u32 alp_khz;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun if (ai_get_pmurev(sih) < 10)
125*4882a593Smuzhiyun return 0;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun /* Remember original core before switch to chipc */
128*4882a593Smuzhiyun core = sii->icbus->drv_cc.core;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun if (bcma_read32(core, CHIPCREGOFFS(pmustatus)) & PST_EXTLPOAVAIL) {
131*4882a593Smuzhiyun u32 ilp_ctr, alp_hz;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun /*
134*4882a593Smuzhiyun * Enable the reg to measure the freq,
135*4882a593Smuzhiyun * in case it was disabled before
136*4882a593Smuzhiyun */
137*4882a593Smuzhiyun bcma_write32(core, CHIPCREGOFFS(pmu_xtalfreq),
138*4882a593Smuzhiyun 1U << PMU_XTALFREQ_REG_MEASURE_SHIFT);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun /* Delay for well over 4 ILP clocks */
141*4882a593Smuzhiyun udelay(1000);
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun /* Read the latched number of ALP ticks per 4 ILP ticks */
144*4882a593Smuzhiyun ilp_ctr = bcma_read32(core, CHIPCREGOFFS(pmu_xtalfreq)) &
145*4882a593Smuzhiyun PMU_XTALFREQ_REG_ILPCTR_MASK;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun /*
148*4882a593Smuzhiyun * Turn off the PMU_XTALFREQ_REG_MEASURE_SHIFT
149*4882a593Smuzhiyun * bit to save power
150*4882a593Smuzhiyun */
151*4882a593Smuzhiyun bcma_write32(core, CHIPCREGOFFS(pmu_xtalfreq), 0);
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun /* Calculate ALP frequency */
154*4882a593Smuzhiyun alp_hz = (ilp_ctr * EXT_ILP_HZ) / 4;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun /*
157*4882a593Smuzhiyun * Round to nearest 100KHz, and at
158*4882a593Smuzhiyun * the same time convert to KHz
159*4882a593Smuzhiyun */
160*4882a593Smuzhiyun alp_khz = (alp_hz + 50000) / 100000 * 100;
161*4882a593Smuzhiyun } else
162*4882a593Smuzhiyun alp_khz = 0;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun return alp_khz;
165*4882a593Smuzhiyun }
166