xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/broadcom/brcm80211/brcmsmac/ampdu.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (c) 2010 Broadcom Corporation
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Permission to use, copy, modify, and/or distribute this software for any
5*4882a593Smuzhiyun  * purpose with or without fee is hereby granted, provided that the above
6*4882a593Smuzhiyun  * copyright notice and this permission notice appear in all copies.
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9*4882a593Smuzhiyun  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10*4882a593Smuzhiyun  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11*4882a593Smuzhiyun  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12*4882a593Smuzhiyun  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13*4882a593Smuzhiyun  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14*4882a593Smuzhiyun  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15*4882a593Smuzhiyun  */
16*4882a593Smuzhiyun #include <net/mac80211.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #include "rate.h"
19*4882a593Smuzhiyun #include "scb.h"
20*4882a593Smuzhiyun #include "phy/phy_hal.h"
21*4882a593Smuzhiyun #include "antsel.h"
22*4882a593Smuzhiyun #include "main.h"
23*4882a593Smuzhiyun #include "ampdu.h"
24*4882a593Smuzhiyun #include "debug.h"
25*4882a593Smuzhiyun #include "brcms_trace_events.h"
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun /* max number of mpdus in an ampdu */
28*4882a593Smuzhiyun #define AMPDU_MAX_MPDU			32
29*4882a593Smuzhiyun /* max number of mpdus in an ampdu to a legacy */
30*4882a593Smuzhiyun #define AMPDU_NUM_MPDU_LEGACY		16
31*4882a593Smuzhiyun /* max Tx ba window size (in pdu) */
32*4882a593Smuzhiyun #define AMPDU_TX_BA_MAX_WSIZE		64
33*4882a593Smuzhiyun /* default Tx ba window size (in pdu) */
34*4882a593Smuzhiyun #define AMPDU_TX_BA_DEF_WSIZE		64
35*4882a593Smuzhiyun /* default Rx ba window size (in pdu) */
36*4882a593Smuzhiyun #define AMPDU_RX_BA_DEF_WSIZE		64
37*4882a593Smuzhiyun /* max Rx ba window size (in pdu) */
38*4882a593Smuzhiyun #define AMPDU_RX_BA_MAX_WSIZE		64
39*4882a593Smuzhiyun /* max dur of tx ampdu (in msec) */
40*4882a593Smuzhiyun #define	AMPDU_MAX_DUR			5
41*4882a593Smuzhiyun /* default tx retry limit */
42*4882a593Smuzhiyun #define AMPDU_DEF_RETRY_LIMIT		5
43*4882a593Smuzhiyun /* default tx retry limit at reg rate */
44*4882a593Smuzhiyun #define AMPDU_DEF_RR_RETRY_LIMIT	2
45*4882a593Smuzhiyun /* default ffpld reserved bytes */
46*4882a593Smuzhiyun #define AMPDU_DEF_FFPLD_RSVD		2048
47*4882a593Smuzhiyun /* # of inis to be freed on detach */
48*4882a593Smuzhiyun #define AMPDU_INI_FREE			10
49*4882a593Smuzhiyun /* max # of mpdus released at a time */
50*4882a593Smuzhiyun #define	AMPDU_SCB_MAX_RELEASE		20
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun #define NUM_FFPLD_FIFO 4	/* number of fifo concerned by pre-loading */
53*4882a593Smuzhiyun #define FFPLD_TX_MAX_UNFL   200	/* default value of the average number of ampdu
54*4882a593Smuzhiyun 				 * without underflows
55*4882a593Smuzhiyun 				 */
56*4882a593Smuzhiyun #define FFPLD_MPDU_SIZE 1800	/* estimate of maximum mpdu size */
57*4882a593Smuzhiyun #define FFPLD_MAX_MCS 23	/* we don't deal with mcs 32 */
58*4882a593Smuzhiyun #define FFPLD_PLD_INCR 1000	/* increments in bytes */
59*4882a593Smuzhiyun #define FFPLD_MAX_AMPDU_CNT 5000	/* maximum number of ampdu we
60*4882a593Smuzhiyun 					 * accumulate between resets.
61*4882a593Smuzhiyun 					 */
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun #define AMPDU_DELIMITER_LEN	4
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun /* max allowed number of mpdus in an ampdu (2 streams) */
66*4882a593Smuzhiyun #define AMPDU_NUM_MPDU		16
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun #define TX_SEQ_TO_INDEX(seq) ((seq) % AMPDU_TX_BA_MAX_WSIZE)
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun /* max possible overhead per mpdu in the ampdu; 3 is for roundup if needed */
71*4882a593Smuzhiyun #define AMPDU_MAX_MPDU_OVERHEAD (FCS_LEN + DOT11_ICV_AES_LEN +\
72*4882a593Smuzhiyun 	AMPDU_DELIMITER_LEN + 3\
73*4882a593Smuzhiyun 	+ DOT11_A4_HDR_LEN + DOT11_QOS_LEN + DOT11_IV_MAX_LEN)
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun /* modulo add/sub, bound = 2^k */
76*4882a593Smuzhiyun #define MODADD_POW2(x, y, bound) (((x) + (y)) & ((bound) - 1))
77*4882a593Smuzhiyun #define MODSUB_POW2(x, y, bound) (((x) - (y)) & ((bound) - 1))
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun /* structure to hold tx fifo information and pre-loading state
80*4882a593Smuzhiyun  * counters specific to tx underflows of ampdus
81*4882a593Smuzhiyun  * some counters might be redundant with the ones in wlc or ampdu structures.
82*4882a593Smuzhiyun  * This allows to maintain a specific state independently of
83*4882a593Smuzhiyun  * how often and/or when the wlc counters are updated.
84*4882a593Smuzhiyun  *
85*4882a593Smuzhiyun  * ampdu_pld_size: number of bytes to be pre-loaded
86*4882a593Smuzhiyun  * mcs2ampdu_table: per-mcs max # of mpdus in an ampdu
87*4882a593Smuzhiyun  * prev_txfunfl: num of underflows last read from the HW macstats counter
88*4882a593Smuzhiyun  * accum_txfunfl: num of underflows since we modified pld params
89*4882a593Smuzhiyun  * accum_txampdu: num of tx ampdu since we modified pld params
90*4882a593Smuzhiyun  * prev_txampdu: previous reading of tx ampdu
91*4882a593Smuzhiyun  * dmaxferrate: estimated dma avg xfer rate in kbits/sec
92*4882a593Smuzhiyun  */
93*4882a593Smuzhiyun struct brcms_fifo_info {
94*4882a593Smuzhiyun 	u16 ampdu_pld_size;
95*4882a593Smuzhiyun 	u8 mcs2ampdu_table[FFPLD_MAX_MCS + 1];
96*4882a593Smuzhiyun 	u16 prev_txfunfl;
97*4882a593Smuzhiyun 	u32 accum_txfunfl;
98*4882a593Smuzhiyun 	u32 accum_txampdu;
99*4882a593Smuzhiyun 	u32 prev_txampdu;
100*4882a593Smuzhiyun 	u32 dmaxferrate;
101*4882a593Smuzhiyun };
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun /* AMPDU module specific state
104*4882a593Smuzhiyun  *
105*4882a593Smuzhiyun  * wlc: pointer to main wlc structure
106*4882a593Smuzhiyun  * scb_handle: scb cubby handle to retrieve data from scb
107*4882a593Smuzhiyun  * ini_enable: per-tid initiator enable/disable of ampdu
108*4882a593Smuzhiyun  * ba_tx_wsize: Tx ba window size (in pdu)
109*4882a593Smuzhiyun  * ba_rx_wsize: Rx ba window size (in pdu)
110*4882a593Smuzhiyun  * retry_limit: mpdu transmit retry limit
111*4882a593Smuzhiyun  * rr_retry_limit: mpdu transmit retry limit at regular rate
112*4882a593Smuzhiyun  * retry_limit_tid: per-tid mpdu transmit retry limit
113*4882a593Smuzhiyun  * rr_retry_limit_tid: per-tid mpdu transmit retry limit at regular rate
114*4882a593Smuzhiyun  * mpdu_density: min mpdu spacing (0-7) ==> 2^(x-1)/8 usec
115*4882a593Smuzhiyun  * max_pdu: max pdus allowed in ampdu
116*4882a593Smuzhiyun  * dur: max duration of an ampdu (in msec)
117*4882a593Smuzhiyun  * rx_factor: maximum rx ampdu factor (0-3) ==> 2^(13+x) bytes
118*4882a593Smuzhiyun  * ffpld_rsvd: number of bytes to reserve for preload
119*4882a593Smuzhiyun  * max_txlen: max size of ampdu per mcs, bw and sgi
120*4882a593Smuzhiyun  * mfbr: enable multiple fallback rate
121*4882a593Smuzhiyun  * tx_max_funl: underflows should be kept such that
122*4882a593Smuzhiyun  *		(tx_max_funfl*underflows) < tx frames
123*4882a593Smuzhiyun  * fifo_tb: table of fifo infos
124*4882a593Smuzhiyun  */
125*4882a593Smuzhiyun struct ampdu_info {
126*4882a593Smuzhiyun 	struct brcms_c_info *wlc;
127*4882a593Smuzhiyun 	int scb_handle;
128*4882a593Smuzhiyun 	u8 ini_enable[AMPDU_MAX_SCB_TID];
129*4882a593Smuzhiyun 	u8 ba_tx_wsize;
130*4882a593Smuzhiyun 	u8 ba_rx_wsize;
131*4882a593Smuzhiyun 	u8 retry_limit;
132*4882a593Smuzhiyun 	u8 rr_retry_limit;
133*4882a593Smuzhiyun 	u8 retry_limit_tid[AMPDU_MAX_SCB_TID];
134*4882a593Smuzhiyun 	u8 rr_retry_limit_tid[AMPDU_MAX_SCB_TID];
135*4882a593Smuzhiyun 	u8 mpdu_density;
136*4882a593Smuzhiyun 	s8 max_pdu;
137*4882a593Smuzhiyun 	u8 dur;
138*4882a593Smuzhiyun 	u8 rx_factor;
139*4882a593Smuzhiyun 	u32 ffpld_rsvd;
140*4882a593Smuzhiyun 	u32 max_txlen[MCS_TABLE_SIZE][2][2];
141*4882a593Smuzhiyun 	bool mfbr;
142*4882a593Smuzhiyun 	u32 tx_max_funl;
143*4882a593Smuzhiyun 	struct brcms_fifo_info fifo_tb[NUM_FFPLD_FIFO];
144*4882a593Smuzhiyun };
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun /* used for flushing ampdu packets */
147*4882a593Smuzhiyun struct cb_del_ampdu_pars {
148*4882a593Smuzhiyun 	struct ieee80211_sta *sta;
149*4882a593Smuzhiyun 	u16 tid;
150*4882a593Smuzhiyun };
151*4882a593Smuzhiyun 
brcms_c_scb_ampdu_update_max_txlen(struct ampdu_info * ampdu,u8 dur)152*4882a593Smuzhiyun static void brcms_c_scb_ampdu_update_max_txlen(struct ampdu_info *ampdu, u8 dur)
153*4882a593Smuzhiyun {
154*4882a593Smuzhiyun 	u32 rate, mcs;
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 	for (mcs = 0; mcs < MCS_TABLE_SIZE; mcs++) {
157*4882a593Smuzhiyun 		/* rate is in Kbps; dur is in msec ==> len = (rate * dur) / 8 */
158*4882a593Smuzhiyun 		/* 20MHz, No SGI */
159*4882a593Smuzhiyun 		rate = mcs_2_rate(mcs, false, false);
160*4882a593Smuzhiyun 		ampdu->max_txlen[mcs][0][0] = (rate * dur) >> 3;
161*4882a593Smuzhiyun 		/* 40 MHz, No SGI */
162*4882a593Smuzhiyun 		rate = mcs_2_rate(mcs, true, false);
163*4882a593Smuzhiyun 		ampdu->max_txlen[mcs][1][0] = (rate * dur) >> 3;
164*4882a593Smuzhiyun 		/* 20MHz, SGI */
165*4882a593Smuzhiyun 		rate = mcs_2_rate(mcs, false, true);
166*4882a593Smuzhiyun 		ampdu->max_txlen[mcs][0][1] = (rate * dur) >> 3;
167*4882a593Smuzhiyun 		/* 40 MHz, SGI */
168*4882a593Smuzhiyun 		rate = mcs_2_rate(mcs, true, true);
169*4882a593Smuzhiyun 		ampdu->max_txlen[mcs][1][1] = (rate * dur) >> 3;
170*4882a593Smuzhiyun 	}
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun 
brcms_c_ampdu_cap(struct ampdu_info * ampdu)173*4882a593Smuzhiyun static bool brcms_c_ampdu_cap(struct ampdu_info *ampdu)
174*4882a593Smuzhiyun {
175*4882a593Smuzhiyun 	if (BRCMS_PHY_11N_CAP(ampdu->wlc->band))
176*4882a593Smuzhiyun 		return true;
177*4882a593Smuzhiyun 	else
178*4882a593Smuzhiyun 		return false;
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun 
brcms_c_ampdu_set(struct ampdu_info * ampdu,bool on)181*4882a593Smuzhiyun static int brcms_c_ampdu_set(struct ampdu_info *ampdu, bool on)
182*4882a593Smuzhiyun {
183*4882a593Smuzhiyun 	struct brcms_c_info *wlc = ampdu->wlc;
184*4882a593Smuzhiyun 	struct bcma_device *core = wlc->hw->d11core;
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun 	wlc->pub->_ampdu = false;
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 	if (on) {
189*4882a593Smuzhiyun 		if (!(wlc->pub->_n_enab & SUPPORT_11N)) {
190*4882a593Smuzhiyun 			brcms_err(core, "wl%d: driver not nmode enabled\n",
191*4882a593Smuzhiyun 				  wlc->pub->unit);
192*4882a593Smuzhiyun 			return -ENOTSUPP;
193*4882a593Smuzhiyun 		}
194*4882a593Smuzhiyun 		if (!brcms_c_ampdu_cap(ampdu)) {
195*4882a593Smuzhiyun 			brcms_err(core, "wl%d: device not ampdu capable\n",
196*4882a593Smuzhiyun 				  wlc->pub->unit);
197*4882a593Smuzhiyun 			return -ENOTSUPP;
198*4882a593Smuzhiyun 		}
199*4882a593Smuzhiyun 		wlc->pub->_ampdu = on;
200*4882a593Smuzhiyun 	}
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	return 0;
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun 
brcms_c_ffpld_init(struct ampdu_info * ampdu)205*4882a593Smuzhiyun static void brcms_c_ffpld_init(struct ampdu_info *ampdu)
206*4882a593Smuzhiyun {
207*4882a593Smuzhiyun 	int i, j;
208*4882a593Smuzhiyun 	struct brcms_fifo_info *fifo;
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 	for (j = 0; j < NUM_FFPLD_FIFO; j++) {
211*4882a593Smuzhiyun 		fifo = (ampdu->fifo_tb + j);
212*4882a593Smuzhiyun 		fifo->ampdu_pld_size = 0;
213*4882a593Smuzhiyun 		for (i = 0; i <= FFPLD_MAX_MCS; i++)
214*4882a593Smuzhiyun 			fifo->mcs2ampdu_table[i] = 255;
215*4882a593Smuzhiyun 		fifo->dmaxferrate = 0;
216*4882a593Smuzhiyun 		fifo->accum_txampdu = 0;
217*4882a593Smuzhiyun 		fifo->prev_txfunfl = 0;
218*4882a593Smuzhiyun 		fifo->accum_txfunfl = 0;
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun 	}
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun 
brcms_c_ampdu_attach(struct brcms_c_info * wlc)223*4882a593Smuzhiyun struct ampdu_info *brcms_c_ampdu_attach(struct brcms_c_info *wlc)
224*4882a593Smuzhiyun {
225*4882a593Smuzhiyun 	struct ampdu_info *ampdu;
226*4882a593Smuzhiyun 	int i;
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun 	ampdu = kzalloc(sizeof(struct ampdu_info), GFP_ATOMIC);
229*4882a593Smuzhiyun 	if (!ampdu)
230*4882a593Smuzhiyun 		return NULL;
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 	ampdu->wlc = wlc;
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 	for (i = 0; i < AMPDU_MAX_SCB_TID; i++)
235*4882a593Smuzhiyun 		ampdu->ini_enable[i] = true;
236*4882a593Smuzhiyun 	/* Disable ampdu for VO by default */
237*4882a593Smuzhiyun 	ampdu->ini_enable[PRIO_8021D_VO] = false;
238*4882a593Smuzhiyun 	ampdu->ini_enable[PRIO_8021D_NC] = false;
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun 	/* Disable ampdu for BK by default since not enough fifo space */
241*4882a593Smuzhiyun 	ampdu->ini_enable[PRIO_8021D_NONE] = false;
242*4882a593Smuzhiyun 	ampdu->ini_enable[PRIO_8021D_BK] = false;
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	ampdu->ba_tx_wsize = AMPDU_TX_BA_DEF_WSIZE;
245*4882a593Smuzhiyun 	ampdu->ba_rx_wsize = AMPDU_RX_BA_DEF_WSIZE;
246*4882a593Smuzhiyun 	ampdu->mpdu_density = AMPDU_DEF_MPDU_DENSITY;
247*4882a593Smuzhiyun 	ampdu->max_pdu = AUTO;
248*4882a593Smuzhiyun 	ampdu->dur = AMPDU_MAX_DUR;
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun 	ampdu->ffpld_rsvd = AMPDU_DEF_FFPLD_RSVD;
251*4882a593Smuzhiyun 	/*
252*4882a593Smuzhiyun 	 * bump max ampdu rcv size to 64k for all 11n
253*4882a593Smuzhiyun 	 * devices except 4321A0 and 4321A1
254*4882a593Smuzhiyun 	 */
255*4882a593Smuzhiyun 	if (BRCMS_ISNPHY(wlc->band) && NREV_LT(wlc->band->phyrev, 2))
256*4882a593Smuzhiyun 		ampdu->rx_factor = IEEE80211_HT_MAX_AMPDU_32K;
257*4882a593Smuzhiyun 	else
258*4882a593Smuzhiyun 		ampdu->rx_factor = IEEE80211_HT_MAX_AMPDU_64K;
259*4882a593Smuzhiyun 	ampdu->retry_limit = AMPDU_DEF_RETRY_LIMIT;
260*4882a593Smuzhiyun 	ampdu->rr_retry_limit = AMPDU_DEF_RR_RETRY_LIMIT;
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 	for (i = 0; i < AMPDU_MAX_SCB_TID; i++) {
263*4882a593Smuzhiyun 		ampdu->retry_limit_tid[i] = ampdu->retry_limit;
264*4882a593Smuzhiyun 		ampdu->rr_retry_limit_tid[i] = ampdu->rr_retry_limit;
265*4882a593Smuzhiyun 	}
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun 	brcms_c_scb_ampdu_update_max_txlen(ampdu, ampdu->dur);
268*4882a593Smuzhiyun 	ampdu->mfbr = false;
269*4882a593Smuzhiyun 	/* try to set ampdu to the default value */
270*4882a593Smuzhiyun 	brcms_c_ampdu_set(ampdu, wlc->pub->_ampdu);
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun 	ampdu->tx_max_funl = FFPLD_TX_MAX_UNFL;
273*4882a593Smuzhiyun 	brcms_c_ffpld_init(ampdu);
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun 	return ampdu;
276*4882a593Smuzhiyun }
277*4882a593Smuzhiyun 
brcms_c_ampdu_detach(struct ampdu_info * ampdu)278*4882a593Smuzhiyun void brcms_c_ampdu_detach(struct ampdu_info *ampdu)
279*4882a593Smuzhiyun {
280*4882a593Smuzhiyun 	kfree(ampdu);
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun 
brcms_c_scb_ampdu_update_config(struct ampdu_info * ampdu,struct scb * scb)283*4882a593Smuzhiyun static void brcms_c_scb_ampdu_update_config(struct ampdu_info *ampdu,
284*4882a593Smuzhiyun 					    struct scb *scb)
285*4882a593Smuzhiyun {
286*4882a593Smuzhiyun 	struct scb_ampdu *scb_ampdu = &scb->scb_ampdu;
287*4882a593Smuzhiyun 	int i;
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun 	scb_ampdu->max_pdu = AMPDU_NUM_MPDU;
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 	/* go back to legacy size if some preloading is occurring */
292*4882a593Smuzhiyun 	for (i = 0; i < NUM_FFPLD_FIFO; i++) {
293*4882a593Smuzhiyun 		if (ampdu->fifo_tb[i].ampdu_pld_size > FFPLD_PLD_INCR)
294*4882a593Smuzhiyun 			scb_ampdu->max_pdu = AMPDU_NUM_MPDU_LEGACY;
295*4882a593Smuzhiyun 	}
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun 	/* apply user override */
298*4882a593Smuzhiyun 	if (ampdu->max_pdu != AUTO)
299*4882a593Smuzhiyun 		scb_ampdu->max_pdu = (u8) ampdu->max_pdu;
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun 	scb_ampdu->release = min_t(u8, scb_ampdu->max_pdu,
302*4882a593Smuzhiyun 				   AMPDU_SCB_MAX_RELEASE);
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun 	if (scb_ampdu->max_rx_ampdu_bytes)
305*4882a593Smuzhiyun 		scb_ampdu->release = min_t(u8, scb_ampdu->release,
306*4882a593Smuzhiyun 			scb_ampdu->max_rx_ampdu_bytes / 1600);
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun 	scb_ampdu->release = min(scb_ampdu->release,
309*4882a593Smuzhiyun 				 ampdu->fifo_tb[TX_AC_BE_FIFO].
310*4882a593Smuzhiyun 				 mcs2ampdu_table[FFPLD_MAX_MCS]);
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun 
brcms_c_scb_ampdu_update_config_all(struct ampdu_info * ampdu)313*4882a593Smuzhiyun static void brcms_c_scb_ampdu_update_config_all(struct ampdu_info *ampdu)
314*4882a593Smuzhiyun {
315*4882a593Smuzhiyun 	brcms_c_scb_ampdu_update_config(ampdu, &ampdu->wlc->pri_scb);
316*4882a593Smuzhiyun }
317*4882a593Smuzhiyun 
brcms_c_ffpld_calc_mcs2ampdu_table(struct ampdu_info * ampdu,int f)318*4882a593Smuzhiyun static void brcms_c_ffpld_calc_mcs2ampdu_table(struct ampdu_info *ampdu, int f)
319*4882a593Smuzhiyun {
320*4882a593Smuzhiyun 	int i;
321*4882a593Smuzhiyun 	u32 phy_rate, dma_rate, tmp;
322*4882a593Smuzhiyun 	u8 max_mpdu;
323*4882a593Smuzhiyun 	struct brcms_fifo_info *fifo = (ampdu->fifo_tb + f);
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun 	/* recompute the dma rate */
326*4882a593Smuzhiyun 	/* note : we divide/multiply by 100 to avoid integer overflows */
327*4882a593Smuzhiyun 	max_mpdu = min_t(u8, fifo->mcs2ampdu_table[FFPLD_MAX_MCS],
328*4882a593Smuzhiyun 			 AMPDU_NUM_MPDU_LEGACY);
329*4882a593Smuzhiyun 	phy_rate = mcs_2_rate(FFPLD_MAX_MCS, true, false);
330*4882a593Smuzhiyun 	dma_rate =
331*4882a593Smuzhiyun 	    (((phy_rate / 100) *
332*4882a593Smuzhiyun 	      (max_mpdu * FFPLD_MPDU_SIZE - fifo->ampdu_pld_size))
333*4882a593Smuzhiyun 	     / (max_mpdu * FFPLD_MPDU_SIZE)) * 100;
334*4882a593Smuzhiyun 	fifo->dmaxferrate = dma_rate;
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun 	/* fill up the mcs2ampdu table; do not recalc the last mcs */
337*4882a593Smuzhiyun 	dma_rate = dma_rate >> 7;
338*4882a593Smuzhiyun 	for (i = 0; i < FFPLD_MAX_MCS; i++) {
339*4882a593Smuzhiyun 		/* shifting to keep it within integer range */
340*4882a593Smuzhiyun 		phy_rate = mcs_2_rate(i, true, false) >> 7;
341*4882a593Smuzhiyun 		if (phy_rate > dma_rate) {
342*4882a593Smuzhiyun 			tmp = ((fifo->ampdu_pld_size * phy_rate) /
343*4882a593Smuzhiyun 			       ((phy_rate - dma_rate) * FFPLD_MPDU_SIZE)) + 1;
344*4882a593Smuzhiyun 			tmp = min_t(u32, tmp, 255);
345*4882a593Smuzhiyun 			fifo->mcs2ampdu_table[i] = (u8) tmp;
346*4882a593Smuzhiyun 		}
347*4882a593Smuzhiyun 	}
348*4882a593Smuzhiyun }
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun /* evaluate the dma transfer rate using the tx underflows as feedback.
351*4882a593Smuzhiyun  * If necessary, increase tx fifo preloading. If not enough,
352*4882a593Smuzhiyun  * decrease maximum ampdu size for each mcs till underflows stop
353*4882a593Smuzhiyun  * Return 1 if pre-loading not active, -1 if not an underflow event,
354*4882a593Smuzhiyun  * 0 if pre-loading module took care of the event.
355*4882a593Smuzhiyun  */
brcms_c_ffpld_check_txfunfl(struct brcms_c_info * wlc,int fid)356*4882a593Smuzhiyun static int brcms_c_ffpld_check_txfunfl(struct brcms_c_info *wlc, int fid)
357*4882a593Smuzhiyun {
358*4882a593Smuzhiyun 	struct ampdu_info *ampdu = wlc->ampdu;
359*4882a593Smuzhiyun 	u32 phy_rate = mcs_2_rate(FFPLD_MAX_MCS, true, false);
360*4882a593Smuzhiyun 	u32 txunfl_ratio;
361*4882a593Smuzhiyun 	u8 max_mpdu;
362*4882a593Smuzhiyun 	u32 current_ampdu_cnt = 0;
363*4882a593Smuzhiyun 	u16 max_pld_size;
364*4882a593Smuzhiyun 	u32 new_txunfl;
365*4882a593Smuzhiyun 	struct brcms_fifo_info *fifo = (ampdu->fifo_tb + fid);
366*4882a593Smuzhiyun 	uint xmtfifo_sz;
367*4882a593Smuzhiyun 	u16 cur_txunfl;
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun 	/* return if we got here for a different reason than underflows */
370*4882a593Smuzhiyun 	cur_txunfl = brcms_b_read_shm(wlc->hw,
371*4882a593Smuzhiyun 				      M_UCODE_MACSTAT +
372*4882a593Smuzhiyun 				      offsetof(struct macstat, txfunfl[fid]));
373*4882a593Smuzhiyun 	new_txunfl = (u16) (cur_txunfl - fifo->prev_txfunfl);
374*4882a593Smuzhiyun 	if (new_txunfl == 0) {
375*4882a593Smuzhiyun 		brcms_dbg_ht(wlc->hw->d11core,
376*4882a593Smuzhiyun 			     "TX status FRAG set but no tx underflows\n");
377*4882a593Smuzhiyun 		return -1;
378*4882a593Smuzhiyun 	}
379*4882a593Smuzhiyun 	fifo->prev_txfunfl = cur_txunfl;
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun 	if (!ampdu->tx_max_funl)
382*4882a593Smuzhiyun 		return 1;
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun 	/* check if fifo is big enough */
385*4882a593Smuzhiyun 	if (brcms_b_xmtfifo_sz_get(wlc->hw, fid, &xmtfifo_sz))
386*4882a593Smuzhiyun 		return -1;
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun 	if ((TXFIFO_SIZE_UNIT * (u32) xmtfifo_sz) <= ampdu->ffpld_rsvd)
389*4882a593Smuzhiyun 		return 1;
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun 	max_pld_size = TXFIFO_SIZE_UNIT * xmtfifo_sz - ampdu->ffpld_rsvd;
392*4882a593Smuzhiyun 	fifo->accum_txfunfl += new_txunfl;
393*4882a593Smuzhiyun 
394*4882a593Smuzhiyun 	/* we need to wait for at least 10 underflows */
395*4882a593Smuzhiyun 	if (fifo->accum_txfunfl < 10)
396*4882a593Smuzhiyun 		return 0;
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun 	brcms_dbg_ht(wlc->hw->d11core, "ampdu_count %d  tx_underflows %d\n",
399*4882a593Smuzhiyun 		     current_ampdu_cnt, fifo->accum_txfunfl);
400*4882a593Smuzhiyun 
401*4882a593Smuzhiyun 	/*
402*4882a593Smuzhiyun 	   compute the current ratio of tx unfl per ampdu.
403*4882a593Smuzhiyun 	   When the current ampdu count becomes too
404*4882a593Smuzhiyun 	   big while the ratio remains small, we reset
405*4882a593Smuzhiyun 	   the current count in order to not
406*4882a593Smuzhiyun 	   introduce too big of a latency in detecting a
407*4882a593Smuzhiyun 	   large amount of tx underflows later.
408*4882a593Smuzhiyun 	 */
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun 	txunfl_ratio = current_ampdu_cnt / fifo->accum_txfunfl;
411*4882a593Smuzhiyun 
412*4882a593Smuzhiyun 	if (txunfl_ratio > ampdu->tx_max_funl) {
413*4882a593Smuzhiyun 		if (current_ampdu_cnt >= FFPLD_MAX_AMPDU_CNT)
414*4882a593Smuzhiyun 			fifo->accum_txfunfl = 0;
415*4882a593Smuzhiyun 
416*4882a593Smuzhiyun 		return 0;
417*4882a593Smuzhiyun 	}
418*4882a593Smuzhiyun 	max_mpdu = min_t(u8, fifo->mcs2ampdu_table[FFPLD_MAX_MCS],
419*4882a593Smuzhiyun 			 AMPDU_NUM_MPDU_LEGACY);
420*4882a593Smuzhiyun 
421*4882a593Smuzhiyun 	/* In case max value max_pdu is already lower than
422*4882a593Smuzhiyun 	   the fifo depth, there is nothing more we can do.
423*4882a593Smuzhiyun 	 */
424*4882a593Smuzhiyun 
425*4882a593Smuzhiyun 	if (fifo->ampdu_pld_size >= max_mpdu * FFPLD_MPDU_SIZE) {
426*4882a593Smuzhiyun 		fifo->accum_txfunfl = 0;
427*4882a593Smuzhiyun 		return 0;
428*4882a593Smuzhiyun 	}
429*4882a593Smuzhiyun 
430*4882a593Smuzhiyun 	if (fifo->ampdu_pld_size < max_pld_size) {
431*4882a593Smuzhiyun 
432*4882a593Smuzhiyun 		/* increment by TX_FIFO_PLD_INC bytes */
433*4882a593Smuzhiyun 		fifo->ampdu_pld_size += FFPLD_PLD_INCR;
434*4882a593Smuzhiyun 		if (fifo->ampdu_pld_size > max_pld_size)
435*4882a593Smuzhiyun 			fifo->ampdu_pld_size = max_pld_size;
436*4882a593Smuzhiyun 
437*4882a593Smuzhiyun 		/* update scb release size */
438*4882a593Smuzhiyun 		brcms_c_scb_ampdu_update_config_all(ampdu);
439*4882a593Smuzhiyun 
440*4882a593Smuzhiyun 		/*
441*4882a593Smuzhiyun 		 * compute a new dma xfer rate for max_mpdu @ max mcs.
442*4882a593Smuzhiyun 		 * This is the minimum dma rate that can achieve no
443*4882a593Smuzhiyun 		 * underflow condition for the current mpdu size.
444*4882a593Smuzhiyun 		 *
445*4882a593Smuzhiyun 		 * note : we divide/multiply by 100 to avoid integer overflows
446*4882a593Smuzhiyun 		 */
447*4882a593Smuzhiyun 		fifo->dmaxferrate =
448*4882a593Smuzhiyun 		    (((phy_rate / 100) *
449*4882a593Smuzhiyun 		      (max_mpdu * FFPLD_MPDU_SIZE - fifo->ampdu_pld_size))
450*4882a593Smuzhiyun 		     / (max_mpdu * FFPLD_MPDU_SIZE)) * 100;
451*4882a593Smuzhiyun 
452*4882a593Smuzhiyun 		brcms_dbg_ht(wlc->hw->d11core,
453*4882a593Smuzhiyun 			     "DMA estimated transfer rate %d; "
454*4882a593Smuzhiyun 			     "pre-load size %d\n",
455*4882a593Smuzhiyun 			     fifo->dmaxferrate, fifo->ampdu_pld_size);
456*4882a593Smuzhiyun 	} else {
457*4882a593Smuzhiyun 
458*4882a593Smuzhiyun 		/* decrease ampdu size */
459*4882a593Smuzhiyun 		if (fifo->mcs2ampdu_table[FFPLD_MAX_MCS] > 1) {
460*4882a593Smuzhiyun 			if (fifo->mcs2ampdu_table[FFPLD_MAX_MCS] == 255)
461*4882a593Smuzhiyun 				fifo->mcs2ampdu_table[FFPLD_MAX_MCS] =
462*4882a593Smuzhiyun 				    AMPDU_NUM_MPDU_LEGACY - 1;
463*4882a593Smuzhiyun 			else
464*4882a593Smuzhiyun 				fifo->mcs2ampdu_table[FFPLD_MAX_MCS] -= 1;
465*4882a593Smuzhiyun 
466*4882a593Smuzhiyun 			/* recompute the table */
467*4882a593Smuzhiyun 			brcms_c_ffpld_calc_mcs2ampdu_table(ampdu, fid);
468*4882a593Smuzhiyun 
469*4882a593Smuzhiyun 			/* update scb release size */
470*4882a593Smuzhiyun 			brcms_c_scb_ampdu_update_config_all(ampdu);
471*4882a593Smuzhiyun 		}
472*4882a593Smuzhiyun 	}
473*4882a593Smuzhiyun 	fifo->accum_txfunfl = 0;
474*4882a593Smuzhiyun 	return 0;
475*4882a593Smuzhiyun }
476*4882a593Smuzhiyun 
477*4882a593Smuzhiyun void
brcms_c_ampdu_tx_operational(struct brcms_c_info * wlc,u8 tid,u8 ba_wsize,uint max_rx_ampdu_bytes)478*4882a593Smuzhiyun brcms_c_ampdu_tx_operational(struct brcms_c_info *wlc, u8 tid,
479*4882a593Smuzhiyun 	u8 ba_wsize,		/* negotiated ba window size (in pdu) */
480*4882a593Smuzhiyun 	uint max_rx_ampdu_bytes) /* from ht_cap in beacon */
481*4882a593Smuzhiyun {
482*4882a593Smuzhiyun 	struct scb_ampdu *scb_ampdu;
483*4882a593Smuzhiyun 	struct scb_ampdu_tid_ini *ini;
484*4882a593Smuzhiyun 	struct ampdu_info *ampdu = wlc->ampdu;
485*4882a593Smuzhiyun 	struct scb *scb = &wlc->pri_scb;
486*4882a593Smuzhiyun 	scb_ampdu = &scb->scb_ampdu;
487*4882a593Smuzhiyun 
488*4882a593Smuzhiyun 	if (!ampdu->ini_enable[tid]) {
489*4882a593Smuzhiyun 		brcms_err(wlc->hw->d11core, "%s: Rejecting tid %d\n",
490*4882a593Smuzhiyun 			  __func__, tid);
491*4882a593Smuzhiyun 		return;
492*4882a593Smuzhiyun 	}
493*4882a593Smuzhiyun 
494*4882a593Smuzhiyun 	ini = &scb_ampdu->ini[tid];
495*4882a593Smuzhiyun 	ini->tid = tid;
496*4882a593Smuzhiyun 	ini->scb = scb_ampdu->scb;
497*4882a593Smuzhiyun 	ini->ba_wsize = ba_wsize;
498*4882a593Smuzhiyun 	scb_ampdu->max_rx_ampdu_bytes = max_rx_ampdu_bytes;
499*4882a593Smuzhiyun }
500*4882a593Smuzhiyun 
brcms_c_ampdu_reset_session(struct brcms_ampdu_session * session,struct brcms_c_info * wlc)501*4882a593Smuzhiyun void brcms_c_ampdu_reset_session(struct brcms_ampdu_session *session,
502*4882a593Smuzhiyun 				 struct brcms_c_info *wlc)
503*4882a593Smuzhiyun {
504*4882a593Smuzhiyun 	session->wlc = wlc;
505*4882a593Smuzhiyun 	skb_queue_head_init(&session->skb_list);
506*4882a593Smuzhiyun 	session->max_ampdu_len = 0;    /* determined from first MPDU */
507*4882a593Smuzhiyun 	session->max_ampdu_frames = 0; /* determined from first MPDU */
508*4882a593Smuzhiyun 	session->ampdu_len = 0;
509*4882a593Smuzhiyun 	session->dma_len = 0;
510*4882a593Smuzhiyun }
511*4882a593Smuzhiyun 
512*4882a593Smuzhiyun /*
513*4882a593Smuzhiyun  * Preps the given packet for AMPDU based on the session data. If the
514*4882a593Smuzhiyun  * frame cannot be accomodated in the current session, -ENOSPC is
515*4882a593Smuzhiyun  * returned.
516*4882a593Smuzhiyun  */
brcms_c_ampdu_add_frame(struct brcms_ampdu_session * session,struct sk_buff * p)517*4882a593Smuzhiyun int brcms_c_ampdu_add_frame(struct brcms_ampdu_session *session,
518*4882a593Smuzhiyun 			    struct sk_buff *p)
519*4882a593Smuzhiyun {
520*4882a593Smuzhiyun 	struct brcms_c_info *wlc = session->wlc;
521*4882a593Smuzhiyun 	struct ampdu_info *ampdu = wlc->ampdu;
522*4882a593Smuzhiyun 	struct scb *scb = &wlc->pri_scb;
523*4882a593Smuzhiyun 	struct scb_ampdu *scb_ampdu = &scb->scb_ampdu;
524*4882a593Smuzhiyun 	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(p);
525*4882a593Smuzhiyun 	struct ieee80211_tx_rate *txrate = tx_info->status.rates;
526*4882a593Smuzhiyun 	struct d11txh *txh = (struct d11txh *)p->data;
527*4882a593Smuzhiyun 	unsigned ampdu_frames;
528*4882a593Smuzhiyun 	u8 ndelim, tid;
529*4882a593Smuzhiyun 	u8 *plcp;
530*4882a593Smuzhiyun 	uint len;
531*4882a593Smuzhiyun 	u16 mcl;
532*4882a593Smuzhiyun 	bool fbr_iscck;
533*4882a593Smuzhiyun 	bool rr;
534*4882a593Smuzhiyun 
535*4882a593Smuzhiyun 	ndelim = txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM];
536*4882a593Smuzhiyun 	plcp = (u8 *)(txh + 1);
537*4882a593Smuzhiyun 	fbr_iscck = !(le16_to_cpu(txh->XtraFrameTypes) & 0x03);
538*4882a593Smuzhiyun 	len = fbr_iscck ? BRCMS_GET_CCK_PLCP_LEN(txh->FragPLCPFallback) :
539*4882a593Smuzhiyun 			  BRCMS_GET_MIMO_PLCP_LEN(txh->FragPLCPFallback);
540*4882a593Smuzhiyun 	len = roundup(len, 4) + (ndelim + 1) * AMPDU_DELIMITER_LEN;
541*4882a593Smuzhiyun 
542*4882a593Smuzhiyun 	ampdu_frames = skb_queue_len(&session->skb_list);
543*4882a593Smuzhiyun 	if (ampdu_frames != 0) {
544*4882a593Smuzhiyun 		struct sk_buff *first;
545*4882a593Smuzhiyun 
546*4882a593Smuzhiyun 		if (ampdu_frames + 1 > session->max_ampdu_frames ||
547*4882a593Smuzhiyun 		    session->ampdu_len + len > session->max_ampdu_len)
548*4882a593Smuzhiyun 			return -ENOSPC;
549*4882a593Smuzhiyun 
550*4882a593Smuzhiyun 		/*
551*4882a593Smuzhiyun 		 * We aren't really out of space if the new frame is of
552*4882a593Smuzhiyun 		 * a different priority, but we want the same behaviour
553*4882a593Smuzhiyun 		 * so return -ENOSPC anyway.
554*4882a593Smuzhiyun 		 *
555*4882a593Smuzhiyun 		 * XXX: The old AMPDU code did this, but is it really
556*4882a593Smuzhiyun 		 * necessary?
557*4882a593Smuzhiyun 		 */
558*4882a593Smuzhiyun 		first = skb_peek(&session->skb_list);
559*4882a593Smuzhiyun 		if (p->priority != first->priority)
560*4882a593Smuzhiyun 			return -ENOSPC;
561*4882a593Smuzhiyun 	}
562*4882a593Smuzhiyun 
563*4882a593Smuzhiyun 	/*
564*4882a593Smuzhiyun 	 * Now that we're sure this frame can be accomodated, update the
565*4882a593Smuzhiyun 	 * session information.
566*4882a593Smuzhiyun 	 */
567*4882a593Smuzhiyun 	session->ampdu_len += len;
568*4882a593Smuzhiyun 	session->dma_len += p->len;
569*4882a593Smuzhiyun 
570*4882a593Smuzhiyun 	tid = (u8)p->priority;
571*4882a593Smuzhiyun 
572*4882a593Smuzhiyun 	/* Handle retry limits */
573*4882a593Smuzhiyun 	if (txrate[0].count <= ampdu->rr_retry_limit_tid[tid]) {
574*4882a593Smuzhiyun 		txrate[0].count++;
575*4882a593Smuzhiyun 		rr = true;
576*4882a593Smuzhiyun 	} else {
577*4882a593Smuzhiyun 		txrate[1].count++;
578*4882a593Smuzhiyun 		rr = false;
579*4882a593Smuzhiyun 	}
580*4882a593Smuzhiyun 
581*4882a593Smuzhiyun 	if (ampdu_frames == 0) {
582*4882a593Smuzhiyun 		u8 plcp0, plcp3, is40, sgi, mcs;
583*4882a593Smuzhiyun 		uint fifo = le16_to_cpu(txh->TxFrameID) & TXFID_QUEUE_MASK;
584*4882a593Smuzhiyun 		struct brcms_fifo_info *f = &ampdu->fifo_tb[fifo];
585*4882a593Smuzhiyun 
586*4882a593Smuzhiyun 		if (rr) {
587*4882a593Smuzhiyun 			plcp0 = plcp[0];
588*4882a593Smuzhiyun 			plcp3 = plcp[3];
589*4882a593Smuzhiyun 		} else {
590*4882a593Smuzhiyun 			plcp0 = txh->FragPLCPFallback[0];
591*4882a593Smuzhiyun 			plcp3 = txh->FragPLCPFallback[3];
592*4882a593Smuzhiyun 
593*4882a593Smuzhiyun 		}
594*4882a593Smuzhiyun 
595*4882a593Smuzhiyun 		/* Limit AMPDU size based on MCS */
596*4882a593Smuzhiyun 		is40 = (plcp0 & MIMO_PLCP_40MHZ) ? 1 : 0;
597*4882a593Smuzhiyun 		sgi = plcp3_issgi(plcp3) ? 1 : 0;
598*4882a593Smuzhiyun 		mcs = plcp0 & ~MIMO_PLCP_40MHZ;
599*4882a593Smuzhiyun 		session->max_ampdu_len = min(scb_ampdu->max_rx_ampdu_bytes,
600*4882a593Smuzhiyun 					     ampdu->max_txlen[mcs][is40][sgi]);
601*4882a593Smuzhiyun 
602*4882a593Smuzhiyun 		session->max_ampdu_frames = scb_ampdu->max_pdu;
603*4882a593Smuzhiyun 		if (mcs_2_rate(mcs, true, false) >= f->dmaxferrate) {
604*4882a593Smuzhiyun 			session->max_ampdu_frames =
605*4882a593Smuzhiyun 				min_t(u16, f->mcs2ampdu_table[mcs],
606*4882a593Smuzhiyun 				      session->max_ampdu_frames);
607*4882a593Smuzhiyun 		}
608*4882a593Smuzhiyun 	}
609*4882a593Smuzhiyun 
610*4882a593Smuzhiyun 	/*
611*4882a593Smuzhiyun 	 * Treat all frames as "middle" frames of AMPDU here. First and
612*4882a593Smuzhiyun 	 * last frames must be fixed up after all MPDUs have been prepped.
613*4882a593Smuzhiyun 	 */
614*4882a593Smuzhiyun 	mcl = le16_to_cpu(txh->MacTxControlLow);
615*4882a593Smuzhiyun 	mcl &= ~TXC_AMPDU_MASK;
616*4882a593Smuzhiyun 	mcl |= (TXC_AMPDU_MIDDLE << TXC_AMPDU_SHIFT);
617*4882a593Smuzhiyun 	mcl &= ~(TXC_STARTMSDU | TXC_SENDRTS | TXC_SENDCTS);
618*4882a593Smuzhiyun 	txh->MacTxControlLow = cpu_to_le16(mcl);
619*4882a593Smuzhiyun 	txh->PreloadSize = 0;	/* always default to 0 */
620*4882a593Smuzhiyun 
621*4882a593Smuzhiyun 	skb_queue_tail(&session->skb_list, p);
622*4882a593Smuzhiyun 
623*4882a593Smuzhiyun 	return 0;
624*4882a593Smuzhiyun }
625*4882a593Smuzhiyun 
brcms_c_ampdu_finalize(struct brcms_ampdu_session * session)626*4882a593Smuzhiyun void brcms_c_ampdu_finalize(struct brcms_ampdu_session *session)
627*4882a593Smuzhiyun {
628*4882a593Smuzhiyun 	struct brcms_c_info *wlc = session->wlc;
629*4882a593Smuzhiyun 	struct ampdu_info *ampdu = wlc->ampdu;
630*4882a593Smuzhiyun 	struct sk_buff *first, *last;
631*4882a593Smuzhiyun 	struct d11txh *txh;
632*4882a593Smuzhiyun 	struct ieee80211_tx_info *tx_info;
633*4882a593Smuzhiyun 	struct ieee80211_tx_rate *txrate;
634*4882a593Smuzhiyun 	u8 ndelim;
635*4882a593Smuzhiyun 	u8 *plcp;
636*4882a593Smuzhiyun 	uint len;
637*4882a593Smuzhiyun 	uint fifo;
638*4882a593Smuzhiyun 	struct brcms_fifo_info *f;
639*4882a593Smuzhiyun 	u16 mcl;
640*4882a593Smuzhiyun 	bool fbr;
641*4882a593Smuzhiyun 	bool fbr_iscck;
642*4882a593Smuzhiyun 	struct ieee80211_rts *rts;
643*4882a593Smuzhiyun 	bool use_rts = false, use_cts = false;
644*4882a593Smuzhiyun 	u16 dma_len = session->dma_len;
645*4882a593Smuzhiyun 	u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ;
646*4882a593Smuzhiyun 	u32 rspec = 0, rspec_fallback = 0;
647*4882a593Smuzhiyun 	u32 rts_rspec = 0, rts_rspec_fallback = 0;
648*4882a593Smuzhiyun 	u8 plcp0, is40, mcs;
649*4882a593Smuzhiyun 	u16 mch;
650*4882a593Smuzhiyun 	u8 preamble_type = BRCMS_GF_PREAMBLE;
651*4882a593Smuzhiyun 	u8 fbr_preamble_type = BRCMS_GF_PREAMBLE;
652*4882a593Smuzhiyun 	u8 rts_preamble_type = BRCMS_LONG_PREAMBLE;
653*4882a593Smuzhiyun 	u8 rts_fbr_preamble_type = BRCMS_LONG_PREAMBLE;
654*4882a593Smuzhiyun 
655*4882a593Smuzhiyun 	if (skb_queue_empty(&session->skb_list))
656*4882a593Smuzhiyun 		return;
657*4882a593Smuzhiyun 
658*4882a593Smuzhiyun 	first = skb_peek(&session->skb_list);
659*4882a593Smuzhiyun 	last = skb_peek_tail(&session->skb_list);
660*4882a593Smuzhiyun 
661*4882a593Smuzhiyun 	/* Need to fix up last MPDU first to adjust AMPDU length */
662*4882a593Smuzhiyun 	txh = (struct d11txh *)last->data;
663*4882a593Smuzhiyun 	fifo = le16_to_cpu(txh->TxFrameID) & TXFID_QUEUE_MASK;
664*4882a593Smuzhiyun 	f = &ampdu->fifo_tb[fifo];
665*4882a593Smuzhiyun 
666*4882a593Smuzhiyun 	mcl = le16_to_cpu(txh->MacTxControlLow);
667*4882a593Smuzhiyun 	mcl &= ~TXC_AMPDU_MASK;
668*4882a593Smuzhiyun 	mcl |= (TXC_AMPDU_LAST << TXC_AMPDU_SHIFT);
669*4882a593Smuzhiyun 	txh->MacTxControlLow = cpu_to_le16(mcl);
670*4882a593Smuzhiyun 
671*4882a593Smuzhiyun 	/* remove the null delimiter after last mpdu */
672*4882a593Smuzhiyun 	ndelim = txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM];
673*4882a593Smuzhiyun 	txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM] = 0;
674*4882a593Smuzhiyun 	session->ampdu_len -= ndelim * AMPDU_DELIMITER_LEN;
675*4882a593Smuzhiyun 
676*4882a593Smuzhiyun 	/* remove the pad len from last mpdu */
677*4882a593Smuzhiyun 	fbr_iscck = ((le16_to_cpu(txh->XtraFrameTypes) & 0x3) == 0);
678*4882a593Smuzhiyun 	len = fbr_iscck ? BRCMS_GET_CCK_PLCP_LEN(txh->FragPLCPFallback) :
679*4882a593Smuzhiyun 			  BRCMS_GET_MIMO_PLCP_LEN(txh->FragPLCPFallback);
680*4882a593Smuzhiyun 	session->ampdu_len -= roundup(len, 4) - len;
681*4882a593Smuzhiyun 
682*4882a593Smuzhiyun 	/* Now fix up the first MPDU */
683*4882a593Smuzhiyun 	tx_info = IEEE80211_SKB_CB(first);
684*4882a593Smuzhiyun 	txrate = tx_info->status.rates;
685*4882a593Smuzhiyun 	txh = (struct d11txh *)first->data;
686*4882a593Smuzhiyun 	plcp = (u8 *)(txh + 1);
687*4882a593Smuzhiyun 	rts = (struct ieee80211_rts *)&txh->rts_frame;
688*4882a593Smuzhiyun 
689*4882a593Smuzhiyun 	mcl = le16_to_cpu(txh->MacTxControlLow);
690*4882a593Smuzhiyun 	/* If only one MPDU leave it marked as last */
691*4882a593Smuzhiyun 	if (first != last) {
692*4882a593Smuzhiyun 		mcl &= ~TXC_AMPDU_MASK;
693*4882a593Smuzhiyun 		mcl |= (TXC_AMPDU_FIRST << TXC_AMPDU_SHIFT);
694*4882a593Smuzhiyun 	}
695*4882a593Smuzhiyun 	mcl |= TXC_STARTMSDU;
696*4882a593Smuzhiyun 	if (ieee80211_is_rts(rts->frame_control)) {
697*4882a593Smuzhiyun 		mcl |= TXC_SENDRTS;
698*4882a593Smuzhiyun 		use_rts = true;
699*4882a593Smuzhiyun 	}
700*4882a593Smuzhiyun 	if (ieee80211_is_cts(rts->frame_control)) {
701*4882a593Smuzhiyun 		mcl |= TXC_SENDCTS;
702*4882a593Smuzhiyun 		use_cts = true;
703*4882a593Smuzhiyun 	}
704*4882a593Smuzhiyun 	txh->MacTxControlLow = cpu_to_le16(mcl);
705*4882a593Smuzhiyun 
706*4882a593Smuzhiyun 	fbr = txrate[1].count > 0;
707*4882a593Smuzhiyun 	if (!fbr)
708*4882a593Smuzhiyun 		plcp0 = plcp[0];
709*4882a593Smuzhiyun 	else
710*4882a593Smuzhiyun 		plcp0 = txh->FragPLCPFallback[0];
711*4882a593Smuzhiyun 
712*4882a593Smuzhiyun 	is40 = (plcp0 & MIMO_PLCP_40MHZ) ? 1 : 0;
713*4882a593Smuzhiyun 	mcs = plcp0 & ~MIMO_PLCP_40MHZ;
714*4882a593Smuzhiyun 
715*4882a593Smuzhiyun 	if (is40) {
716*4882a593Smuzhiyun 		if (CHSPEC_SB_UPPER(wlc_phy_chanspec_get(wlc->band->pi)))
717*4882a593Smuzhiyun 			mimo_ctlchbw = PHY_TXC1_BW_20MHZ_UP;
718*4882a593Smuzhiyun 		else
719*4882a593Smuzhiyun 			mimo_ctlchbw = PHY_TXC1_BW_20MHZ;
720*4882a593Smuzhiyun 	}
721*4882a593Smuzhiyun 
722*4882a593Smuzhiyun 	/* rebuild the rspec and rspec_fallback */
723*4882a593Smuzhiyun 	rspec = RSPEC_MIMORATE;
724*4882a593Smuzhiyun 	rspec |= plcp[0] & ~MIMO_PLCP_40MHZ;
725*4882a593Smuzhiyun 	if (plcp[0] & MIMO_PLCP_40MHZ)
726*4882a593Smuzhiyun 		rspec |= (PHY_TXC1_BW_40MHZ << RSPEC_BW_SHIFT);
727*4882a593Smuzhiyun 
728*4882a593Smuzhiyun 	fbr_iscck = !(le16_to_cpu(txh->XtraFrameTypes) & 0x03);
729*4882a593Smuzhiyun 	if (fbr_iscck) {
730*4882a593Smuzhiyun 		rspec_fallback =
731*4882a593Smuzhiyun 			cck_rspec(cck_phy2mac_rate(txh->FragPLCPFallback[0]));
732*4882a593Smuzhiyun 	} else {
733*4882a593Smuzhiyun 		rspec_fallback = RSPEC_MIMORATE;
734*4882a593Smuzhiyun 		rspec_fallback |= txh->FragPLCPFallback[0] & ~MIMO_PLCP_40MHZ;
735*4882a593Smuzhiyun 		if (txh->FragPLCPFallback[0] & MIMO_PLCP_40MHZ)
736*4882a593Smuzhiyun 			rspec_fallback |= PHY_TXC1_BW_40MHZ << RSPEC_BW_SHIFT;
737*4882a593Smuzhiyun 	}
738*4882a593Smuzhiyun 
739*4882a593Smuzhiyun 	if (use_rts || use_cts) {
740*4882a593Smuzhiyun 		rts_rspec =
741*4882a593Smuzhiyun 			brcms_c_rspec_to_rts_rspec(wlc, rspec,
742*4882a593Smuzhiyun 						   false, mimo_ctlchbw);
743*4882a593Smuzhiyun 		rts_rspec_fallback =
744*4882a593Smuzhiyun 			brcms_c_rspec_to_rts_rspec(wlc, rspec_fallback,
745*4882a593Smuzhiyun 						   false, mimo_ctlchbw);
746*4882a593Smuzhiyun 	}
747*4882a593Smuzhiyun 
748*4882a593Smuzhiyun 	BRCMS_SET_MIMO_PLCP_LEN(plcp, session->ampdu_len);
749*4882a593Smuzhiyun 	/* mark plcp to indicate ampdu */
750*4882a593Smuzhiyun 	BRCMS_SET_MIMO_PLCP_AMPDU(plcp);
751*4882a593Smuzhiyun 
752*4882a593Smuzhiyun 	/* reset the mixed mode header durations */
753*4882a593Smuzhiyun 	if (txh->MModeLen) {
754*4882a593Smuzhiyun 		u16 mmodelen = brcms_c_calc_lsig_len(wlc, rspec,
755*4882a593Smuzhiyun 						     session->ampdu_len);
756*4882a593Smuzhiyun 		txh->MModeLen = cpu_to_le16(mmodelen);
757*4882a593Smuzhiyun 		preamble_type = BRCMS_MM_PREAMBLE;
758*4882a593Smuzhiyun 	}
759*4882a593Smuzhiyun 	if (txh->MModeFbrLen) {
760*4882a593Smuzhiyun 		u16 mmfbrlen = brcms_c_calc_lsig_len(wlc, rspec_fallback,
761*4882a593Smuzhiyun 						     session->ampdu_len);
762*4882a593Smuzhiyun 		txh->MModeFbrLen = cpu_to_le16(mmfbrlen);
763*4882a593Smuzhiyun 		fbr_preamble_type = BRCMS_MM_PREAMBLE;
764*4882a593Smuzhiyun 	}
765*4882a593Smuzhiyun 
766*4882a593Smuzhiyun 	/* set the preload length */
767*4882a593Smuzhiyun 	if (mcs_2_rate(mcs, true, false) >= f->dmaxferrate) {
768*4882a593Smuzhiyun 		dma_len = min(dma_len, f->ampdu_pld_size);
769*4882a593Smuzhiyun 		txh->PreloadSize = cpu_to_le16(dma_len);
770*4882a593Smuzhiyun 	} else {
771*4882a593Smuzhiyun 		txh->PreloadSize = 0;
772*4882a593Smuzhiyun 	}
773*4882a593Smuzhiyun 
774*4882a593Smuzhiyun 	mch = le16_to_cpu(txh->MacTxControlHigh);
775*4882a593Smuzhiyun 
776*4882a593Smuzhiyun 	/* update RTS dur fields */
777*4882a593Smuzhiyun 	if (use_rts || use_cts) {
778*4882a593Smuzhiyun 		u16 durid;
779*4882a593Smuzhiyun 		if ((mch & TXC_PREAMBLE_RTS_MAIN_SHORT) ==
780*4882a593Smuzhiyun 		    TXC_PREAMBLE_RTS_MAIN_SHORT)
781*4882a593Smuzhiyun 			rts_preamble_type = BRCMS_SHORT_PREAMBLE;
782*4882a593Smuzhiyun 
783*4882a593Smuzhiyun 		if ((mch & TXC_PREAMBLE_RTS_FB_SHORT) ==
784*4882a593Smuzhiyun 		     TXC_PREAMBLE_RTS_FB_SHORT)
785*4882a593Smuzhiyun 			rts_fbr_preamble_type = BRCMS_SHORT_PREAMBLE;
786*4882a593Smuzhiyun 
787*4882a593Smuzhiyun 		durid = brcms_c_compute_rtscts_dur(wlc, use_cts, rts_rspec,
788*4882a593Smuzhiyun 						   rspec, rts_preamble_type,
789*4882a593Smuzhiyun 						   preamble_type,
790*4882a593Smuzhiyun 						   session->ampdu_len, true);
791*4882a593Smuzhiyun 		rts->duration = cpu_to_le16(durid);
792*4882a593Smuzhiyun 		durid = brcms_c_compute_rtscts_dur(wlc, use_cts,
793*4882a593Smuzhiyun 						   rts_rspec_fallback,
794*4882a593Smuzhiyun 						   rspec_fallback,
795*4882a593Smuzhiyun 						   rts_fbr_preamble_type,
796*4882a593Smuzhiyun 						   fbr_preamble_type,
797*4882a593Smuzhiyun 						   session->ampdu_len, true);
798*4882a593Smuzhiyun 		txh->RTSDurFallback = cpu_to_le16(durid);
799*4882a593Smuzhiyun 		/* set TxFesTimeNormal */
800*4882a593Smuzhiyun 		txh->TxFesTimeNormal = rts->duration;
801*4882a593Smuzhiyun 		/* set fallback rate version of TxFesTimeNormal */
802*4882a593Smuzhiyun 		txh->TxFesTimeFallback = txh->RTSDurFallback;
803*4882a593Smuzhiyun 	}
804*4882a593Smuzhiyun 
805*4882a593Smuzhiyun 	/* set flag and plcp for fallback rate */
806*4882a593Smuzhiyun 	if (fbr) {
807*4882a593Smuzhiyun 		mch |= TXC_AMPDU_FBR;
808*4882a593Smuzhiyun 		txh->MacTxControlHigh = cpu_to_le16(mch);
809*4882a593Smuzhiyun 		BRCMS_SET_MIMO_PLCP_AMPDU(plcp);
810*4882a593Smuzhiyun 		BRCMS_SET_MIMO_PLCP_AMPDU(txh->FragPLCPFallback);
811*4882a593Smuzhiyun 	}
812*4882a593Smuzhiyun 
813*4882a593Smuzhiyun 	brcms_dbg_ht(wlc->hw->d11core, "wl%d: count %d ampdu_len %d\n",
814*4882a593Smuzhiyun 		     wlc->pub->unit, skb_queue_len(&session->skb_list),
815*4882a593Smuzhiyun 		     session->ampdu_len);
816*4882a593Smuzhiyun }
817*4882a593Smuzhiyun 
818*4882a593Smuzhiyun static void
brcms_c_ampdu_rate_status(struct brcms_c_info * wlc,struct ieee80211_tx_info * tx_info,struct tx_status * txs,u8 mcs)819*4882a593Smuzhiyun brcms_c_ampdu_rate_status(struct brcms_c_info *wlc,
820*4882a593Smuzhiyun 			  struct ieee80211_tx_info *tx_info,
821*4882a593Smuzhiyun 			  struct tx_status *txs, u8 mcs)
822*4882a593Smuzhiyun {
823*4882a593Smuzhiyun 	struct ieee80211_tx_rate *txrate = tx_info->status.rates;
824*4882a593Smuzhiyun 	int i;
825*4882a593Smuzhiyun 
826*4882a593Smuzhiyun 	/* clear the rest of the rates */
827*4882a593Smuzhiyun 	for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) {
828*4882a593Smuzhiyun 		txrate[i].idx = -1;
829*4882a593Smuzhiyun 		txrate[i].count = 0;
830*4882a593Smuzhiyun 	}
831*4882a593Smuzhiyun }
832*4882a593Smuzhiyun 
833*4882a593Smuzhiyun static void
brcms_c_ampdu_dotxstatus_complete(struct ampdu_info * ampdu,struct scb * scb,struct sk_buff * p,struct tx_status * txs,u32 s1,u32 s2)834*4882a593Smuzhiyun brcms_c_ampdu_dotxstatus_complete(struct ampdu_info *ampdu, struct scb *scb,
835*4882a593Smuzhiyun 			      struct sk_buff *p, struct tx_status *txs,
836*4882a593Smuzhiyun 			      u32 s1, u32 s2)
837*4882a593Smuzhiyun {
838*4882a593Smuzhiyun 	struct scb_ampdu *scb_ampdu;
839*4882a593Smuzhiyun 	struct brcms_c_info *wlc = ampdu->wlc;
840*4882a593Smuzhiyun 	struct scb_ampdu_tid_ini *ini;
841*4882a593Smuzhiyun 	u8 bitmap[8], queue, tid;
842*4882a593Smuzhiyun 	struct d11txh *txh;
843*4882a593Smuzhiyun 	u8 *plcp;
844*4882a593Smuzhiyun 	struct ieee80211_hdr *h;
845*4882a593Smuzhiyun 	u16 seq, start_seq = 0, bindex, index, mcl;
846*4882a593Smuzhiyun 	u8 mcs = 0;
847*4882a593Smuzhiyun 	bool ba_recd = false, ack_recd = false;
848*4882a593Smuzhiyun 	u8 suc_mpdu = 0, tot_mpdu = 0;
849*4882a593Smuzhiyun 	uint supr_status;
850*4882a593Smuzhiyun 	bool retry = true;
851*4882a593Smuzhiyun 	u16 mimoantsel = 0;
852*4882a593Smuzhiyun 	u8 retry_limit;
853*4882a593Smuzhiyun 	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(p);
854*4882a593Smuzhiyun 
855*4882a593Smuzhiyun #ifdef DEBUG
856*4882a593Smuzhiyun 	u8 hole[AMPDU_MAX_MPDU];
857*4882a593Smuzhiyun 	memset(hole, 0, sizeof(hole));
858*4882a593Smuzhiyun #endif
859*4882a593Smuzhiyun 
860*4882a593Smuzhiyun 	scb_ampdu = &scb->scb_ampdu;
861*4882a593Smuzhiyun 	tid = (u8) (p->priority);
862*4882a593Smuzhiyun 
863*4882a593Smuzhiyun 	ini = &scb_ampdu->ini[tid];
864*4882a593Smuzhiyun 	retry_limit = ampdu->retry_limit_tid[tid];
865*4882a593Smuzhiyun 	memset(bitmap, 0, sizeof(bitmap));
866*4882a593Smuzhiyun 	queue = txs->frameid & TXFID_QUEUE_MASK;
867*4882a593Smuzhiyun 	supr_status = txs->status & TX_STATUS_SUPR_MASK;
868*4882a593Smuzhiyun 
869*4882a593Smuzhiyun 	if (txs->status & TX_STATUS_ACK_RCV) {
870*4882a593Smuzhiyun 		WARN_ON(!(txs->status & TX_STATUS_INTERMEDIATE));
871*4882a593Smuzhiyun 		start_seq = txs->sequence >> SEQNUM_SHIFT;
872*4882a593Smuzhiyun 		bitmap[0] = (txs->status & TX_STATUS_BA_BMAP03_MASK) >>
873*4882a593Smuzhiyun 		    TX_STATUS_BA_BMAP03_SHIFT;
874*4882a593Smuzhiyun 
875*4882a593Smuzhiyun 		WARN_ON(s1 & TX_STATUS_INTERMEDIATE);
876*4882a593Smuzhiyun 		WARN_ON(!(s1 & TX_STATUS_AMPDU));
877*4882a593Smuzhiyun 
878*4882a593Smuzhiyun 		bitmap[0] |=
879*4882a593Smuzhiyun 		    (s1 & TX_STATUS_BA_BMAP47_MASK) <<
880*4882a593Smuzhiyun 		    TX_STATUS_BA_BMAP47_SHIFT;
881*4882a593Smuzhiyun 		bitmap[1] = (s1 >> 8) & 0xff;
882*4882a593Smuzhiyun 		bitmap[2] = (s1 >> 16) & 0xff;
883*4882a593Smuzhiyun 		bitmap[3] = (s1 >> 24) & 0xff;
884*4882a593Smuzhiyun 
885*4882a593Smuzhiyun 		bitmap[4] = s2 & 0xff;
886*4882a593Smuzhiyun 		bitmap[5] = (s2 >> 8) & 0xff;
887*4882a593Smuzhiyun 		bitmap[6] = (s2 >> 16) & 0xff;
888*4882a593Smuzhiyun 		bitmap[7] = (s2 >> 24) & 0xff;
889*4882a593Smuzhiyun 
890*4882a593Smuzhiyun 		ba_recd = true;
891*4882a593Smuzhiyun 	} else {
892*4882a593Smuzhiyun 		if (supr_status) {
893*4882a593Smuzhiyun 			if (supr_status == TX_STATUS_SUPR_BADCH) {
894*4882a593Smuzhiyun 				brcms_dbg_ht(wlc->hw->d11core,
895*4882a593Smuzhiyun 					  "%s: Pkt tx suppressed, illegal channel possibly %d\n",
896*4882a593Smuzhiyun 					  __func__, CHSPEC_CHANNEL(
897*4882a593Smuzhiyun 					  wlc->default_bss->chanspec));
898*4882a593Smuzhiyun 			} else {
899*4882a593Smuzhiyun 				if (supr_status != TX_STATUS_SUPR_FRAG)
900*4882a593Smuzhiyun 					brcms_err(wlc->hw->d11core,
901*4882a593Smuzhiyun 						  "%s: supr_status 0x%x\n",
902*4882a593Smuzhiyun 						  __func__, supr_status);
903*4882a593Smuzhiyun 			}
904*4882a593Smuzhiyun 			/* no need to retry for badch; will fail again */
905*4882a593Smuzhiyun 			if (supr_status == TX_STATUS_SUPR_BADCH ||
906*4882a593Smuzhiyun 			    supr_status == TX_STATUS_SUPR_EXPTIME) {
907*4882a593Smuzhiyun 				retry = false;
908*4882a593Smuzhiyun 			} else if (supr_status == TX_STATUS_SUPR_EXPTIME) {
909*4882a593Smuzhiyun 				/* TX underflow:
910*4882a593Smuzhiyun 				 *   try tuning pre-loading or ampdu size
911*4882a593Smuzhiyun 				 */
912*4882a593Smuzhiyun 			} else if (supr_status == TX_STATUS_SUPR_FRAG) {
913*4882a593Smuzhiyun 				/*
914*4882a593Smuzhiyun 				 * if there were underflows, but pre-loading
915*4882a593Smuzhiyun 				 * is not active, notify rate adaptation.
916*4882a593Smuzhiyun 				 */
917*4882a593Smuzhiyun 				brcms_c_ffpld_check_txfunfl(wlc, queue);
918*4882a593Smuzhiyun 			}
919*4882a593Smuzhiyun 		} else if (txs->phyerr) {
920*4882a593Smuzhiyun 			brcms_dbg_ht(wlc->hw->d11core,
921*4882a593Smuzhiyun 				     "%s: ampdu tx phy error (0x%x)\n",
922*4882a593Smuzhiyun 				     __func__, txs->phyerr);
923*4882a593Smuzhiyun 		}
924*4882a593Smuzhiyun 	}
925*4882a593Smuzhiyun 
926*4882a593Smuzhiyun 	/* loop through all pkts and retry if not acked */
927*4882a593Smuzhiyun 	while (p) {
928*4882a593Smuzhiyun 		tx_info = IEEE80211_SKB_CB(p);
929*4882a593Smuzhiyun 		txh = (struct d11txh *) p->data;
930*4882a593Smuzhiyun 		mcl = le16_to_cpu(txh->MacTxControlLow);
931*4882a593Smuzhiyun 		plcp = (u8 *) (txh + 1);
932*4882a593Smuzhiyun 		h = (struct ieee80211_hdr *)(plcp + D11_PHY_HDR_LEN);
933*4882a593Smuzhiyun 		seq = le16_to_cpu(h->seq_ctrl) >> SEQNUM_SHIFT;
934*4882a593Smuzhiyun 
935*4882a593Smuzhiyun 		trace_brcms_txdesc(&wlc->hw->d11core->dev, txh, sizeof(*txh));
936*4882a593Smuzhiyun 
937*4882a593Smuzhiyun 		if (tot_mpdu == 0) {
938*4882a593Smuzhiyun 			mcs = plcp[0] & MIMO_PLCP_MCS_MASK;
939*4882a593Smuzhiyun 			mimoantsel = le16_to_cpu(txh->ABI_MimoAntSel);
940*4882a593Smuzhiyun 		}
941*4882a593Smuzhiyun 
942*4882a593Smuzhiyun 		index = TX_SEQ_TO_INDEX(seq);
943*4882a593Smuzhiyun 		ack_recd = false;
944*4882a593Smuzhiyun 		if (ba_recd) {
945*4882a593Smuzhiyun 			bindex = MODSUB_POW2(seq, start_seq, SEQNUM_MAX);
946*4882a593Smuzhiyun 			brcms_dbg_ht(wlc->hw->d11core,
947*4882a593Smuzhiyun 				     "tid %d seq %d, start_seq %d, bindex %d set %d, index %d\n",
948*4882a593Smuzhiyun 				     tid, seq, start_seq, bindex,
949*4882a593Smuzhiyun 				     isset(bitmap, bindex), index);
950*4882a593Smuzhiyun 			/* if acked then clear bit and free packet */
951*4882a593Smuzhiyun 			if ((bindex < AMPDU_TX_BA_MAX_WSIZE)
952*4882a593Smuzhiyun 			    && isset(bitmap, bindex)) {
953*4882a593Smuzhiyun 				ini->txretry[index] = 0;
954*4882a593Smuzhiyun 
955*4882a593Smuzhiyun 				/*
956*4882a593Smuzhiyun 				 * ampdu_ack_len:
957*4882a593Smuzhiyun 				 *   number of acked aggregated frames
958*4882a593Smuzhiyun 				 */
959*4882a593Smuzhiyun 				/* ampdu_len: number of aggregated frames */
960*4882a593Smuzhiyun 				brcms_c_ampdu_rate_status(wlc, tx_info, txs,
961*4882a593Smuzhiyun 							  mcs);
962*4882a593Smuzhiyun 				tx_info->flags |= IEEE80211_TX_STAT_ACK;
963*4882a593Smuzhiyun 				tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
964*4882a593Smuzhiyun 				tx_info->status.ampdu_ack_len =
965*4882a593Smuzhiyun 					tx_info->status.ampdu_len = 1;
966*4882a593Smuzhiyun 
967*4882a593Smuzhiyun 				skb_pull(p, D11_PHY_HDR_LEN);
968*4882a593Smuzhiyun 				skb_pull(p, D11_TXH_LEN);
969*4882a593Smuzhiyun 
970*4882a593Smuzhiyun 				ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw,
971*4882a593Smuzhiyun 							    p);
972*4882a593Smuzhiyun 				ack_recd = true;
973*4882a593Smuzhiyun 				suc_mpdu++;
974*4882a593Smuzhiyun 			}
975*4882a593Smuzhiyun 		}
976*4882a593Smuzhiyun 		/* either retransmit or send bar if ack not recd */
977*4882a593Smuzhiyun 		if (!ack_recd) {
978*4882a593Smuzhiyun 			if (retry && (ini->txretry[index] < (int)retry_limit)) {
979*4882a593Smuzhiyun 				int ret;
980*4882a593Smuzhiyun 				ini->txretry[index]++;
981*4882a593Smuzhiyun 				ret = brcms_c_txfifo(wlc, queue, p);
982*4882a593Smuzhiyun 				/*
983*4882a593Smuzhiyun 				 * We shouldn't be out of space in the DMA
984*4882a593Smuzhiyun 				 * ring here since we're reinserting a frame
985*4882a593Smuzhiyun 				 * that was just pulled out.
986*4882a593Smuzhiyun 				 */
987*4882a593Smuzhiyun 				WARN_ONCE(ret, "queue %d out of txds\n", queue);
988*4882a593Smuzhiyun 			} else {
989*4882a593Smuzhiyun 				/* Retry timeout */
990*4882a593Smuzhiyun 				ieee80211_tx_info_clear_status(tx_info);
991*4882a593Smuzhiyun 				tx_info->status.ampdu_ack_len = 0;
992*4882a593Smuzhiyun 				tx_info->status.ampdu_len = 1;
993*4882a593Smuzhiyun 				tx_info->flags |=
994*4882a593Smuzhiyun 				    IEEE80211_TX_STAT_AMPDU_NO_BACK;
995*4882a593Smuzhiyun 				skb_pull(p, D11_PHY_HDR_LEN);
996*4882a593Smuzhiyun 				skb_pull(p, D11_TXH_LEN);
997*4882a593Smuzhiyun 				brcms_dbg_ht(wlc->hw->d11core,
998*4882a593Smuzhiyun 					     "BA Timeout, seq %d\n",
999*4882a593Smuzhiyun 					     seq);
1000*4882a593Smuzhiyun 				ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw,
1001*4882a593Smuzhiyun 							    p);
1002*4882a593Smuzhiyun 			}
1003*4882a593Smuzhiyun 		}
1004*4882a593Smuzhiyun 		tot_mpdu++;
1005*4882a593Smuzhiyun 
1006*4882a593Smuzhiyun 		/* break out if last packet of ampdu */
1007*4882a593Smuzhiyun 		if (((mcl & TXC_AMPDU_MASK) >> TXC_AMPDU_SHIFT) ==
1008*4882a593Smuzhiyun 		    TXC_AMPDU_LAST)
1009*4882a593Smuzhiyun 			break;
1010*4882a593Smuzhiyun 
1011*4882a593Smuzhiyun 		p = dma_getnexttxp(wlc->hw->di[queue], DMA_RANGE_TRANSMITTED);
1012*4882a593Smuzhiyun 	}
1013*4882a593Smuzhiyun 
1014*4882a593Smuzhiyun 	/* update rate state */
1015*4882a593Smuzhiyun 	brcms_c_antsel_antsel2id(wlc->asi, mimoantsel);
1016*4882a593Smuzhiyun }
1017*4882a593Smuzhiyun 
1018*4882a593Smuzhiyun void
brcms_c_ampdu_dotxstatus(struct ampdu_info * ampdu,struct scb * scb,struct sk_buff * p,struct tx_status * txs)1019*4882a593Smuzhiyun brcms_c_ampdu_dotxstatus(struct ampdu_info *ampdu, struct scb *scb,
1020*4882a593Smuzhiyun 		     struct sk_buff *p, struct tx_status *txs)
1021*4882a593Smuzhiyun {
1022*4882a593Smuzhiyun 	struct brcms_c_info *wlc = ampdu->wlc;
1023*4882a593Smuzhiyun 	u32 s1 = 0, s2 = 0;
1024*4882a593Smuzhiyun 
1025*4882a593Smuzhiyun 	/* BMAC_NOTE: For the split driver, second level txstatus comes later
1026*4882a593Smuzhiyun 	 * So if the ACK was received then wait for the second level else just
1027*4882a593Smuzhiyun 	 * call the first one
1028*4882a593Smuzhiyun 	 */
1029*4882a593Smuzhiyun 	if (txs->status & TX_STATUS_ACK_RCV) {
1030*4882a593Smuzhiyun 		u8 status_delay = 0;
1031*4882a593Smuzhiyun 
1032*4882a593Smuzhiyun 		/* wait till the next 8 bytes of txstatus is available */
1033*4882a593Smuzhiyun 		s1 = bcma_read32(wlc->hw->d11core, D11REGOFFS(frmtxstatus));
1034*4882a593Smuzhiyun 		while ((s1 & TXS_V) == 0) {
1035*4882a593Smuzhiyun 			udelay(1);
1036*4882a593Smuzhiyun 			status_delay++;
1037*4882a593Smuzhiyun 			if (status_delay > 10)
1038*4882a593Smuzhiyun 				return; /* error condition */
1039*4882a593Smuzhiyun 			s1 = bcma_read32(wlc->hw->d11core,
1040*4882a593Smuzhiyun 					 D11REGOFFS(frmtxstatus));
1041*4882a593Smuzhiyun 		}
1042*4882a593Smuzhiyun 
1043*4882a593Smuzhiyun 		s2 = bcma_read32(wlc->hw->d11core, D11REGOFFS(frmtxstatus2));
1044*4882a593Smuzhiyun 	}
1045*4882a593Smuzhiyun 
1046*4882a593Smuzhiyun 	if (scb) {
1047*4882a593Smuzhiyun 		brcms_c_ampdu_dotxstatus_complete(ampdu, scb, p, txs, s1, s2);
1048*4882a593Smuzhiyun 	} else {
1049*4882a593Smuzhiyun 		/* loop through all pkts and free */
1050*4882a593Smuzhiyun 		u8 queue = txs->frameid & TXFID_QUEUE_MASK;
1051*4882a593Smuzhiyun 		struct d11txh *txh;
1052*4882a593Smuzhiyun 		u16 mcl;
1053*4882a593Smuzhiyun 		while (p) {
1054*4882a593Smuzhiyun 			txh = (struct d11txh *) p->data;
1055*4882a593Smuzhiyun 			trace_brcms_txdesc(&wlc->hw->d11core->dev, txh,
1056*4882a593Smuzhiyun 					   sizeof(*txh));
1057*4882a593Smuzhiyun 			mcl = le16_to_cpu(txh->MacTxControlLow);
1058*4882a593Smuzhiyun 			brcmu_pkt_buf_free_skb(p);
1059*4882a593Smuzhiyun 			/* break out if last packet of ampdu */
1060*4882a593Smuzhiyun 			if (((mcl & TXC_AMPDU_MASK) >> TXC_AMPDU_SHIFT) ==
1061*4882a593Smuzhiyun 			    TXC_AMPDU_LAST)
1062*4882a593Smuzhiyun 				break;
1063*4882a593Smuzhiyun 			p = dma_getnexttxp(wlc->hw->di[queue],
1064*4882a593Smuzhiyun 					   DMA_RANGE_TRANSMITTED);
1065*4882a593Smuzhiyun 		}
1066*4882a593Smuzhiyun 	}
1067*4882a593Smuzhiyun }
1068*4882a593Smuzhiyun 
brcms_c_ampdu_macaddr_upd(struct brcms_c_info * wlc)1069*4882a593Smuzhiyun void brcms_c_ampdu_macaddr_upd(struct brcms_c_info *wlc)
1070*4882a593Smuzhiyun {
1071*4882a593Smuzhiyun 	char template[T_RAM_ACCESS_SZ * 2];
1072*4882a593Smuzhiyun 
1073*4882a593Smuzhiyun 	/* driver needs to write the ta in the template; ta is at offset 16 */
1074*4882a593Smuzhiyun 	memset(template, 0, sizeof(template));
1075*4882a593Smuzhiyun 	memcpy(template, wlc->pub->cur_etheraddr, ETH_ALEN);
1076*4882a593Smuzhiyun 	brcms_b_write_template_ram(wlc->hw, (T_BA_TPL_BASE + 16),
1077*4882a593Smuzhiyun 				  (T_RAM_ACCESS_SZ * 2),
1078*4882a593Smuzhiyun 				  template);
1079*4882a593Smuzhiyun }
1080*4882a593Smuzhiyun 
brcms_c_aggregatable(struct brcms_c_info * wlc,u8 tid)1081*4882a593Smuzhiyun bool brcms_c_aggregatable(struct brcms_c_info *wlc, u8 tid)
1082*4882a593Smuzhiyun {
1083*4882a593Smuzhiyun 	return wlc->ampdu->ini_enable[tid];
1084*4882a593Smuzhiyun }
1085*4882a593Smuzhiyun 
brcms_c_ampdu_shm_upd(struct ampdu_info * ampdu)1086*4882a593Smuzhiyun void brcms_c_ampdu_shm_upd(struct ampdu_info *ampdu)
1087*4882a593Smuzhiyun {
1088*4882a593Smuzhiyun 	struct brcms_c_info *wlc = ampdu->wlc;
1089*4882a593Smuzhiyun 
1090*4882a593Smuzhiyun 	/*
1091*4882a593Smuzhiyun 	 * Extend ucode internal watchdog timer to
1092*4882a593Smuzhiyun 	 * match larger received frames
1093*4882a593Smuzhiyun 	 */
1094*4882a593Smuzhiyun 	if ((ampdu->rx_factor & IEEE80211_HT_AMPDU_PARM_FACTOR) ==
1095*4882a593Smuzhiyun 	    IEEE80211_HT_MAX_AMPDU_64K) {
1096*4882a593Smuzhiyun 		brcms_b_write_shm(wlc->hw, M_MIMO_MAXSYM, MIMO_MAXSYM_MAX);
1097*4882a593Smuzhiyun 		brcms_b_write_shm(wlc->hw, M_WATCHDOG_8TU, WATCHDOG_8TU_MAX);
1098*4882a593Smuzhiyun 	} else {
1099*4882a593Smuzhiyun 		brcms_b_write_shm(wlc->hw, M_MIMO_MAXSYM, MIMO_MAXSYM_DEF);
1100*4882a593Smuzhiyun 		brcms_b_write_shm(wlc->hw, M_WATCHDOG_8TU, WATCHDOG_8TU_DEF);
1101*4882a593Smuzhiyun 	}
1102*4882a593Smuzhiyun }
1103*4882a593Smuzhiyun 
1104*4882a593Smuzhiyun /*
1105*4882a593Smuzhiyun  * callback function that helps invalidating ampdu packets in a DMA queue
1106*4882a593Smuzhiyun  */
dma_cb_fn_ampdu(void * txi,void * arg_a)1107*4882a593Smuzhiyun static void dma_cb_fn_ampdu(void *txi, void *arg_a)
1108*4882a593Smuzhiyun {
1109*4882a593Smuzhiyun 	struct ieee80211_sta *sta = arg_a;
1110*4882a593Smuzhiyun 	struct ieee80211_tx_info *tx_info = (struct ieee80211_tx_info *)txi;
1111*4882a593Smuzhiyun 
1112*4882a593Smuzhiyun 	if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) &&
1113*4882a593Smuzhiyun 	    (tx_info->rate_driver_data[0] == sta || sta == NULL))
1114*4882a593Smuzhiyun 		tx_info->rate_driver_data[0] = NULL;
1115*4882a593Smuzhiyun }
1116*4882a593Smuzhiyun 
1117*4882a593Smuzhiyun /*
1118*4882a593Smuzhiyun  * When a remote party is no longer available for ampdu communication, any
1119*4882a593Smuzhiyun  * pending tx ampdu packets in the driver have to be flushed.
1120*4882a593Smuzhiyun  */
brcms_c_ampdu_flush(struct brcms_c_info * wlc,struct ieee80211_sta * sta,u16 tid)1121*4882a593Smuzhiyun void brcms_c_ampdu_flush(struct brcms_c_info *wlc,
1122*4882a593Smuzhiyun 		     struct ieee80211_sta *sta, u16 tid)
1123*4882a593Smuzhiyun {
1124*4882a593Smuzhiyun 	brcms_c_inval_dma_pkts(wlc->hw, sta, dma_cb_fn_ampdu);
1125*4882a593Smuzhiyun }
1126