1*4882a593Smuzhiyun // SPDX-License-Identifier: ISC 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2014 Broadcom Corporation 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef BRCMF_CHIP_H 6*4882a593Smuzhiyun #define BRCMF_CHIP_H 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <linux/types.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define CORE_CC_REG(base, field) \ 11*4882a593Smuzhiyun (base + offsetof(struct chipcregs, field)) 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /** 14*4882a593Smuzhiyun * struct brcmf_chip - chip level information. 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * @chip: chip identifier. 17*4882a593Smuzhiyun * @chiprev: chip revision. 18*4882a593Smuzhiyun * @cc_caps: chipcommon core capabilities. 19*4882a593Smuzhiyun * @cc_caps_ext: chipcommon core extended capabilities. 20*4882a593Smuzhiyun * @pmucaps: PMU capabilities. 21*4882a593Smuzhiyun * @pmurev: PMU revision. 22*4882a593Smuzhiyun * @rambase: RAM base address (only applicable for ARM CR4 chips). 23*4882a593Smuzhiyun * @ramsize: amount of RAM on chip including retention. 24*4882a593Smuzhiyun * @srsize: amount of retention RAM on chip. 25*4882a593Smuzhiyun * @name: string representation of the chip identifier. 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun struct brcmf_chip { 28*4882a593Smuzhiyun u32 chip; 29*4882a593Smuzhiyun u32 chiprev; 30*4882a593Smuzhiyun u32 cc_caps; 31*4882a593Smuzhiyun u32 cc_caps_ext; 32*4882a593Smuzhiyun u32 pmucaps; 33*4882a593Smuzhiyun u32 pmurev; 34*4882a593Smuzhiyun u32 rambase; 35*4882a593Smuzhiyun u32 ramsize; 36*4882a593Smuzhiyun u32 srsize; 37*4882a593Smuzhiyun char name[12]; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /** 41*4882a593Smuzhiyun * struct brcmf_core - core related information. 42*4882a593Smuzhiyun * 43*4882a593Smuzhiyun * @id: core identifier. 44*4882a593Smuzhiyun * @rev: core revision. 45*4882a593Smuzhiyun * @base: base address of core register space. 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun struct brcmf_core { 48*4882a593Smuzhiyun u16 id; 49*4882a593Smuzhiyun u16 rev; 50*4882a593Smuzhiyun u32 base; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /** 54*4882a593Smuzhiyun * struct brcmf_buscore_ops - buscore specific callbacks. 55*4882a593Smuzhiyun * 56*4882a593Smuzhiyun * @read32: read 32-bit value over bus. 57*4882a593Smuzhiyun * @write32: write 32-bit value over bus. 58*4882a593Smuzhiyun * @prepare: prepare bus for core configuration. 59*4882a593Smuzhiyun * @setup: bus-specific core setup. 60*4882a593Smuzhiyun * @active: chip becomes active. 61*4882a593Smuzhiyun * The callback should use the provided @rstvec when non-zero. 62*4882a593Smuzhiyun */ 63*4882a593Smuzhiyun struct brcmf_buscore_ops { 64*4882a593Smuzhiyun u32 (*read32)(void *ctx, u32 addr); 65*4882a593Smuzhiyun void (*write32)(void *ctx, u32 addr, u32 value); 66*4882a593Smuzhiyun int (*prepare)(void *ctx); 67*4882a593Smuzhiyun int (*reset)(void *ctx, struct brcmf_chip *chip); 68*4882a593Smuzhiyun int (*setup)(void *ctx, struct brcmf_chip *chip); 69*4882a593Smuzhiyun void (*activate)(void *ctx, struct brcmf_chip *chip, u32 rstvec); 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun int brcmf_chip_get_raminfo(struct brcmf_chip *pub); 73*4882a593Smuzhiyun struct brcmf_chip *brcmf_chip_attach(void *ctx, 74*4882a593Smuzhiyun const struct brcmf_buscore_ops *ops); 75*4882a593Smuzhiyun void brcmf_chip_detach(struct brcmf_chip *chip); 76*4882a593Smuzhiyun struct brcmf_core *brcmf_chip_get_core(struct brcmf_chip *chip, u16 coreid); 77*4882a593Smuzhiyun struct brcmf_core *brcmf_chip_get_d11core(struct brcmf_chip *pub, u8 unit); 78*4882a593Smuzhiyun struct brcmf_core *brcmf_chip_get_chipcommon(struct brcmf_chip *chip); 79*4882a593Smuzhiyun struct brcmf_core *brcmf_chip_get_pmu(struct brcmf_chip *pub); 80*4882a593Smuzhiyun bool brcmf_chip_iscoreup(struct brcmf_core *core); 81*4882a593Smuzhiyun void brcmf_chip_coredisable(struct brcmf_core *core, u32 prereset, u32 reset); 82*4882a593Smuzhiyun void brcmf_chip_resetcore(struct brcmf_core *core, u32 prereset, u32 reset, 83*4882a593Smuzhiyun u32 postreset); 84*4882a593Smuzhiyun void brcmf_chip_set_passive(struct brcmf_chip *ci); 85*4882a593Smuzhiyun bool brcmf_chip_set_active(struct brcmf_chip *ci, u32 rstvec); 86*4882a593Smuzhiyun bool brcmf_chip_sr_capable(struct brcmf_chip *pub); 87*4882a593Smuzhiyun char *brcmf_chip_name(u32 chipid, u32 chiprev, char *buf, uint len); 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #endif /* BRCMF_AXIDMP_H */ 90