xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/broadcom/b43legacy/xmit.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #ifndef B43legacy_XMIT_H_
3*4882a593Smuzhiyun #define B43legacy_XMIT_H_
4*4882a593Smuzhiyun 
5*4882a593Smuzhiyun #include "main.h"
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #define _b43legacy_declare_plcp_hdr(size)	\
9*4882a593Smuzhiyun 	struct b43legacy_plcp_hdr##size {	\
10*4882a593Smuzhiyun 		union {				\
11*4882a593Smuzhiyun 			__le32 data;		\
12*4882a593Smuzhiyun 			__u8 raw[size];		\
13*4882a593Smuzhiyun 		} __packed;	\
14*4882a593Smuzhiyun 	} __packed
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun /* struct b43legacy_plcp_hdr4 */
17*4882a593Smuzhiyun _b43legacy_declare_plcp_hdr(4);
18*4882a593Smuzhiyun /* struct b43legacy_plcp_hdr6 */
19*4882a593Smuzhiyun _b43legacy_declare_plcp_hdr(6);
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #undef _b43legacy_declare_plcp_hdr
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun /* TX header for v3 firmware */
25*4882a593Smuzhiyun struct b43legacy_txhdr_fw3 {
26*4882a593Smuzhiyun 	__le32 mac_ctl;				/* MAC TX control */
27*4882a593Smuzhiyun 	__le16 mac_frame_ctl;			/* Copy of the FrameControl */
28*4882a593Smuzhiyun 	__le16 tx_fes_time_norm;		/* TX FES Time Normal */
29*4882a593Smuzhiyun 	__le16 phy_ctl;				/* PHY TX control */
30*4882a593Smuzhiyun 	__u8 iv[16];				/* Encryption IV */
31*4882a593Smuzhiyun 	__u8 tx_receiver[6];			/* TX Frame Receiver address */
32*4882a593Smuzhiyun 	__le16 tx_fes_time_fb;			/* TX FES Time Fallback */
33*4882a593Smuzhiyun 	struct b43legacy_plcp_hdr4 rts_plcp_fb;	/* RTS fallback PLCP */
34*4882a593Smuzhiyun 	__le16 rts_dur_fb;			/* RTS fallback duration */
35*4882a593Smuzhiyun 	struct b43legacy_plcp_hdr4 plcp_fb;	/* Fallback PLCP */
36*4882a593Smuzhiyun 	__le16 dur_fb;				/* Fallback duration */
37*4882a593Smuzhiyun 	PAD_BYTES(2);
38*4882a593Smuzhiyun 	__le16 cookie;
39*4882a593Smuzhiyun 	__le16 unknown_scb_stuff;
40*4882a593Smuzhiyun 	struct b43legacy_plcp_hdr6 rts_plcp;	/* RTS PLCP */
41*4882a593Smuzhiyun 	__u8 rts_frame[18];			/* The RTS frame (if used) */
42*4882a593Smuzhiyun 	struct b43legacy_plcp_hdr6 plcp;
43*4882a593Smuzhiyun } __packed;
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun /* MAC TX control */
46*4882a593Smuzhiyun #define B43legacy_TX4_MAC_KEYIDX	0x0FF00000 /* Security key index */
47*4882a593Smuzhiyun #define B43legacy_TX4_MAC_KEYIDX_SHIFT	20
48*4882a593Smuzhiyun #define B43legacy_TX4_MAC_KEYALG	0x00070000 /* Security key algorithm */
49*4882a593Smuzhiyun #define B43legacy_TX4_MAC_KEYALG_SHIFT	16
50*4882a593Smuzhiyun #define B43legacy_TX4_MAC_LIFETIME	0x00001000
51*4882a593Smuzhiyun #define B43legacy_TX4_MAC_FRAMEBURST	0x00000800
52*4882a593Smuzhiyun #define B43legacy_TX4_MAC_SENDCTS	0x00000400
53*4882a593Smuzhiyun #define B43legacy_TX4_MAC_AMPDU		0x00000300
54*4882a593Smuzhiyun #define B43legacy_TX4_MAC_AMPDU_SHIFT	8
55*4882a593Smuzhiyun #define B43legacy_TX4_MAC_CTSFALLBACKOFDM	0x00000200
56*4882a593Smuzhiyun #define B43legacy_TX4_MAC_FALLBACKOFDM	0x00000100
57*4882a593Smuzhiyun #define B43legacy_TX4_MAC_5GHZ		0x00000080
58*4882a593Smuzhiyun #define B43legacy_TX4_MAC_IGNPMQ	0x00000020
59*4882a593Smuzhiyun #define B43legacy_TX4_MAC_HWSEQ		0x00000010 /* Use Hardware Seq No */
60*4882a593Smuzhiyun #define B43legacy_TX4_MAC_STMSDU	0x00000008 /* Start MSDU */
61*4882a593Smuzhiyun #define B43legacy_TX4_MAC_SENDRTS	0x00000004
62*4882a593Smuzhiyun #define B43legacy_TX4_MAC_LONGFRAME	0x00000002
63*4882a593Smuzhiyun #define B43legacy_TX4_MAC_ACK		0x00000001
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun /* Extra Frame Types */
66*4882a593Smuzhiyun #define B43legacy_TX4_EFT_FBOFDM	0x0001 /* Data frame fb rate type */
67*4882a593Smuzhiyun #define B43legacy_TX4_EFT_RTSOFDM	0x0004 /* RTS/CTS rate type */
68*4882a593Smuzhiyun #define B43legacy_TX4_EFT_RTSFBOFDM	0x0010 /* RTS/CTS fallback rate type */
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun /* PHY TX control word */
71*4882a593Smuzhiyun #define B43legacy_TX4_PHY_ENC		0x0003 /* Data frame encoding */
72*4882a593Smuzhiyun #define B43legacy_TX4_PHY_ENC_CCK	0x0000 /* CCK */
73*4882a593Smuzhiyun #define B43legacy_TX4_PHY_ENC_OFDM	0x0001 /* Data frame rate type */
74*4882a593Smuzhiyun #define B43legacy_TX4_PHY_SHORTPRMBL	0x0010 /* Use short preamble */
75*4882a593Smuzhiyun #define B43legacy_TX4_PHY_ANT		0x03C0 /* Antenna selection */
76*4882a593Smuzhiyun #define  B43legacy_TX4_PHY_ANT0		0x0000 /* Use antenna 0 */
77*4882a593Smuzhiyun #define  B43legacy_TX4_PHY_ANT1		0x0100 /* Use antenna 1 */
78*4882a593Smuzhiyun #define  B43legacy_TX4_PHY_ANTLAST	0x0300 /* Use last used antenna */
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun int b43legacy_generate_txhdr(struct b43legacy_wldev *dev,
83*4882a593Smuzhiyun 			      u8 *txhdr,
84*4882a593Smuzhiyun 			      const unsigned char *fragment_data,
85*4882a593Smuzhiyun 			      unsigned int fragment_len,
86*4882a593Smuzhiyun 			      struct ieee80211_tx_info *info,
87*4882a593Smuzhiyun 			      u16 cookie);
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun /* Transmit Status */
91*4882a593Smuzhiyun struct b43legacy_txstatus {
92*4882a593Smuzhiyun 	u16 cookie;	/* The cookie from the txhdr */
93*4882a593Smuzhiyun 	u16 seq;	/* Sequence number */
94*4882a593Smuzhiyun 	u8 phy_stat;	/* PHY TX status */
95*4882a593Smuzhiyun 	u8 frame_count;	/* Frame transmit count */
96*4882a593Smuzhiyun 	u8 rts_count;	/* RTS transmit count */
97*4882a593Smuzhiyun 	u8 supp_reason;	/* Suppression reason */
98*4882a593Smuzhiyun 	/* flags */
99*4882a593Smuzhiyun 	u8 pm_indicated;/* PM mode indicated to AP */
100*4882a593Smuzhiyun 	u8 intermediate;/* Intermediate status notification */
101*4882a593Smuzhiyun 	u8 for_ampdu;	/* Status is for an AMPDU (afterburner) */
102*4882a593Smuzhiyun 	u8 acked;	/* Wireless ACK received */
103*4882a593Smuzhiyun };
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun /* txstatus supp_reason values */
106*4882a593Smuzhiyun enum {
107*4882a593Smuzhiyun 	B43legacy_TXST_SUPP_NONE,	/* Not suppressed */
108*4882a593Smuzhiyun 	B43legacy_TXST_SUPP_PMQ,	/* Suppressed due to PMQ entry */
109*4882a593Smuzhiyun 	B43legacy_TXST_SUPP_FLUSH,	/* Suppressed due to flush request */
110*4882a593Smuzhiyun 	B43legacy_TXST_SUPP_PREV,	/* Previous fragment failed */
111*4882a593Smuzhiyun 	B43legacy_TXST_SUPP_CHAN,	/* Channel mismatch */
112*4882a593Smuzhiyun 	B43legacy_TXST_SUPP_LIFE,	/* Lifetime expired */
113*4882a593Smuzhiyun 	B43legacy_TXST_SUPP_UNDER,	/* Buffer underflow */
114*4882a593Smuzhiyun 	B43legacy_TXST_SUPP_ABNACK,	/* Afterburner NACK */
115*4882a593Smuzhiyun };
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun /* Transmit Status as received through DMA/PIO on old chips */
118*4882a593Smuzhiyun struct b43legacy_hwtxstatus {
119*4882a593Smuzhiyun 	PAD_BYTES(4);
120*4882a593Smuzhiyun 	__le16 cookie;
121*4882a593Smuzhiyun 	u8 flags;
122*4882a593Smuzhiyun 	u8 count;
123*4882a593Smuzhiyun 	PAD_BYTES(2);
124*4882a593Smuzhiyun 	__le16 seq;
125*4882a593Smuzhiyun 	u8 phy_stat;
126*4882a593Smuzhiyun 	PAD_BYTES(1);
127*4882a593Smuzhiyun } __packed;
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun /* Receive header for v3 firmware. */
131*4882a593Smuzhiyun struct b43legacy_rxhdr_fw3 {
132*4882a593Smuzhiyun 	__le16 frame_len;	/* Frame length */
133*4882a593Smuzhiyun 	PAD_BYTES(2);
134*4882a593Smuzhiyun 	__le16 phy_status0;	/* PHY RX Status 0 */
135*4882a593Smuzhiyun 	__u8 jssi;		/* PHY RX Status 1: JSSI */
136*4882a593Smuzhiyun 	__u8 sig_qual;		/* PHY RX Status 1: Signal Quality */
137*4882a593Smuzhiyun 	PAD_BYTES(2);		/* PHY RX Status 2 */
138*4882a593Smuzhiyun 	__le16 phy_status3;	/* PHY RX Status 3 */
139*4882a593Smuzhiyun 	__le16 mac_status;	/* MAC RX status */
140*4882a593Smuzhiyun 	__le16 mac_time;
141*4882a593Smuzhiyun 	__le16 channel;
142*4882a593Smuzhiyun } __packed;
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun /* PHY RX Status 0 */
146*4882a593Smuzhiyun #define B43legacy_RX_PHYST0_GAINCTL	0x4000 /* Gain Control */
147*4882a593Smuzhiyun #define B43legacy_RX_PHYST0_PLCPHCF	0x0200
148*4882a593Smuzhiyun #define B43legacy_RX_PHYST0_PLCPFV	0x0100
149*4882a593Smuzhiyun #define B43legacy_RX_PHYST0_SHORTPRMBL	0x0080 /* Recvd with Short Preamble */
150*4882a593Smuzhiyun #define B43legacy_RX_PHYST0_LCRS	0x0040
151*4882a593Smuzhiyun #define B43legacy_RX_PHYST0_ANT		0x0020 /* Antenna */
152*4882a593Smuzhiyun #define B43legacy_RX_PHYST0_UNSRATE	0x0010
153*4882a593Smuzhiyun #define B43legacy_RX_PHYST0_CLIP	0x000C
154*4882a593Smuzhiyun #define B43legacy_RX_PHYST0_CLIP_SHIFT	2
155*4882a593Smuzhiyun #define B43legacy_RX_PHYST0_FTYPE	0x0003 /* Frame type */
156*4882a593Smuzhiyun #define  B43legacy_RX_PHYST0_CCK	0x0000 /* Frame type: CCK */
157*4882a593Smuzhiyun #define  B43legacy_RX_PHYST0_OFDM	0x0001 /* Frame type: OFDM */
158*4882a593Smuzhiyun #define  B43legacy_RX_PHYST0_PRE_N	0x0002 /* Pre-standard N-PHY frame */
159*4882a593Smuzhiyun #define  B43legacy_RX_PHYST0_STD_N	0x0003 /* Standard N-PHY frame */
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun /* PHY RX Status 2 */
162*4882a593Smuzhiyun #define B43legacy_RX_PHYST2_LNAG	0xC000 /* LNA Gain */
163*4882a593Smuzhiyun #define B43legacy_RX_PHYST2_LNAG_SHIFT	14
164*4882a593Smuzhiyun #define B43legacy_RX_PHYST2_PNAG	0x3C00 /* PNA Gain */
165*4882a593Smuzhiyun #define B43legacy_RX_PHYST2_PNAG_SHIFT	10
166*4882a593Smuzhiyun #define B43legacy_RX_PHYST2_FOFF	0x03FF /* F offset */
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun /* PHY RX Status 3 */
169*4882a593Smuzhiyun #define B43legacy_RX_PHYST3_DIGG	0x1800 /* DIG Gain */
170*4882a593Smuzhiyun #define B43legacy_RX_PHYST3_DIGG_SHIFT	11
171*4882a593Smuzhiyun #define B43legacy_RX_PHYST3_TRSTATE	0x0400 /* TR state */
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun /* MAC RX Status */
174*4882a593Smuzhiyun #define B43legacy_RX_MAC_BEACONSENT	0x00008000 /* Beacon send flag */
175*4882a593Smuzhiyun #define B43legacy_RX_MAC_KEYIDX		0x000007E0 /* Key index */
176*4882a593Smuzhiyun #define B43legacy_RX_MAC_KEYIDX_SHIFT	5
177*4882a593Smuzhiyun #define B43legacy_RX_MAC_DECERR		0x00000010 /* Decrypt error */
178*4882a593Smuzhiyun #define B43legacy_RX_MAC_DEC		0x00000008 /* Decryption attempted */
179*4882a593Smuzhiyun #define B43legacy_RX_MAC_PADDING	0x00000004 /* Pad bytes present */
180*4882a593Smuzhiyun #define B43legacy_RX_MAC_RESP		0x00000002 /* Response frame xmitted */
181*4882a593Smuzhiyun #define B43legacy_RX_MAC_FCSERR		0x00000001 /* FCS error */
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun /* RX channel */
184*4882a593Smuzhiyun #define B43legacy_RX_CHAN_GAIN		0xFC00 /* Gain */
185*4882a593Smuzhiyun #define B43legacy_RX_CHAN_GAIN_SHIFT	10
186*4882a593Smuzhiyun #define B43legacy_RX_CHAN_ID		0x03FC /* Channel ID */
187*4882a593Smuzhiyun #define B43legacy_RX_CHAN_ID_SHIFT	2
188*4882a593Smuzhiyun #define B43legacy_RX_CHAN_PHYTYPE	0x0003 /* PHY type */
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun u8 b43legacy_plcp_get_ratecode_cck(const u8 bitrate);
193*4882a593Smuzhiyun u8 b43legacy_plcp_get_ratecode_ofdm(const u8 bitrate);
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun void b43legacy_generate_plcp_hdr(struct b43legacy_plcp_hdr4 *plcp,
196*4882a593Smuzhiyun 			       const u16 octets, const u8 bitrate);
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun void b43legacy_rx(struct b43legacy_wldev *dev,
199*4882a593Smuzhiyun 		struct sk_buff *skb,
200*4882a593Smuzhiyun 		const void *_rxhdr);
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun void b43legacy_handle_txstatus(struct b43legacy_wldev *dev,
203*4882a593Smuzhiyun 			       const struct b43legacy_txstatus *status);
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun void b43legacy_handle_hwtxstatus(struct b43legacy_wldev *dev,
206*4882a593Smuzhiyun 				 const struct b43legacy_hwtxstatus *hw);
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun void b43legacy_tx_suspend(struct b43legacy_wldev *dev);
209*4882a593Smuzhiyun void b43legacy_tx_resume(struct b43legacy_wldev *dev);
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun #define B43legacy_NR_QOSPARMS	22
213*4882a593Smuzhiyun enum {
214*4882a593Smuzhiyun 	B43legacy_QOSPARM_TXOP = 0,
215*4882a593Smuzhiyun 	B43legacy_QOSPARM_CWMIN,
216*4882a593Smuzhiyun 	B43legacy_QOSPARM_CWMAX,
217*4882a593Smuzhiyun 	B43legacy_QOSPARM_CWCUR,
218*4882a593Smuzhiyun 	B43legacy_QOSPARM_AIFS,
219*4882a593Smuzhiyun 	B43legacy_QOSPARM_BSLOTS,
220*4882a593Smuzhiyun 	B43legacy_QOSPARM_REGGAP,
221*4882a593Smuzhiyun 	B43legacy_QOSPARM_STATUS,
222*4882a593Smuzhiyun };
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun void b43legacy_qos_init(struct b43legacy_wldev *dev);
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun /* Helper functions for converting the key-table index from "firmware-format"
228*4882a593Smuzhiyun  * to "raw-format" and back. The firmware API changed for this at some revision.
229*4882a593Smuzhiyun  * We need to account for that here. */
230*4882a593Smuzhiyun static inline
b43legacy_new_kidx_api(struct b43legacy_wldev * dev)231*4882a593Smuzhiyun int b43legacy_new_kidx_api(struct b43legacy_wldev *dev)
232*4882a593Smuzhiyun {
233*4882a593Smuzhiyun 	/* FIXME: Not sure the change was at rev 351 */
234*4882a593Smuzhiyun 	return (dev->fw.rev >= 351);
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun static inline
b43legacy_kidx_to_fw(struct b43legacy_wldev * dev,u8 raw_kidx)237*4882a593Smuzhiyun u8 b43legacy_kidx_to_fw(struct b43legacy_wldev *dev, u8 raw_kidx)
238*4882a593Smuzhiyun {
239*4882a593Smuzhiyun 	u8 firmware_kidx;
240*4882a593Smuzhiyun 	if (b43legacy_new_kidx_api(dev))
241*4882a593Smuzhiyun 		firmware_kidx = raw_kidx;
242*4882a593Smuzhiyun 	else {
243*4882a593Smuzhiyun 		if (raw_kidx >= 4) /* Is per STA key? */
244*4882a593Smuzhiyun 			firmware_kidx = raw_kidx - 4;
245*4882a593Smuzhiyun 		else
246*4882a593Smuzhiyun 			firmware_kidx = raw_kidx; /* TX default key */
247*4882a593Smuzhiyun 	}
248*4882a593Smuzhiyun 	return firmware_kidx;
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun static inline
b43legacy_kidx_to_raw(struct b43legacy_wldev * dev,u8 firmware_kidx)251*4882a593Smuzhiyun u8 b43legacy_kidx_to_raw(struct b43legacy_wldev *dev, u8 firmware_kidx)
252*4882a593Smuzhiyun {
253*4882a593Smuzhiyun 	u8 raw_kidx;
254*4882a593Smuzhiyun 	if (b43legacy_new_kidx_api(dev))
255*4882a593Smuzhiyun 		raw_kidx = firmware_kidx;
256*4882a593Smuzhiyun 	else
257*4882a593Smuzhiyun 		/* RX default keys or per STA keys */
258*4882a593Smuzhiyun 		raw_kidx = firmware_kidx + 4;
259*4882a593Smuzhiyun 	return raw_kidx;
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun #endif /* B43legacy_XMIT_H_ */
263