xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/broadcom/b43legacy/phy.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun 
4*4882a593Smuzhiyun   Broadcom B43legacy wireless driver
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
7*4882a593Smuzhiyun 		     Stefano Brivio <stefano.brivio@polimi.it>
8*4882a593Smuzhiyun 		     Michael Buesch <m@bues.ch>
9*4882a593Smuzhiyun 		     Danny van Dyk <kugelfang@gentoo.org>
10*4882a593Smuzhiyun 		     Andreas Jaggi <andreas.jaggi@waterwave.ch>
11*4882a593Smuzhiyun   Copyright (c) 2007 Larry Finger <Larry.Finger@lwfinger.net>
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun   Some parts of the code in this file are derived from the ipw2200
14*4882a593Smuzhiyun   driver  Copyright(c) 2003 - 2004 Intel Corporation.
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun */
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #ifndef B43legacy_PHY_H_
20*4882a593Smuzhiyun #define B43legacy_PHY_H_
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #include <linux/types.h>
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun enum {
25*4882a593Smuzhiyun 	B43legacy_ANTENNA0,	  /* Antenna 0 */
26*4882a593Smuzhiyun 	B43legacy_ANTENNA1,	  /* Antenna 0 */
27*4882a593Smuzhiyun 	B43legacy_ANTENNA_AUTO1,  /* Automatic, starting with antenna 1 */
28*4882a593Smuzhiyun 	B43legacy_ANTENNA_AUTO0,  /* Automatic, starting with antenna 0 */
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun 	B43legacy_ANTENNA_AUTO	= B43legacy_ANTENNA_AUTO0,
31*4882a593Smuzhiyun 	B43legacy_ANTENNA_DEFAULT = B43legacy_ANTENNA_AUTO,
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun enum {
35*4882a593Smuzhiyun 	B43legacy_INTERFMODE_NONE,
36*4882a593Smuzhiyun 	B43legacy_INTERFMODE_NONWLAN,
37*4882a593Smuzhiyun 	B43legacy_INTERFMODE_MANUALWLAN,
38*4882a593Smuzhiyun 	B43legacy_INTERFMODE_AUTOWLAN,
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun /*** PHY Registers ***/
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun /* Routing */
44*4882a593Smuzhiyun #define B43legacy_PHYROUTE_OFDM_GPHY	0x400
45*4882a593Smuzhiyun #define B43legacy_PHYROUTE_EXT_GPHY	0x800
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun /* Base registers. */
48*4882a593Smuzhiyun #define B43legacy_PHY_BASE(reg)	(reg)
49*4882a593Smuzhiyun /* OFDM (A) registers of a G-PHY */
50*4882a593Smuzhiyun #define B43legacy_PHY_OFDM(reg)	((reg) | B43legacy_PHYROUTE_OFDM_GPHY)
51*4882a593Smuzhiyun /* Extended G-PHY registers */
52*4882a593Smuzhiyun #define B43legacy_PHY_EXTG(reg)	((reg) | B43legacy_PHYROUTE_EXT_GPHY)
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun /* Extended G-PHY Registers */
56*4882a593Smuzhiyun #define B43legacy_PHY_CLASSCTL		B43legacy_PHY_EXTG(0x02)	/* Classify control */
57*4882a593Smuzhiyun #define B43legacy_PHY_GTABCTL		B43legacy_PHY_EXTG(0x03)	/* G-PHY table control (see below) */
58*4882a593Smuzhiyun #define  B43legacy_PHY_GTABOFF		0x03FF			/* G-PHY table offset (see below) */
59*4882a593Smuzhiyun #define  B43legacy_PHY_GTABNR		0xFC00			/* G-PHY table number (see below) */
60*4882a593Smuzhiyun #define  B43legacy_PHY_GTABNR_SHIFT	10
61*4882a593Smuzhiyun #define B43legacy_PHY_GTABDATA		B43legacy_PHY_EXTG(0x04)	/* G-PHY table data */
62*4882a593Smuzhiyun #define B43legacy_PHY_LO_MASK		B43legacy_PHY_EXTG(0x0F)	/* Local Oscillator control mask */
63*4882a593Smuzhiyun #define B43legacy_PHY_LO_CTL		B43legacy_PHY_EXTG(0x10)	/* Local Oscillator control */
64*4882a593Smuzhiyun #define B43legacy_PHY_RFOVER		B43legacy_PHY_EXTG(0x11)	/* RF override */
65*4882a593Smuzhiyun #define B43legacy_PHY_RFOVERVAL		B43legacy_PHY_EXTG(0x12)	/* RF override value */
66*4882a593Smuzhiyun /*** OFDM table numbers ***/
67*4882a593Smuzhiyun #define B43legacy_OFDMTAB(number, offset)				\
68*4882a593Smuzhiyun 			  (((number) << B43legacy_PHY_OTABLENR_SHIFT)	\
69*4882a593Smuzhiyun 			  | (offset))
70*4882a593Smuzhiyun #define B43legacy_OFDMTAB_AGC1		B43legacy_OFDMTAB(0x00, 0)
71*4882a593Smuzhiyun #define B43legacy_OFDMTAB_GAIN0		B43legacy_OFDMTAB(0x00, 0)
72*4882a593Smuzhiyun #define B43legacy_OFDMTAB_GAINX		B43legacy_OFDMTAB(0x01, 0)
73*4882a593Smuzhiyun #define B43legacy_OFDMTAB_GAIN1		B43legacy_OFDMTAB(0x01, 4)
74*4882a593Smuzhiyun #define B43legacy_OFDMTAB_AGC3		B43legacy_OFDMTAB(0x02, 0)
75*4882a593Smuzhiyun #define B43legacy_OFDMTAB_GAIN2		B43legacy_OFDMTAB(0x02, 3)
76*4882a593Smuzhiyun #define B43legacy_OFDMTAB_LNAHPFGAIN1	B43legacy_OFDMTAB(0x03, 0)
77*4882a593Smuzhiyun #define B43legacy_OFDMTAB_WRSSI		B43legacy_OFDMTAB(0x04, 0)
78*4882a593Smuzhiyun #define B43legacy_OFDMTAB_LNAHPFGAIN2	B43legacy_OFDMTAB(0x04, 0)
79*4882a593Smuzhiyun #define B43legacy_OFDMTAB_NOISESCALE	B43legacy_OFDMTAB(0x05, 0)
80*4882a593Smuzhiyun #define B43legacy_OFDMTAB_AGC2		B43legacy_OFDMTAB(0x06, 0)
81*4882a593Smuzhiyun #define B43legacy_OFDMTAB_ROTOR		B43legacy_OFDMTAB(0x08, 0)
82*4882a593Smuzhiyun #define B43legacy_OFDMTAB_ADVRETARD	B43legacy_OFDMTAB(0x09, 0)
83*4882a593Smuzhiyun #define B43legacy_OFDMTAB_DAC		B43legacy_OFDMTAB(0x0C, 0)
84*4882a593Smuzhiyun #define B43legacy_OFDMTAB_DC		B43legacy_OFDMTAB(0x0E, 7)
85*4882a593Smuzhiyun #define B43legacy_OFDMTAB_PWRDYN2	B43legacy_OFDMTAB(0x0E, 12)
86*4882a593Smuzhiyun #define B43legacy_OFDMTAB_LNAGAIN	B43legacy_OFDMTAB(0x0E, 13)
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun #define B43legacy_OFDMTAB_LPFGAIN	B43legacy_OFDMTAB(0x0F, 12)
89*4882a593Smuzhiyun #define B43legacy_OFDMTAB_RSSI		B43legacy_OFDMTAB(0x10, 0)
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun #define B43legacy_OFDMTAB_AGC1_R1	B43legacy_OFDMTAB(0x13, 0)
92*4882a593Smuzhiyun #define B43legacy_OFDMTAB_GAINX_R1	B43legacy_OFDMTAB(0x14, 0)
93*4882a593Smuzhiyun #define B43legacy_OFDMTAB_MINSIGSQ	B43legacy_OFDMTAB(0x14, 1)
94*4882a593Smuzhiyun #define B43legacy_OFDMTAB_AGC3_R1	B43legacy_OFDMTAB(0x15, 0)
95*4882a593Smuzhiyun #define B43legacy_OFDMTAB_WRSSI_R1	B43legacy_OFDMTAB(0x15, 4)
96*4882a593Smuzhiyun #define B43legacy_OFDMTAB_TSSI		B43legacy_OFDMTAB(0x15, 0)
97*4882a593Smuzhiyun #define B43legacy_OFDMTAB_DACRFPABB	B43legacy_OFDMTAB(0x16, 0)
98*4882a593Smuzhiyun #define B43legacy_OFDMTAB_DACOFF	B43legacy_OFDMTAB(0x17, 0)
99*4882a593Smuzhiyun #define B43legacy_OFDMTAB_DCBIAS	B43legacy_OFDMTAB(0x18, 0)
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun void b43legacy_put_attenuation_into_ranges(int *_bbatt, int *_rfatt);
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun /* OFDM (A) PHY Registers */
104*4882a593Smuzhiyun #define B43legacy_PHY_VERSION_OFDM	B43legacy_PHY_OFDM(0x00)	/* Versioning register for A-PHY */
105*4882a593Smuzhiyun #define B43legacy_PHY_BBANDCFG		B43legacy_PHY_OFDM(0x01)	/* Baseband config */
106*4882a593Smuzhiyun #define  B43legacy_PHY_BBANDCFG_RXANT	0x180			/* RX Antenna selection */
107*4882a593Smuzhiyun #define  B43legacy_PHY_BBANDCFG_RXANT_SHIFT	7
108*4882a593Smuzhiyun #define B43legacy_PHY_PWRDOWN		B43legacy_PHY_OFDM(0x03)	/* Powerdown */
109*4882a593Smuzhiyun #define B43legacy_PHY_CRSTHRES1		B43legacy_PHY_OFDM(0x06)	/* CRS Threshold 1 */
110*4882a593Smuzhiyun #define B43legacy_PHY_LNAHPFCTL		B43legacy_PHY_OFDM(0x1C)	/* LNA/HPF control */
111*4882a593Smuzhiyun #define B43legacy_PHY_ADIVRELATED	B43legacy_PHY_OFDM(0x27)	/* FIXME rename */
112*4882a593Smuzhiyun #define B43legacy_PHY_CRS0		B43legacy_PHY_OFDM(0x29)
113*4882a593Smuzhiyun #define B43legacy_PHY_ANTDWELL		B43legacy_PHY_OFDM(0x2B)	/* Antenna dwell */
114*4882a593Smuzhiyun #define  B43legacy_PHY_ANTDWELL_AUTODIV1	0x0100			/* Automatic RX diversity start antenna */
115*4882a593Smuzhiyun #define B43legacy_PHY_ENCORE		B43legacy_PHY_OFDM(0x49)	/* "Encore" (RangeMax / BroadRange) */
116*4882a593Smuzhiyun #define  B43legacy_PHY_ENCORE_EN	0x0200				/* Encore enable */
117*4882a593Smuzhiyun #define B43legacy_PHY_LMS		B43legacy_PHY_OFDM(0x55)
118*4882a593Smuzhiyun #define B43legacy_PHY_OFDM61		B43legacy_PHY_OFDM(0x61)	/* FIXME rename */
119*4882a593Smuzhiyun #define  B43legacy_PHY_OFDM61_10	0x0010				/* FIXME rename */
120*4882a593Smuzhiyun #define B43legacy_PHY_IQBAL		B43legacy_PHY_OFDM(0x69)	/* I/Q balance */
121*4882a593Smuzhiyun #define B43legacy_PHY_OTABLECTL		B43legacy_PHY_OFDM(0x72)	/* OFDM table control (see below) */
122*4882a593Smuzhiyun #define  B43legacy_PHY_OTABLEOFF	0x03FF				/* OFDM table offset (see below) */
123*4882a593Smuzhiyun #define  B43legacy_PHY_OTABLENR		0xFC00				/* OFDM table number (see below) */
124*4882a593Smuzhiyun #define  B43legacy_PHY_OTABLENR_SHIFT	10
125*4882a593Smuzhiyun #define B43legacy_PHY_OTABLEI		B43legacy_PHY_OFDM(0x73)	/* OFDM table data I */
126*4882a593Smuzhiyun #define B43legacy_PHY_OTABLEQ		B43legacy_PHY_OFDM(0x74)	/* OFDM table data Q */
127*4882a593Smuzhiyun #define B43legacy_PHY_HPWR_TSSICTL	B43legacy_PHY_OFDM(0x78)	/* Hardware power TSSI control */
128*4882a593Smuzhiyun #define B43legacy_PHY_NRSSITHRES	B43legacy_PHY_OFDM(0x8A)	/* NRSSI threshold */
129*4882a593Smuzhiyun #define B43legacy_PHY_ANTWRSETT		B43legacy_PHY_OFDM(0x8C)	/* Antenna WR settle */
130*4882a593Smuzhiyun #define  B43legacy_PHY_ANTWRSETT_ARXDIV	0x2000				/* Automatic RX diversity enabled */
131*4882a593Smuzhiyun #define B43legacy_PHY_CLIPPWRDOWNT	B43legacy_PHY_OFDM(0x93)	/* Clip powerdown threshold */
132*4882a593Smuzhiyun #define B43legacy_PHY_OFDM9B		B43legacy_PHY_OFDM(0x9B)	/* FIXME rename */
133*4882a593Smuzhiyun #define B43legacy_PHY_N1P1GAIN		B43legacy_PHY_OFDM(0xA0)
134*4882a593Smuzhiyun #define B43legacy_PHY_P1P2GAIN		B43legacy_PHY_OFDM(0xA1)
135*4882a593Smuzhiyun #define B43legacy_PHY_N1N2GAIN		B43legacy_PHY_OFDM(0xA2)
136*4882a593Smuzhiyun #define B43legacy_PHY_CLIPTHRES		B43legacy_PHY_OFDM(0xA3)
137*4882a593Smuzhiyun #define B43legacy_PHY_CLIPN1P2THRES	B43legacy_PHY_OFDM(0xA4)
138*4882a593Smuzhiyun #define B43legacy_PHY_DIVSRCHIDX	B43legacy_PHY_OFDM(0xA8)	/* Divider search gain/index */
139*4882a593Smuzhiyun #define B43legacy_PHY_CLIPP2THRES	B43legacy_PHY_OFDM(0xA9)
140*4882a593Smuzhiyun #define B43legacy_PHY_CLIPP3THRES	B43legacy_PHY_OFDM(0xAA)
141*4882a593Smuzhiyun #define B43legacy_PHY_DIVP1P2GAIN	B43legacy_PHY_OFDM(0xAB)
142*4882a593Smuzhiyun #define B43legacy_PHY_DIVSRCHGAINBACK	B43legacy_PHY_OFDM(0xAD)	/* Divider search gain back */
143*4882a593Smuzhiyun #define B43legacy_PHY_DIVSRCHGAINCHNG	B43legacy_PHY_OFDM(0xAE)	/* Divider search gain change */
144*4882a593Smuzhiyun #define B43legacy_PHY_CRSTHRES1_R1	B43legacy_PHY_OFDM(0xC0)	/* CRS Threshold 1 (rev 1 only) */
145*4882a593Smuzhiyun #define B43legacy_PHY_CRSTHRES2_R1	B43legacy_PHY_OFDM(0xC1)	/* CRS Threshold 2 (rev 1 only) */
146*4882a593Smuzhiyun #define B43legacy_PHY_TSSIP_LTBASE	B43legacy_PHY_OFDM(0x380)	/* TSSI power lookup table base */
147*4882a593Smuzhiyun #define B43legacy_PHY_DC_LTBASE		B43legacy_PHY_OFDM(0x3A0)	/* DC lookup table base */
148*4882a593Smuzhiyun #define B43legacy_PHY_GAIN_LTBASE	B43legacy_PHY_OFDM(0x3C0)	/* Gain lookup table base */
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun void b43legacy_put_attenuation_into_ranges(int *_bbatt, int *_rfatt);
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun /* Masks for the different PHY versioning registers. */
153*4882a593Smuzhiyun #define B43legacy_PHYVER_ANALOG		0xF000
154*4882a593Smuzhiyun #define B43legacy_PHYVER_ANALOG_SHIFT	12
155*4882a593Smuzhiyun #define B43legacy_PHYVER_TYPE		0x0F00
156*4882a593Smuzhiyun #define B43legacy_PHYVER_TYPE_SHIFT	8
157*4882a593Smuzhiyun #define B43legacy_PHYVER_VERSION	0x00FF
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun struct b43legacy_wldev;
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun void b43legacy_phy_lock(struct b43legacy_wldev *dev);
162*4882a593Smuzhiyun void b43legacy_phy_unlock(struct b43legacy_wldev *dev);
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun /* Card uses the loopback gain stuff */
165*4882a593Smuzhiyun #define has_loopback_gain(phy)			 \
166*4882a593Smuzhiyun 	(((phy)->rev > 1) || ((phy)->gmode))
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun u16 b43legacy_phy_read(struct b43legacy_wldev *dev, u16 offset);
169*4882a593Smuzhiyun void b43legacy_phy_write(struct b43legacy_wldev *dev, u16 offset, u16 val);
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun int b43legacy_phy_init_tssi2dbm_table(struct b43legacy_wldev *dev);
172*4882a593Smuzhiyun int b43legacy_phy_init(struct b43legacy_wldev *dev);
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun void b43legacy_set_rx_antenna(struct b43legacy_wldev *dev, int antenna);
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun void b43legacy_phy_set_antenna_diversity(struct b43legacy_wldev *dev);
177*4882a593Smuzhiyun void b43legacy_phy_calibrate(struct b43legacy_wldev *dev);
178*4882a593Smuzhiyun int b43legacy_phy_connect(struct b43legacy_wldev *dev, int connect);
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun void b43legacy_phy_lo_b_measure(struct b43legacy_wldev *dev);
181*4882a593Smuzhiyun void b43legacy_phy_lo_g_measure(struct b43legacy_wldev *dev);
182*4882a593Smuzhiyun void b43legacy_phy_xmitpower(struct b43legacy_wldev *dev);
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun /* Adjust the LocalOscillator to the saved values.
185*4882a593Smuzhiyun  * "fixed" is only set to 1 once in initialization. Set to 0 otherwise.
186*4882a593Smuzhiyun  */
187*4882a593Smuzhiyun void b43legacy_phy_lo_adjust(struct b43legacy_wldev *dev, int fixed);
188*4882a593Smuzhiyun void b43legacy_phy_lo_mark_all_unused(struct b43legacy_wldev *dev);
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun void b43legacy_phy_set_baseband_attenuation(struct b43legacy_wldev *dev,
191*4882a593Smuzhiyun 					    u16 baseband_attenuation);
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun void b43legacy_power_saving_ctl_bits(struct b43legacy_wldev *dev,
194*4882a593Smuzhiyun 				     int bit25, int bit26);
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun #endif /* B43legacy_PHY_H_ */
197