xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/broadcom/b43/xmit.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun 
4*4882a593Smuzhiyun   Broadcom B43 wireless driver
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun   Transmission (TX/RX) related functions.
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun   Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
9*4882a593Smuzhiyun   Copyright (C) 2005 Stefano Brivio <stefano.brivio@polimi.it>
10*4882a593Smuzhiyun   Copyright (C) 2005, 2006 Michael Buesch <m@bues.ch>
11*4882a593Smuzhiyun   Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
12*4882a593Smuzhiyun   Copyright (C) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun */
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #include "xmit.h"
18*4882a593Smuzhiyun #include "phy_common.h"
19*4882a593Smuzhiyun #include "dma.h"
20*4882a593Smuzhiyun #include "pio.h"
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun static const struct b43_tx_legacy_rate_phy_ctl_entry b43_tx_legacy_rate_phy_ctl[] = {
23*4882a593Smuzhiyun 	{ B43_CCK_RATE_1MB,	0x0,			0x0 },
24*4882a593Smuzhiyun 	{ B43_CCK_RATE_2MB,	0x0,			0x1 },
25*4882a593Smuzhiyun 	{ B43_CCK_RATE_5MB,	0x0,			0x2 },
26*4882a593Smuzhiyun 	{ B43_CCK_RATE_11MB,	0x0,			0x3 },
27*4882a593Smuzhiyun 	{ B43_OFDM_RATE_6MB,	B43_TXH_PHY1_CRATE_1_2,	B43_TXH_PHY1_MODUL_BPSK },
28*4882a593Smuzhiyun 	{ B43_OFDM_RATE_9MB,	B43_TXH_PHY1_CRATE_3_4,	B43_TXH_PHY1_MODUL_BPSK },
29*4882a593Smuzhiyun 	{ B43_OFDM_RATE_12MB,	B43_TXH_PHY1_CRATE_1_2,	B43_TXH_PHY1_MODUL_QPSK },
30*4882a593Smuzhiyun 	{ B43_OFDM_RATE_18MB,	B43_TXH_PHY1_CRATE_3_4,	B43_TXH_PHY1_MODUL_QPSK },
31*4882a593Smuzhiyun 	{ B43_OFDM_RATE_24MB,	B43_TXH_PHY1_CRATE_1_2,	B43_TXH_PHY1_MODUL_QAM16 },
32*4882a593Smuzhiyun 	{ B43_OFDM_RATE_36MB,	B43_TXH_PHY1_CRATE_3_4,	B43_TXH_PHY1_MODUL_QAM16 },
33*4882a593Smuzhiyun 	{ B43_OFDM_RATE_48MB,	B43_TXH_PHY1_CRATE_2_3,	B43_TXH_PHY1_MODUL_QAM64 },
34*4882a593Smuzhiyun 	{ B43_OFDM_RATE_54MB,	B43_TXH_PHY1_CRATE_3_4,	B43_TXH_PHY1_MODUL_QAM64 },
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun static const struct b43_tx_legacy_rate_phy_ctl_entry *
b43_tx_legacy_rate_phy_ctl_ent(u8 bitrate)38*4882a593Smuzhiyun b43_tx_legacy_rate_phy_ctl_ent(u8 bitrate)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun 	const struct b43_tx_legacy_rate_phy_ctl_entry *e;
41*4882a593Smuzhiyun 	unsigned int i;
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(b43_tx_legacy_rate_phy_ctl); i++) {
44*4882a593Smuzhiyun 		e = &(b43_tx_legacy_rate_phy_ctl[i]);
45*4882a593Smuzhiyun 		if (e->bitrate == bitrate)
46*4882a593Smuzhiyun 			return e;
47*4882a593Smuzhiyun 	}
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun 	B43_WARN_ON(1);
50*4882a593Smuzhiyun 	return NULL;
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun /* Extract the bitrate index out of a CCK PLCP header. */
b43_plcp_get_bitrate_idx_cck(struct b43_plcp_hdr6 * plcp)54*4882a593Smuzhiyun static int b43_plcp_get_bitrate_idx_cck(struct b43_plcp_hdr6 *plcp)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun 	switch (plcp->raw[0]) {
57*4882a593Smuzhiyun 	case 0x0A:
58*4882a593Smuzhiyun 		return 0;
59*4882a593Smuzhiyun 	case 0x14:
60*4882a593Smuzhiyun 		return 1;
61*4882a593Smuzhiyun 	case 0x37:
62*4882a593Smuzhiyun 		return 2;
63*4882a593Smuzhiyun 	case 0x6E:
64*4882a593Smuzhiyun 		return 3;
65*4882a593Smuzhiyun 	}
66*4882a593Smuzhiyun 	return -1;
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun /* Extract the bitrate index out of an OFDM PLCP header. */
b43_plcp_get_bitrate_idx_ofdm(struct b43_plcp_hdr6 * plcp,bool ghz5)70*4882a593Smuzhiyun static int b43_plcp_get_bitrate_idx_ofdm(struct b43_plcp_hdr6 *plcp, bool ghz5)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun 	/* For 2 GHz band first OFDM rate is at index 4, see main.c */
73*4882a593Smuzhiyun 	int base = ghz5 ? 0 : 4;
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun 	switch (plcp->raw[0] & 0xF) {
76*4882a593Smuzhiyun 	case 0xB:
77*4882a593Smuzhiyun 		return base + 0;
78*4882a593Smuzhiyun 	case 0xF:
79*4882a593Smuzhiyun 		return base + 1;
80*4882a593Smuzhiyun 	case 0xA:
81*4882a593Smuzhiyun 		return base + 2;
82*4882a593Smuzhiyun 	case 0xE:
83*4882a593Smuzhiyun 		return base + 3;
84*4882a593Smuzhiyun 	case 0x9:
85*4882a593Smuzhiyun 		return base + 4;
86*4882a593Smuzhiyun 	case 0xD:
87*4882a593Smuzhiyun 		return base + 5;
88*4882a593Smuzhiyun 	case 0x8:
89*4882a593Smuzhiyun 		return base + 6;
90*4882a593Smuzhiyun 	case 0xC:
91*4882a593Smuzhiyun 		return base + 7;
92*4882a593Smuzhiyun 	}
93*4882a593Smuzhiyun 	return -1;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun 
b43_plcp_get_ratecode_cck(const u8 bitrate)96*4882a593Smuzhiyun u8 b43_plcp_get_ratecode_cck(const u8 bitrate)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun 	switch (bitrate) {
99*4882a593Smuzhiyun 	case B43_CCK_RATE_1MB:
100*4882a593Smuzhiyun 		return 0x0A;
101*4882a593Smuzhiyun 	case B43_CCK_RATE_2MB:
102*4882a593Smuzhiyun 		return 0x14;
103*4882a593Smuzhiyun 	case B43_CCK_RATE_5MB:
104*4882a593Smuzhiyun 		return 0x37;
105*4882a593Smuzhiyun 	case B43_CCK_RATE_11MB:
106*4882a593Smuzhiyun 		return 0x6E;
107*4882a593Smuzhiyun 	}
108*4882a593Smuzhiyun 	B43_WARN_ON(1);
109*4882a593Smuzhiyun 	return 0;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun 
b43_plcp_get_ratecode_ofdm(const u8 bitrate)112*4882a593Smuzhiyun u8 b43_plcp_get_ratecode_ofdm(const u8 bitrate)
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun 	switch (bitrate) {
115*4882a593Smuzhiyun 	case B43_OFDM_RATE_6MB:
116*4882a593Smuzhiyun 		return 0xB;
117*4882a593Smuzhiyun 	case B43_OFDM_RATE_9MB:
118*4882a593Smuzhiyun 		return 0xF;
119*4882a593Smuzhiyun 	case B43_OFDM_RATE_12MB:
120*4882a593Smuzhiyun 		return 0xA;
121*4882a593Smuzhiyun 	case B43_OFDM_RATE_18MB:
122*4882a593Smuzhiyun 		return 0xE;
123*4882a593Smuzhiyun 	case B43_OFDM_RATE_24MB:
124*4882a593Smuzhiyun 		return 0x9;
125*4882a593Smuzhiyun 	case B43_OFDM_RATE_36MB:
126*4882a593Smuzhiyun 		return 0xD;
127*4882a593Smuzhiyun 	case B43_OFDM_RATE_48MB:
128*4882a593Smuzhiyun 		return 0x8;
129*4882a593Smuzhiyun 	case B43_OFDM_RATE_54MB:
130*4882a593Smuzhiyun 		return 0xC;
131*4882a593Smuzhiyun 	}
132*4882a593Smuzhiyun 	B43_WARN_ON(1);
133*4882a593Smuzhiyun 	return 0;
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun 
b43_generate_plcp_hdr(struct b43_plcp_hdr4 * plcp,const u16 octets,const u8 bitrate)136*4882a593Smuzhiyun void b43_generate_plcp_hdr(struct b43_plcp_hdr4 *plcp,
137*4882a593Smuzhiyun 			   const u16 octets, const u8 bitrate)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun 	__u8 *raw = plcp->raw;
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	if (b43_is_ofdm_rate(bitrate)) {
142*4882a593Smuzhiyun 		u32 d;
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 		d = b43_plcp_get_ratecode_ofdm(bitrate);
145*4882a593Smuzhiyun 		B43_WARN_ON(octets & 0xF000);
146*4882a593Smuzhiyun 		d |= (octets << 5);
147*4882a593Smuzhiyun 		plcp->data = cpu_to_le32(d);
148*4882a593Smuzhiyun 	} else {
149*4882a593Smuzhiyun 		u32 plen;
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 		plen = octets * 16 / bitrate;
152*4882a593Smuzhiyun 		if ((octets * 16 % bitrate) > 0) {
153*4882a593Smuzhiyun 			plen++;
154*4882a593Smuzhiyun 			if ((bitrate == B43_CCK_RATE_11MB)
155*4882a593Smuzhiyun 			    && ((octets * 8 % 11) < 4)) {
156*4882a593Smuzhiyun 				raw[1] = 0x84;
157*4882a593Smuzhiyun 			} else
158*4882a593Smuzhiyun 				raw[1] = 0x04;
159*4882a593Smuzhiyun 		} else
160*4882a593Smuzhiyun 			raw[1] = 0x04;
161*4882a593Smuzhiyun 		plcp->data |= cpu_to_le32(plen << 16);
162*4882a593Smuzhiyun 		raw[0] = b43_plcp_get_ratecode_cck(bitrate);
163*4882a593Smuzhiyun 	}
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun /* TODO: verify if needed for SSLPN or LCN  */
b43_generate_tx_phy_ctl1(struct b43_wldev * dev,u8 bitrate)167*4882a593Smuzhiyun static u16 b43_generate_tx_phy_ctl1(struct b43_wldev *dev, u8 bitrate)
168*4882a593Smuzhiyun {
169*4882a593Smuzhiyun 	const struct b43_phy *phy = &dev->phy;
170*4882a593Smuzhiyun 	const struct b43_tx_legacy_rate_phy_ctl_entry *e;
171*4882a593Smuzhiyun 	u16 control = 0;
172*4882a593Smuzhiyun 	u16 bw;
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	if (phy->type == B43_PHYTYPE_LP)
175*4882a593Smuzhiyun 		bw = B43_TXH_PHY1_BW_20;
176*4882a593Smuzhiyun 	else /* FIXME */
177*4882a593Smuzhiyun 		bw = B43_TXH_PHY1_BW_20;
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 	if (0) { /* FIXME: MIMO */
180*4882a593Smuzhiyun 	} else if (b43_is_cck_rate(bitrate) && phy->type != B43_PHYTYPE_LP) {
181*4882a593Smuzhiyun 		control = bw;
182*4882a593Smuzhiyun 	} else {
183*4882a593Smuzhiyun 		control = bw;
184*4882a593Smuzhiyun 		e = b43_tx_legacy_rate_phy_ctl_ent(bitrate);
185*4882a593Smuzhiyun 		if (e) {
186*4882a593Smuzhiyun 			control |= e->coding_rate;
187*4882a593Smuzhiyun 			control |= e->modulation;
188*4882a593Smuzhiyun 		}
189*4882a593Smuzhiyun 		control |= B43_TXH_PHY1_MODE_SISO;
190*4882a593Smuzhiyun 	}
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun 	return control;
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun 
b43_calc_fallback_rate(u8 bitrate,int gmode)195*4882a593Smuzhiyun static u8 b43_calc_fallback_rate(u8 bitrate, int gmode)
196*4882a593Smuzhiyun {
197*4882a593Smuzhiyun 	switch (bitrate) {
198*4882a593Smuzhiyun 	case B43_CCK_RATE_1MB:
199*4882a593Smuzhiyun 		return B43_CCK_RATE_1MB;
200*4882a593Smuzhiyun 	case B43_CCK_RATE_2MB:
201*4882a593Smuzhiyun 		return B43_CCK_RATE_1MB;
202*4882a593Smuzhiyun 	case B43_CCK_RATE_5MB:
203*4882a593Smuzhiyun 		return B43_CCK_RATE_2MB;
204*4882a593Smuzhiyun 	case B43_CCK_RATE_11MB:
205*4882a593Smuzhiyun 		return B43_CCK_RATE_5MB;
206*4882a593Smuzhiyun 	/*
207*4882a593Smuzhiyun 	 * Don't just fallback to CCK; it may be in 5GHz operation
208*4882a593Smuzhiyun 	 * and falling back to CCK won't work out very well.
209*4882a593Smuzhiyun 	 */
210*4882a593Smuzhiyun 	case B43_OFDM_RATE_6MB:
211*4882a593Smuzhiyun 		if (gmode)
212*4882a593Smuzhiyun 			return B43_CCK_RATE_5MB;
213*4882a593Smuzhiyun 		else
214*4882a593Smuzhiyun 			return B43_OFDM_RATE_6MB;
215*4882a593Smuzhiyun 	case B43_OFDM_RATE_9MB:
216*4882a593Smuzhiyun 		return B43_OFDM_RATE_6MB;
217*4882a593Smuzhiyun 	case B43_OFDM_RATE_12MB:
218*4882a593Smuzhiyun 		return B43_OFDM_RATE_9MB;
219*4882a593Smuzhiyun 	case B43_OFDM_RATE_18MB:
220*4882a593Smuzhiyun 		return B43_OFDM_RATE_12MB;
221*4882a593Smuzhiyun 	case B43_OFDM_RATE_24MB:
222*4882a593Smuzhiyun 		return B43_OFDM_RATE_18MB;
223*4882a593Smuzhiyun 	case B43_OFDM_RATE_36MB:
224*4882a593Smuzhiyun 		return B43_OFDM_RATE_24MB;
225*4882a593Smuzhiyun 	case B43_OFDM_RATE_48MB:
226*4882a593Smuzhiyun 		return B43_OFDM_RATE_36MB;
227*4882a593Smuzhiyun 	case B43_OFDM_RATE_54MB:
228*4882a593Smuzhiyun 		return B43_OFDM_RATE_48MB;
229*4882a593Smuzhiyun 	}
230*4882a593Smuzhiyun 	B43_WARN_ON(1);
231*4882a593Smuzhiyun 	return 0;
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun /* Generate a TX data header. */
b43_generate_txhdr(struct b43_wldev * dev,u8 * _txhdr,struct sk_buff * skb_frag,struct ieee80211_tx_info * info,u16 cookie)235*4882a593Smuzhiyun int b43_generate_txhdr(struct b43_wldev *dev,
236*4882a593Smuzhiyun 		       u8 *_txhdr,
237*4882a593Smuzhiyun 		       struct sk_buff *skb_frag,
238*4882a593Smuzhiyun 		       struct ieee80211_tx_info *info,
239*4882a593Smuzhiyun 		       u16 cookie)
240*4882a593Smuzhiyun {
241*4882a593Smuzhiyun 	const unsigned char *fragment_data = skb_frag->data;
242*4882a593Smuzhiyun 	unsigned int fragment_len = skb_frag->len;
243*4882a593Smuzhiyun 	struct b43_txhdr *txhdr = (struct b43_txhdr *)_txhdr;
244*4882a593Smuzhiyun 	const struct b43_phy *phy = &dev->phy;
245*4882a593Smuzhiyun 	const struct ieee80211_hdr *wlhdr =
246*4882a593Smuzhiyun 	    (const struct ieee80211_hdr *)fragment_data;
247*4882a593Smuzhiyun 	int use_encryption = !!info->control.hw_key;
248*4882a593Smuzhiyun 	__le16 fctl = wlhdr->frame_control;
249*4882a593Smuzhiyun 	struct ieee80211_rate *fbrate;
250*4882a593Smuzhiyun 	u8 rate, rate_fb;
251*4882a593Smuzhiyun 	int rate_ofdm, rate_fb_ofdm;
252*4882a593Smuzhiyun 	unsigned int plcp_fragment_len;
253*4882a593Smuzhiyun 	u32 mac_ctl = 0;
254*4882a593Smuzhiyun 	u16 phy_ctl = 0;
255*4882a593Smuzhiyun 	bool fill_phy_ctl1 = (phy->type == B43_PHYTYPE_LP ||
256*4882a593Smuzhiyun 			      phy->type == B43_PHYTYPE_N ||
257*4882a593Smuzhiyun 			      phy->type == B43_PHYTYPE_HT);
258*4882a593Smuzhiyun 	u8 extra_ft = 0;
259*4882a593Smuzhiyun 	struct ieee80211_rate *txrate;
260*4882a593Smuzhiyun 	struct ieee80211_tx_rate *rates;
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 	memset(txhdr, 0, sizeof(*txhdr));
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun 	txrate = ieee80211_get_tx_rate(dev->wl->hw, info);
265*4882a593Smuzhiyun 	rate = txrate ? txrate->hw_value : B43_CCK_RATE_1MB;
266*4882a593Smuzhiyun 	rate_ofdm = b43_is_ofdm_rate(rate);
267*4882a593Smuzhiyun 	fbrate = ieee80211_get_alt_retry_rate(dev->wl->hw, info, 0) ? : txrate;
268*4882a593Smuzhiyun 	rate_fb = fbrate->hw_value;
269*4882a593Smuzhiyun 	rate_fb_ofdm = b43_is_ofdm_rate(rate_fb);
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	if (rate_ofdm)
272*4882a593Smuzhiyun 		txhdr->phy_rate = b43_plcp_get_ratecode_ofdm(rate);
273*4882a593Smuzhiyun 	else
274*4882a593Smuzhiyun 		txhdr->phy_rate = b43_plcp_get_ratecode_cck(rate);
275*4882a593Smuzhiyun 	txhdr->mac_frame_ctl = wlhdr->frame_control;
276*4882a593Smuzhiyun 	memcpy(txhdr->tx_receiver, wlhdr->addr1, ETH_ALEN);
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun 	/* Calculate duration for fallback rate */
279*4882a593Smuzhiyun 	if ((rate_fb == rate) ||
280*4882a593Smuzhiyun 	    (wlhdr->duration_id & cpu_to_le16(0x8000)) ||
281*4882a593Smuzhiyun 	    (wlhdr->duration_id == cpu_to_le16(0))) {
282*4882a593Smuzhiyun 		/* If the fallback rate equals the normal rate or the
283*4882a593Smuzhiyun 		 * dur_id field contains an AID, CFP magic or 0,
284*4882a593Smuzhiyun 		 * use the original dur_id field. */
285*4882a593Smuzhiyun 		txhdr->dur_fb = wlhdr->duration_id;
286*4882a593Smuzhiyun 	} else {
287*4882a593Smuzhiyun 		txhdr->dur_fb = ieee80211_generic_frame_duration(
288*4882a593Smuzhiyun 			dev->wl->hw, info->control.vif, info->band,
289*4882a593Smuzhiyun 			fragment_len, fbrate);
290*4882a593Smuzhiyun 	}
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun 	plcp_fragment_len = fragment_len + FCS_LEN;
293*4882a593Smuzhiyun 	if (use_encryption) {
294*4882a593Smuzhiyun 		u8 key_idx = info->control.hw_key->hw_key_idx;
295*4882a593Smuzhiyun 		struct b43_key *key;
296*4882a593Smuzhiyun 		int wlhdr_len;
297*4882a593Smuzhiyun 		size_t iv_len;
298*4882a593Smuzhiyun 
299*4882a593Smuzhiyun 		B43_WARN_ON(key_idx >= ARRAY_SIZE(dev->key));
300*4882a593Smuzhiyun 		key = &(dev->key[key_idx]);
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun 		if (unlikely(!key->keyconf)) {
303*4882a593Smuzhiyun 			/* This key is invalid. This might only happen
304*4882a593Smuzhiyun 			 * in a short timeframe after machine resume before
305*4882a593Smuzhiyun 			 * we were able to reconfigure keys.
306*4882a593Smuzhiyun 			 * Drop this packet completely. Do not transmit it
307*4882a593Smuzhiyun 			 * unencrypted to avoid leaking information. */
308*4882a593Smuzhiyun 			return -ENOKEY;
309*4882a593Smuzhiyun 		}
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun 		/* Hardware appends ICV. */
312*4882a593Smuzhiyun 		plcp_fragment_len += info->control.hw_key->icv_len;
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun 		key_idx = b43_kidx_to_fw(dev, key_idx);
315*4882a593Smuzhiyun 		mac_ctl |= (key_idx << B43_TXH_MAC_KEYIDX_SHIFT) &
316*4882a593Smuzhiyun 			   B43_TXH_MAC_KEYIDX;
317*4882a593Smuzhiyun 		mac_ctl |= (key->algorithm << B43_TXH_MAC_KEYALG_SHIFT) &
318*4882a593Smuzhiyun 			   B43_TXH_MAC_KEYALG;
319*4882a593Smuzhiyun 		wlhdr_len = ieee80211_hdrlen(fctl);
320*4882a593Smuzhiyun 		if (key->algorithm == B43_SEC_ALGO_TKIP) {
321*4882a593Smuzhiyun 			u16 phase1key[5];
322*4882a593Smuzhiyun 			int i;
323*4882a593Smuzhiyun 			/* we give the phase1key and iv16 here, the key is stored in
324*4882a593Smuzhiyun 			 * shm. With that the hardware can do phase 2 and encryption.
325*4882a593Smuzhiyun 			 */
326*4882a593Smuzhiyun 			ieee80211_get_tkip_p1k(info->control.hw_key, skb_frag, phase1key);
327*4882a593Smuzhiyun 			/* phase1key is in host endian. Copy to little-endian txhdr->iv. */
328*4882a593Smuzhiyun 			for (i = 0; i < 5; i++) {
329*4882a593Smuzhiyun 				txhdr->iv[i * 2 + 0] = phase1key[i];
330*4882a593Smuzhiyun 				txhdr->iv[i * 2 + 1] = phase1key[i] >> 8;
331*4882a593Smuzhiyun 			}
332*4882a593Smuzhiyun 			/* iv16 */
333*4882a593Smuzhiyun 			memcpy(txhdr->iv + 10, ((u8 *) wlhdr) + wlhdr_len, 3);
334*4882a593Smuzhiyun 		} else {
335*4882a593Smuzhiyun 			iv_len = min_t(size_t, info->control.hw_key->iv_len,
336*4882a593Smuzhiyun 				     ARRAY_SIZE(txhdr->iv));
337*4882a593Smuzhiyun 			memcpy(txhdr->iv, ((u8 *) wlhdr) + wlhdr_len, iv_len);
338*4882a593Smuzhiyun 		}
339*4882a593Smuzhiyun 	}
340*4882a593Smuzhiyun 	switch (dev->fw.hdr_format) {
341*4882a593Smuzhiyun 	case B43_FW_HDR_598:
342*4882a593Smuzhiyun 		b43_generate_plcp_hdr((struct b43_plcp_hdr4 *)(&txhdr->format_598.plcp),
343*4882a593Smuzhiyun 				      plcp_fragment_len, rate);
344*4882a593Smuzhiyun 		break;
345*4882a593Smuzhiyun 	case B43_FW_HDR_351:
346*4882a593Smuzhiyun 		b43_generate_plcp_hdr((struct b43_plcp_hdr4 *)(&txhdr->format_351.plcp),
347*4882a593Smuzhiyun 				      plcp_fragment_len, rate);
348*4882a593Smuzhiyun 		break;
349*4882a593Smuzhiyun 	case B43_FW_HDR_410:
350*4882a593Smuzhiyun 		b43_generate_plcp_hdr((struct b43_plcp_hdr4 *)(&txhdr->format_410.plcp),
351*4882a593Smuzhiyun 				      plcp_fragment_len, rate);
352*4882a593Smuzhiyun 		break;
353*4882a593Smuzhiyun 	}
354*4882a593Smuzhiyun 	b43_generate_plcp_hdr((struct b43_plcp_hdr4 *)(&txhdr->plcp_fb),
355*4882a593Smuzhiyun 			      plcp_fragment_len, rate_fb);
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun 	/* Extra Frame Types */
358*4882a593Smuzhiyun 	if (rate_fb_ofdm)
359*4882a593Smuzhiyun 		extra_ft |= B43_TXH_EFT_FB_OFDM;
360*4882a593Smuzhiyun 	else
361*4882a593Smuzhiyun 		extra_ft |= B43_TXH_EFT_FB_CCK;
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun 	/* Set channel radio code. Note that the micrcode ORs 0x100 to
364*4882a593Smuzhiyun 	 * this value before comparing it to the value in SHM, if this
365*4882a593Smuzhiyun 	 * is a 5Ghz packet.
366*4882a593Smuzhiyun 	 */
367*4882a593Smuzhiyun 	txhdr->chan_radio_code = phy->channel;
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun 	/* PHY TX Control word */
370*4882a593Smuzhiyun 	if (rate_ofdm)
371*4882a593Smuzhiyun 		phy_ctl |= B43_TXH_PHY_ENC_OFDM;
372*4882a593Smuzhiyun 	else
373*4882a593Smuzhiyun 		phy_ctl |= B43_TXH_PHY_ENC_CCK;
374*4882a593Smuzhiyun 	if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
375*4882a593Smuzhiyun 		phy_ctl |= B43_TXH_PHY_SHORTPRMBL;
376*4882a593Smuzhiyun 
377*4882a593Smuzhiyun 	switch (b43_ieee80211_antenna_sanitize(dev, 0)) {
378*4882a593Smuzhiyun 	case 0: /* Default */
379*4882a593Smuzhiyun 		phy_ctl |= B43_TXH_PHY_ANT01AUTO;
380*4882a593Smuzhiyun 		break;
381*4882a593Smuzhiyun 	case 1: /* Antenna 0 */
382*4882a593Smuzhiyun 		phy_ctl |= B43_TXH_PHY_ANT0;
383*4882a593Smuzhiyun 		break;
384*4882a593Smuzhiyun 	case 2: /* Antenna 1 */
385*4882a593Smuzhiyun 		phy_ctl |= B43_TXH_PHY_ANT1;
386*4882a593Smuzhiyun 		break;
387*4882a593Smuzhiyun 	case 3: /* Antenna 2 */
388*4882a593Smuzhiyun 		phy_ctl |= B43_TXH_PHY_ANT2;
389*4882a593Smuzhiyun 		break;
390*4882a593Smuzhiyun 	case 4: /* Antenna 3 */
391*4882a593Smuzhiyun 		phy_ctl |= B43_TXH_PHY_ANT3;
392*4882a593Smuzhiyun 		break;
393*4882a593Smuzhiyun 	default:
394*4882a593Smuzhiyun 		B43_WARN_ON(1);
395*4882a593Smuzhiyun 	}
396*4882a593Smuzhiyun 
397*4882a593Smuzhiyun 	rates = info->control.rates;
398*4882a593Smuzhiyun 	/* MAC control */
399*4882a593Smuzhiyun 	if (!(info->flags & IEEE80211_TX_CTL_NO_ACK))
400*4882a593Smuzhiyun 		mac_ctl |= B43_TXH_MAC_ACK;
401*4882a593Smuzhiyun 	/* use hardware sequence counter as the non-TID counter */
402*4882a593Smuzhiyun 	if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)
403*4882a593Smuzhiyun 		mac_ctl |= B43_TXH_MAC_HWSEQ;
404*4882a593Smuzhiyun 	if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
405*4882a593Smuzhiyun 		mac_ctl |= B43_TXH_MAC_STMSDU;
406*4882a593Smuzhiyun 	if (!phy->gmode)
407*4882a593Smuzhiyun 		mac_ctl |= B43_TXH_MAC_5GHZ;
408*4882a593Smuzhiyun 
409*4882a593Smuzhiyun 	/* Overwrite rates[0].count to make the retry calculation
410*4882a593Smuzhiyun 	 * in the tx status easier. need the actual retry limit to
411*4882a593Smuzhiyun 	 * detect whether the fallback rate was used.
412*4882a593Smuzhiyun 	 */
413*4882a593Smuzhiyun 	if ((rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
414*4882a593Smuzhiyun 	    (rates[0].count <= dev->wl->hw->conf.long_frame_max_tx_count)) {
415*4882a593Smuzhiyun 		rates[0].count = dev->wl->hw->conf.long_frame_max_tx_count;
416*4882a593Smuzhiyun 		mac_ctl |= B43_TXH_MAC_LONGFRAME;
417*4882a593Smuzhiyun 	} else {
418*4882a593Smuzhiyun 		rates[0].count = dev->wl->hw->conf.short_frame_max_tx_count;
419*4882a593Smuzhiyun 	}
420*4882a593Smuzhiyun 
421*4882a593Smuzhiyun 	/* Generate the RTS or CTS-to-self frame */
422*4882a593Smuzhiyun 	if ((rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
423*4882a593Smuzhiyun 	    (rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)) {
424*4882a593Smuzhiyun 		unsigned int len;
425*4882a593Smuzhiyun 		struct ieee80211_hdr *hdr;
426*4882a593Smuzhiyun 		int rts_rate, rts_rate_fb;
427*4882a593Smuzhiyun 		int rts_rate_ofdm, rts_rate_fb_ofdm;
428*4882a593Smuzhiyun 		struct b43_plcp_hdr6 *plcp;
429*4882a593Smuzhiyun 		struct ieee80211_rate *rts_cts_rate;
430*4882a593Smuzhiyun 
431*4882a593Smuzhiyun 		rts_cts_rate = ieee80211_get_rts_cts_rate(dev->wl->hw, info);
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun 		rts_rate = rts_cts_rate ? rts_cts_rate->hw_value : B43_CCK_RATE_1MB;
434*4882a593Smuzhiyun 		rts_rate_ofdm = b43_is_ofdm_rate(rts_rate);
435*4882a593Smuzhiyun 		rts_rate_fb = b43_calc_fallback_rate(rts_rate, phy->gmode);
436*4882a593Smuzhiyun 		rts_rate_fb_ofdm = b43_is_ofdm_rate(rts_rate_fb);
437*4882a593Smuzhiyun 
438*4882a593Smuzhiyun 		if (rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
439*4882a593Smuzhiyun 			struct ieee80211_cts *cts;
440*4882a593Smuzhiyun 
441*4882a593Smuzhiyun 			switch (dev->fw.hdr_format) {
442*4882a593Smuzhiyun 			case B43_FW_HDR_598:
443*4882a593Smuzhiyun 				cts = (struct ieee80211_cts *)
444*4882a593Smuzhiyun 					(txhdr->format_598.rts_frame);
445*4882a593Smuzhiyun 				break;
446*4882a593Smuzhiyun 			case B43_FW_HDR_351:
447*4882a593Smuzhiyun 				cts = (struct ieee80211_cts *)
448*4882a593Smuzhiyun 					(txhdr->format_351.rts_frame);
449*4882a593Smuzhiyun 				break;
450*4882a593Smuzhiyun 			case B43_FW_HDR_410:
451*4882a593Smuzhiyun 				cts = (struct ieee80211_cts *)
452*4882a593Smuzhiyun 					(txhdr->format_410.rts_frame);
453*4882a593Smuzhiyun 				break;
454*4882a593Smuzhiyun 			}
455*4882a593Smuzhiyun 			ieee80211_ctstoself_get(dev->wl->hw, info->control.vif,
456*4882a593Smuzhiyun 						fragment_data, fragment_len,
457*4882a593Smuzhiyun 						info, cts);
458*4882a593Smuzhiyun 			mac_ctl |= B43_TXH_MAC_SENDCTS;
459*4882a593Smuzhiyun 			len = sizeof(struct ieee80211_cts);
460*4882a593Smuzhiyun 		} else {
461*4882a593Smuzhiyun 			struct ieee80211_rts *rts;
462*4882a593Smuzhiyun 
463*4882a593Smuzhiyun 			switch (dev->fw.hdr_format) {
464*4882a593Smuzhiyun 			case B43_FW_HDR_598:
465*4882a593Smuzhiyun 				rts = (struct ieee80211_rts *)
466*4882a593Smuzhiyun 					(txhdr->format_598.rts_frame);
467*4882a593Smuzhiyun 				break;
468*4882a593Smuzhiyun 			case B43_FW_HDR_351:
469*4882a593Smuzhiyun 				rts = (struct ieee80211_rts *)
470*4882a593Smuzhiyun 					(txhdr->format_351.rts_frame);
471*4882a593Smuzhiyun 				break;
472*4882a593Smuzhiyun 			case B43_FW_HDR_410:
473*4882a593Smuzhiyun 				rts = (struct ieee80211_rts *)
474*4882a593Smuzhiyun 					(txhdr->format_410.rts_frame);
475*4882a593Smuzhiyun 				break;
476*4882a593Smuzhiyun 			}
477*4882a593Smuzhiyun 			ieee80211_rts_get(dev->wl->hw, info->control.vif,
478*4882a593Smuzhiyun 					  fragment_data, fragment_len,
479*4882a593Smuzhiyun 					  info, rts);
480*4882a593Smuzhiyun 			mac_ctl |= B43_TXH_MAC_SENDRTS;
481*4882a593Smuzhiyun 			len = sizeof(struct ieee80211_rts);
482*4882a593Smuzhiyun 		}
483*4882a593Smuzhiyun 		len += FCS_LEN;
484*4882a593Smuzhiyun 
485*4882a593Smuzhiyun 		/* Generate the PLCP headers for the RTS/CTS frame */
486*4882a593Smuzhiyun 		switch (dev->fw.hdr_format) {
487*4882a593Smuzhiyun 		case B43_FW_HDR_598:
488*4882a593Smuzhiyun 			plcp = &txhdr->format_598.rts_plcp;
489*4882a593Smuzhiyun 			break;
490*4882a593Smuzhiyun 		case B43_FW_HDR_351:
491*4882a593Smuzhiyun 			plcp = &txhdr->format_351.rts_plcp;
492*4882a593Smuzhiyun 			break;
493*4882a593Smuzhiyun 		case B43_FW_HDR_410:
494*4882a593Smuzhiyun 			plcp = &txhdr->format_410.rts_plcp;
495*4882a593Smuzhiyun 			break;
496*4882a593Smuzhiyun 		}
497*4882a593Smuzhiyun 		b43_generate_plcp_hdr((struct b43_plcp_hdr4 *)plcp,
498*4882a593Smuzhiyun 				      len, rts_rate);
499*4882a593Smuzhiyun 		plcp = &txhdr->rts_plcp_fb;
500*4882a593Smuzhiyun 		b43_generate_plcp_hdr((struct b43_plcp_hdr4 *)plcp,
501*4882a593Smuzhiyun 				      len, rts_rate_fb);
502*4882a593Smuzhiyun 
503*4882a593Smuzhiyun 		switch (dev->fw.hdr_format) {
504*4882a593Smuzhiyun 		case B43_FW_HDR_598:
505*4882a593Smuzhiyun 			hdr = (struct ieee80211_hdr *)
506*4882a593Smuzhiyun 				(&txhdr->format_598.rts_frame);
507*4882a593Smuzhiyun 			break;
508*4882a593Smuzhiyun 		case B43_FW_HDR_351:
509*4882a593Smuzhiyun 			hdr = (struct ieee80211_hdr *)
510*4882a593Smuzhiyun 				(&txhdr->format_351.rts_frame);
511*4882a593Smuzhiyun 			break;
512*4882a593Smuzhiyun 		case B43_FW_HDR_410:
513*4882a593Smuzhiyun 			hdr = (struct ieee80211_hdr *)
514*4882a593Smuzhiyun 				(&txhdr->format_410.rts_frame);
515*4882a593Smuzhiyun 			break;
516*4882a593Smuzhiyun 		}
517*4882a593Smuzhiyun 		txhdr->rts_dur_fb = hdr->duration_id;
518*4882a593Smuzhiyun 
519*4882a593Smuzhiyun 		if (rts_rate_ofdm) {
520*4882a593Smuzhiyun 			extra_ft |= B43_TXH_EFT_RTS_OFDM;
521*4882a593Smuzhiyun 			txhdr->phy_rate_rts =
522*4882a593Smuzhiyun 			    b43_plcp_get_ratecode_ofdm(rts_rate);
523*4882a593Smuzhiyun 		} else {
524*4882a593Smuzhiyun 			extra_ft |= B43_TXH_EFT_RTS_CCK;
525*4882a593Smuzhiyun 			txhdr->phy_rate_rts =
526*4882a593Smuzhiyun 			    b43_plcp_get_ratecode_cck(rts_rate);
527*4882a593Smuzhiyun 		}
528*4882a593Smuzhiyun 		if (rts_rate_fb_ofdm)
529*4882a593Smuzhiyun 			extra_ft |= B43_TXH_EFT_RTSFB_OFDM;
530*4882a593Smuzhiyun 		else
531*4882a593Smuzhiyun 			extra_ft |= B43_TXH_EFT_RTSFB_CCK;
532*4882a593Smuzhiyun 
533*4882a593Smuzhiyun 		if (rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS &&
534*4882a593Smuzhiyun 		    fill_phy_ctl1) {
535*4882a593Smuzhiyun 			txhdr->phy_ctl1_rts = cpu_to_le16(
536*4882a593Smuzhiyun 				b43_generate_tx_phy_ctl1(dev, rts_rate));
537*4882a593Smuzhiyun 			txhdr->phy_ctl1_rts_fb = cpu_to_le16(
538*4882a593Smuzhiyun 				b43_generate_tx_phy_ctl1(dev, rts_rate_fb));
539*4882a593Smuzhiyun 		}
540*4882a593Smuzhiyun 	}
541*4882a593Smuzhiyun 
542*4882a593Smuzhiyun 	/* Magic cookie */
543*4882a593Smuzhiyun 	switch (dev->fw.hdr_format) {
544*4882a593Smuzhiyun 	case B43_FW_HDR_598:
545*4882a593Smuzhiyun 		txhdr->format_598.cookie = cpu_to_le16(cookie);
546*4882a593Smuzhiyun 		break;
547*4882a593Smuzhiyun 	case B43_FW_HDR_351:
548*4882a593Smuzhiyun 		txhdr->format_351.cookie = cpu_to_le16(cookie);
549*4882a593Smuzhiyun 		break;
550*4882a593Smuzhiyun 	case B43_FW_HDR_410:
551*4882a593Smuzhiyun 		txhdr->format_410.cookie = cpu_to_le16(cookie);
552*4882a593Smuzhiyun 		break;
553*4882a593Smuzhiyun 	}
554*4882a593Smuzhiyun 
555*4882a593Smuzhiyun 	if (fill_phy_ctl1) {
556*4882a593Smuzhiyun 		txhdr->phy_ctl1 =
557*4882a593Smuzhiyun 			cpu_to_le16(b43_generate_tx_phy_ctl1(dev, rate));
558*4882a593Smuzhiyun 		txhdr->phy_ctl1_fb =
559*4882a593Smuzhiyun 			cpu_to_le16(b43_generate_tx_phy_ctl1(dev, rate_fb));
560*4882a593Smuzhiyun 	}
561*4882a593Smuzhiyun 
562*4882a593Smuzhiyun 	/* Apply the bitfields */
563*4882a593Smuzhiyun 	txhdr->mac_ctl = cpu_to_le32(mac_ctl);
564*4882a593Smuzhiyun 	txhdr->phy_ctl = cpu_to_le16(phy_ctl);
565*4882a593Smuzhiyun 	txhdr->extra_ft = extra_ft;
566*4882a593Smuzhiyun 
567*4882a593Smuzhiyun 	return 0;
568*4882a593Smuzhiyun }
569*4882a593Smuzhiyun 
b43_rssi_postprocess(struct b43_wldev * dev,u8 in_rssi,int ofdm,int adjust_2053,int adjust_2050)570*4882a593Smuzhiyun static s8 b43_rssi_postprocess(struct b43_wldev *dev,
571*4882a593Smuzhiyun 			       u8 in_rssi, int ofdm,
572*4882a593Smuzhiyun 			       int adjust_2053, int adjust_2050)
573*4882a593Smuzhiyun {
574*4882a593Smuzhiyun 	struct b43_phy *phy = &dev->phy;
575*4882a593Smuzhiyun 	struct b43_phy_g *gphy = phy->g;
576*4882a593Smuzhiyun 	s32 tmp;
577*4882a593Smuzhiyun 
578*4882a593Smuzhiyun 	switch (phy->radio_ver) {
579*4882a593Smuzhiyun 	case 0x2050:
580*4882a593Smuzhiyun 		if (ofdm) {
581*4882a593Smuzhiyun 			tmp = in_rssi;
582*4882a593Smuzhiyun 			if (tmp > 127)
583*4882a593Smuzhiyun 				tmp -= 256;
584*4882a593Smuzhiyun 			tmp *= 73;
585*4882a593Smuzhiyun 			tmp /= 64;
586*4882a593Smuzhiyun 			if (adjust_2050)
587*4882a593Smuzhiyun 				tmp += 25;
588*4882a593Smuzhiyun 			else
589*4882a593Smuzhiyun 				tmp -= 3;
590*4882a593Smuzhiyun 		} else {
591*4882a593Smuzhiyun 			if (dev->dev->bus_sprom->
592*4882a593Smuzhiyun 			    boardflags_lo & B43_BFL_RSSI) {
593*4882a593Smuzhiyun 				if (in_rssi > 63)
594*4882a593Smuzhiyun 					in_rssi = 63;
595*4882a593Smuzhiyun 				B43_WARN_ON(phy->type != B43_PHYTYPE_G);
596*4882a593Smuzhiyun 				tmp = gphy->nrssi_lt[in_rssi];
597*4882a593Smuzhiyun 				tmp = 31 - tmp;
598*4882a593Smuzhiyun 				tmp *= -131;
599*4882a593Smuzhiyun 				tmp /= 128;
600*4882a593Smuzhiyun 				tmp -= 57;
601*4882a593Smuzhiyun 			} else {
602*4882a593Smuzhiyun 				tmp = in_rssi;
603*4882a593Smuzhiyun 				tmp = 31 - tmp;
604*4882a593Smuzhiyun 				tmp *= -149;
605*4882a593Smuzhiyun 				tmp /= 128;
606*4882a593Smuzhiyun 				tmp -= 68;
607*4882a593Smuzhiyun 			}
608*4882a593Smuzhiyun 			if (phy->type == B43_PHYTYPE_G && adjust_2050)
609*4882a593Smuzhiyun 				tmp += 25;
610*4882a593Smuzhiyun 		}
611*4882a593Smuzhiyun 		break;
612*4882a593Smuzhiyun 	case 0x2060:
613*4882a593Smuzhiyun 		if (in_rssi > 127)
614*4882a593Smuzhiyun 			tmp = in_rssi - 256;
615*4882a593Smuzhiyun 		else
616*4882a593Smuzhiyun 			tmp = in_rssi;
617*4882a593Smuzhiyun 		break;
618*4882a593Smuzhiyun 	default:
619*4882a593Smuzhiyun 		tmp = in_rssi;
620*4882a593Smuzhiyun 		tmp -= 11;
621*4882a593Smuzhiyun 		tmp *= 103;
622*4882a593Smuzhiyun 		tmp /= 64;
623*4882a593Smuzhiyun 		if (adjust_2053)
624*4882a593Smuzhiyun 			tmp -= 109;
625*4882a593Smuzhiyun 		else
626*4882a593Smuzhiyun 			tmp -= 83;
627*4882a593Smuzhiyun 	}
628*4882a593Smuzhiyun 
629*4882a593Smuzhiyun 	return (s8) tmp;
630*4882a593Smuzhiyun }
631*4882a593Smuzhiyun 
b43_rx(struct b43_wldev * dev,struct sk_buff * skb,const void * _rxhdr)632*4882a593Smuzhiyun void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr)
633*4882a593Smuzhiyun {
634*4882a593Smuzhiyun 	struct ieee80211_rx_status status;
635*4882a593Smuzhiyun 	struct b43_plcp_hdr6 *plcp;
636*4882a593Smuzhiyun 	struct ieee80211_hdr *wlhdr;
637*4882a593Smuzhiyun 	const struct b43_rxhdr_fw4 *rxhdr = _rxhdr;
638*4882a593Smuzhiyun 	__le16 fctl;
639*4882a593Smuzhiyun 	u16 phystat0, phystat3;
640*4882a593Smuzhiyun 	u16 chanstat, mactime;
641*4882a593Smuzhiyun 	u32 macstat;
642*4882a593Smuzhiyun 	u16 chanid;
643*4882a593Smuzhiyun 	int padding, rate_idx;
644*4882a593Smuzhiyun 
645*4882a593Smuzhiyun 	memset(&status, 0, sizeof(status));
646*4882a593Smuzhiyun 
647*4882a593Smuzhiyun 	/* Get metadata about the frame from the header. */
648*4882a593Smuzhiyun 	phystat0 = le16_to_cpu(rxhdr->phy_status0);
649*4882a593Smuzhiyun 	phystat3 = le16_to_cpu(rxhdr->phy_status3);
650*4882a593Smuzhiyun 	switch (dev->fw.hdr_format) {
651*4882a593Smuzhiyun 	case B43_FW_HDR_598:
652*4882a593Smuzhiyun 		macstat = le32_to_cpu(rxhdr->format_598.mac_status);
653*4882a593Smuzhiyun 		mactime = le16_to_cpu(rxhdr->format_598.mac_time);
654*4882a593Smuzhiyun 		chanstat = le16_to_cpu(rxhdr->format_598.channel);
655*4882a593Smuzhiyun 		break;
656*4882a593Smuzhiyun 	case B43_FW_HDR_410:
657*4882a593Smuzhiyun 	case B43_FW_HDR_351:
658*4882a593Smuzhiyun 		macstat = le32_to_cpu(rxhdr->format_351.mac_status);
659*4882a593Smuzhiyun 		mactime = le16_to_cpu(rxhdr->format_351.mac_time);
660*4882a593Smuzhiyun 		chanstat = le16_to_cpu(rxhdr->format_351.channel);
661*4882a593Smuzhiyun 		break;
662*4882a593Smuzhiyun 	}
663*4882a593Smuzhiyun 
664*4882a593Smuzhiyun 	if (unlikely(macstat & B43_RX_MAC_FCSERR)) {
665*4882a593Smuzhiyun 		dev->wl->ieee_stats.dot11FCSErrorCount++;
666*4882a593Smuzhiyun 		status.flag |= RX_FLAG_FAILED_FCS_CRC;
667*4882a593Smuzhiyun 	}
668*4882a593Smuzhiyun 	if (unlikely(phystat0 & (B43_RX_PHYST0_PLCPHCF | B43_RX_PHYST0_PLCPFV)))
669*4882a593Smuzhiyun 		status.flag |= RX_FLAG_FAILED_PLCP_CRC;
670*4882a593Smuzhiyun 	if (phystat0 & B43_RX_PHYST0_SHORTPRMBL)
671*4882a593Smuzhiyun 		status.enc_flags |= RX_ENC_FLAG_SHORTPRE;
672*4882a593Smuzhiyun 	if (macstat & B43_RX_MAC_DECERR) {
673*4882a593Smuzhiyun 		/* Decryption with the given key failed.
674*4882a593Smuzhiyun 		 * Drop the packet. We also won't be able to decrypt it with
675*4882a593Smuzhiyun 		 * the key in software. */
676*4882a593Smuzhiyun 		goto drop;
677*4882a593Smuzhiyun 	}
678*4882a593Smuzhiyun 
679*4882a593Smuzhiyun 	/* Skip PLCP and padding */
680*4882a593Smuzhiyun 	padding = (macstat & B43_RX_MAC_PADDING) ? 2 : 0;
681*4882a593Smuzhiyun 	if (unlikely(skb->len < (sizeof(struct b43_plcp_hdr6) + padding))) {
682*4882a593Smuzhiyun 		b43dbg(dev->wl, "RX: Packet size underrun (1)\n");
683*4882a593Smuzhiyun 		goto drop;
684*4882a593Smuzhiyun 	}
685*4882a593Smuzhiyun 	plcp = (struct b43_plcp_hdr6 *)(skb->data + padding);
686*4882a593Smuzhiyun 	skb_pull(skb, sizeof(struct b43_plcp_hdr6) + padding);
687*4882a593Smuzhiyun 	/* The skb contains the Wireless Header + payload data now */
688*4882a593Smuzhiyun 	if (unlikely(skb->len < (2 + 2 + 6 /*minimum hdr */  + FCS_LEN))) {
689*4882a593Smuzhiyun 		b43dbg(dev->wl, "RX: Packet size underrun (2)\n");
690*4882a593Smuzhiyun 		goto drop;
691*4882a593Smuzhiyun 	}
692*4882a593Smuzhiyun 	wlhdr = (struct ieee80211_hdr *)(skb->data);
693*4882a593Smuzhiyun 	fctl = wlhdr->frame_control;
694*4882a593Smuzhiyun 
695*4882a593Smuzhiyun 	if (macstat & B43_RX_MAC_DEC) {
696*4882a593Smuzhiyun 		unsigned int keyidx;
697*4882a593Smuzhiyun 		int wlhdr_len;
698*4882a593Smuzhiyun 
699*4882a593Smuzhiyun 		keyidx = ((macstat & B43_RX_MAC_KEYIDX)
700*4882a593Smuzhiyun 			  >> B43_RX_MAC_KEYIDX_SHIFT);
701*4882a593Smuzhiyun 		/* We must adjust the key index here. We want the "physical"
702*4882a593Smuzhiyun 		 * key index, but the ucode passed it slightly different.
703*4882a593Smuzhiyun 		 */
704*4882a593Smuzhiyun 		keyidx = b43_kidx_to_raw(dev, keyidx);
705*4882a593Smuzhiyun 		B43_WARN_ON(keyidx >= ARRAY_SIZE(dev->key));
706*4882a593Smuzhiyun 
707*4882a593Smuzhiyun 		if (dev->key[keyidx].algorithm != B43_SEC_ALGO_NONE) {
708*4882a593Smuzhiyun 			wlhdr_len = ieee80211_hdrlen(fctl);
709*4882a593Smuzhiyun 			if (unlikely(skb->len < (wlhdr_len + 3))) {
710*4882a593Smuzhiyun 				b43dbg(dev->wl,
711*4882a593Smuzhiyun 				       "RX: Packet size underrun (3)\n");
712*4882a593Smuzhiyun 				goto drop;
713*4882a593Smuzhiyun 			}
714*4882a593Smuzhiyun 			status.flag |= RX_FLAG_DECRYPTED;
715*4882a593Smuzhiyun 		}
716*4882a593Smuzhiyun 	}
717*4882a593Smuzhiyun 
718*4882a593Smuzhiyun 	/* Link quality statistics */
719*4882a593Smuzhiyun 	switch (chanstat & B43_RX_CHAN_PHYTYPE) {
720*4882a593Smuzhiyun 	case B43_PHYTYPE_HT:
721*4882a593Smuzhiyun 		/* TODO: is max the right choice? */
722*4882a593Smuzhiyun 		status.signal = max_t(__s8,
723*4882a593Smuzhiyun 			max(rxhdr->phy_ht_power0, rxhdr->phy_ht_power1),
724*4882a593Smuzhiyun 			rxhdr->phy_ht_power2);
725*4882a593Smuzhiyun 		break;
726*4882a593Smuzhiyun 	case B43_PHYTYPE_N:
727*4882a593Smuzhiyun 		/* Broadcom has code for min and avg, but always uses max */
728*4882a593Smuzhiyun 		if (rxhdr->power0 == 16 || rxhdr->power0 == 32)
729*4882a593Smuzhiyun 			status.signal = max(rxhdr->power1, rxhdr->power2);
730*4882a593Smuzhiyun 		else
731*4882a593Smuzhiyun 			status.signal = max(rxhdr->power0, rxhdr->power1);
732*4882a593Smuzhiyun 		break;
733*4882a593Smuzhiyun 	case B43_PHYTYPE_B:
734*4882a593Smuzhiyun 	case B43_PHYTYPE_G:
735*4882a593Smuzhiyun 	case B43_PHYTYPE_LP:
736*4882a593Smuzhiyun 		status.signal = b43_rssi_postprocess(dev, rxhdr->jssi,
737*4882a593Smuzhiyun 						  (phystat0 & B43_RX_PHYST0_OFDM),
738*4882a593Smuzhiyun 						  (phystat0 & B43_RX_PHYST0_GAINCTL),
739*4882a593Smuzhiyun 						  (phystat3 & B43_RX_PHYST3_TRSTATE));
740*4882a593Smuzhiyun 		break;
741*4882a593Smuzhiyun 	}
742*4882a593Smuzhiyun 
743*4882a593Smuzhiyun 	if (phystat0 & B43_RX_PHYST0_OFDM)
744*4882a593Smuzhiyun 		rate_idx = b43_plcp_get_bitrate_idx_ofdm(plcp,
745*4882a593Smuzhiyun 					!!(chanstat & B43_RX_CHAN_5GHZ));
746*4882a593Smuzhiyun 	else
747*4882a593Smuzhiyun 		rate_idx = b43_plcp_get_bitrate_idx_cck(plcp);
748*4882a593Smuzhiyun 	if (unlikely(rate_idx == -1)) {
749*4882a593Smuzhiyun 		/* PLCP seems to be corrupted.
750*4882a593Smuzhiyun 		 * Drop the frame, if we are not interested in corrupted frames. */
751*4882a593Smuzhiyun 		if (!(dev->wl->filter_flags & FIF_PLCPFAIL))
752*4882a593Smuzhiyun 			goto drop;
753*4882a593Smuzhiyun 	}
754*4882a593Smuzhiyun 	status.rate_idx = rate_idx;
755*4882a593Smuzhiyun 	status.antenna = !!(phystat0 & B43_RX_PHYST0_ANT);
756*4882a593Smuzhiyun 
757*4882a593Smuzhiyun 	/*
758*4882a593Smuzhiyun 	 * All frames on monitor interfaces and beacons always need a full
759*4882a593Smuzhiyun 	 * 64-bit timestamp. Monitor interfaces need it for diagnostic
760*4882a593Smuzhiyun 	 * purposes and beacons for IBSS merging.
761*4882a593Smuzhiyun 	 * This code assumes we get to process the packet within 16 bits
762*4882a593Smuzhiyun 	 * of timestamp, i.e. about 65 milliseconds after the PHY received
763*4882a593Smuzhiyun 	 * the first symbol.
764*4882a593Smuzhiyun 	 */
765*4882a593Smuzhiyun 	if (ieee80211_is_beacon(fctl) || dev->wl->radiotap_enabled) {
766*4882a593Smuzhiyun 		u16 low_mactime_now;
767*4882a593Smuzhiyun 
768*4882a593Smuzhiyun 		b43_tsf_read(dev, &status.mactime);
769*4882a593Smuzhiyun 		low_mactime_now = status.mactime;
770*4882a593Smuzhiyun 		status.mactime = status.mactime & ~0xFFFFULL;
771*4882a593Smuzhiyun 		status.mactime += mactime;
772*4882a593Smuzhiyun 		if (low_mactime_now <= mactime)
773*4882a593Smuzhiyun 			status.mactime -= 0x10000;
774*4882a593Smuzhiyun 		status.flag |= RX_FLAG_MACTIME_START;
775*4882a593Smuzhiyun 	}
776*4882a593Smuzhiyun 
777*4882a593Smuzhiyun 	chanid = (chanstat & B43_RX_CHAN_ID) >> B43_RX_CHAN_ID_SHIFT;
778*4882a593Smuzhiyun 	switch (chanstat & B43_RX_CHAN_PHYTYPE) {
779*4882a593Smuzhiyun 	case B43_PHYTYPE_G:
780*4882a593Smuzhiyun 		status.band = NL80211_BAND_2GHZ;
781*4882a593Smuzhiyun 		/* Somewhere between 478.104 and 508.1084 firmware for G-PHY
782*4882a593Smuzhiyun 		 * has been modified to be compatible with N-PHY and others.
783*4882a593Smuzhiyun 		 */
784*4882a593Smuzhiyun 		if (dev->fw.rev >= 508)
785*4882a593Smuzhiyun 			status.freq = ieee80211_channel_to_frequency(chanid, status.band);
786*4882a593Smuzhiyun 		else
787*4882a593Smuzhiyun 			status.freq = chanid + 2400;
788*4882a593Smuzhiyun 		break;
789*4882a593Smuzhiyun 	case B43_PHYTYPE_N:
790*4882a593Smuzhiyun 	case B43_PHYTYPE_LP:
791*4882a593Smuzhiyun 	case B43_PHYTYPE_HT:
792*4882a593Smuzhiyun 		/* chanid is the SHM channel cookie. Which is the plain
793*4882a593Smuzhiyun 		 * channel number in b43. */
794*4882a593Smuzhiyun 		if (chanstat & B43_RX_CHAN_5GHZ)
795*4882a593Smuzhiyun 			status.band = NL80211_BAND_5GHZ;
796*4882a593Smuzhiyun 		else
797*4882a593Smuzhiyun 			status.band = NL80211_BAND_2GHZ;
798*4882a593Smuzhiyun 		status.freq =
799*4882a593Smuzhiyun 			ieee80211_channel_to_frequency(chanid, status.band);
800*4882a593Smuzhiyun 		break;
801*4882a593Smuzhiyun 	default:
802*4882a593Smuzhiyun 		B43_WARN_ON(1);
803*4882a593Smuzhiyun 		goto drop;
804*4882a593Smuzhiyun 	}
805*4882a593Smuzhiyun 
806*4882a593Smuzhiyun 	memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
807*4882a593Smuzhiyun 	ieee80211_rx_ni(dev->wl->hw, skb);
808*4882a593Smuzhiyun 
809*4882a593Smuzhiyun #if B43_DEBUG
810*4882a593Smuzhiyun 	dev->rx_count++;
811*4882a593Smuzhiyun #endif
812*4882a593Smuzhiyun 	return;
813*4882a593Smuzhiyun drop:
814*4882a593Smuzhiyun 	dev_kfree_skb_any(skb);
815*4882a593Smuzhiyun }
816*4882a593Smuzhiyun 
b43_handle_txstatus(struct b43_wldev * dev,const struct b43_txstatus * status)817*4882a593Smuzhiyun void b43_handle_txstatus(struct b43_wldev *dev,
818*4882a593Smuzhiyun 			 const struct b43_txstatus *status)
819*4882a593Smuzhiyun {
820*4882a593Smuzhiyun 	b43_debugfs_log_txstat(dev, status);
821*4882a593Smuzhiyun 
822*4882a593Smuzhiyun 	if (status->intermediate)
823*4882a593Smuzhiyun 		return;
824*4882a593Smuzhiyun 	if (status->for_ampdu)
825*4882a593Smuzhiyun 		return;
826*4882a593Smuzhiyun 	if (!status->acked)
827*4882a593Smuzhiyun 		dev->wl->ieee_stats.dot11ACKFailureCount++;
828*4882a593Smuzhiyun 	if (status->rts_count) {
829*4882a593Smuzhiyun 		if (status->rts_count == 0xF)	//FIXME
830*4882a593Smuzhiyun 			dev->wl->ieee_stats.dot11RTSFailureCount++;
831*4882a593Smuzhiyun 		else
832*4882a593Smuzhiyun 			dev->wl->ieee_stats.dot11RTSSuccessCount++;
833*4882a593Smuzhiyun 	}
834*4882a593Smuzhiyun 
835*4882a593Smuzhiyun 	if (b43_using_pio_transfers(dev))
836*4882a593Smuzhiyun 		b43_pio_handle_txstatus(dev, status);
837*4882a593Smuzhiyun 	else
838*4882a593Smuzhiyun 		b43_dma_handle_txstatus(dev, status);
839*4882a593Smuzhiyun 
840*4882a593Smuzhiyun 	b43_phy_txpower_check(dev, 0);
841*4882a593Smuzhiyun }
842*4882a593Smuzhiyun 
843*4882a593Smuzhiyun /* Fill out the mac80211 TXstatus report based on the b43-specific
844*4882a593Smuzhiyun  * txstatus report data. This returns a boolean whether the frame was
845*4882a593Smuzhiyun  * successfully transmitted. */
b43_fill_txstatus_report(struct b43_wldev * dev,struct ieee80211_tx_info * report,const struct b43_txstatus * status)846*4882a593Smuzhiyun bool b43_fill_txstatus_report(struct b43_wldev *dev,
847*4882a593Smuzhiyun 			      struct ieee80211_tx_info *report,
848*4882a593Smuzhiyun 			      const struct b43_txstatus *status)
849*4882a593Smuzhiyun {
850*4882a593Smuzhiyun 	bool frame_success = true;
851*4882a593Smuzhiyun 	int retry_limit;
852*4882a593Smuzhiyun 
853*4882a593Smuzhiyun 	/* preserve the confiured retry limit before clearing the status
854*4882a593Smuzhiyun 	 * The xmit function has overwritten the rc's value with the actual
855*4882a593Smuzhiyun 	 * retry limit done by the hardware */
856*4882a593Smuzhiyun 	retry_limit = report->status.rates[0].count;
857*4882a593Smuzhiyun 	ieee80211_tx_info_clear_status(report);
858*4882a593Smuzhiyun 
859*4882a593Smuzhiyun 	if (status->acked) {
860*4882a593Smuzhiyun 		/* The frame was ACKed. */
861*4882a593Smuzhiyun 		report->flags |= IEEE80211_TX_STAT_ACK;
862*4882a593Smuzhiyun 	} else {
863*4882a593Smuzhiyun 		/* The frame was not ACKed... */
864*4882a593Smuzhiyun 		if (!(report->flags & IEEE80211_TX_CTL_NO_ACK)) {
865*4882a593Smuzhiyun 			/* ...but we expected an ACK. */
866*4882a593Smuzhiyun 			frame_success = false;
867*4882a593Smuzhiyun 		}
868*4882a593Smuzhiyun 	}
869*4882a593Smuzhiyun 	if (status->frame_count == 0) {
870*4882a593Smuzhiyun 		/* The frame was not transmitted at all. */
871*4882a593Smuzhiyun 		report->status.rates[0].count = 0;
872*4882a593Smuzhiyun 	} else if (status->rts_count > dev->wl->hw->conf.short_frame_max_tx_count) {
873*4882a593Smuzhiyun 		/*
874*4882a593Smuzhiyun 		 * If the short retries (RTS, not data frame) have exceeded
875*4882a593Smuzhiyun 		 * the limit, the hw will not have tried the selected rate,
876*4882a593Smuzhiyun 		 * but will have used the fallback rate instead.
877*4882a593Smuzhiyun 		 * Don't let the rate control count attempts for the selected
878*4882a593Smuzhiyun 		 * rate in this case, otherwise the statistics will be off.
879*4882a593Smuzhiyun 		 */
880*4882a593Smuzhiyun 		report->status.rates[0].count = 0;
881*4882a593Smuzhiyun 		report->status.rates[1].count = status->frame_count;
882*4882a593Smuzhiyun 	} else {
883*4882a593Smuzhiyun 		if (status->frame_count > retry_limit) {
884*4882a593Smuzhiyun 			report->status.rates[0].count = retry_limit;
885*4882a593Smuzhiyun 			report->status.rates[1].count = status->frame_count -
886*4882a593Smuzhiyun 					retry_limit;
887*4882a593Smuzhiyun 
888*4882a593Smuzhiyun 		} else {
889*4882a593Smuzhiyun 			report->status.rates[0].count = status->frame_count;
890*4882a593Smuzhiyun 			report->status.rates[1].idx = -1;
891*4882a593Smuzhiyun 		}
892*4882a593Smuzhiyun 	}
893*4882a593Smuzhiyun 
894*4882a593Smuzhiyun 	return frame_success;
895*4882a593Smuzhiyun }
896*4882a593Smuzhiyun 
897*4882a593Smuzhiyun /* Stop any TX operation on the device (suspend the hardware queues) */
b43_tx_suspend(struct b43_wldev * dev)898*4882a593Smuzhiyun void b43_tx_suspend(struct b43_wldev *dev)
899*4882a593Smuzhiyun {
900*4882a593Smuzhiyun 	if (b43_using_pio_transfers(dev))
901*4882a593Smuzhiyun 		b43_pio_tx_suspend(dev);
902*4882a593Smuzhiyun 	else
903*4882a593Smuzhiyun 		b43_dma_tx_suspend(dev);
904*4882a593Smuzhiyun }
905*4882a593Smuzhiyun 
906*4882a593Smuzhiyun /* Resume any TX operation on the device (resume the hardware queues) */
b43_tx_resume(struct b43_wldev * dev)907*4882a593Smuzhiyun void b43_tx_resume(struct b43_wldev *dev)
908*4882a593Smuzhiyun {
909*4882a593Smuzhiyun 	if (b43_using_pio_transfers(dev))
910*4882a593Smuzhiyun 		b43_pio_tx_resume(dev);
911*4882a593Smuzhiyun 	else
912*4882a593Smuzhiyun 		b43_dma_tx_resume(dev);
913*4882a593Smuzhiyun }
914