1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef B43_RADIO_2057_H_ 3*4882a593Smuzhiyun #define B43_RADIO_2057_H_ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <linux/types.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include "tables_nphy.h" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define R2057_DACBUF_VINCM_CORE0 0x000 10*4882a593Smuzhiyun #define R2057_IDCODE 0x001 11*4882a593Smuzhiyun #define R2057_RCCAL_MASTER 0x002 12*4882a593Smuzhiyun #define R2057_RCCAL_CAP_SIZE 0x003 13*4882a593Smuzhiyun #define R2057_RCAL_CONFIG 0x004 14*4882a593Smuzhiyun #define R2057_GPAIO_CONFIG 0x005 15*4882a593Smuzhiyun #define R2057_GPAIO_SEL1 0x006 16*4882a593Smuzhiyun #define R2057_GPAIO_SEL0 0x007 17*4882a593Smuzhiyun #define R2057_CLPO_CONFIG 0x008 18*4882a593Smuzhiyun #define R2057_BANDGAP_CONFIG 0x009 19*4882a593Smuzhiyun #define R2057_BANDGAP_RCAL_TRIM 0x00a 20*4882a593Smuzhiyun #define R2057_AFEREG_CONFIG 0x00b 21*4882a593Smuzhiyun #define R2057_TEMPSENSE_CONFIG 0x00c 22*4882a593Smuzhiyun #define R2057_XTAL_CONFIG1 0x00d 23*4882a593Smuzhiyun #define R2057_XTAL_ICORE_SIZE 0x00e 24*4882a593Smuzhiyun #define R2057_XTAL_BUF_SIZE 0x00f 25*4882a593Smuzhiyun #define R2057_XTAL_PULLCAP_SIZE 0x010 26*4882a593Smuzhiyun #define R2057_RFPLL_MASTER 0x011 27*4882a593Smuzhiyun #define R2057_VCOMONITOR_VTH_L 0x012 28*4882a593Smuzhiyun #define R2057_VCOMONITOR_VTH_H 0x013 29*4882a593Smuzhiyun #define R2057_VCOCAL_BIASRESET_RFPLLREG_VOUT 0x014 30*4882a593Smuzhiyun #define R2057_VCO_VARCSIZE_IDAC 0x015 31*4882a593Smuzhiyun #define R2057_VCOCAL_COUNTVAL0 0x016 32*4882a593Smuzhiyun #define R2057_VCOCAL_COUNTVAL1 0x017 33*4882a593Smuzhiyun #define R2057_VCOCAL_INTCLK_COUNT 0x018 34*4882a593Smuzhiyun #define R2057_VCOCAL_MASTER 0x019 35*4882a593Smuzhiyun #define R2057_VCOCAL_NUMCAPCHANGE 0x01a 36*4882a593Smuzhiyun #define R2057_VCOCAL_WINSIZE 0x01b 37*4882a593Smuzhiyun #define R2057_VCOCAL_DELAY_AFTER_REFRESH 0x01c 38*4882a593Smuzhiyun #define R2057_VCOCAL_DELAY_AFTER_CLOSELOOP 0x01d 39*4882a593Smuzhiyun #define R2057_VCOCAL_DELAY_AFTER_OPENLOOP 0x01e 40*4882a593Smuzhiyun #define R2057_VCOCAL_DELAY_BEFORE_OPENLOOP 0x01f 41*4882a593Smuzhiyun #define R2057_VCO_FORCECAPEN_FORCECAP1 0x020 42*4882a593Smuzhiyun #define R2057_VCO_FORCECAP0 0x021 43*4882a593Smuzhiyun #define R2057_RFPLL_REFMASTER_SPAREXTALSIZE 0x022 44*4882a593Smuzhiyun #define R2057_RFPLL_PFD_RESET_PW 0x023 45*4882a593Smuzhiyun #define R2057_RFPLL_LOOPFILTER_R2 0x024 46*4882a593Smuzhiyun #define R2057_RFPLL_LOOPFILTER_R1 0x025 47*4882a593Smuzhiyun #define R2057_RFPLL_LOOPFILTER_C3 0x026 48*4882a593Smuzhiyun #define R2057_RFPLL_LOOPFILTER_C2 0x027 49*4882a593Smuzhiyun #define R2057_RFPLL_LOOPFILTER_C1 0x028 50*4882a593Smuzhiyun #define R2057_CP_KPD_IDAC 0x029 51*4882a593Smuzhiyun #define R2057_RFPLL_IDACS 0x02a 52*4882a593Smuzhiyun #define R2057_RFPLL_MISC_EN 0x02b 53*4882a593Smuzhiyun #define R2057_RFPLL_MMD0 0x02c 54*4882a593Smuzhiyun #define R2057_RFPLL_MMD1 0x02d 55*4882a593Smuzhiyun #define R2057_RFPLL_MISC_CAL_RESETN 0x02e 56*4882a593Smuzhiyun #define R2057_JTAGXTAL_SIZE_CPBIAS_FILTRES 0x02f 57*4882a593Smuzhiyun #define R2057_VCO_ALCREF_BBPLLXTAL_SIZE 0x030 58*4882a593Smuzhiyun #define R2057_VCOCAL_READCAP0 0x031 59*4882a593Smuzhiyun #define R2057_VCOCAL_READCAP1 0x032 60*4882a593Smuzhiyun #define R2057_VCOCAL_STATUS 0x033 61*4882a593Smuzhiyun #define R2057_LOGEN_PUS 0x034 62*4882a593Smuzhiyun #define R2057_LOGEN_PTAT_RESETS 0x035 63*4882a593Smuzhiyun #define R2057_VCOBUF_IDACS 0x036 64*4882a593Smuzhiyun #define R2057_VCOBUF_TUNE 0x037 65*4882a593Smuzhiyun #define R2057_CMOSBUF_TX2GQ_IDACS 0x038 66*4882a593Smuzhiyun #define R2057_CMOSBUF_TX2GI_IDACS 0x039 67*4882a593Smuzhiyun #define R2057_CMOSBUF_TX5GQ_IDACS 0x03a 68*4882a593Smuzhiyun #define R2057_CMOSBUF_TX5GI_IDACS 0x03b 69*4882a593Smuzhiyun #define R2057_CMOSBUF_RX2GQ_IDACS 0x03c 70*4882a593Smuzhiyun #define R2057_CMOSBUF_RX2GI_IDACS 0x03d 71*4882a593Smuzhiyun #define R2057_CMOSBUF_RX5GQ_IDACS 0x03e 72*4882a593Smuzhiyun #define R2057_CMOSBUF_RX5GI_IDACS 0x03f 73*4882a593Smuzhiyun #define R2057_LOGEN_MX2G_IDACS 0x040 74*4882a593Smuzhiyun #define R2057_LOGEN_MX2G_TUNE 0x041 75*4882a593Smuzhiyun #define R2057_LOGEN_MX5G_IDACS 0x042 76*4882a593Smuzhiyun #define R2057_LOGEN_MX5G_TUNE 0x043 77*4882a593Smuzhiyun #define R2057_LOGEN_MX5G_RCCR 0x044 78*4882a593Smuzhiyun #define R2057_LOGEN_INDBUF2G_IDAC 0x045 79*4882a593Smuzhiyun #define R2057_LOGEN_INDBUF2G_IBOOST 0x046 80*4882a593Smuzhiyun #define R2057_LOGEN_INDBUF2G_TUNE 0x047 81*4882a593Smuzhiyun #define R2057_LOGEN_INDBUF5G_IDAC 0x048 82*4882a593Smuzhiyun #define R2057_LOGEN_INDBUF5G_IBOOST 0x049 83*4882a593Smuzhiyun #define R2057_LOGEN_INDBUF5G_TUNE 0x04a 84*4882a593Smuzhiyun #define R2057_CMOSBUF_TX_RCCR 0x04b 85*4882a593Smuzhiyun #define R2057_CMOSBUF_RX_RCCR 0x04c 86*4882a593Smuzhiyun #define R2057_LOGEN_SEL_PKDET 0x04d 87*4882a593Smuzhiyun #define R2057_CMOSBUF_SHAREIQ_PTAT 0x04e 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* MISC core 0 */ 90*4882a593Smuzhiyun #define R2057_RXTXBIAS_CONFIG_CORE0 0x04f 91*4882a593Smuzhiyun #define R2057_TXGM_TXRF_PUS_CORE0 0x050 92*4882a593Smuzhiyun #define R2057_TXGM_IDAC_BLEED_CORE0 0x051 93*4882a593Smuzhiyun #define R2057_TXGM_GAIN_CORE0 0x056 94*4882a593Smuzhiyun #define R2057_TXGM2G_PKDET_PUS_CORE0 0x057 95*4882a593Smuzhiyun #define R2057_PAD2G_PTATS_CORE0 0x058 96*4882a593Smuzhiyun #define R2057_PAD2G_IDACS_CORE0 0x059 97*4882a593Smuzhiyun #define R2057_PAD2G_BOOST_PU_CORE0 0x05a 98*4882a593Smuzhiyun #define R2057_PAD2G_CASCV_GAIN_CORE0 0x05b 99*4882a593Smuzhiyun #define R2057_TXMIX2G_TUNE_BOOST_PU_CORE0 0x05c 100*4882a593Smuzhiyun #define R2057_TXMIX2G_LODC_CORE0 0x05d 101*4882a593Smuzhiyun #define R2057_PAD2G_TUNE_PUS_CORE0 0x05e 102*4882a593Smuzhiyun #define R2057_IPA2G_GAIN_CORE0 0x05f 103*4882a593Smuzhiyun #define R2057_TSSI2G_SPARE1_CORE0 0x060 104*4882a593Smuzhiyun #define R2057_TSSI2G_SPARE2_CORE0 0x061 105*4882a593Smuzhiyun #define R2057_IPA2G_TUNEV_CASCV_PTAT_CORE0 0x062 106*4882a593Smuzhiyun #define R2057_IPA2G_IMAIN_CORE0 0x063 107*4882a593Smuzhiyun #define R2057_IPA2G_CASCONV_CORE0 0x064 108*4882a593Smuzhiyun #define R2057_IPA2G_CASCOFFV_CORE0 0x065 109*4882a593Smuzhiyun #define R2057_IPA2G_BIAS_FILTER_CORE0 0x066 110*4882a593Smuzhiyun #define R2057_TX5G_PKDET_CORE0 0x069 111*4882a593Smuzhiyun #define R2057_PGA_PTAT_TXGM5G_PU_CORE0 0x06a 112*4882a593Smuzhiyun #define R2057_PAD5G_PTATS1_CORE0 0x06b 113*4882a593Smuzhiyun #define R2057_PAD5G_CLASS_PTATS2_CORE0 0x06c 114*4882a593Smuzhiyun #define R2057_PGA_BOOSTPTAT_IMAIN_CORE0 0x06d 115*4882a593Smuzhiyun #define R2057_PAD5G_CASCV_IMAIN_CORE0 0x06e 116*4882a593Smuzhiyun #define R2057_TXMIX5G_IBOOST_PAD_IAUX_CORE0 0x06f 117*4882a593Smuzhiyun #define R2057_PGA_BOOST_TUNE_CORE0 0x070 118*4882a593Smuzhiyun #define R2057_PGA_GAIN_CORE0 0x071 119*4882a593Smuzhiyun #define R2057_PAD5G_CASCOFFV_GAIN_PUS_CORE0 0x072 120*4882a593Smuzhiyun #define R2057_TXMIX5G_BOOST_TUNE_CORE0 0x073 121*4882a593Smuzhiyun #define R2057_PAD5G_TUNE_MISC_PUS_CORE0 0x074 122*4882a593Smuzhiyun #define R2057_IPA5G_IAUX_CORE0 0x075 123*4882a593Smuzhiyun #define R2057_IPA5G_GAIN_CORE0 0x076 124*4882a593Smuzhiyun #define R2057_TSSI5G_SPARE1_CORE0 0x077 125*4882a593Smuzhiyun #define R2057_TSSI5G_SPARE2_CORE0 0x078 126*4882a593Smuzhiyun #define R2057_IPA5G_CASCOFFV_PU_CORE0 0x079 127*4882a593Smuzhiyun #define R2057_IPA5G_PTAT_CORE0 0x07a 128*4882a593Smuzhiyun #define R2057_IPA5G_IMAIN_CORE0 0x07b 129*4882a593Smuzhiyun #define R2057_IPA5G_CASCONV_CORE0 0x07c 130*4882a593Smuzhiyun #define R2057_IPA5G_BIAS_FILTER_CORE0 0x07d 131*4882a593Smuzhiyun #define R2057_PAD_BIAS_FILTER_BWS_CORE0 0x080 132*4882a593Smuzhiyun #define R2057_TR2G_CONFIG1_CORE0_NU 0x081 133*4882a593Smuzhiyun #define R2057_TR2G_CONFIG2_CORE0_NU 0x082 134*4882a593Smuzhiyun #define R2057_LNA5G_RFEN_CORE0 0x083 135*4882a593Smuzhiyun #define R2057_TR5G_CONFIG2_CORE0_NU 0x084 136*4882a593Smuzhiyun #define R2057_RXRFBIAS_IBOOST_PU_CORE0 0x085 137*4882a593Smuzhiyun #define R2057_RXRF_IABAND_RXGM_IMAIN_PTAT_CORE0 0x086 138*4882a593Smuzhiyun #define R2057_RXGM_CMFBITAIL_AUXPTAT_CORE0 0x087 139*4882a593Smuzhiyun #define R2057_RXMIX_ICORE_RXGM_IAUX_CORE0 0x088 140*4882a593Smuzhiyun #define R2057_RXMIX_CMFBITAIL_PU_CORE0 0x089 141*4882a593Smuzhiyun #define R2057_LNA2_IMAIN_PTAT_PU_CORE0 0x08a 142*4882a593Smuzhiyun #define R2057_LNA2_IAUX_PTAT_CORE0 0x08b 143*4882a593Smuzhiyun #define R2057_LNA1_IMAIN_PTAT_PU_CORE0 0x08c 144*4882a593Smuzhiyun #define R2057_LNA15G_INPUT_MATCH_TUNE_CORE0 0x08d 145*4882a593Smuzhiyun #define R2057_RXRFBIAS_BANDSEL_CORE0 0x08e 146*4882a593Smuzhiyun #define R2057_TIA_CONFIG_CORE0 0x08f 147*4882a593Smuzhiyun #define R2057_TIA_IQGAIN_CORE0 0x090 148*4882a593Smuzhiyun #define R2057_TIA_IBIAS2_CORE0 0x091 149*4882a593Smuzhiyun #define R2057_TIA_IBIAS1_CORE0 0x092 150*4882a593Smuzhiyun #define R2057_TIA_SPARE_Q_CORE0 0x093 151*4882a593Smuzhiyun #define R2057_TIA_SPARE_I_CORE0 0x094 152*4882a593Smuzhiyun #define R2057_RXMIX2G_PUS_CORE0 0x095 153*4882a593Smuzhiyun #define R2057_RXMIX2G_VCMREFS_CORE0 0x096 154*4882a593Smuzhiyun #define R2057_RXMIX2G_LODC_QI_CORE0 0x097 155*4882a593Smuzhiyun #define R2057_W12G_BW_LNA2G_PUS_CORE0 0x098 156*4882a593Smuzhiyun #define R2057_LNA2G_GAIN_CORE0 0x099 157*4882a593Smuzhiyun #define R2057_LNA2G_TUNE_CORE0 0x09a 158*4882a593Smuzhiyun #define R2057_RXMIX5G_PUS_CORE0 0x09b 159*4882a593Smuzhiyun #define R2057_RXMIX5G_VCMREFS_CORE0 0x09c 160*4882a593Smuzhiyun #define R2057_RXMIX5G_LODC_QI_CORE0 0x09d 161*4882a593Smuzhiyun #define R2057_W15G_BW_LNA5G_PUS_CORE0 0x09e 162*4882a593Smuzhiyun #define R2057_LNA5G_GAIN_CORE0 0x09f 163*4882a593Smuzhiyun #define R2057_LNA5G_TUNE_CORE0 0x0a0 164*4882a593Smuzhiyun #define R2057_LPFSEL_TXRX_RXBB_PUS_CORE0 0x0a1 165*4882a593Smuzhiyun #define R2057_RXBB_BIAS_MASTER_CORE0 0x0a2 166*4882a593Smuzhiyun #define R2057_RXBB_VGABUF_IDACS_CORE0 0x0a3 167*4882a593Smuzhiyun #define R2057_LPF_VCMREF_TXBUF_VCMREF_CORE0 0x0a4 168*4882a593Smuzhiyun #define R2057_TXBUF_VINCM_CORE0 0x0a5 169*4882a593Smuzhiyun #define R2057_TXBUF_IDACS_CORE0 0x0a6 170*4882a593Smuzhiyun #define R2057_LPF_RESP_RXBUF_BW_CORE0 0x0a7 171*4882a593Smuzhiyun #define R2057_RXBB_CC_CORE0 0x0a8 172*4882a593Smuzhiyun #define R2057_RXBB_SPARE3_CORE0 0x0a9 173*4882a593Smuzhiyun #define R2057_RXBB_RCCAL_HPC_CORE0 0x0aa 174*4882a593Smuzhiyun #define R2057_LPF_IDACS_CORE0 0x0ab 175*4882a593Smuzhiyun #define R2057_LPFBYP_DCLOOP_BYP_IDAC_CORE0 0x0ac 176*4882a593Smuzhiyun #define R2057_TXBUF_GAIN_CORE0 0x0ad 177*4882a593Smuzhiyun #define R2057_AFELOOPBACK_AACI_RESP_CORE0 0x0ae 178*4882a593Smuzhiyun #define R2057_RXBUF_DEGEN_CORE0 0x0af 179*4882a593Smuzhiyun #define R2057_RXBB_SPARE2_CORE0 0x0b0 180*4882a593Smuzhiyun #define R2057_RXBB_SPARE1_CORE0 0x0b1 181*4882a593Smuzhiyun #define R2057_RSSI_MASTER_CORE0 0x0b2 182*4882a593Smuzhiyun #define R2057_W2_MASTER_CORE0 0x0b3 183*4882a593Smuzhiyun #define R2057_NB_MASTER_CORE0 0x0b4 184*4882a593Smuzhiyun #define R2057_W2_IDACS0_Q_CORE0 0x0b5 185*4882a593Smuzhiyun #define R2057_W2_IDACS1_Q_CORE0 0x0b6 186*4882a593Smuzhiyun #define R2057_W2_IDACS0_I_CORE0 0x0b7 187*4882a593Smuzhiyun #define R2057_W2_IDACS1_I_CORE0 0x0b8 188*4882a593Smuzhiyun #define R2057_RSSI_GPAIOSEL_W1_IDACS_CORE0 0x0b9 189*4882a593Smuzhiyun #define R2057_NB_IDACS_Q_CORE0 0x0ba 190*4882a593Smuzhiyun #define R2057_NB_IDACS_I_CORE0 0x0bb 191*4882a593Smuzhiyun #define R2057_BACKUP4_CORE0 0x0c1 192*4882a593Smuzhiyun #define R2057_BACKUP3_CORE0 0x0c2 193*4882a593Smuzhiyun #define R2057_BACKUP2_CORE0 0x0c3 194*4882a593Smuzhiyun #define R2057_BACKUP1_CORE0 0x0c4 195*4882a593Smuzhiyun #define R2057_SPARE16_CORE0 0x0c5 196*4882a593Smuzhiyun #define R2057_SPARE15_CORE0 0x0c6 197*4882a593Smuzhiyun #define R2057_SPARE14_CORE0 0x0c7 198*4882a593Smuzhiyun #define R2057_SPARE13_CORE0 0x0c8 199*4882a593Smuzhiyun #define R2057_SPARE12_CORE0 0x0c9 200*4882a593Smuzhiyun #define R2057_SPARE11_CORE0 0x0ca 201*4882a593Smuzhiyun #define R2057_TX2G_BIAS_RESETS_CORE0 0x0cb 202*4882a593Smuzhiyun #define R2057_TX5G_BIAS_RESETS_CORE0 0x0cc 203*4882a593Smuzhiyun #define R2057_IQTEST_SEL_PU 0x0cd 204*4882a593Smuzhiyun #define R2057_XTAL_CONFIG2 0x0ce 205*4882a593Smuzhiyun #define R2057_BUFS_MISC_LPFBW_CORE0 0x0cf 206*4882a593Smuzhiyun #define R2057_TXLPF_RCCAL_CORE0 0x0d0 207*4882a593Smuzhiyun #define R2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE0 0x0d1 208*4882a593Smuzhiyun #define R2057_LPF_GAIN_CORE0 0x0d2 209*4882a593Smuzhiyun #define R2057_DACBUF_IDACS_BW_CORE0 0x0d3 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun /* MISC core 1 */ 212*4882a593Smuzhiyun #define R2057_RXTXBIAS_CONFIG_CORE1 0x0d4 213*4882a593Smuzhiyun #define R2057_TXGM_TXRF_PUS_CORE1 0x0d5 214*4882a593Smuzhiyun #define R2057_TXGM_IDAC_BLEED_CORE1 0x0d6 215*4882a593Smuzhiyun #define R2057_TXGM_GAIN_CORE1 0x0db 216*4882a593Smuzhiyun #define R2057_TXGM2G_PKDET_PUS_CORE1 0x0dc 217*4882a593Smuzhiyun #define R2057_PAD2G_PTATS_CORE1 0x0dd 218*4882a593Smuzhiyun #define R2057_PAD2G_IDACS_CORE1 0x0de 219*4882a593Smuzhiyun #define R2057_PAD2G_BOOST_PU_CORE1 0x0df 220*4882a593Smuzhiyun #define R2057_PAD2G_CASCV_GAIN_CORE1 0x0e0 221*4882a593Smuzhiyun #define R2057_TXMIX2G_TUNE_BOOST_PU_CORE1 0x0e1 222*4882a593Smuzhiyun #define R2057_TXMIX2G_LODC_CORE1 0x0e2 223*4882a593Smuzhiyun #define R2057_PAD2G_TUNE_PUS_CORE1 0x0e3 224*4882a593Smuzhiyun #define R2057_IPA2G_GAIN_CORE1 0x0e4 225*4882a593Smuzhiyun #define R2057_TSSI2G_SPARE1_CORE1 0x0e5 226*4882a593Smuzhiyun #define R2057_TSSI2G_SPARE2_CORE1 0x0e6 227*4882a593Smuzhiyun #define R2057_IPA2G_TUNEV_CASCV_PTAT_CORE1 0x0e7 228*4882a593Smuzhiyun #define R2057_IPA2G_IMAIN_CORE1 0x0e8 229*4882a593Smuzhiyun #define R2057_IPA2G_CASCONV_CORE1 0x0e9 230*4882a593Smuzhiyun #define R2057_IPA2G_CASCOFFV_CORE1 0x0ea 231*4882a593Smuzhiyun #define R2057_IPA2G_BIAS_FILTER_CORE1 0x0eb 232*4882a593Smuzhiyun #define R2057_TX5G_PKDET_CORE1 0x0ee 233*4882a593Smuzhiyun #define R2057_PGA_PTAT_TXGM5G_PU_CORE1 0x0ef 234*4882a593Smuzhiyun #define R2057_PAD5G_PTATS1_CORE1 0x0f0 235*4882a593Smuzhiyun #define R2057_PAD5G_CLASS_PTATS2_CORE1 0x0f1 236*4882a593Smuzhiyun #define R2057_PGA_BOOSTPTAT_IMAIN_CORE1 0x0f2 237*4882a593Smuzhiyun #define R2057_PAD5G_CASCV_IMAIN_CORE1 0x0f3 238*4882a593Smuzhiyun #define R2057_TXMIX5G_IBOOST_PAD_IAUX_CORE1 0x0f4 239*4882a593Smuzhiyun #define R2057_PGA_BOOST_TUNE_CORE1 0x0f5 240*4882a593Smuzhiyun #define R2057_PGA_GAIN_CORE1 0x0f6 241*4882a593Smuzhiyun #define R2057_PAD5G_CASCOFFV_GAIN_PUS_CORE1 0x0f7 242*4882a593Smuzhiyun #define R2057_TXMIX5G_BOOST_TUNE_CORE1 0x0f8 243*4882a593Smuzhiyun #define R2057_PAD5G_TUNE_MISC_PUS_CORE1 0x0f9 244*4882a593Smuzhiyun #define R2057_IPA5G_IAUX_CORE1 0x0fa 245*4882a593Smuzhiyun #define R2057_IPA5G_GAIN_CORE1 0x0fb 246*4882a593Smuzhiyun #define R2057_TSSI5G_SPARE1_CORE1 0x0fc 247*4882a593Smuzhiyun #define R2057_TSSI5G_SPARE2_CORE1 0x0fd 248*4882a593Smuzhiyun #define R2057_IPA5G_CASCOFFV_PU_CORE1 0x0fe 249*4882a593Smuzhiyun #define R2057_IPA5G_PTAT_CORE1 0x0ff 250*4882a593Smuzhiyun #define R2057_IPA5G_IMAIN_CORE1 0x100 251*4882a593Smuzhiyun #define R2057_IPA5G_CASCONV_CORE1 0x101 252*4882a593Smuzhiyun #define R2057_IPA5G_BIAS_FILTER_CORE1 0x102 253*4882a593Smuzhiyun #define R2057_PAD_BIAS_FILTER_BWS_CORE1 0x105 254*4882a593Smuzhiyun #define R2057_TR2G_CONFIG1_CORE1_NU 0x106 255*4882a593Smuzhiyun #define R2057_TR2G_CONFIG2_CORE1_NU 0x107 256*4882a593Smuzhiyun #define R2057_LNA5G_RFEN_CORE1 0x108 257*4882a593Smuzhiyun #define R2057_TR5G_CONFIG2_CORE1_NU 0x109 258*4882a593Smuzhiyun #define R2057_RXRFBIAS_IBOOST_PU_CORE1 0x10a 259*4882a593Smuzhiyun #define R2057_RXRF_IABAND_RXGM_IMAIN_PTAT_CORE1 0x10b 260*4882a593Smuzhiyun #define R2057_RXGM_CMFBITAIL_AUXPTAT_CORE1 0x10c 261*4882a593Smuzhiyun #define R2057_RXMIX_ICORE_RXGM_IAUX_CORE1 0x10d 262*4882a593Smuzhiyun #define R2057_RXMIX_CMFBITAIL_PU_CORE1 0x10e 263*4882a593Smuzhiyun #define R2057_LNA2_IMAIN_PTAT_PU_CORE1 0x10f 264*4882a593Smuzhiyun #define R2057_LNA2_IAUX_PTAT_CORE1 0x110 265*4882a593Smuzhiyun #define R2057_LNA1_IMAIN_PTAT_PU_CORE1 0x111 266*4882a593Smuzhiyun #define R2057_LNA15G_INPUT_MATCH_TUNE_CORE1 0x112 267*4882a593Smuzhiyun #define R2057_RXRFBIAS_BANDSEL_CORE1 0x113 268*4882a593Smuzhiyun #define R2057_TIA_CONFIG_CORE1 0x114 269*4882a593Smuzhiyun #define R2057_TIA_IQGAIN_CORE1 0x115 270*4882a593Smuzhiyun #define R2057_TIA_IBIAS2_CORE1 0x116 271*4882a593Smuzhiyun #define R2057_TIA_IBIAS1_CORE1 0x117 272*4882a593Smuzhiyun #define R2057_TIA_SPARE_Q_CORE1 0x118 273*4882a593Smuzhiyun #define R2057_TIA_SPARE_I_CORE1 0x119 274*4882a593Smuzhiyun #define R2057_RXMIX2G_PUS_CORE1 0x11a 275*4882a593Smuzhiyun #define R2057_RXMIX2G_VCMREFS_CORE1 0x11b 276*4882a593Smuzhiyun #define R2057_RXMIX2G_LODC_QI_CORE1 0x11c 277*4882a593Smuzhiyun #define R2057_W12G_BW_LNA2G_PUS_CORE1 0x11d 278*4882a593Smuzhiyun #define R2057_LNA2G_GAIN_CORE1 0x11e 279*4882a593Smuzhiyun #define R2057_LNA2G_TUNE_CORE1 0x11f 280*4882a593Smuzhiyun #define R2057_RXMIX5G_PUS_CORE1 0x120 281*4882a593Smuzhiyun #define R2057_RXMIX5G_VCMREFS_CORE1 0x121 282*4882a593Smuzhiyun #define R2057_RXMIX5G_LODC_QI_CORE1 0x122 283*4882a593Smuzhiyun #define R2057_W15G_BW_LNA5G_PUS_CORE1 0x123 284*4882a593Smuzhiyun #define R2057_LNA5G_GAIN_CORE1 0x124 285*4882a593Smuzhiyun #define R2057_LNA5G_TUNE_CORE1 0x125 286*4882a593Smuzhiyun #define R2057_LPFSEL_TXRX_RXBB_PUS_CORE1 0x126 287*4882a593Smuzhiyun #define R2057_RXBB_BIAS_MASTER_CORE1 0x127 288*4882a593Smuzhiyun #define R2057_RXBB_VGABUF_IDACS_CORE1 0x128 289*4882a593Smuzhiyun #define R2057_LPF_VCMREF_TXBUF_VCMREF_CORE1 0x129 290*4882a593Smuzhiyun #define R2057_TXBUF_VINCM_CORE1 0x12a 291*4882a593Smuzhiyun #define R2057_TXBUF_IDACS_CORE1 0x12b 292*4882a593Smuzhiyun #define R2057_LPF_RESP_RXBUF_BW_CORE1 0x12c 293*4882a593Smuzhiyun #define R2057_RXBB_CC_CORE1 0x12d 294*4882a593Smuzhiyun #define R2057_RXBB_SPARE3_CORE1 0x12e 295*4882a593Smuzhiyun #define R2057_RXBB_RCCAL_HPC_CORE1 0x12f 296*4882a593Smuzhiyun #define R2057_LPF_IDACS_CORE1 0x130 297*4882a593Smuzhiyun #define R2057_LPFBYP_DCLOOP_BYP_IDAC_CORE1 0x131 298*4882a593Smuzhiyun #define R2057_TXBUF_GAIN_CORE1 0x132 299*4882a593Smuzhiyun #define R2057_AFELOOPBACK_AACI_RESP_CORE1 0x133 300*4882a593Smuzhiyun #define R2057_RXBUF_DEGEN_CORE1 0x134 301*4882a593Smuzhiyun #define R2057_RXBB_SPARE2_CORE1 0x135 302*4882a593Smuzhiyun #define R2057_RXBB_SPARE1_CORE1 0x136 303*4882a593Smuzhiyun #define R2057_RSSI_MASTER_CORE1 0x137 304*4882a593Smuzhiyun #define R2057_W2_MASTER_CORE1 0x138 305*4882a593Smuzhiyun #define R2057_NB_MASTER_CORE1 0x139 306*4882a593Smuzhiyun #define R2057_W2_IDACS0_Q_CORE1 0x13a 307*4882a593Smuzhiyun #define R2057_W2_IDACS1_Q_CORE1 0x13b 308*4882a593Smuzhiyun #define R2057_W2_IDACS0_I_CORE1 0x13c 309*4882a593Smuzhiyun #define R2057_W2_IDACS1_I_CORE1 0x13d 310*4882a593Smuzhiyun #define R2057_RSSI_GPAIOSEL_W1_IDACS_CORE1 0x13e 311*4882a593Smuzhiyun #define R2057_NB_IDACS_Q_CORE1 0x13f 312*4882a593Smuzhiyun #define R2057_NB_IDACS_I_CORE1 0x140 313*4882a593Smuzhiyun #define R2057_BACKUP4_CORE1 0x146 314*4882a593Smuzhiyun #define R2057_BACKUP3_CORE1 0x147 315*4882a593Smuzhiyun #define R2057_BACKUP2_CORE1 0x148 316*4882a593Smuzhiyun #define R2057_BACKUP1_CORE1 0x149 317*4882a593Smuzhiyun #define R2057_SPARE16_CORE1 0x14a 318*4882a593Smuzhiyun #define R2057_SPARE15_CORE1 0x14b 319*4882a593Smuzhiyun #define R2057_SPARE14_CORE1 0x14c 320*4882a593Smuzhiyun #define R2057_SPARE13_CORE1 0x14d 321*4882a593Smuzhiyun #define R2057_SPARE12_CORE1 0x14e 322*4882a593Smuzhiyun #define R2057_SPARE11_CORE1 0x14f 323*4882a593Smuzhiyun #define R2057_TX2G_BIAS_RESETS_CORE1 0x150 324*4882a593Smuzhiyun #define R2057_TX5G_BIAS_RESETS_CORE1 0x151 325*4882a593Smuzhiyun #define R2057_SPARE8_CORE1 0x152 326*4882a593Smuzhiyun #define R2057_SPARE7_CORE1 0x153 327*4882a593Smuzhiyun #define R2057_BUFS_MISC_LPFBW_CORE1 0x154 328*4882a593Smuzhiyun #define R2057_TXLPF_RCCAL_CORE1 0x155 329*4882a593Smuzhiyun #define R2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE1 0x156 330*4882a593Smuzhiyun #define R2057_LPF_GAIN_CORE1 0x157 331*4882a593Smuzhiyun #define R2057_DACBUF_IDACS_BW_CORE1 0x158 332*4882a593Smuzhiyun 333*4882a593Smuzhiyun #define R2057_DACBUF_VINCM_CORE1 0x159 334*4882a593Smuzhiyun #define R2057_RCCAL_START_R1_Q1_P1 0x15a 335*4882a593Smuzhiyun #define R2057_RCCAL_X1 0x15b 336*4882a593Smuzhiyun #define R2057_RCCAL_TRC0 0x15c 337*4882a593Smuzhiyun #define R2057_RCCAL_TRC1 0x15d 338*4882a593Smuzhiyun #define R2057_RCCAL_DONE_OSCCAP 0x15e 339*4882a593Smuzhiyun #define R2057_RCCAL_N0_0 0x15f 340*4882a593Smuzhiyun #define R2057_RCCAL_N0_1 0x160 341*4882a593Smuzhiyun #define R2057_RCCAL_N1_0 0x161 342*4882a593Smuzhiyun #define R2057_RCCAL_N1_1 0x162 343*4882a593Smuzhiyun #define R2057_RCAL_STATUS 0x163 344*4882a593Smuzhiyun #define R2057_XTALPUOVR_PINCTRL 0x164 345*4882a593Smuzhiyun #define R2057_OVR_REG0 0x165 346*4882a593Smuzhiyun #define R2057_OVR_REG1 0x166 347*4882a593Smuzhiyun #define R2057_OVR_REG2 0x167 348*4882a593Smuzhiyun #define R2057_OVR_REG3 0x168 349*4882a593Smuzhiyun #define R2057_OVR_REG4 0x169 350*4882a593Smuzhiyun #define R2057_RCCAL_SCAP_VAL 0x16a 351*4882a593Smuzhiyun #define R2057_RCCAL_BCAP_VAL 0x16b 352*4882a593Smuzhiyun #define R2057_RCCAL_HPC_VAL 0x16c 353*4882a593Smuzhiyun #define R2057_RCCAL_OVERRIDES 0x16d 354*4882a593Smuzhiyun 355*4882a593Smuzhiyun /* TX core 0 */ 356*4882a593Smuzhiyun #define R2057_TX0_IQCAL_GAIN_BW 0x170 357*4882a593Smuzhiyun #define R2057_TX0_LOFT_FINE_I 0x171 358*4882a593Smuzhiyun #define R2057_TX0_LOFT_FINE_Q 0x172 359*4882a593Smuzhiyun #define R2057_TX0_LOFT_COARSE_I 0x173 360*4882a593Smuzhiyun #define R2057_TX0_LOFT_COARSE_Q 0x174 361*4882a593Smuzhiyun #define R2057_TX0_TX_SSI_MASTER 0x175 362*4882a593Smuzhiyun #define R2057_TX0_IQCAL_VCM_HG 0x176 363*4882a593Smuzhiyun #define R2057_TX0_IQCAL_IDAC 0x177 364*4882a593Smuzhiyun #define R2057_TX0_TSSI_VCM 0x178 365*4882a593Smuzhiyun #define R2057_TX0_TX_SSI_MUX 0x179 366*4882a593Smuzhiyun #define R2057_TX0_TSSIA 0x17a 367*4882a593Smuzhiyun #define R2057_TX0_TSSIG 0x17b 368*4882a593Smuzhiyun #define R2057_TX0_TSSI_MISC1 0x17c 369*4882a593Smuzhiyun #define R2057_TX0_TXRXCOUPLE_2G_ATTEN 0x17d 370*4882a593Smuzhiyun #define R2057_TX0_TXRXCOUPLE_2G_PWRUP 0x17e 371*4882a593Smuzhiyun #define R2057_TX0_TXRXCOUPLE_5G_ATTEN 0x17f 372*4882a593Smuzhiyun #define R2057_TX0_TXRXCOUPLE_5G_PWRUP 0x180 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun /* TX core 1 */ 375*4882a593Smuzhiyun #define R2057_TX1_IQCAL_GAIN_BW 0x190 376*4882a593Smuzhiyun #define R2057_TX1_LOFT_FINE_I 0x191 377*4882a593Smuzhiyun #define R2057_TX1_LOFT_FINE_Q 0x192 378*4882a593Smuzhiyun #define R2057_TX1_LOFT_COARSE_I 0x193 379*4882a593Smuzhiyun #define R2057_TX1_LOFT_COARSE_Q 0x194 380*4882a593Smuzhiyun #define R2057_TX1_TX_SSI_MASTER 0x195 381*4882a593Smuzhiyun #define R2057_TX1_IQCAL_VCM_HG 0x196 382*4882a593Smuzhiyun #define R2057_TX1_IQCAL_IDAC 0x197 383*4882a593Smuzhiyun #define R2057_TX1_TSSI_VCM 0x198 384*4882a593Smuzhiyun #define R2057_TX1_TX_SSI_MUX 0x199 385*4882a593Smuzhiyun #define R2057_TX1_TSSIA 0x19a 386*4882a593Smuzhiyun #define R2057_TX1_TSSIG 0x19b 387*4882a593Smuzhiyun #define R2057_TX1_TSSI_MISC1 0x19c 388*4882a593Smuzhiyun #define R2057_TX1_TXRXCOUPLE_2G_ATTEN 0x19d 389*4882a593Smuzhiyun #define R2057_TX1_TXRXCOUPLE_2G_PWRUP 0x19e 390*4882a593Smuzhiyun #define R2057_TX1_TXRXCOUPLE_5G_ATTEN 0x19f 391*4882a593Smuzhiyun #define R2057_TX1_TXRXCOUPLE_5G_PWRUP 0x1a0 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun #define R2057_AFE_VCM_CAL_MASTER_CORE0 0x1a1 394*4882a593Smuzhiyun #define R2057_AFE_SET_VCM_I_CORE0 0x1a2 395*4882a593Smuzhiyun #define R2057_AFE_SET_VCM_Q_CORE0 0x1a3 396*4882a593Smuzhiyun #define R2057_AFE_STATUS_VCM_IQADC_CORE0 0x1a4 397*4882a593Smuzhiyun #define R2057_AFE_STATUS_VCM_I_CORE0 0x1a5 398*4882a593Smuzhiyun #define R2057_AFE_STATUS_VCM_Q_CORE0 0x1a6 399*4882a593Smuzhiyun #define R2057_AFE_VCM_CAL_MASTER_CORE1 0x1a7 400*4882a593Smuzhiyun #define R2057_AFE_SET_VCM_I_CORE1 0x1a8 401*4882a593Smuzhiyun #define R2057_AFE_SET_VCM_Q_CORE1 0x1a9 402*4882a593Smuzhiyun #define R2057_AFE_STATUS_VCM_IQADC_CORE1 0x1aa 403*4882a593Smuzhiyun #define R2057_AFE_STATUS_VCM_I_CORE1 0x1ab 404*4882a593Smuzhiyun #define R2057_AFE_STATUS_VCM_Q_CORE1 0x1ac 405*4882a593Smuzhiyun 406*4882a593Smuzhiyun #define R2057v7_DACBUF_VINCM_CORE0 0x1ad 407*4882a593Smuzhiyun #define R2057v7_RCCAL_MASTER 0x1ae 408*4882a593Smuzhiyun #define R2057v7_TR2G_CONFIG3_CORE0_NU 0x1af 409*4882a593Smuzhiyun #define R2057v7_TR2G_CONFIG3_CORE1_NU 0x1b0 410*4882a593Smuzhiyun #define R2057v7_LOGEN_PUS1 0x1b1 411*4882a593Smuzhiyun #define R2057v7_OVR_REG5 0x1b2 412*4882a593Smuzhiyun #define R2057v7_OVR_REG6 0x1b3 413*4882a593Smuzhiyun #define R2057v7_OVR_REG7 0x1b4 414*4882a593Smuzhiyun #define R2057v7_OVR_REG8 0x1b5 415*4882a593Smuzhiyun #define R2057v7_OVR_REG9 0x1b6 416*4882a593Smuzhiyun #define R2057v7_OVR_REG10 0x1b7 417*4882a593Smuzhiyun #define R2057v7_OVR_REG11 0x1b8 418*4882a593Smuzhiyun #define R2057v7_OVR_REG12 0x1b9 419*4882a593Smuzhiyun #define R2057v7_OVR_REG13 0x1ba 420*4882a593Smuzhiyun #define R2057v7_OVR_REG14 0x1bb 421*4882a593Smuzhiyun #define R2057v7_OVR_REG15 0x1bc 422*4882a593Smuzhiyun #define R2057v7_OVR_REG16 0x1bd 423*4882a593Smuzhiyun #define R2057v7_OVR_REG1 0x1be 424*4882a593Smuzhiyun #define R2057v7_OVR_REG18 0x1bf 425*4882a593Smuzhiyun #define R2057v7_OVR_REG19 0x1c0 426*4882a593Smuzhiyun #define R2057v7_OVR_REG20 0x1c1 427*4882a593Smuzhiyun #define R2057v7_OVR_REG21 0x1c2 428*4882a593Smuzhiyun #define R2057v7_OVR_REG2 0x1c3 429*4882a593Smuzhiyun #define R2057v7_OVR_REG23 0x1c4 430*4882a593Smuzhiyun #define R2057v7_OVR_REG24 0x1c5 431*4882a593Smuzhiyun #define R2057v7_OVR_REG25 0x1c6 432*4882a593Smuzhiyun #define R2057v7_OVR_REG26 0x1c7 433*4882a593Smuzhiyun #define R2057v7_OVR_REG27 0x1c8 434*4882a593Smuzhiyun #define R2057v7_OVR_REG28 0x1c9 435*4882a593Smuzhiyun #define R2057v7_IQTEST_SEL_PU2 0x1ca 436*4882a593Smuzhiyun 437*4882a593Smuzhiyun #define R2057_VCM_MASK 0x7 438*4882a593Smuzhiyun 439*4882a593Smuzhiyun struct b43_nphy_chantabent_rev7 { 440*4882a593Smuzhiyun /* The channel frequency in MHz */ 441*4882a593Smuzhiyun u16 freq; 442*4882a593Smuzhiyun /* Radio regs values on channelswitch */ 443*4882a593Smuzhiyun u8 radio_vcocal_countval0; 444*4882a593Smuzhiyun u8 radio_vcocal_countval1; 445*4882a593Smuzhiyun u8 radio_rfpll_refmaster_sparextalsize; 446*4882a593Smuzhiyun u8 radio_rfpll_loopfilter_r1; 447*4882a593Smuzhiyun u8 radio_rfpll_loopfilter_c2; 448*4882a593Smuzhiyun u8 radio_rfpll_loopfilter_c1; 449*4882a593Smuzhiyun u8 radio_cp_kpd_idac; 450*4882a593Smuzhiyun u8 radio_rfpll_mmd0; 451*4882a593Smuzhiyun u8 radio_rfpll_mmd1; 452*4882a593Smuzhiyun u8 radio_vcobuf_tune; 453*4882a593Smuzhiyun u8 radio_logen_mx2g_tune; 454*4882a593Smuzhiyun u8 radio_logen_mx5g_tune; 455*4882a593Smuzhiyun u8 radio_logen_indbuf2g_tune; 456*4882a593Smuzhiyun u8 radio_logen_indbuf5g_tune; 457*4882a593Smuzhiyun u8 radio_txmix2g_tune_boost_pu_core0; 458*4882a593Smuzhiyun u8 radio_pad2g_tune_pus_core0; 459*4882a593Smuzhiyun u8 radio_pga_boost_tune_core0; 460*4882a593Smuzhiyun u8 radio_txmix5g_boost_tune_core0; 461*4882a593Smuzhiyun u8 radio_pad5g_tune_misc_pus_core0; 462*4882a593Smuzhiyun u8 radio_lna2g_tune_core0; 463*4882a593Smuzhiyun u8 radio_lna5g_tune_core0; 464*4882a593Smuzhiyun u8 radio_txmix2g_tune_boost_pu_core1; 465*4882a593Smuzhiyun u8 radio_pad2g_tune_pus_core1; 466*4882a593Smuzhiyun u8 radio_pga_boost_tune_core1; 467*4882a593Smuzhiyun u8 radio_txmix5g_boost_tune_core1; 468*4882a593Smuzhiyun u8 radio_pad5g_tune_misc_pus_core1; 469*4882a593Smuzhiyun u8 radio_lna2g_tune_core1; 470*4882a593Smuzhiyun u8 radio_lna5g_tune_core1; 471*4882a593Smuzhiyun /* PHY res values on channelswitch */ 472*4882a593Smuzhiyun struct b43_phy_n_sfo_cfg phy_regs; 473*4882a593Smuzhiyun }; 474*4882a593Smuzhiyun 475*4882a593Smuzhiyun struct b43_nphy_chantabent_rev7_2g { 476*4882a593Smuzhiyun /* The channel frequency in MHz */ 477*4882a593Smuzhiyun u16 freq; 478*4882a593Smuzhiyun /* Radio regs values on channelswitch */ 479*4882a593Smuzhiyun u8 radio_vcocal_countval0; 480*4882a593Smuzhiyun u8 radio_vcocal_countval1; 481*4882a593Smuzhiyun u8 radio_rfpll_refmaster_sparextalsize; 482*4882a593Smuzhiyun u8 radio_rfpll_loopfilter_r1; 483*4882a593Smuzhiyun u8 radio_rfpll_loopfilter_c2; 484*4882a593Smuzhiyun u8 radio_rfpll_loopfilter_c1; 485*4882a593Smuzhiyun u8 radio_cp_kpd_idac; 486*4882a593Smuzhiyun u8 radio_rfpll_mmd0; 487*4882a593Smuzhiyun u8 radio_rfpll_mmd1; 488*4882a593Smuzhiyun u8 radio_vcobuf_tune; 489*4882a593Smuzhiyun u8 radio_logen_mx2g_tune; 490*4882a593Smuzhiyun u8 radio_logen_indbuf2g_tune; 491*4882a593Smuzhiyun u8 radio_txmix2g_tune_boost_pu_core0; 492*4882a593Smuzhiyun u8 radio_pad2g_tune_pus_core0; 493*4882a593Smuzhiyun u8 radio_lna2g_tune_core0; 494*4882a593Smuzhiyun u8 radio_txmix2g_tune_boost_pu_core1; 495*4882a593Smuzhiyun u8 radio_pad2g_tune_pus_core1; 496*4882a593Smuzhiyun u8 radio_lna2g_tune_core1; 497*4882a593Smuzhiyun /* PHY regs values on channelswitch */ 498*4882a593Smuzhiyun struct b43_phy_n_sfo_cfg phy_regs; 499*4882a593Smuzhiyun }; 500*4882a593Smuzhiyun 501*4882a593Smuzhiyun void r2057_upload_inittabs(struct b43_wldev *dev); 502*4882a593Smuzhiyun 503*4882a593Smuzhiyun void r2057_get_chantabent_rev7(struct b43_wldev *dev, u16 freq, 504*4882a593Smuzhiyun const struct b43_nphy_chantabent_rev7 **tabent_r7, 505*4882a593Smuzhiyun const struct b43_nphy_chantabent_rev7_2g **tabent_r7_2g); 506*4882a593Smuzhiyun 507*4882a593Smuzhiyun #endif /* B43_RADIO_2057_H_ */ 508