xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/broadcom/b43/pio.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #ifndef B43_PIO_H_
3*4882a593Smuzhiyun #define B43_PIO_H_
4*4882a593Smuzhiyun 
5*4882a593Smuzhiyun #include "b43.h"
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <linux/interrupt.h>
8*4882a593Smuzhiyun #include <linux/io.h>
9*4882a593Smuzhiyun #include <linux/list.h>
10*4882a593Smuzhiyun #include <linux/skbuff.h>
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun /*** Registers for PIO queues up to revision 7. ***/
14*4882a593Smuzhiyun /* TX queue. */
15*4882a593Smuzhiyun #define B43_PIO_TXCTL			0x00
16*4882a593Smuzhiyun #define  B43_PIO_TXCTL_WRITELO		0x0001
17*4882a593Smuzhiyun #define  B43_PIO_TXCTL_WRITEHI		0x0002
18*4882a593Smuzhiyun #define  B43_PIO_TXCTL_EOF		0x0004
19*4882a593Smuzhiyun #define  B43_PIO_TXCTL_FREADY		0x0008
20*4882a593Smuzhiyun #define  B43_PIO_TXCTL_FLUSHREQ		0x0020
21*4882a593Smuzhiyun #define  B43_PIO_TXCTL_FLUSHPEND	0x0040
22*4882a593Smuzhiyun #define  B43_PIO_TXCTL_SUSPREQ		0x0080
23*4882a593Smuzhiyun #define  B43_PIO_TXCTL_QSUSP		0x0100
24*4882a593Smuzhiyun #define  B43_PIO_TXCTL_COMMCNT		0xFC00
25*4882a593Smuzhiyun #define  B43_PIO_TXCTL_COMMCNT_SHIFT	10
26*4882a593Smuzhiyun #define B43_PIO_TXDATA			0x02
27*4882a593Smuzhiyun #define B43_PIO_TXQBUFSIZE		0x04
28*4882a593Smuzhiyun /* RX queue. */
29*4882a593Smuzhiyun #define B43_PIO_RXCTL			0x00
30*4882a593Smuzhiyun #define  B43_PIO_RXCTL_FRAMERDY		0x0001
31*4882a593Smuzhiyun #define  B43_PIO_RXCTL_DATARDY		0x0002
32*4882a593Smuzhiyun #define B43_PIO_RXDATA			0x02
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun /*** Registers for PIO queues revision 8 and later. ***/
35*4882a593Smuzhiyun /* TX queue */
36*4882a593Smuzhiyun #define B43_PIO8_TXCTL			0x00
37*4882a593Smuzhiyun #define  B43_PIO8_TXCTL_0_7		0x00000001
38*4882a593Smuzhiyun #define  B43_PIO8_TXCTL_8_15		0x00000002
39*4882a593Smuzhiyun #define  B43_PIO8_TXCTL_16_23		0x00000004
40*4882a593Smuzhiyun #define  B43_PIO8_TXCTL_24_31		0x00000008
41*4882a593Smuzhiyun #define  B43_PIO8_TXCTL_EOF		0x00000010
42*4882a593Smuzhiyun #define  B43_PIO8_TXCTL_FREADY		0x00000080
43*4882a593Smuzhiyun #define  B43_PIO8_TXCTL_SUSPREQ		0x00000100
44*4882a593Smuzhiyun #define  B43_PIO8_TXCTL_QSUSP		0x00000200
45*4882a593Smuzhiyun #define  B43_PIO8_TXCTL_FLUSHREQ	0x00000400
46*4882a593Smuzhiyun #define  B43_PIO8_TXCTL_FLUSHPEND	0x00000800
47*4882a593Smuzhiyun #define B43_PIO8_TXDATA			0x04
48*4882a593Smuzhiyun /* RX queue */
49*4882a593Smuzhiyun #define B43_PIO8_RXCTL			0x00
50*4882a593Smuzhiyun #define  B43_PIO8_RXCTL_FRAMERDY	0x00000001
51*4882a593Smuzhiyun #define  B43_PIO8_RXCTL_DATARDY		0x00000002
52*4882a593Smuzhiyun #define B43_PIO8_RXDATA			0x04
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun /* The maximum number of TX-packets the HW can handle. */
56*4882a593Smuzhiyun #define B43_PIO_MAX_NR_TXPACKETS	32
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun struct b43_pio_txpacket {
60*4882a593Smuzhiyun 	/* Pointer to the TX queue we belong to. */
61*4882a593Smuzhiyun 	struct b43_pio_txqueue *queue;
62*4882a593Smuzhiyun 	/* The TX data packet. */
63*4882a593Smuzhiyun 	struct sk_buff *skb;
64*4882a593Smuzhiyun 	/* Index in the (struct b43_pio_txqueue)->packets array. */
65*4882a593Smuzhiyun 	u8 index;
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun 	struct list_head list;
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun struct b43_pio_txqueue {
71*4882a593Smuzhiyun 	struct b43_wldev *dev;
72*4882a593Smuzhiyun 	u16 mmio_base;
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 	/* The device queue buffer size in bytes. */
75*4882a593Smuzhiyun 	u16 buffer_size;
76*4882a593Smuzhiyun 	/* The number of used bytes in the device queue buffer. */
77*4882a593Smuzhiyun 	u16 buffer_used;
78*4882a593Smuzhiyun 	/* The number of packets that can still get queued.
79*4882a593Smuzhiyun 	 * This is decremented on queueing a packet and incremented
80*4882a593Smuzhiyun 	 * after receiving the transmit status. */
81*4882a593Smuzhiyun 	u16 free_packet_slots;
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	/* True, if the mac80211 queue was stopped due to overflow at TX. */
84*4882a593Smuzhiyun 	bool stopped;
85*4882a593Smuzhiyun 	/* Our b43 queue index number */
86*4882a593Smuzhiyun 	u8 index;
87*4882a593Smuzhiyun 	/* The mac80211 QoS queue priority. */
88*4882a593Smuzhiyun 	u8 queue_prio;
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	/* Buffer for TX packet meta data. */
91*4882a593Smuzhiyun 	struct b43_pio_txpacket packets[B43_PIO_MAX_NR_TXPACKETS];
92*4882a593Smuzhiyun 	struct list_head packets_list;
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	/* Shortcut to the 802.11 core revision. This is to
95*4882a593Smuzhiyun 	 * avoid horrible pointer dereferencing in the fastpaths. */
96*4882a593Smuzhiyun 	u8 rev;
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun struct b43_pio_rxqueue {
100*4882a593Smuzhiyun 	struct b43_wldev *dev;
101*4882a593Smuzhiyun 	u16 mmio_base;
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun 	/* Shortcut to the 802.11 core revision. This is to
104*4882a593Smuzhiyun 	 * avoid horrible pointer dereferencing in the fastpaths. */
105*4882a593Smuzhiyun 	u8 rev;
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 
b43_piotx_read16(struct b43_pio_txqueue * q,u16 offset)109*4882a593Smuzhiyun static inline u16 b43_piotx_read16(struct b43_pio_txqueue *q, u16 offset)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun 	return b43_read16(q->dev, q->mmio_base + offset);
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun 
b43_piotx_read32(struct b43_pio_txqueue * q,u16 offset)114*4882a593Smuzhiyun static inline u32 b43_piotx_read32(struct b43_pio_txqueue *q, u16 offset)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun 	return b43_read32(q->dev, q->mmio_base + offset);
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun 
b43_piotx_write16(struct b43_pio_txqueue * q,u16 offset,u16 value)119*4882a593Smuzhiyun static inline void b43_piotx_write16(struct b43_pio_txqueue *q,
120*4882a593Smuzhiyun 				     u16 offset, u16 value)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun 	b43_write16(q->dev, q->mmio_base + offset, value);
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun 
b43_piotx_write32(struct b43_pio_txqueue * q,u16 offset,u32 value)125*4882a593Smuzhiyun static inline void b43_piotx_write32(struct b43_pio_txqueue *q,
126*4882a593Smuzhiyun 				     u16 offset, u32 value)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun 	b43_write32(q->dev, q->mmio_base + offset, value);
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 
b43_piorx_read16(struct b43_pio_rxqueue * q,u16 offset)132*4882a593Smuzhiyun static inline u16 b43_piorx_read16(struct b43_pio_rxqueue *q, u16 offset)
133*4882a593Smuzhiyun {
134*4882a593Smuzhiyun 	return b43_read16(q->dev, q->mmio_base + offset);
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun 
b43_piorx_read32(struct b43_pio_rxqueue * q,u16 offset)137*4882a593Smuzhiyun static inline u32 b43_piorx_read32(struct b43_pio_rxqueue *q, u16 offset)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun 	return b43_read32(q->dev, q->mmio_base + offset);
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun 
b43_piorx_write16(struct b43_pio_rxqueue * q,u16 offset,u16 value)142*4882a593Smuzhiyun static inline void b43_piorx_write16(struct b43_pio_rxqueue *q,
143*4882a593Smuzhiyun 				     u16 offset, u16 value)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun 	b43_write16(q->dev, q->mmio_base + offset, value);
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun 
b43_piorx_write32(struct b43_pio_rxqueue * q,u16 offset,u32 value)148*4882a593Smuzhiyun static inline void b43_piorx_write32(struct b43_pio_rxqueue *q,
149*4882a593Smuzhiyun 				     u16 offset, u32 value)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun 	b43_write32(q->dev, q->mmio_base + offset, value);
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun int b43_pio_init(struct b43_wldev *dev);
156*4882a593Smuzhiyun void b43_pio_free(struct b43_wldev *dev);
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun int b43_pio_tx(struct b43_wldev *dev, struct sk_buff *skb);
159*4882a593Smuzhiyun void b43_pio_handle_txstatus(struct b43_wldev *dev,
160*4882a593Smuzhiyun 			     const struct b43_txstatus *status);
161*4882a593Smuzhiyun void b43_pio_rx(struct b43_pio_rxqueue *q);
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun void b43_pio_tx_suspend(struct b43_wldev *dev);
164*4882a593Smuzhiyun void b43_pio_tx_resume(struct b43_wldev *dev);
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun #endif /* B43_PIO_H_ */
167