1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef B43_PHY_LCN_H_ 3*4882a593Smuzhiyun #define B43_PHY_LCN_H_ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include "phy_common.h" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define B43_PHY_LCN_AFE_CTL1 B43_PHY_OFDM(0x03B) 9*4882a593Smuzhiyun #define B43_PHY_LCN_AFE_CTL2 B43_PHY_OFDM(0x03C) 10*4882a593Smuzhiyun #define B43_PHY_LCN_RF_CTL1 B43_PHY_OFDM(0x04C) 11*4882a593Smuzhiyun #define B43_PHY_LCN_RF_CTL2 B43_PHY_OFDM(0x04D) 12*4882a593Smuzhiyun #define B43_PHY_LCN_TABLE_ADDR B43_PHY_OFDM(0x055) /* Table address */ 13*4882a593Smuzhiyun #define B43_PHY_LCN_TABLE_DATALO B43_PHY_OFDM(0x056) /* Table data low */ 14*4882a593Smuzhiyun #define B43_PHY_LCN_TABLE_DATAHI B43_PHY_OFDM(0x057) /* Table data high */ 15*4882a593Smuzhiyun #define B43_PHY_LCN_RF_CTL3 B43_PHY_OFDM(0x0B0) 16*4882a593Smuzhiyun #define B43_PHY_LCN_RF_CTL4 B43_PHY_OFDM(0x0B1) 17*4882a593Smuzhiyun #define B43_PHY_LCN_RF_CTL5 B43_PHY_OFDM(0x0B7) 18*4882a593Smuzhiyun #define B43_PHY_LCN_RF_CTL6 B43_PHY_OFDM(0x0F9) 19*4882a593Smuzhiyun #define B43_PHY_LCN_RF_CTL7 B43_PHY_OFDM(0x0FA) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun struct b43_phy_lcn { 23*4882a593Smuzhiyun bool hw_pwr_ctl; 24*4882a593Smuzhiyun bool hw_pwr_ctl_capable; 25*4882a593Smuzhiyun u8 tx_pwr_curr_idx; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun struct b43_phy_operations; 30*4882a593Smuzhiyun extern const struct b43_phy_operations b43_phyops_lcn; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #endif /* B43_PHY_LCN_H_ */ 33