xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/broadcom/b43/phy_g.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #ifndef LINUX_B43_PHY_G_H_
3*4882a593Smuzhiyun #define LINUX_B43_PHY_G_H_
4*4882a593Smuzhiyun 
5*4882a593Smuzhiyun /* OFDM PHY registers are defined in the A-PHY header. */
6*4882a593Smuzhiyun #include "phy_a.h"
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun /* CCK (B) PHY Registers */
9*4882a593Smuzhiyun #define B43_PHY_VERSION_CCK		B43_PHY_CCK(0x00)	/* Versioning register for B-PHY */
10*4882a593Smuzhiyun #define B43_PHY_CCKBBANDCFG		B43_PHY_CCK(0x01)	/* Contains antenna 0/1 control bit */
11*4882a593Smuzhiyun #define B43_PHY_PGACTL			B43_PHY_CCK(0x15)	/* PGA control */
12*4882a593Smuzhiyun #define  B43_PHY_PGACTL_LPF		0x1000	/* Low pass filter (?) */
13*4882a593Smuzhiyun #define  B43_PHY_PGACTL_LOWBANDW	0x0040	/* Low bandwidth flag */
14*4882a593Smuzhiyun #define  B43_PHY_PGACTL_UNKNOWN		0xEFA0
15*4882a593Smuzhiyun #define B43_PHY_FBCTL1			B43_PHY_CCK(0x18)	/* Frequency bandwidth control 1 */
16*4882a593Smuzhiyun #define B43_PHY_ITSSI			B43_PHY_CCK(0x29)	/* Idle TSSI */
17*4882a593Smuzhiyun #define B43_PHY_LO_LEAKAGE		B43_PHY_CCK(0x2D)	/* Measured LO leakage */
18*4882a593Smuzhiyun #define B43_PHY_ENERGY			B43_PHY_CCK(0x33)	/* Energy */
19*4882a593Smuzhiyun #define B43_PHY_SYNCCTL			B43_PHY_CCK(0x35)
20*4882a593Smuzhiyun #define B43_PHY_FBCTL2			B43_PHY_CCK(0x38)	/* Frequency bandwidth control 2 */
21*4882a593Smuzhiyun #define B43_PHY_DACCTL			B43_PHY_CCK(0x60)	/* DAC control */
22*4882a593Smuzhiyun #define B43_PHY_RCCALOVER		B43_PHY_CCK(0x78)	/* RC calibration override */
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun /* Extended G-PHY Registers */
25*4882a593Smuzhiyun #define B43_PHY_CLASSCTL		B43_PHY_EXTG(0x02)	/* Classify control */
26*4882a593Smuzhiyun #define B43_PHY_GTABCTL			B43_PHY_EXTG(0x03)	/* G-PHY table control (see below) */
27*4882a593Smuzhiyun #define  B43_PHY_GTABOFF		0x03FF	/* G-PHY table offset (see below) */
28*4882a593Smuzhiyun #define  B43_PHY_GTABNR			0xFC00	/* G-PHY table number (see below) */
29*4882a593Smuzhiyun #define  B43_PHY_GTABNR_SHIFT		10
30*4882a593Smuzhiyun #define B43_PHY_GTABDATA		B43_PHY_EXTG(0x04)	/* G-PHY table data */
31*4882a593Smuzhiyun #define B43_PHY_LO_MASK			B43_PHY_EXTG(0x0F)	/* Local Oscillator control mask */
32*4882a593Smuzhiyun #define B43_PHY_LO_CTL			B43_PHY_EXTG(0x10)	/* Local Oscillator control */
33*4882a593Smuzhiyun #define B43_PHY_RFOVER			B43_PHY_EXTG(0x11)	/* RF override */
34*4882a593Smuzhiyun #define B43_PHY_RFOVERVAL		B43_PHY_EXTG(0x12)	/* RF override value */
35*4882a593Smuzhiyun #define  B43_PHY_RFOVERVAL_EXTLNA	0x8000
36*4882a593Smuzhiyun #define  B43_PHY_RFOVERVAL_LNA		0x7000
37*4882a593Smuzhiyun #define  B43_PHY_RFOVERVAL_LNA_SHIFT	12
38*4882a593Smuzhiyun #define  B43_PHY_RFOVERVAL_PGA		0x0F00
39*4882a593Smuzhiyun #define  B43_PHY_RFOVERVAL_PGA_SHIFT	8
40*4882a593Smuzhiyun #define  B43_PHY_RFOVERVAL_UNK		0x0010	/* Unknown, always set. */
41*4882a593Smuzhiyun #define  B43_PHY_RFOVERVAL_TRSWRX	0x00E0
42*4882a593Smuzhiyun #define  B43_PHY_RFOVERVAL_BW		0x0003	/* Bandwidth flags */
43*4882a593Smuzhiyun #define   B43_PHY_RFOVERVAL_BW_LPF	0x0001	/* Low Pass Filter */
44*4882a593Smuzhiyun #define   B43_PHY_RFOVERVAL_BW_LBW	0x0002	/* Low Bandwidth (when set), high when unset */
45*4882a593Smuzhiyun #define B43_PHY_ANALOGOVER		B43_PHY_EXTG(0x14)	/* Analog override */
46*4882a593Smuzhiyun #define B43_PHY_ANALOGOVERVAL		B43_PHY_EXTG(0x15)	/* Analog override value */
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun /*** G-PHY table numbers */
50*4882a593Smuzhiyun #define B43_GTAB(number, offset)	(((number) << B43_PHY_GTABNR_SHIFT) | (offset))
51*4882a593Smuzhiyun #define B43_GTAB_NRSSI			B43_GTAB(0x00, 0)
52*4882a593Smuzhiyun #define B43_GTAB_TRFEMW			B43_GTAB(0x0C, 0x120)
53*4882a593Smuzhiyun #define B43_GTAB_ORIGTR			B43_GTAB(0x2E, 0x298)
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun u16 b43_gtab_read(struct b43_wldev *dev, u16 table, u16 offset);
56*4882a593Smuzhiyun void b43_gtab_write(struct b43_wldev *dev, u16 table, u16 offset, u16 value);
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun /* Returns the boolean whether "TX Magnification" is enabled. */
60*4882a593Smuzhiyun #define has_tx_magnification(phy) \
61*4882a593Smuzhiyun 	(((phy)->rev >= 2) &&			\
62*4882a593Smuzhiyun 	 ((phy)->radio_ver == 0x2050) &&	\
63*4882a593Smuzhiyun 	 ((phy)->radio_rev == 8))
64*4882a593Smuzhiyun /* Card uses the loopback gain stuff */
65*4882a593Smuzhiyun #define has_loopback_gain(phy) \
66*4882a593Smuzhiyun 	(((phy)->rev > 1) || ((phy)->gmode))
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun /* Radio Attenuation (RF Attenuation) */
69*4882a593Smuzhiyun struct b43_rfatt {
70*4882a593Smuzhiyun 	u8 att;			/* Attenuation value */
71*4882a593Smuzhiyun 	bool with_padmix;	/* Flag, PAD Mixer enabled. */
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun struct b43_rfatt_list {
74*4882a593Smuzhiyun 	/* Attenuation values list */
75*4882a593Smuzhiyun 	const struct b43_rfatt *list;
76*4882a593Smuzhiyun 	u8 len;
77*4882a593Smuzhiyun 	/* Minimum/Maximum attenuation values */
78*4882a593Smuzhiyun 	u8 min_val;
79*4882a593Smuzhiyun 	u8 max_val;
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun /* Returns true, if the values are the same. */
b43_compare_rfatt(const struct b43_rfatt * a,const struct b43_rfatt * b)83*4882a593Smuzhiyun static inline bool b43_compare_rfatt(const struct b43_rfatt *a,
84*4882a593Smuzhiyun 				     const struct b43_rfatt *b)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun 	return ((a->att == b->att) &&
87*4882a593Smuzhiyun 		(a->with_padmix == b->with_padmix));
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun /* Baseband Attenuation */
91*4882a593Smuzhiyun struct b43_bbatt {
92*4882a593Smuzhiyun 	u8 att;			/* Attenuation value */
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun struct b43_bbatt_list {
95*4882a593Smuzhiyun 	/* Attenuation values list */
96*4882a593Smuzhiyun 	const struct b43_bbatt *list;
97*4882a593Smuzhiyun 	u8 len;
98*4882a593Smuzhiyun 	/* Minimum/Maximum attenuation values */
99*4882a593Smuzhiyun 	u8 min_val;
100*4882a593Smuzhiyun 	u8 max_val;
101*4882a593Smuzhiyun };
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun /* Returns true, if the values are the same. */
b43_compare_bbatt(const struct b43_bbatt * a,const struct b43_bbatt * b)104*4882a593Smuzhiyun static inline bool b43_compare_bbatt(const struct b43_bbatt *a,
105*4882a593Smuzhiyun 				     const struct b43_bbatt *b)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun 	return (a->att == b->att);
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun /* tx_control bits. */
111*4882a593Smuzhiyun #define B43_TXCTL_PA3DB		0x40	/* PA Gain 3dB */
112*4882a593Smuzhiyun #define B43_TXCTL_PA2DB		0x20	/* PA Gain 2dB */
113*4882a593Smuzhiyun #define B43_TXCTL_TXMIX		0x10	/* TX Mixer Gain */
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun struct b43_txpower_lo_control;
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun struct b43_phy_g {
118*4882a593Smuzhiyun 	/* ACI (adjacent channel interference) flags. */
119*4882a593Smuzhiyun 	bool aci_enable;
120*4882a593Smuzhiyun 	bool aci_wlan_automatic;
121*4882a593Smuzhiyun 	bool aci_hw_rssi;
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	/* Radio switched on/off */
124*4882a593Smuzhiyun 	bool radio_on;
125*4882a593Smuzhiyun 	struct {
126*4882a593Smuzhiyun 		/* Values saved when turning the radio off.
127*4882a593Smuzhiyun 		 * They are needed when turning it on again. */
128*4882a593Smuzhiyun 		bool valid;
129*4882a593Smuzhiyun 		u16 rfover;
130*4882a593Smuzhiyun 		u16 rfoverval;
131*4882a593Smuzhiyun 	} radio_off_context;
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	u16 minlowsig[2];
134*4882a593Smuzhiyun 	u16 minlowsigpos[2];
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	/* Pointer to the table used to convert a
137*4882a593Smuzhiyun 	 * TSSI value to dBm-Q5.2 */
138*4882a593Smuzhiyun 	const s8 *tssi2dbm;
139*4882a593Smuzhiyun 	/* tssi2dbm is kmalloc()ed. Only used for free()ing. */
140*4882a593Smuzhiyun 	bool dyn_tssi_tbl;
141*4882a593Smuzhiyun 	/* Target idle TSSI */
142*4882a593Smuzhiyun 	int tgt_idle_tssi;
143*4882a593Smuzhiyun 	/* Current idle TSSI */
144*4882a593Smuzhiyun 	int cur_idle_tssi;
145*4882a593Smuzhiyun 	/* The current average TSSI. */
146*4882a593Smuzhiyun 	u8 average_tssi;
147*4882a593Smuzhiyun 	/* Current TX power level attenuation control values */
148*4882a593Smuzhiyun 	struct b43_bbatt bbatt;
149*4882a593Smuzhiyun 	struct b43_rfatt rfatt;
150*4882a593Smuzhiyun 	u8 tx_control;		/* B43_TXCTL_XXX */
151*4882a593Smuzhiyun 	/* The calculated attenuation deltas that are used later
152*4882a593Smuzhiyun 	 * when adjusting the actual power output. */
153*4882a593Smuzhiyun 	int bbatt_delta;
154*4882a593Smuzhiyun 	int rfatt_delta;
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 	/* LocalOscillator control values. */
157*4882a593Smuzhiyun 	struct b43_txpower_lo_control *lo_control;
158*4882a593Smuzhiyun 	/* Values from b43_calc_loopback_gain() */
159*4882a593Smuzhiyun 	s16 max_lb_gain;	/* Maximum Loopback gain in hdB */
160*4882a593Smuzhiyun 	s16 trsw_rx_gain;	/* TRSW RX gain in hdB */
161*4882a593Smuzhiyun 	s16 lna_lod_gain;	/* LNA lod */
162*4882a593Smuzhiyun 	s16 lna_gain;		/* LNA */
163*4882a593Smuzhiyun 	s16 pga_gain;		/* PGA */
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 	/* Current Interference Mitigation mode */
166*4882a593Smuzhiyun 	int interfmode;
167*4882a593Smuzhiyun 	/* Stack of saved values from the Interference Mitigation code.
168*4882a593Smuzhiyun 	 * Each value in the stack is laid out as follows:
169*4882a593Smuzhiyun 	 * bit 0-11:  offset
170*4882a593Smuzhiyun 	 * bit 12-15: register ID
171*4882a593Smuzhiyun 	 * bit 16-32: value
172*4882a593Smuzhiyun 	 * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
173*4882a593Smuzhiyun 	 */
174*4882a593Smuzhiyun #define B43_INTERFSTACK_SIZE	26
175*4882a593Smuzhiyun 	u32 interfstack[B43_INTERFSTACK_SIZE];	//FIXME: use a data structure
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	/* Saved values from the NRSSI Slope calculation */
178*4882a593Smuzhiyun 	s16 nrssi[2];
179*4882a593Smuzhiyun 	s32 nrssislope;
180*4882a593Smuzhiyun 	/* In memory nrssi lookup table. */
181*4882a593Smuzhiyun 	s8 nrssi_lt[64];
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 	u16 lofcal;
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	u16 initval;		//FIXME rename?
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun 	/* The device does address auto increment for the OFDM tables.
188*4882a593Smuzhiyun 	 * We cache the previously used address here and omit the address
189*4882a593Smuzhiyun 	 * write on the next table access, if possible. */
190*4882a593Smuzhiyun 	u16 ofdmtab_addr; /* The address currently set in hardware. */
191*4882a593Smuzhiyun 	enum { /* The last data flow direction. */
192*4882a593Smuzhiyun 		B43_OFDMTAB_DIRECTION_UNKNOWN = 0,
193*4882a593Smuzhiyun 		B43_OFDMTAB_DIRECTION_READ,
194*4882a593Smuzhiyun 		B43_OFDMTAB_DIRECTION_WRITE,
195*4882a593Smuzhiyun 	} ofdmtab_addr_direction;
196*4882a593Smuzhiyun };
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun void b43_gphy_set_baseband_attenuation(struct b43_wldev *dev,
199*4882a593Smuzhiyun 				       u16 baseband_attenuation);
200*4882a593Smuzhiyun void b43_gphy_channel_switch(struct b43_wldev *dev,
201*4882a593Smuzhiyun 			     unsigned int channel,
202*4882a593Smuzhiyun 			     bool synthetic_pu_workaround);
203*4882a593Smuzhiyun u8 * b43_generate_dyn_tssi2dbm_tab(struct b43_wldev *dev,
204*4882a593Smuzhiyun 				   s16 pab0, s16 pab1, s16 pab2);
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun struct b43_phy_operations;
207*4882a593Smuzhiyun extern const struct b43_phy_operations b43_phyops_g;
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun #endif /* LINUX_B43_PHY_G_H_ */
210