1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef LINUX_B43_PHY_COMMON_H_ 3*4882a593Smuzhiyun #define LINUX_B43_PHY_COMMON_H_ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <linux/types.h> 6*4882a593Smuzhiyun #include <linux/nl80211.h> 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun struct b43_wldev; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* PHY register routing bits */ 11*4882a593Smuzhiyun #define B43_PHYROUTE 0x0C00 /* PHY register routing bits mask */ 12*4882a593Smuzhiyun #define B43_PHYROUTE_BASE 0x0000 /* Base registers */ 13*4882a593Smuzhiyun #define B43_PHYROUTE_OFDM_GPHY 0x0400 /* OFDM register routing for G-PHYs */ 14*4882a593Smuzhiyun #define B43_PHYROUTE_EXT_GPHY 0x0800 /* Extended G-PHY registers */ 15*4882a593Smuzhiyun #define B43_PHYROUTE_N_BMODE 0x0C00 /* N-PHY BMODE registers */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* CCK (B-PHY) registers. */ 18*4882a593Smuzhiyun #define B43_PHY_CCK(reg) ((reg) | B43_PHYROUTE_BASE) 19*4882a593Smuzhiyun /* N-PHY registers. */ 20*4882a593Smuzhiyun #define B43_PHY_N(reg) ((reg) | B43_PHYROUTE_BASE) 21*4882a593Smuzhiyun /* N-PHY BMODE registers. */ 22*4882a593Smuzhiyun #define B43_PHY_N_BMODE(reg) ((reg) | B43_PHYROUTE_N_BMODE) 23*4882a593Smuzhiyun /* OFDM (A-PHY) registers. */ 24*4882a593Smuzhiyun #define B43_PHY_OFDM(reg) ((reg) | B43_PHYROUTE_OFDM_GPHY) 25*4882a593Smuzhiyun /* Extended G-PHY registers. */ 26*4882a593Smuzhiyun #define B43_PHY_EXTG(reg) ((reg) | B43_PHYROUTE_EXT_GPHY) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* Masks for the PHY versioning registers. */ 30*4882a593Smuzhiyun #define B43_PHYVER_ANALOG 0xF000 31*4882a593Smuzhiyun #define B43_PHYVER_ANALOG_SHIFT 12 32*4882a593Smuzhiyun #define B43_PHYVER_TYPE 0x0F00 33*4882a593Smuzhiyun #define B43_PHYVER_TYPE_SHIFT 8 34*4882a593Smuzhiyun #define B43_PHYVER_VERSION 0x00FF 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* PHY writes need to be flushed if we reach limit */ 37*4882a593Smuzhiyun #define B43_MAX_WRITES_IN_ROW 24 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /** 40*4882a593Smuzhiyun * enum b43_interference_mitigation - Interference Mitigation mode 41*4882a593Smuzhiyun * 42*4882a593Smuzhiyun * @B43_INTERFMODE_NONE: Disabled 43*4882a593Smuzhiyun * @B43_INTERFMODE_NONWLAN: Non-WLAN Interference Mitigation 44*4882a593Smuzhiyun * @B43_INTERFMODE_MANUALWLAN: WLAN Interference Mitigation 45*4882a593Smuzhiyun * @B43_INTERFMODE_AUTOWLAN: Automatic WLAN Interference Mitigation 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun enum b43_interference_mitigation { 48*4882a593Smuzhiyun B43_INTERFMODE_NONE, 49*4882a593Smuzhiyun B43_INTERFMODE_NONWLAN, 50*4882a593Smuzhiyun B43_INTERFMODE_MANUALWLAN, 51*4882a593Smuzhiyun B43_INTERFMODE_AUTOWLAN, 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* Antenna identifiers */ 55*4882a593Smuzhiyun enum { 56*4882a593Smuzhiyun B43_ANTENNA0 = 0, /* Antenna 0 */ 57*4882a593Smuzhiyun B43_ANTENNA1 = 1, /* Antenna 1 */ 58*4882a593Smuzhiyun B43_ANTENNA_AUTO0 = 2, /* Automatic, starting with antenna 0 */ 59*4882a593Smuzhiyun B43_ANTENNA_AUTO1 = 3, /* Automatic, starting with antenna 1 */ 60*4882a593Smuzhiyun B43_ANTENNA2 = 4, 61*4882a593Smuzhiyun B43_ANTENNA3 = 8, 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun B43_ANTENNA_AUTO = B43_ANTENNA_AUTO0, 64*4882a593Smuzhiyun B43_ANTENNA_DEFAULT = B43_ANTENNA_AUTO, 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /** 68*4882a593Smuzhiyun * enum b43_txpwr_result - Return value for the recalc_txpower PHY op. 69*4882a593Smuzhiyun * 70*4882a593Smuzhiyun * @B43_TXPWR_RES_NEED_ADJUST: Values changed. Hardware adjustment is needed. 71*4882a593Smuzhiyun * @B43_TXPWR_RES_DONE: No more work to do. Everything is done. 72*4882a593Smuzhiyun */ 73*4882a593Smuzhiyun enum b43_txpwr_result { 74*4882a593Smuzhiyun B43_TXPWR_RES_NEED_ADJUST, 75*4882a593Smuzhiyun B43_TXPWR_RES_DONE, 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /** 79*4882a593Smuzhiyun * struct b43_phy_operations - Function pointers for PHY ops. 80*4882a593Smuzhiyun * 81*4882a593Smuzhiyun * @allocate: Allocate and initialise the PHY data structures. 82*4882a593Smuzhiyun * Must not be NULL. 83*4882a593Smuzhiyun * @free: Destroy and free the PHY data structures. 84*4882a593Smuzhiyun * Must not be NULL. 85*4882a593Smuzhiyun * 86*4882a593Smuzhiyun * @prepare_structs: Prepare the PHY data structures. 87*4882a593Smuzhiyun * The data structures allocated in @allocate are 88*4882a593Smuzhiyun * initialized here. 89*4882a593Smuzhiyun * Must not be NULL. 90*4882a593Smuzhiyun * @prepare_hardware: Prepare the PHY. This is called before b43_chip_init to 91*4882a593Smuzhiyun * do some early early PHY hardware init. 92*4882a593Smuzhiyun * Can be NULL, if not required. 93*4882a593Smuzhiyun * @init: Initialize the PHY. 94*4882a593Smuzhiyun * Must not be NULL. 95*4882a593Smuzhiyun * @exit: Shutdown the PHY. 96*4882a593Smuzhiyun * Can be NULL, if not required. 97*4882a593Smuzhiyun * 98*4882a593Smuzhiyun * @phy_read: Read from a PHY register. 99*4882a593Smuzhiyun * Must not be NULL. 100*4882a593Smuzhiyun * @phy_write: Write to a PHY register. 101*4882a593Smuzhiyun * Must not be NULL. 102*4882a593Smuzhiyun * @phy_maskset: Maskset a PHY register, taking shortcuts. 103*4882a593Smuzhiyun * If it is NULL, a generic algorithm is used. 104*4882a593Smuzhiyun * @radio_read: Read from a Radio register. 105*4882a593Smuzhiyun * Must not be NULL. 106*4882a593Smuzhiyun * @radio_write: Write to a Radio register. 107*4882a593Smuzhiyun * Must not be NULL. 108*4882a593Smuzhiyun * 109*4882a593Smuzhiyun * @supports_hwpctl: Returns a boolean whether Hardware Power Control 110*4882a593Smuzhiyun * is supported or not. 111*4882a593Smuzhiyun * If NULL, hwpctl is assumed to be never supported. 112*4882a593Smuzhiyun * @software_rfkill: Turn the radio ON or OFF. 113*4882a593Smuzhiyun * Possible state values are 114*4882a593Smuzhiyun * RFKILL_STATE_SOFT_BLOCKED or 115*4882a593Smuzhiyun * RFKILL_STATE_UNBLOCKED 116*4882a593Smuzhiyun * Must not be NULL. 117*4882a593Smuzhiyun * @switch_analog: Turn the Analog on/off. 118*4882a593Smuzhiyun * Must not be NULL. 119*4882a593Smuzhiyun * @switch_channel: Switch the radio to another channel. 120*4882a593Smuzhiyun * Must not be NULL. 121*4882a593Smuzhiyun * @get_default_chan: Just returns the default channel number. 122*4882a593Smuzhiyun * Must not be NULL. 123*4882a593Smuzhiyun * @set_rx_antenna: Set the antenna used for RX. 124*4882a593Smuzhiyun * Can be NULL, if not supported. 125*4882a593Smuzhiyun * @interf_mitigation: Switch the Interference Mitigation mode. 126*4882a593Smuzhiyun * Can be NULL, if not supported. 127*4882a593Smuzhiyun * 128*4882a593Smuzhiyun * @recalc_txpower: Recalculate the transmission power parameters. 129*4882a593Smuzhiyun * This callback has to recalculate the TX power settings, 130*4882a593Smuzhiyun * but does not need to write them to the hardware, yet. 131*4882a593Smuzhiyun * Returns enum b43_txpwr_result to indicate whether the hardware 132*4882a593Smuzhiyun * needs to be adjusted. 133*4882a593Smuzhiyun * If B43_TXPWR_NEED_ADJUST is returned, @adjust_txpower 134*4882a593Smuzhiyun * will be called later. 135*4882a593Smuzhiyun * If the parameter "ignore_tssi" is true, the TSSI values should 136*4882a593Smuzhiyun * be ignored and a recalculation of the power settings should be 137*4882a593Smuzhiyun * done even if the TSSI values did not change. 138*4882a593Smuzhiyun * This function may sleep, but should not. 139*4882a593Smuzhiyun * Must not be NULL. 140*4882a593Smuzhiyun * @adjust_txpower: Write the previously calculated TX power settings 141*4882a593Smuzhiyun * (from @recalc_txpower) to the hardware. 142*4882a593Smuzhiyun * This function may sleep. 143*4882a593Smuzhiyun * Can be NULL, if (and ONLY if) @recalc_txpower _always_ 144*4882a593Smuzhiyun * returns B43_TXPWR_RES_DONE. 145*4882a593Smuzhiyun * 146*4882a593Smuzhiyun * @pwork_15sec: Periodic work. Called every 15 seconds. 147*4882a593Smuzhiyun * Can be NULL, if not required. 148*4882a593Smuzhiyun * @pwork_60sec: Periodic work. Called every 60 seconds. 149*4882a593Smuzhiyun * Can be NULL, if not required. 150*4882a593Smuzhiyun */ 151*4882a593Smuzhiyun struct b43_phy_operations { 152*4882a593Smuzhiyun /* Initialisation */ 153*4882a593Smuzhiyun int (*allocate)(struct b43_wldev *dev); 154*4882a593Smuzhiyun void (*free)(struct b43_wldev *dev); 155*4882a593Smuzhiyun void (*prepare_structs)(struct b43_wldev *dev); 156*4882a593Smuzhiyun int (*prepare_hardware)(struct b43_wldev *dev); 157*4882a593Smuzhiyun int (*init)(struct b43_wldev *dev); 158*4882a593Smuzhiyun void (*exit)(struct b43_wldev *dev); 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun /* Register access */ 161*4882a593Smuzhiyun u16 (*phy_read)(struct b43_wldev *dev, u16 reg); 162*4882a593Smuzhiyun void (*phy_write)(struct b43_wldev *dev, u16 reg, u16 value); 163*4882a593Smuzhiyun void (*phy_maskset)(struct b43_wldev *dev, u16 reg, u16 mask, u16 set); 164*4882a593Smuzhiyun u16 (*radio_read)(struct b43_wldev *dev, u16 reg); 165*4882a593Smuzhiyun void (*radio_write)(struct b43_wldev *dev, u16 reg, u16 value); 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun /* Radio */ 168*4882a593Smuzhiyun bool (*supports_hwpctl)(struct b43_wldev *dev); 169*4882a593Smuzhiyun void (*software_rfkill)(struct b43_wldev *dev, bool blocked); 170*4882a593Smuzhiyun void (*switch_analog)(struct b43_wldev *dev, bool on); 171*4882a593Smuzhiyun int (*switch_channel)(struct b43_wldev *dev, unsigned int new_channel); 172*4882a593Smuzhiyun unsigned int (*get_default_chan)(struct b43_wldev *dev); 173*4882a593Smuzhiyun void (*set_rx_antenna)(struct b43_wldev *dev, int antenna); 174*4882a593Smuzhiyun int (*interf_mitigation)(struct b43_wldev *dev, 175*4882a593Smuzhiyun enum b43_interference_mitigation new_mode); 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun /* Transmission power adjustment */ 178*4882a593Smuzhiyun enum b43_txpwr_result (*recalc_txpower)(struct b43_wldev *dev, 179*4882a593Smuzhiyun bool ignore_tssi); 180*4882a593Smuzhiyun void (*adjust_txpower)(struct b43_wldev *dev); 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun /* Misc */ 183*4882a593Smuzhiyun void (*pwork_15sec)(struct b43_wldev *dev); 184*4882a593Smuzhiyun void (*pwork_60sec)(struct b43_wldev *dev); 185*4882a593Smuzhiyun }; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun struct b43_phy_g; 188*4882a593Smuzhiyun struct b43_phy_n; 189*4882a593Smuzhiyun struct b43_phy_lp; 190*4882a593Smuzhiyun struct b43_phy_ht; 191*4882a593Smuzhiyun struct b43_phy_lcn; 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun struct b43_phy { 194*4882a593Smuzhiyun /* Hardware operation callbacks. */ 195*4882a593Smuzhiyun const struct b43_phy_operations *ops; 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun /* Most hardware context information is stored in the standard- 198*4882a593Smuzhiyun * specific data structures pointed to by the pointers below. 199*4882a593Smuzhiyun * Only one of them is valid (the currently enabled PHY). */ 200*4882a593Smuzhiyun #ifdef CONFIG_B43_DEBUG 201*4882a593Smuzhiyun /* No union for debug build to force NULL derefs in buggy code. */ 202*4882a593Smuzhiyun struct { 203*4882a593Smuzhiyun #else 204*4882a593Smuzhiyun union { 205*4882a593Smuzhiyun #endif 206*4882a593Smuzhiyun /* G-PHY specific information */ 207*4882a593Smuzhiyun struct b43_phy_g *g; 208*4882a593Smuzhiyun /* N-PHY specific information */ 209*4882a593Smuzhiyun struct b43_phy_n *n; 210*4882a593Smuzhiyun /* LP-PHY specific information */ 211*4882a593Smuzhiyun struct b43_phy_lp *lp; 212*4882a593Smuzhiyun /* HT-PHY specific information */ 213*4882a593Smuzhiyun struct b43_phy_ht *ht; 214*4882a593Smuzhiyun /* LCN-PHY specific information */ 215*4882a593Smuzhiyun struct b43_phy_lcn *lcn; 216*4882a593Smuzhiyun /* AC-PHY specific information */ 217*4882a593Smuzhiyun struct b43_phy_ac *ac; 218*4882a593Smuzhiyun }; 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun /* Band support flags. */ 221*4882a593Smuzhiyun bool supports_2ghz; 222*4882a593Smuzhiyun bool supports_5ghz; 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun /* Is GMODE (2 GHz mode) bit enabled? */ 225*4882a593Smuzhiyun bool gmode; 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun /* After power reset full init has to be performed */ 228*4882a593Smuzhiyun bool do_full_init; 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun /* Analog Type */ 231*4882a593Smuzhiyun u8 analog; 232*4882a593Smuzhiyun /* B43_PHYTYPE_ */ 233*4882a593Smuzhiyun u8 type; 234*4882a593Smuzhiyun /* PHY revision number. */ 235*4882a593Smuzhiyun u8 rev; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun /* Count writes since last read */ 238*4882a593Smuzhiyun u8 writes_counter; 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun /* Radio versioning */ 241*4882a593Smuzhiyun u16 radio_manuf; /* Radio manufacturer */ 242*4882a593Smuzhiyun u16 radio_ver; /* Radio version */ 243*4882a593Smuzhiyun u8 radio_rev; /* Radio revision */ 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun /* Software state of the radio */ 246*4882a593Smuzhiyun bool radio_on; 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun /* Desired TX power level (in dBm). 249*4882a593Smuzhiyun * This is set by the user and adjusted in b43_phy_xmitpower(). */ 250*4882a593Smuzhiyun int desired_txpower; 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun /* Hardware Power Control enabled? */ 253*4882a593Smuzhiyun bool hardware_power_control; 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun /* The time (in absolute jiffies) when the next TX power output 256*4882a593Smuzhiyun * check is needed. */ 257*4882a593Smuzhiyun unsigned long next_txpwr_check_time; 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun /* Current channel */ 260*4882a593Smuzhiyun struct cfg80211_chan_def *chandef; 261*4882a593Smuzhiyun unsigned int channel; 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun /* PHY TX errors counter. */ 264*4882a593Smuzhiyun atomic_t txerr_cnt; 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun #ifdef CONFIG_B43_DEBUG 267*4882a593Smuzhiyun /* PHY registers locked (w.r.t. firmware) */ 268*4882a593Smuzhiyun bool phy_locked; 269*4882a593Smuzhiyun /* Radio registers locked (w.r.t. firmware) */ 270*4882a593Smuzhiyun bool radio_locked; 271*4882a593Smuzhiyun #endif /* B43_DEBUG */ 272*4882a593Smuzhiyun }; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun /** 276*4882a593Smuzhiyun * b43_phy_allocate - Allocate PHY structs 277*4882a593Smuzhiyun * Allocate the PHY data structures, based on the current dev->phy.type 278*4882a593Smuzhiyun */ 279*4882a593Smuzhiyun int b43_phy_allocate(struct b43_wldev *dev); 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun /** 282*4882a593Smuzhiyun * b43_phy_free - Free PHY structs 283*4882a593Smuzhiyun */ 284*4882a593Smuzhiyun void b43_phy_free(struct b43_wldev *dev); 285*4882a593Smuzhiyun 286*4882a593Smuzhiyun /** 287*4882a593Smuzhiyun * b43_phy_init - Initialise the PHY 288*4882a593Smuzhiyun */ 289*4882a593Smuzhiyun int b43_phy_init(struct b43_wldev *dev); 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun /** 292*4882a593Smuzhiyun * b43_phy_exit - Cleanup PHY 293*4882a593Smuzhiyun */ 294*4882a593Smuzhiyun void b43_phy_exit(struct b43_wldev *dev); 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun /** 297*4882a593Smuzhiyun * b43_has_hardware_pctl - Hardware Power Control supported? 298*4882a593Smuzhiyun * Returns a boolean, whether hardware power control is supported. 299*4882a593Smuzhiyun */ 300*4882a593Smuzhiyun bool b43_has_hardware_pctl(struct b43_wldev *dev); 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun /** 303*4882a593Smuzhiyun * b43_phy_read - 16bit PHY register read access 304*4882a593Smuzhiyun */ 305*4882a593Smuzhiyun u16 b43_phy_read(struct b43_wldev *dev, u16 reg); 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun /** 308*4882a593Smuzhiyun * b43_phy_write - 16bit PHY register write access 309*4882a593Smuzhiyun */ 310*4882a593Smuzhiyun void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value); 311*4882a593Smuzhiyun 312*4882a593Smuzhiyun /** 313*4882a593Smuzhiyun * b43_phy_copy - copy contents of 16bit PHY register to another 314*4882a593Smuzhiyun */ 315*4882a593Smuzhiyun void b43_phy_copy(struct b43_wldev *dev, u16 destreg, u16 srcreg); 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun /** 318*4882a593Smuzhiyun * b43_phy_mask - Mask a PHY register with a mask 319*4882a593Smuzhiyun */ 320*4882a593Smuzhiyun void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask); 321*4882a593Smuzhiyun 322*4882a593Smuzhiyun /** 323*4882a593Smuzhiyun * b43_phy_set - OR a PHY register with a bitmap 324*4882a593Smuzhiyun */ 325*4882a593Smuzhiyun void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set); 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun /** 328*4882a593Smuzhiyun * b43_phy_maskset - Mask and OR a PHY register with a mask and bitmap 329*4882a593Smuzhiyun */ 330*4882a593Smuzhiyun void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set); 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun /** 333*4882a593Smuzhiyun * b43_radio_read - 16bit Radio register read access 334*4882a593Smuzhiyun */ 335*4882a593Smuzhiyun u16 b43_radio_read(struct b43_wldev *dev, u16 reg); 336*4882a593Smuzhiyun #define b43_radio_read16 b43_radio_read /* DEPRECATED */ 337*4882a593Smuzhiyun 338*4882a593Smuzhiyun /** 339*4882a593Smuzhiyun * b43_radio_write - 16bit Radio register write access 340*4882a593Smuzhiyun */ 341*4882a593Smuzhiyun void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value); 342*4882a593Smuzhiyun #define b43_radio_write16 b43_radio_write /* DEPRECATED */ 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun /** 345*4882a593Smuzhiyun * b43_radio_mask - Mask a 16bit radio register with a mask 346*4882a593Smuzhiyun */ 347*4882a593Smuzhiyun void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask); 348*4882a593Smuzhiyun 349*4882a593Smuzhiyun /** 350*4882a593Smuzhiyun * b43_radio_set - OR a 16bit radio register with a bitmap 351*4882a593Smuzhiyun */ 352*4882a593Smuzhiyun void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set); 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun /** 355*4882a593Smuzhiyun * b43_radio_maskset - Mask and OR a radio register with a mask and bitmap 356*4882a593Smuzhiyun */ 357*4882a593Smuzhiyun void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set); 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun /** 360*4882a593Smuzhiyun * b43_radio_wait_value - Waits for a given value in masked register read 361*4882a593Smuzhiyun */ 362*4882a593Smuzhiyun bool b43_radio_wait_value(struct b43_wldev *dev, u16 offset, u16 mask, 363*4882a593Smuzhiyun u16 value, int delay, int timeout); 364*4882a593Smuzhiyun 365*4882a593Smuzhiyun /** 366*4882a593Smuzhiyun * b43_radio_lock - Lock firmware radio register access 367*4882a593Smuzhiyun */ 368*4882a593Smuzhiyun void b43_radio_lock(struct b43_wldev *dev); 369*4882a593Smuzhiyun 370*4882a593Smuzhiyun /** 371*4882a593Smuzhiyun * b43_radio_unlock - Unlock firmware radio register access 372*4882a593Smuzhiyun */ 373*4882a593Smuzhiyun void b43_radio_unlock(struct b43_wldev *dev); 374*4882a593Smuzhiyun 375*4882a593Smuzhiyun /** 376*4882a593Smuzhiyun * b43_phy_lock - Lock firmware PHY register access 377*4882a593Smuzhiyun */ 378*4882a593Smuzhiyun void b43_phy_lock(struct b43_wldev *dev); 379*4882a593Smuzhiyun 380*4882a593Smuzhiyun /** 381*4882a593Smuzhiyun * b43_phy_unlock - Unlock firmware PHY register access 382*4882a593Smuzhiyun */ 383*4882a593Smuzhiyun void b43_phy_unlock(struct b43_wldev *dev); 384*4882a593Smuzhiyun 385*4882a593Smuzhiyun void b43_phy_put_into_reset(struct b43_wldev *dev); 386*4882a593Smuzhiyun void b43_phy_take_out_of_reset(struct b43_wldev *dev); 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun /** 389*4882a593Smuzhiyun * b43_switch_channel - Switch to another channel 390*4882a593Smuzhiyun */ 391*4882a593Smuzhiyun int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel); 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun /** 394*4882a593Smuzhiyun * b43_software_rfkill - Turn the radio ON or OFF in software. 395*4882a593Smuzhiyun */ 396*4882a593Smuzhiyun void b43_software_rfkill(struct b43_wldev *dev, bool blocked); 397*4882a593Smuzhiyun 398*4882a593Smuzhiyun /** 399*4882a593Smuzhiyun * b43_phy_txpower_check - Check TX power output. 400*4882a593Smuzhiyun * 401*4882a593Smuzhiyun * Compare the current TX power output to the desired power emission 402*4882a593Smuzhiyun * and schedule an adjustment in case it mismatches. 403*4882a593Smuzhiyun * 404*4882a593Smuzhiyun * @flags: OR'ed enum b43_phy_txpower_check_flags flags. 405*4882a593Smuzhiyun * See the docs below. 406*4882a593Smuzhiyun */ 407*4882a593Smuzhiyun void b43_phy_txpower_check(struct b43_wldev *dev, unsigned int flags); 408*4882a593Smuzhiyun /** 409*4882a593Smuzhiyun * enum b43_phy_txpower_check_flags - Flags for b43_phy_txpower_check() 410*4882a593Smuzhiyun * 411*4882a593Smuzhiyun * @B43_TXPWR_IGNORE_TIME: Ignore the schedule time and force-redo 412*4882a593Smuzhiyun * the check now. 413*4882a593Smuzhiyun * @B43_TXPWR_IGNORE_TSSI: Redo the recalculation, even if the average 414*4882a593Smuzhiyun * TSSI did not change. 415*4882a593Smuzhiyun */ 416*4882a593Smuzhiyun enum b43_phy_txpower_check_flags { 417*4882a593Smuzhiyun B43_TXPWR_IGNORE_TIME = (1 << 0), 418*4882a593Smuzhiyun B43_TXPWR_IGNORE_TSSI = (1 << 1), 419*4882a593Smuzhiyun }; 420*4882a593Smuzhiyun 421*4882a593Smuzhiyun struct work_struct; 422*4882a593Smuzhiyun void b43_phy_txpower_adjust_work(struct work_struct *work); 423*4882a593Smuzhiyun 424*4882a593Smuzhiyun /** 425*4882a593Smuzhiyun * b43_phy_shm_tssi_read - Read the average of the last 4 TSSI from SHM. 426*4882a593Smuzhiyun * 427*4882a593Smuzhiyun * @shm_offset: The SHM address to read the values from. 428*4882a593Smuzhiyun * 429*4882a593Smuzhiyun * Returns the average of the 4 TSSI values, or a negative error code. 430*4882a593Smuzhiyun */ 431*4882a593Smuzhiyun int b43_phy_shm_tssi_read(struct b43_wldev *dev, u16 shm_offset); 432*4882a593Smuzhiyun 433*4882a593Smuzhiyun /** 434*4882a593Smuzhiyun * b43_phy_switch_analog_generic - Generic PHY operation for switching the Analog. 435*4882a593Smuzhiyun * 436*4882a593Smuzhiyun * It does the switching based on the PHY0 core register. 437*4882a593Smuzhiyun * Do _not_ call this directly. Only use it as a switch_analog callback 438*4882a593Smuzhiyun * for struct b43_phy_operations. 439*4882a593Smuzhiyun */ 440*4882a593Smuzhiyun void b43_phyop_switch_analog_generic(struct b43_wldev *dev, bool on); 441*4882a593Smuzhiyun 442*4882a593Smuzhiyun bool b43_is_40mhz(struct b43_wldev *dev); 443*4882a593Smuzhiyun 444*4882a593Smuzhiyun void b43_phy_force_clock(struct b43_wldev *dev, bool force); 445*4882a593Smuzhiyun 446*4882a593Smuzhiyun #endif /* LINUX_B43_PHY_COMMON_H_ */ 447