1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2002,2003 Oliver Kurth 4*4882a593Smuzhiyun * (c) 2003,2004 Joerg Albert <joerg.albert@gmx.de> 5*4882a593Smuzhiyun * (c) 2007 Guido Guenther <agx@sigxcpu.org> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This driver was based on information from the Sourceforge driver 8*4882a593Smuzhiyun * released and maintained by Atmel: 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * http://sourceforge.net/projects/atmelwlandriver/ 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * Although the code was completely re-written, 13*4882a593Smuzhiyun * it would have been impossible without Atmel's decision to 14*4882a593Smuzhiyun * release an Open Source driver (unfortunately the firmware was 15*4882a593Smuzhiyun * kept binary only). Thanks for that decision to Atmel! 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #ifndef _AT76_USB_H 19*4882a593Smuzhiyun #define _AT76_USB_H 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* Board types */ 22*4882a593Smuzhiyun enum board_type { 23*4882a593Smuzhiyun BOARD_503_ISL3861 = 1, 24*4882a593Smuzhiyun BOARD_503_ISL3863 = 2, 25*4882a593Smuzhiyun BOARD_503 = 3, 26*4882a593Smuzhiyun BOARD_503_ACC = 4, 27*4882a593Smuzhiyun BOARD_505 = 5, 28*4882a593Smuzhiyun BOARD_505_2958 = 6, 29*4882a593Smuzhiyun BOARD_505A = 7, 30*4882a593Smuzhiyun BOARD_505AMX = 8 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define CMD_STATUS_IDLE 0x00 34*4882a593Smuzhiyun #define CMD_STATUS_COMPLETE 0x01 35*4882a593Smuzhiyun #define CMD_STATUS_UNKNOWN 0x02 36*4882a593Smuzhiyun #define CMD_STATUS_INVALID_PARAMETER 0x03 37*4882a593Smuzhiyun #define CMD_STATUS_FUNCTION_NOT_SUPPORTED 0x04 38*4882a593Smuzhiyun #define CMD_STATUS_TIME_OUT 0x07 39*4882a593Smuzhiyun #define CMD_STATUS_IN_PROGRESS 0x08 40*4882a593Smuzhiyun #define CMD_STATUS_HOST_FAILURE 0xff 41*4882a593Smuzhiyun #define CMD_STATUS_SCAN_FAILED 0xf0 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* answers to get op mode */ 44*4882a593Smuzhiyun #define OPMODE_NONE 0x00 45*4882a593Smuzhiyun #define OPMODE_NORMAL_NIC_WITH_FLASH 0x01 46*4882a593Smuzhiyun #define OPMODE_HW_CONFIG_MODE 0x02 47*4882a593Smuzhiyun #define OPMODE_DFU_MODE_WITH_FLASH 0x03 48*4882a593Smuzhiyun #define OPMODE_NORMAL_NIC_WITHOUT_FLASH 0x04 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define CMD_SET_MIB 0x01 51*4882a593Smuzhiyun #define CMD_GET_MIB 0x02 52*4882a593Smuzhiyun #define CMD_SCAN 0x03 53*4882a593Smuzhiyun #define CMD_JOIN 0x04 54*4882a593Smuzhiyun #define CMD_START_IBSS 0x05 55*4882a593Smuzhiyun #define CMD_RADIO_ON 0x06 56*4882a593Smuzhiyun #define CMD_RADIO_OFF 0x07 57*4882a593Smuzhiyun #define CMD_STARTUP 0x0B 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define MIB_LOCAL 0x01 60*4882a593Smuzhiyun #define MIB_MAC_ADDR 0x02 61*4882a593Smuzhiyun #define MIB_MAC 0x03 62*4882a593Smuzhiyun #define MIB_MAC_MGMT 0x05 63*4882a593Smuzhiyun #define MIB_MAC_WEP 0x06 64*4882a593Smuzhiyun #define MIB_PHY 0x07 65*4882a593Smuzhiyun #define MIB_FW_VERSION 0x08 66*4882a593Smuzhiyun #define MIB_MDOMAIN 0x09 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define ADHOC_MODE 1 69*4882a593Smuzhiyun #define INFRASTRUCTURE_MODE 2 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* values for struct mib_local, field preamble_type */ 72*4882a593Smuzhiyun #define PREAMBLE_TYPE_LONG 0 73*4882a593Smuzhiyun #define PREAMBLE_TYPE_SHORT 1 74*4882a593Smuzhiyun #define PREAMBLE_TYPE_AUTO 2 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* values for tx_rate */ 77*4882a593Smuzhiyun #define TX_RATE_1MBIT 0 78*4882a593Smuzhiyun #define TX_RATE_2MBIT 1 79*4882a593Smuzhiyun #define TX_RATE_5_5MBIT 2 80*4882a593Smuzhiyun #define TX_RATE_11MBIT 3 81*4882a593Smuzhiyun #define TX_RATE_AUTO 4 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* power management modes */ 84*4882a593Smuzhiyun #define AT76_PM_OFF 1 85*4882a593Smuzhiyun #define AT76_PM_ON 2 86*4882a593Smuzhiyun #define AT76_PM_SMART 3 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun struct hwcfg_r505 { 89*4882a593Smuzhiyun u8 cr39_values[14]; 90*4882a593Smuzhiyun u8 reserved1[14]; 91*4882a593Smuzhiyun u8 bb_cr[14]; 92*4882a593Smuzhiyun u8 pidvid[4]; 93*4882a593Smuzhiyun u8 mac_addr[ETH_ALEN]; 94*4882a593Smuzhiyun u8 regulatory_domain; 95*4882a593Smuzhiyun u8 reserved2[14]; 96*4882a593Smuzhiyun u8 cr15_values[14]; 97*4882a593Smuzhiyun u8 reserved3[3]; 98*4882a593Smuzhiyun } __packed; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun struct hwcfg_rfmd { 101*4882a593Smuzhiyun u8 cr20_values[14]; 102*4882a593Smuzhiyun u8 cr21_values[14]; 103*4882a593Smuzhiyun u8 bb_cr[14]; 104*4882a593Smuzhiyun u8 pidvid[4]; 105*4882a593Smuzhiyun u8 mac_addr[ETH_ALEN]; 106*4882a593Smuzhiyun u8 regulatory_domain; 107*4882a593Smuzhiyun u8 low_power_values[14]; 108*4882a593Smuzhiyun u8 normal_power_values[14]; 109*4882a593Smuzhiyun u8 reserved1[3]; 110*4882a593Smuzhiyun } __packed; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun struct hwcfg_intersil { 113*4882a593Smuzhiyun u8 mac_addr[ETH_ALEN]; 114*4882a593Smuzhiyun u8 cr31_values[14]; 115*4882a593Smuzhiyun u8 cr58_values[14]; 116*4882a593Smuzhiyun u8 pidvid[4]; 117*4882a593Smuzhiyun u8 regulatory_domain; 118*4882a593Smuzhiyun u8 reserved[1]; 119*4882a593Smuzhiyun } __packed; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun union at76_hwcfg { 122*4882a593Smuzhiyun struct hwcfg_intersil i; 123*4882a593Smuzhiyun struct hwcfg_rfmd r3; 124*4882a593Smuzhiyun struct hwcfg_r505 r5; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #define WEP_SMALL_KEY_LEN (40 / 8) 128*4882a593Smuzhiyun #define WEP_LARGE_KEY_LEN (104 / 8) 129*4882a593Smuzhiyun #define WEP_KEYS (4) 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun struct at76_card_config { 132*4882a593Smuzhiyun u8 exclude_unencrypted; 133*4882a593Smuzhiyun u8 promiscuous_mode; 134*4882a593Smuzhiyun u8 short_retry_limit; 135*4882a593Smuzhiyun u8 encryption_type; 136*4882a593Smuzhiyun __le16 rts_threshold; 137*4882a593Smuzhiyun __le16 fragmentation_threshold; /* 256..2346 */ 138*4882a593Smuzhiyun u8 basic_rate_set[4]; 139*4882a593Smuzhiyun u8 auto_rate_fallback; /* 0,1 */ 140*4882a593Smuzhiyun u8 channel; 141*4882a593Smuzhiyun u8 privacy_invoked; 142*4882a593Smuzhiyun u8 wep_default_key_id; /* 0..3 */ 143*4882a593Smuzhiyun u8 current_ssid[32]; 144*4882a593Smuzhiyun u8 wep_default_key_value[4][WEP_LARGE_KEY_LEN]; 145*4882a593Smuzhiyun u8 ssid_len; 146*4882a593Smuzhiyun u8 short_preamble; 147*4882a593Smuzhiyun __le16 beacon_period; 148*4882a593Smuzhiyun } __packed; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun struct at76_command { 151*4882a593Smuzhiyun u8 cmd; 152*4882a593Smuzhiyun u8 reserved; 153*4882a593Smuzhiyun __le16 size; 154*4882a593Smuzhiyun u8 data[]; 155*4882a593Smuzhiyun } __packed; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun /* Length of Atmel-specific Rx header before 802.11 frame */ 158*4882a593Smuzhiyun #define AT76_RX_HDRLEN offsetof(struct at76_rx_buffer, packet) 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun struct at76_rx_buffer { 161*4882a593Smuzhiyun __le16 wlength; 162*4882a593Smuzhiyun u8 rx_rate; 163*4882a593Smuzhiyun u8 newbss; 164*4882a593Smuzhiyun u8 fragmentation; 165*4882a593Smuzhiyun u8 rssi; 166*4882a593Smuzhiyun u8 link_quality; 167*4882a593Smuzhiyun u8 noise_level; 168*4882a593Smuzhiyun __le32 rx_time; 169*4882a593Smuzhiyun u8 packet[IEEE80211_MAX_FRAG_THRESHOLD]; 170*4882a593Smuzhiyun } __packed; 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun /* Length of Atmel-specific Tx header before 802.11 frame */ 173*4882a593Smuzhiyun #define AT76_TX_HDRLEN offsetof(struct at76_tx_buffer, packet) 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun struct at76_tx_buffer { 176*4882a593Smuzhiyun __le16 wlength; 177*4882a593Smuzhiyun u8 tx_rate; 178*4882a593Smuzhiyun u8 padding; 179*4882a593Smuzhiyun u8 reserved[4]; 180*4882a593Smuzhiyun u8 packet[IEEE80211_MAX_FRAG_THRESHOLD]; 181*4882a593Smuzhiyun } __packed; 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun /* defines for scan_type below */ 184*4882a593Smuzhiyun #define SCAN_TYPE_ACTIVE 0 185*4882a593Smuzhiyun #define SCAN_TYPE_PASSIVE 1 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun struct at76_req_scan { 188*4882a593Smuzhiyun u8 bssid[ETH_ALEN]; 189*4882a593Smuzhiyun u8 essid[32]; 190*4882a593Smuzhiyun u8 scan_type; 191*4882a593Smuzhiyun u8 channel; 192*4882a593Smuzhiyun __le16 probe_delay; 193*4882a593Smuzhiyun __le16 min_channel_time; 194*4882a593Smuzhiyun __le16 max_channel_time; 195*4882a593Smuzhiyun u8 essid_size; 196*4882a593Smuzhiyun u8 international_scan; 197*4882a593Smuzhiyun } __packed; 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun struct at76_req_ibss { 200*4882a593Smuzhiyun u8 bssid[ETH_ALEN]; 201*4882a593Smuzhiyun u8 essid[32]; 202*4882a593Smuzhiyun u8 bss_type; 203*4882a593Smuzhiyun u8 channel; 204*4882a593Smuzhiyun u8 essid_size; 205*4882a593Smuzhiyun u8 reserved[3]; 206*4882a593Smuzhiyun } __packed; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun struct at76_req_join { 209*4882a593Smuzhiyun u8 bssid[ETH_ALEN]; 210*4882a593Smuzhiyun u8 essid[32]; 211*4882a593Smuzhiyun u8 bss_type; 212*4882a593Smuzhiyun u8 channel; 213*4882a593Smuzhiyun __le16 timeout; 214*4882a593Smuzhiyun u8 essid_size; 215*4882a593Smuzhiyun u8 reserved; 216*4882a593Smuzhiyun } __packed; 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun struct mib_local { 219*4882a593Smuzhiyun u16 reserved0; 220*4882a593Smuzhiyun u8 beacon_enable; 221*4882a593Smuzhiyun u8 txautorate_fallback; 222*4882a593Smuzhiyun u8 reserved1; 223*4882a593Smuzhiyun u8 ssid_size; 224*4882a593Smuzhiyun u8 promiscuous_mode; 225*4882a593Smuzhiyun u16 reserved2; 226*4882a593Smuzhiyun u8 preamble_type; 227*4882a593Smuzhiyun u16 reserved3; 228*4882a593Smuzhiyun } __packed; 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun struct mib_mac_addr { 231*4882a593Smuzhiyun u8 mac_addr[ETH_ALEN]; 232*4882a593Smuzhiyun u8 res[2]; /* ??? */ 233*4882a593Smuzhiyun u8 group_addr[4][ETH_ALEN]; 234*4882a593Smuzhiyun u8 group_addr_status[4]; 235*4882a593Smuzhiyun } __packed; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun struct mib_mac { 238*4882a593Smuzhiyun __le32 max_tx_msdu_lifetime; 239*4882a593Smuzhiyun __le32 max_rx_lifetime; 240*4882a593Smuzhiyun __le16 frag_threshold; 241*4882a593Smuzhiyun __le16 rts_threshold; 242*4882a593Smuzhiyun __le16 cwmin; 243*4882a593Smuzhiyun __le16 cwmax; 244*4882a593Smuzhiyun u8 short_retry_time; 245*4882a593Smuzhiyun u8 long_retry_time; 246*4882a593Smuzhiyun u8 scan_type; /* active or passive */ 247*4882a593Smuzhiyun u8 scan_channel; 248*4882a593Smuzhiyun __le16 probe_delay; /* delay before ProbeReq in active scan, RO */ 249*4882a593Smuzhiyun __le16 min_channel_time; 250*4882a593Smuzhiyun __le16 max_channel_time; 251*4882a593Smuzhiyun __le16 listen_interval; 252*4882a593Smuzhiyun u8 desired_ssid[32]; 253*4882a593Smuzhiyun u8 desired_bssid[ETH_ALEN]; 254*4882a593Smuzhiyun u8 desired_bsstype; /* ad-hoc or infrastructure */ 255*4882a593Smuzhiyun u8 reserved2; 256*4882a593Smuzhiyun } __packed; 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun struct mib_mac_mgmt { 259*4882a593Smuzhiyun __le16 beacon_period; 260*4882a593Smuzhiyun __le16 CFP_max_duration; 261*4882a593Smuzhiyun __le16 medium_occupancy_limit; 262*4882a593Smuzhiyun __le16 station_id; /* assoc id */ 263*4882a593Smuzhiyun __le16 ATIM_window; 264*4882a593Smuzhiyun u8 CFP_mode; 265*4882a593Smuzhiyun u8 privacy_option_implemented; 266*4882a593Smuzhiyun u8 DTIM_period; 267*4882a593Smuzhiyun u8 CFP_period; 268*4882a593Smuzhiyun u8 current_bssid[ETH_ALEN]; 269*4882a593Smuzhiyun u8 current_essid[32]; 270*4882a593Smuzhiyun u8 current_bss_type; 271*4882a593Smuzhiyun u8 power_mgmt_mode; 272*4882a593Smuzhiyun /* rfmd and 505 */ 273*4882a593Smuzhiyun u8 ibss_change; 274*4882a593Smuzhiyun u8 res; 275*4882a593Smuzhiyun u8 multi_domain_capability_implemented; 276*4882a593Smuzhiyun u8 multi_domain_capability_enabled; 277*4882a593Smuzhiyun u8 country_string[IEEE80211_COUNTRY_STRING_LEN]; 278*4882a593Smuzhiyun u8 reserved[3]; 279*4882a593Smuzhiyun } __packed; 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun struct mib_mac_wep { 282*4882a593Smuzhiyun u8 privacy_invoked; /* 0 disable encr., 1 enable encr */ 283*4882a593Smuzhiyun u8 wep_default_key_id; 284*4882a593Smuzhiyun u8 wep_key_mapping_len; 285*4882a593Smuzhiyun u8 exclude_unencrypted; 286*4882a593Smuzhiyun __le32 wep_icv_error_count; 287*4882a593Smuzhiyun __le32 wep_excluded_count; 288*4882a593Smuzhiyun u8 wep_default_keyvalue[WEP_KEYS][WEP_LARGE_KEY_LEN]; 289*4882a593Smuzhiyun u8 encryption_level; /* 1 for 40bit, 2 for 104bit encryption */ 290*4882a593Smuzhiyun } __packed; 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun struct mib_phy { 293*4882a593Smuzhiyun __le32 ed_threshold; 294*4882a593Smuzhiyun 295*4882a593Smuzhiyun __le16 slot_time; 296*4882a593Smuzhiyun __le16 sifs_time; 297*4882a593Smuzhiyun __le16 preamble_length; 298*4882a593Smuzhiyun __le16 plcp_header_length; 299*4882a593Smuzhiyun __le16 mpdu_max_length; 300*4882a593Smuzhiyun __le16 cca_mode_supported; 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun u8 operation_rate_set[4]; 303*4882a593Smuzhiyun u8 channel_id; 304*4882a593Smuzhiyun u8 current_cca_mode; 305*4882a593Smuzhiyun u8 phy_type; 306*4882a593Smuzhiyun u8 current_reg_domain; 307*4882a593Smuzhiyun } __packed; 308*4882a593Smuzhiyun 309*4882a593Smuzhiyun struct mib_fw_version { 310*4882a593Smuzhiyun u8 major; 311*4882a593Smuzhiyun u8 minor; 312*4882a593Smuzhiyun u8 patch; 313*4882a593Smuzhiyun u8 build; 314*4882a593Smuzhiyun } __packed; 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun struct mib_mdomain { 317*4882a593Smuzhiyun u8 tx_powerlevel[14]; 318*4882a593Smuzhiyun u8 channel_list[14]; /* 0 for invalid channels */ 319*4882a593Smuzhiyun } __packed; 320*4882a593Smuzhiyun 321*4882a593Smuzhiyun struct set_mib_buffer { 322*4882a593Smuzhiyun u8 type; 323*4882a593Smuzhiyun u8 size; 324*4882a593Smuzhiyun u8 index; 325*4882a593Smuzhiyun u8 reserved; 326*4882a593Smuzhiyun union { 327*4882a593Smuzhiyun u8 byte; 328*4882a593Smuzhiyun __le16 word; 329*4882a593Smuzhiyun u8 addr[ETH_ALEN]; 330*4882a593Smuzhiyun struct mib_mac_wep wep_mib; 331*4882a593Smuzhiyun } data; 332*4882a593Smuzhiyun } __packed; 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun struct at76_fw_header { 335*4882a593Smuzhiyun __le32 crc; /* CRC32 of the whole image */ 336*4882a593Smuzhiyun __le32 board_type; /* firmware compatibility code */ 337*4882a593Smuzhiyun u8 build; /* firmware build number */ 338*4882a593Smuzhiyun u8 patch; /* firmware patch level */ 339*4882a593Smuzhiyun u8 minor; /* firmware minor version */ 340*4882a593Smuzhiyun u8 major; /* firmware major version */ 341*4882a593Smuzhiyun __le32 str_offset; /* offset of the copyright string */ 342*4882a593Smuzhiyun __le32 int_fw_offset; /* internal firmware image offset */ 343*4882a593Smuzhiyun __le32 int_fw_len; /* internal firmware image length */ 344*4882a593Smuzhiyun __le32 ext_fw_offset; /* external firmware image offset */ 345*4882a593Smuzhiyun __le32 ext_fw_len; /* external firmware image length */ 346*4882a593Smuzhiyun } __packed; 347*4882a593Smuzhiyun 348*4882a593Smuzhiyun /* a description of a regulatory domain and the allowed channels */ 349*4882a593Smuzhiyun struct reg_domain { 350*4882a593Smuzhiyun u16 code; 351*4882a593Smuzhiyun char const *name; 352*4882a593Smuzhiyun u32 channel_map; /* if bit N is set, channel (N+1) is allowed */ 353*4882a593Smuzhiyun }; 354*4882a593Smuzhiyun 355*4882a593Smuzhiyun /* Data for one loaded firmware file */ 356*4882a593Smuzhiyun struct fwentry { 357*4882a593Smuzhiyun const char *const fwname; 358*4882a593Smuzhiyun const struct firmware *fw; 359*4882a593Smuzhiyun int extfw_size; 360*4882a593Smuzhiyun int intfw_size; 361*4882a593Smuzhiyun /* pointer to loaded firmware, no need to free */ 362*4882a593Smuzhiyun u8 *extfw; /* external firmware, extfw_size bytes long */ 363*4882a593Smuzhiyun u8 *intfw; /* internal firmware, intfw_size bytes long */ 364*4882a593Smuzhiyun enum board_type board_type; /* board type */ 365*4882a593Smuzhiyun struct mib_fw_version fw_version; 366*4882a593Smuzhiyun int loaded; /* Loaded and parsed successfully */ 367*4882a593Smuzhiyun }; 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun struct at76_priv { 370*4882a593Smuzhiyun struct usb_device *udev; /* USB device pointer */ 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun struct sk_buff *rx_skb; /* skbuff for receiving data */ 373*4882a593Smuzhiyun struct sk_buff *tx_skb; /* skbuff for transmitting data */ 374*4882a593Smuzhiyun void *bulk_out_buffer; /* buffer for sending data */ 375*4882a593Smuzhiyun 376*4882a593Smuzhiyun struct urb *tx_urb; /* URB for sending data */ 377*4882a593Smuzhiyun struct urb *rx_urb; /* URB for receiving data */ 378*4882a593Smuzhiyun 379*4882a593Smuzhiyun unsigned int tx_pipe; /* bulk out pipe */ 380*4882a593Smuzhiyun unsigned int rx_pipe; /* bulk in pipe */ 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun struct mutex mtx; /* locks this structure */ 383*4882a593Smuzhiyun 384*4882a593Smuzhiyun /* work queues */ 385*4882a593Smuzhiyun struct work_struct work_set_promisc; 386*4882a593Smuzhiyun struct work_struct work_submit_rx; 387*4882a593Smuzhiyun struct work_struct work_join_bssid; 388*4882a593Smuzhiyun struct delayed_work dwork_hw_scan; 389*4882a593Smuzhiyun 390*4882a593Smuzhiyun struct tasklet_struct rx_tasklet; 391*4882a593Smuzhiyun 392*4882a593Smuzhiyun /* the WEP stuff */ 393*4882a593Smuzhiyun int wep_enabled; /* 1 if WEP is enabled */ 394*4882a593Smuzhiyun int wep_key_id; /* key id to be used */ 395*4882a593Smuzhiyun u8 wep_keys[WEP_KEYS][WEP_LARGE_KEY_LEN]; /* WEP keys */ 396*4882a593Smuzhiyun u8 wep_keys_len[WEP_KEYS]; /* length of WEP keys */ 397*4882a593Smuzhiyun 398*4882a593Smuzhiyun int channel; 399*4882a593Smuzhiyun int iw_mode; 400*4882a593Smuzhiyun u8 bssid[ETH_ALEN]; 401*4882a593Smuzhiyun u8 essid[IW_ESSID_MAX_SIZE]; 402*4882a593Smuzhiyun int essid_size; 403*4882a593Smuzhiyun int radio_on; 404*4882a593Smuzhiyun int promisc; 405*4882a593Smuzhiyun 406*4882a593Smuzhiyun int preamble_type; /* 0 - long, 1 - short, 2 - auto */ 407*4882a593Smuzhiyun int auth_mode; /* authentication type: 0 open, 1 shared key */ 408*4882a593Smuzhiyun int txrate; /* 0,1,2,3 = 1,2,5.5,11 Mbps, 4 is auto */ 409*4882a593Smuzhiyun int frag_threshold; /* threshold for fragmentation of tx packets */ 410*4882a593Smuzhiyun int rts_threshold; /* threshold for RTS mechanism */ 411*4882a593Smuzhiyun int short_retry_limit; 412*4882a593Smuzhiyun 413*4882a593Smuzhiyun int scan_min_time; /* scan min channel time */ 414*4882a593Smuzhiyun int scan_max_time; /* scan max channel time */ 415*4882a593Smuzhiyun int scan_mode; /* SCAN_TYPE_ACTIVE, SCAN_TYPE_PASSIVE */ 416*4882a593Smuzhiyun int scan_need_any; /* if set, need to scan for any ESSID */ 417*4882a593Smuzhiyun bool scanning; /* if set, the scan is running */ 418*4882a593Smuzhiyun 419*4882a593Smuzhiyun u16 assoc_id; /* current association ID, if associated */ 420*4882a593Smuzhiyun 421*4882a593Smuzhiyun u8 pm_mode; /* power management mode */ 422*4882a593Smuzhiyun u32 pm_period; /* power management period in microseconds */ 423*4882a593Smuzhiyun 424*4882a593Smuzhiyun struct reg_domain const *domain; /* reg domain description */ 425*4882a593Smuzhiyun 426*4882a593Smuzhiyun /* These fields contain HW config provided by the device (not all of 427*4882a593Smuzhiyun * these fields are used by all board types) */ 428*4882a593Smuzhiyun u8 mac_addr[ETH_ALEN]; 429*4882a593Smuzhiyun u8 regulatory_domain; 430*4882a593Smuzhiyun 431*4882a593Smuzhiyun struct at76_card_config card_config; 432*4882a593Smuzhiyun 433*4882a593Smuzhiyun enum board_type board_type; 434*4882a593Smuzhiyun struct mib_fw_version fw_version; 435*4882a593Smuzhiyun 436*4882a593Smuzhiyun unsigned int device_unplugged:1; 437*4882a593Smuzhiyun unsigned int netdev_registered:1; 438*4882a593Smuzhiyun struct set_mib_buffer mib_buf; /* global buffer for set_mib calls */ 439*4882a593Smuzhiyun 440*4882a593Smuzhiyun int beacon_period; /* period of mgmt beacons, Kus */ 441*4882a593Smuzhiyun 442*4882a593Smuzhiyun struct ieee80211_hw *hw; 443*4882a593Smuzhiyun int mac80211_registered; 444*4882a593Smuzhiyun }; 445*4882a593Smuzhiyun 446*4882a593Smuzhiyun #define AT76_SUPPORTED_FILTERS 0 447*4882a593Smuzhiyun 448*4882a593Smuzhiyun #define SCAN_POLL_INTERVAL (HZ / 4) 449*4882a593Smuzhiyun 450*4882a593Smuzhiyun #define CMD_COMPLETION_TIMEOUT (5 * HZ) 451*4882a593Smuzhiyun 452*4882a593Smuzhiyun #define DEF_RTS_THRESHOLD 1536 453*4882a593Smuzhiyun #define DEF_FRAG_THRESHOLD 1536 454*4882a593Smuzhiyun #define DEF_SHORT_RETRY_LIMIT 8 455*4882a593Smuzhiyun #define DEF_CHANNEL 10 456*4882a593Smuzhiyun #define DEF_SCAN_MIN_TIME 10 457*4882a593Smuzhiyun #define DEF_SCAN_MAX_TIME 120 458*4882a593Smuzhiyun 459*4882a593Smuzhiyun /* the max padding size for tx in bytes (see calc_padding) */ 460*4882a593Smuzhiyun #define MAX_PADDING_SIZE 53 461*4882a593Smuzhiyun 462*4882a593Smuzhiyun #endif /* _AT76_USB_H */ 463