1*4882a593Smuzhiyun /* SPDX-License-Identifier: ISC */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun * Copyright (c) 2012-2017 Qualcomm Atheros, Inc. 5*4882a593Smuzhiyun * Copyright (c) 2006-2012 Wilocity 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* 9*4882a593Smuzhiyun * This file contains the definitions of the WMI protocol specified in the 10*4882a593Smuzhiyun * Wireless Module Interface (WMI) for the Qualcomm 11*4882a593Smuzhiyun * 60 GHz wireless solution. 12*4882a593Smuzhiyun * It includes definitions of all the commands and events. 13*4882a593Smuzhiyun * Commands are messages from the host to the WM. 14*4882a593Smuzhiyun * Events are messages from the WM to the host. 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * This is an automatically generated file. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #ifndef __WILOCITY_WMI_H__ 20*4882a593Smuzhiyun #define __WILOCITY_WMI_H__ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define WMI_DEFAULT_ASSOC_STA (1) 23*4882a593Smuzhiyun #define WMI_MAC_LEN (6) 24*4882a593Smuzhiyun #define WMI_PROX_RANGE_NUM (3) 25*4882a593Smuzhiyun #define WMI_MAX_LOSS_DMG_BEACONS (20) 26*4882a593Smuzhiyun #define MAX_NUM_OF_SECTORS (128) 27*4882a593Smuzhiyun #define WMI_INVALID_TEMPERATURE (0xFFFFFFFF) 28*4882a593Smuzhiyun #define WMI_SCHED_MAX_ALLOCS_PER_CMD (4) 29*4882a593Smuzhiyun #define WMI_RF_DTYPE_LENGTH (3) 30*4882a593Smuzhiyun #define WMI_RF_ETYPE_LENGTH (3) 31*4882a593Smuzhiyun #define WMI_RF_RX2TX_LENGTH (3) 32*4882a593Smuzhiyun #define WMI_RF_ETYPE_VAL_PER_RANGE (5) 33*4882a593Smuzhiyun /* DTYPE configuration array size 34*4882a593Smuzhiyun * must always be kept equal to (WMI_RF_DTYPE_LENGTH+1) 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun #define WMI_RF_DTYPE_CONF_LENGTH (4) 37*4882a593Smuzhiyun /* ETYPE configuration array size 38*4882a593Smuzhiyun * must always be kept equal to 39*4882a593Smuzhiyun * (WMI_RF_ETYPE_LENGTH+WMI_RF_ETYPE_VAL_PER_RANGE) 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun #define WMI_RF_ETYPE_CONF_LENGTH (8) 42*4882a593Smuzhiyun /* RX2TX configuration array size 43*4882a593Smuzhiyun * must always be kept equal to (WMI_RF_RX2TX_LENGTH+1) 44*4882a593Smuzhiyun */ 45*4882a593Smuzhiyun #define WMI_RF_RX2TX_CONF_LENGTH (4) 46*4882a593Smuzhiyun /* Qos configuration */ 47*4882a593Smuzhiyun #define WMI_QOS_NUM_OF_PRIORITY (4) 48*4882a593Smuzhiyun #define WMI_QOS_MIN_DEFAULT_WEIGHT (10) 49*4882a593Smuzhiyun #define WMI_QOS_VRING_SLOT_MIN_MS (2) 50*4882a593Smuzhiyun #define WMI_QOS_VRING_SLOT_MAX_MS (10) 51*4882a593Smuzhiyun /* (WMI_QOS_MIN_DEFAULT_WEIGHT * WMI_QOS_VRING_SLOT_MAX_MS / 52*4882a593Smuzhiyun * WMI_QOS_VRING_SLOT_MIN_MS) 53*4882a593Smuzhiyun */ 54*4882a593Smuzhiyun #define WMI_QOS_MAX_WEIGHT 50 55*4882a593Smuzhiyun #define WMI_QOS_SET_VIF_PRIORITY (0xFF) 56*4882a593Smuzhiyun #define WMI_QOS_DEFAULT_PRIORITY (WMI_QOS_NUM_OF_PRIORITY) 57*4882a593Smuzhiyun #define WMI_MAX_XIF_PORTS_NUM (8) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* Mailbox interface 60*4882a593Smuzhiyun * used for commands and events 61*4882a593Smuzhiyun */ 62*4882a593Smuzhiyun enum wmi_mid { 63*4882a593Smuzhiyun MID_DEFAULT = 0x00, 64*4882a593Smuzhiyun FIRST_DBG_MID_ID = 0x10, 65*4882a593Smuzhiyun LAST_DBG_MID_ID = 0xFE, 66*4882a593Smuzhiyun MID_BROADCAST = 0xFF, 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* FW capability IDs 70*4882a593Smuzhiyun * Each ID maps to a bit in a 32-bit bitmask value provided by the FW to 71*4882a593Smuzhiyun * the host 72*4882a593Smuzhiyun */ 73*4882a593Smuzhiyun enum wmi_fw_capability { 74*4882a593Smuzhiyun WMI_FW_CAPABILITY_FTM = 0, 75*4882a593Smuzhiyun WMI_FW_CAPABILITY_PS_CONFIG = 1, 76*4882a593Smuzhiyun WMI_FW_CAPABILITY_RF_SECTORS = 2, 77*4882a593Smuzhiyun WMI_FW_CAPABILITY_MGMT_RETRY_LIMIT = 3, 78*4882a593Smuzhiyun WMI_FW_CAPABILITY_AP_SME_OFFLOAD_PARTIAL = 4, 79*4882a593Smuzhiyun WMI_FW_CAPABILITY_WMI_ONLY = 5, 80*4882a593Smuzhiyun WMI_FW_CAPABILITY_THERMAL_THROTTLING = 7, 81*4882a593Smuzhiyun WMI_FW_CAPABILITY_D3_SUSPEND = 8, 82*4882a593Smuzhiyun WMI_FW_CAPABILITY_LONG_RANGE = 9, 83*4882a593Smuzhiyun WMI_FW_CAPABILITY_FIXED_SCHEDULING = 10, 84*4882a593Smuzhiyun WMI_FW_CAPABILITY_MULTI_DIRECTED_OMNIS = 11, 85*4882a593Smuzhiyun WMI_FW_CAPABILITY_RSSI_REPORTING = 12, 86*4882a593Smuzhiyun WMI_FW_CAPABILITY_SET_SILENT_RSSI_TABLE = 13, 87*4882a593Smuzhiyun WMI_FW_CAPABILITY_LO_POWER_CALIB_FROM_OTP = 14, 88*4882a593Smuzhiyun WMI_FW_CAPABILITY_PNO = 15, 89*4882a593Smuzhiyun WMI_FW_CAPABILITY_CHANNEL_BONDING = 17, 90*4882a593Smuzhiyun WMI_FW_CAPABILITY_REF_CLOCK_CONTROL = 18, 91*4882a593Smuzhiyun WMI_FW_CAPABILITY_AP_SME_OFFLOAD_NONE = 19, 92*4882a593Smuzhiyun WMI_FW_CAPABILITY_MULTI_VIFS = 20, 93*4882a593Smuzhiyun WMI_FW_CAPABILITY_FT_ROAMING = 21, 94*4882a593Smuzhiyun WMI_FW_CAPABILITY_BACK_WIN_SIZE_64 = 22, 95*4882a593Smuzhiyun WMI_FW_CAPABILITY_AMSDU = 23, 96*4882a593Smuzhiyun WMI_FW_CAPABILITY_RAW_MODE = 24, 97*4882a593Smuzhiyun WMI_FW_CAPABILITY_TX_REQ_EXT = 25, 98*4882a593Smuzhiyun WMI_FW_CAPABILITY_CHANNEL_4 = 26, 99*4882a593Smuzhiyun WMI_FW_CAPABILITY_IPA = 27, 100*4882a593Smuzhiyun WMI_FW_CAPABILITY_TEMPERATURE_ALL_RF = 30, 101*4882a593Smuzhiyun WMI_FW_CAPABILITY_SPLIT_REKEY = 31, 102*4882a593Smuzhiyun WMI_FW_CAPABILITY_MAX, 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* WMI_CMD_HDR */ 106*4882a593Smuzhiyun struct wmi_cmd_hdr { 107*4882a593Smuzhiyun u8 mid; 108*4882a593Smuzhiyun u8 reserved; 109*4882a593Smuzhiyun __le16 command_id; 110*4882a593Smuzhiyun __le32 fw_timestamp; 111*4882a593Smuzhiyun } __packed; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun /* List of Commands */ 114*4882a593Smuzhiyun enum wmi_command_id { 115*4882a593Smuzhiyun WMI_CONNECT_CMDID = 0x01, 116*4882a593Smuzhiyun WMI_DISCONNECT_CMDID = 0x03, 117*4882a593Smuzhiyun WMI_DISCONNECT_STA_CMDID = 0x04, 118*4882a593Smuzhiyun WMI_START_SCHED_SCAN_CMDID = 0x05, 119*4882a593Smuzhiyun WMI_STOP_SCHED_SCAN_CMDID = 0x06, 120*4882a593Smuzhiyun WMI_START_SCAN_CMDID = 0x07, 121*4882a593Smuzhiyun WMI_SET_BSS_FILTER_CMDID = 0x09, 122*4882a593Smuzhiyun WMI_SET_PROBED_SSID_CMDID = 0x0A, 123*4882a593Smuzhiyun /* deprecated */ 124*4882a593Smuzhiyun WMI_SET_LISTEN_INT_CMDID = 0x0B, 125*4882a593Smuzhiyun WMI_FT_AUTH_CMDID = 0x0C, 126*4882a593Smuzhiyun WMI_FT_REASSOC_CMDID = 0x0D, 127*4882a593Smuzhiyun WMI_UPDATE_FT_IES_CMDID = 0x0E, 128*4882a593Smuzhiyun WMI_BCON_CTRL_CMDID = 0x0F, 129*4882a593Smuzhiyun WMI_ADD_CIPHER_KEY_CMDID = 0x16, 130*4882a593Smuzhiyun WMI_DELETE_CIPHER_KEY_CMDID = 0x17, 131*4882a593Smuzhiyun WMI_PCP_CONF_CMDID = 0x18, 132*4882a593Smuzhiyun WMI_SET_APPIE_CMDID = 0x3F, 133*4882a593Smuzhiyun WMI_SET_WSC_STATUS_CMDID = 0x41, 134*4882a593Smuzhiyun WMI_PXMT_RANGE_CFG_CMDID = 0x42, 135*4882a593Smuzhiyun WMI_PXMT_SNR2_RANGE_CFG_CMDID = 0x43, 136*4882a593Smuzhiyun WMI_RADAR_GENERAL_CONFIG_CMDID = 0x100, 137*4882a593Smuzhiyun WMI_RADAR_CONFIG_SELECT_CMDID = 0x101, 138*4882a593Smuzhiyun WMI_RADAR_PARAMS_CONFIG_CMDID = 0x102, 139*4882a593Smuzhiyun WMI_RADAR_SET_MODE_CMDID = 0x103, 140*4882a593Smuzhiyun WMI_RADAR_CONTROL_CMDID = 0x104, 141*4882a593Smuzhiyun WMI_RADAR_PCI_CONTROL_CMDID = 0x105, 142*4882a593Smuzhiyun WMI_MEM_READ_CMDID = 0x800, 143*4882a593Smuzhiyun WMI_MEM_WR_CMDID = 0x801, 144*4882a593Smuzhiyun WMI_ECHO_CMDID = 0x803, 145*4882a593Smuzhiyun WMI_DEEP_ECHO_CMDID = 0x804, 146*4882a593Smuzhiyun WMI_CONFIG_MAC_CMDID = 0x805, 147*4882a593Smuzhiyun /* deprecated */ 148*4882a593Smuzhiyun WMI_CONFIG_PHY_DEBUG_CMDID = 0x806, 149*4882a593Smuzhiyun WMI_ADD_DEBUG_TX_PCKT_CMDID = 0x808, 150*4882a593Smuzhiyun WMI_PHY_GET_STATISTICS_CMDID = 0x809, 151*4882a593Smuzhiyun /* deprecated */ 152*4882a593Smuzhiyun WMI_FS_TUNE_CMDID = 0x80A, 153*4882a593Smuzhiyun /* deprecated */ 154*4882a593Smuzhiyun WMI_CORR_MEASURE_CMDID = 0x80B, 155*4882a593Smuzhiyun WMI_READ_RSSI_CMDID = 0x80C, 156*4882a593Smuzhiyun WMI_TEMP_SENSE_CMDID = 0x80E, 157*4882a593Smuzhiyun WMI_DC_CALIB_CMDID = 0x80F, 158*4882a593Smuzhiyun /* deprecated */ 159*4882a593Smuzhiyun WMI_SEND_TONE_CMDID = 0x810, 160*4882a593Smuzhiyun /* deprecated */ 161*4882a593Smuzhiyun WMI_IQ_TX_CALIB_CMDID = 0x811, 162*4882a593Smuzhiyun /* deprecated */ 163*4882a593Smuzhiyun WMI_IQ_RX_CALIB_CMDID = 0x812, 164*4882a593Smuzhiyun WMI_SET_WORK_MODE_CMDID = 0x815, 165*4882a593Smuzhiyun WMI_LO_LEAKAGE_CALIB_CMDID = 0x816, 166*4882a593Smuzhiyun WMI_LO_POWER_CALIB_FROM_OTP_CMDID = 0x817, 167*4882a593Smuzhiyun WMI_SILENT_RSSI_CALIB_CMDID = 0x81D, 168*4882a593Smuzhiyun /* deprecated */ 169*4882a593Smuzhiyun WMI_RF_RX_TEST_CMDID = 0x81E, 170*4882a593Smuzhiyun WMI_CFG_RX_CHAIN_CMDID = 0x820, 171*4882a593Smuzhiyun WMI_VRING_CFG_CMDID = 0x821, 172*4882a593Smuzhiyun WMI_BCAST_VRING_CFG_CMDID = 0x822, 173*4882a593Smuzhiyun WMI_RING_BA_EN_CMDID = 0x823, 174*4882a593Smuzhiyun WMI_RING_BA_DIS_CMDID = 0x824, 175*4882a593Smuzhiyun WMI_RCP_ADDBA_RESP_CMDID = 0x825, 176*4882a593Smuzhiyun WMI_RCP_DELBA_CMDID = 0x826, 177*4882a593Smuzhiyun WMI_SET_SSID_CMDID = 0x827, 178*4882a593Smuzhiyun WMI_GET_SSID_CMDID = 0x828, 179*4882a593Smuzhiyun WMI_SET_PCP_CHANNEL_CMDID = 0x829, 180*4882a593Smuzhiyun WMI_GET_PCP_CHANNEL_CMDID = 0x82A, 181*4882a593Smuzhiyun WMI_SW_TX_REQ_CMDID = 0x82B, 182*4882a593Smuzhiyun /* Event is shared between WMI_SW_TX_REQ_CMDID and 183*4882a593Smuzhiyun * WMI_SW_TX_REQ_EXT_CMDID 184*4882a593Smuzhiyun */ 185*4882a593Smuzhiyun WMI_SW_TX_REQ_EXT_CMDID = 0x82C, 186*4882a593Smuzhiyun WMI_MLME_PUSH_CMDID = 0x835, 187*4882a593Smuzhiyun WMI_BEAMFORMING_MGMT_CMDID = 0x836, 188*4882a593Smuzhiyun WMI_BF_TXSS_MGMT_CMDID = 0x837, 189*4882a593Smuzhiyun WMI_BF_SM_MGMT_CMDID = 0x838, 190*4882a593Smuzhiyun WMI_BF_RXSS_MGMT_CMDID = 0x839, 191*4882a593Smuzhiyun WMI_BF_TRIG_CMDID = 0x83A, 192*4882a593Smuzhiyun WMI_RCP_ADDBA_RESP_EDMA_CMDID = 0x83B, 193*4882a593Smuzhiyun WMI_LINK_MAINTAIN_CFG_WRITE_CMDID = 0x842, 194*4882a593Smuzhiyun WMI_LINK_MAINTAIN_CFG_READ_CMDID = 0x843, 195*4882a593Smuzhiyun WMI_SET_LINK_MONITOR_CMDID = 0x845, 196*4882a593Smuzhiyun WMI_SET_SECTORS_CMDID = 0x849, 197*4882a593Smuzhiyun WMI_MAINTAIN_PAUSE_CMDID = 0x850, 198*4882a593Smuzhiyun WMI_MAINTAIN_RESUME_CMDID = 0x851, 199*4882a593Smuzhiyun WMI_RS_MGMT_CMDID = 0x852, 200*4882a593Smuzhiyun WMI_RF_MGMT_CMDID = 0x853, 201*4882a593Smuzhiyun WMI_RF_XPM_READ_CMDID = 0x856, 202*4882a593Smuzhiyun WMI_RF_XPM_WRITE_CMDID = 0x857, 203*4882a593Smuzhiyun WMI_LED_CFG_CMDID = 0x858, 204*4882a593Smuzhiyun WMI_SET_CONNECT_SNR_THR_CMDID = 0x85B, 205*4882a593Smuzhiyun WMI_SET_ACTIVE_SILENT_RSSI_TABLE_CMDID = 0x85C, 206*4882a593Smuzhiyun WMI_RF_PWR_ON_DELAY_CMDID = 0x85D, 207*4882a593Smuzhiyun WMI_SET_HIGH_POWER_TABLE_PARAMS_CMDID = 0x85E, 208*4882a593Smuzhiyun WMI_FIXED_SCHEDULING_UL_CONFIG_CMDID = 0x85F, 209*4882a593Smuzhiyun /* Performance monitoring commands */ 210*4882a593Smuzhiyun WMI_BF_CTRL_CMDID = 0x862, 211*4882a593Smuzhiyun WMI_NOTIFY_REQ_CMDID = 0x863, 212*4882a593Smuzhiyun WMI_GET_STATUS_CMDID = 0x864, 213*4882a593Smuzhiyun WMI_GET_RF_STATUS_CMDID = 0x866, 214*4882a593Smuzhiyun WMI_GET_BASEBAND_TYPE_CMDID = 0x867, 215*4882a593Smuzhiyun WMI_VRING_SWITCH_TIMING_CONFIG_CMDID = 0x868, 216*4882a593Smuzhiyun WMI_UNIT_TEST_CMDID = 0x900, 217*4882a593Smuzhiyun WMI_FLASH_READ_CMDID = 0x902, 218*4882a593Smuzhiyun WMI_FLASH_WRITE_CMDID = 0x903, 219*4882a593Smuzhiyun /* Power management */ 220*4882a593Smuzhiyun WMI_TRAFFIC_SUSPEND_CMDID = 0x904, 221*4882a593Smuzhiyun WMI_TRAFFIC_RESUME_CMDID = 0x905, 222*4882a593Smuzhiyun /* P2P */ 223*4882a593Smuzhiyun WMI_P2P_CFG_CMDID = 0x910, 224*4882a593Smuzhiyun WMI_PORT_ALLOCATE_CMDID = 0x911, 225*4882a593Smuzhiyun WMI_PORT_DELETE_CMDID = 0x912, 226*4882a593Smuzhiyun WMI_POWER_MGMT_CFG_CMDID = 0x913, 227*4882a593Smuzhiyun WMI_START_LISTEN_CMDID = 0x914, 228*4882a593Smuzhiyun WMI_START_SEARCH_CMDID = 0x915, 229*4882a593Smuzhiyun WMI_DISCOVERY_START_CMDID = 0x916, 230*4882a593Smuzhiyun WMI_DISCOVERY_STOP_CMDID = 0x917, 231*4882a593Smuzhiyun WMI_PCP_START_CMDID = 0x918, 232*4882a593Smuzhiyun WMI_PCP_STOP_CMDID = 0x919, 233*4882a593Smuzhiyun WMI_GET_PCP_FACTOR_CMDID = 0x91B, 234*4882a593Smuzhiyun /* Power Save Configuration Commands */ 235*4882a593Smuzhiyun WMI_PS_DEV_PROFILE_CFG_CMDID = 0x91C, 236*4882a593Smuzhiyun WMI_RS_ENABLE_CMDID = 0x91E, 237*4882a593Smuzhiyun WMI_RS_CFG_EX_CMDID = 0x91F, 238*4882a593Smuzhiyun WMI_GET_DETAILED_RS_RES_EX_CMDID = 0x920, 239*4882a593Smuzhiyun /* deprecated */ 240*4882a593Smuzhiyun WMI_RS_CFG_CMDID = 0x921, 241*4882a593Smuzhiyun /* deprecated */ 242*4882a593Smuzhiyun WMI_GET_DETAILED_RS_RES_CMDID = 0x922, 243*4882a593Smuzhiyun WMI_AOA_MEAS_CMDID = 0x923, 244*4882a593Smuzhiyun WMI_BRP_SET_ANT_LIMIT_CMDID = 0x924, 245*4882a593Smuzhiyun WMI_SET_MGMT_RETRY_LIMIT_CMDID = 0x930, 246*4882a593Smuzhiyun WMI_GET_MGMT_RETRY_LIMIT_CMDID = 0x931, 247*4882a593Smuzhiyun WMI_NEW_STA_CMDID = 0x935, 248*4882a593Smuzhiyun WMI_DEL_STA_CMDID = 0x936, 249*4882a593Smuzhiyun WMI_SET_THERMAL_THROTTLING_CFG_CMDID = 0x940, 250*4882a593Smuzhiyun WMI_GET_THERMAL_THROTTLING_CFG_CMDID = 0x941, 251*4882a593Smuzhiyun /* Read Power Save profile type */ 252*4882a593Smuzhiyun WMI_PS_DEV_PROFILE_CFG_READ_CMDID = 0x942, 253*4882a593Smuzhiyun WMI_TSF_SYNC_CMDID = 0x973, 254*4882a593Smuzhiyun WMI_TOF_SESSION_START_CMDID = 0x991, 255*4882a593Smuzhiyun WMI_TOF_GET_CAPABILITIES_CMDID = 0x992, 256*4882a593Smuzhiyun WMI_TOF_SET_LCR_CMDID = 0x993, 257*4882a593Smuzhiyun WMI_TOF_SET_LCI_CMDID = 0x994, 258*4882a593Smuzhiyun WMI_TOF_CFG_RESPONDER_CMDID = 0x996, 259*4882a593Smuzhiyun WMI_TOF_SET_TX_RX_OFFSET_CMDID = 0x997, 260*4882a593Smuzhiyun WMI_TOF_GET_TX_RX_OFFSET_CMDID = 0x998, 261*4882a593Smuzhiyun WMI_TOF_CHANNEL_INFO_CMDID = 0x999, 262*4882a593Smuzhiyun WMI_GET_RF_SECTOR_PARAMS_CMDID = 0x9A0, 263*4882a593Smuzhiyun WMI_SET_RF_SECTOR_PARAMS_CMDID = 0x9A1, 264*4882a593Smuzhiyun WMI_GET_SELECTED_RF_SECTOR_INDEX_CMDID = 0x9A2, 265*4882a593Smuzhiyun WMI_SET_SELECTED_RF_SECTOR_INDEX_CMDID = 0x9A3, 266*4882a593Smuzhiyun WMI_SET_RF_SECTOR_ON_CMDID = 0x9A4, 267*4882a593Smuzhiyun WMI_PRIO_TX_SECTORS_ORDER_CMDID = 0x9A5, 268*4882a593Smuzhiyun WMI_PRIO_TX_SECTORS_NUMBER_CMDID = 0x9A6, 269*4882a593Smuzhiyun WMI_PRIO_TX_SECTORS_SET_DEFAULT_CFG_CMDID = 0x9A7, 270*4882a593Smuzhiyun /* deprecated */ 271*4882a593Smuzhiyun WMI_BF_CONTROL_CMDID = 0x9AA, 272*4882a593Smuzhiyun WMI_BF_CONTROL_EX_CMDID = 0x9AB, 273*4882a593Smuzhiyun WMI_TX_STATUS_RING_ADD_CMDID = 0x9C0, 274*4882a593Smuzhiyun WMI_RX_STATUS_RING_ADD_CMDID = 0x9C1, 275*4882a593Smuzhiyun WMI_TX_DESC_RING_ADD_CMDID = 0x9C2, 276*4882a593Smuzhiyun WMI_RX_DESC_RING_ADD_CMDID = 0x9C3, 277*4882a593Smuzhiyun WMI_BCAST_DESC_RING_ADD_CMDID = 0x9C4, 278*4882a593Smuzhiyun WMI_CFG_DEF_RX_OFFLOAD_CMDID = 0x9C5, 279*4882a593Smuzhiyun WMI_SCHEDULING_SCHEME_CMDID = 0xA01, 280*4882a593Smuzhiyun WMI_FIXED_SCHEDULING_CONFIG_CMDID = 0xA02, 281*4882a593Smuzhiyun WMI_ENABLE_FIXED_SCHEDULING_CMDID = 0xA03, 282*4882a593Smuzhiyun WMI_SET_MULTI_DIRECTED_OMNIS_CONFIG_CMDID = 0xA04, 283*4882a593Smuzhiyun WMI_SET_LONG_RANGE_CONFIG_CMDID = 0xA05, 284*4882a593Smuzhiyun WMI_GET_ASSOC_LIST_CMDID = 0xA06, 285*4882a593Smuzhiyun WMI_GET_CCA_INDICATIONS_CMDID = 0xA07, 286*4882a593Smuzhiyun WMI_SET_CCA_INDICATIONS_BI_AVG_NUM_CMDID = 0xA08, 287*4882a593Smuzhiyun WMI_INTERNAL_FW_IOCTL_CMDID = 0xA0B, 288*4882a593Smuzhiyun WMI_LINK_STATS_CMDID = 0xA0C, 289*4882a593Smuzhiyun WMI_SET_GRANT_MCS_CMDID = 0xA0E, 290*4882a593Smuzhiyun WMI_SET_AP_SLOT_SIZE_CMDID = 0xA0F, 291*4882a593Smuzhiyun WMI_SET_VRING_PRIORITY_WEIGHT_CMDID = 0xA10, 292*4882a593Smuzhiyun WMI_SET_VRING_PRIORITY_CMDID = 0xA11, 293*4882a593Smuzhiyun WMI_RBUFCAP_CFG_CMDID = 0xA12, 294*4882a593Smuzhiyun WMI_TEMP_SENSE_ALL_CMDID = 0xA13, 295*4882a593Smuzhiyun WMI_SET_MAC_ADDRESS_CMDID = 0xF003, 296*4882a593Smuzhiyun WMI_ABORT_SCAN_CMDID = 0xF007, 297*4882a593Smuzhiyun WMI_SET_PROMISCUOUS_MODE_CMDID = 0xF041, 298*4882a593Smuzhiyun /* deprecated */ 299*4882a593Smuzhiyun WMI_GET_PMK_CMDID = 0xF048, 300*4882a593Smuzhiyun WMI_SET_PASSPHRASE_CMDID = 0xF049, 301*4882a593Smuzhiyun /* deprecated */ 302*4882a593Smuzhiyun WMI_SEND_ASSOC_RES_CMDID = 0xF04A, 303*4882a593Smuzhiyun /* deprecated */ 304*4882a593Smuzhiyun WMI_SET_ASSOC_REQ_RELAY_CMDID = 0xF04B, 305*4882a593Smuzhiyun WMI_MAC_ADDR_REQ_CMDID = 0xF04D, 306*4882a593Smuzhiyun WMI_FW_VER_CMDID = 0xF04E, 307*4882a593Smuzhiyun WMI_PMC_CMDID = 0xF04F, 308*4882a593Smuzhiyun }; 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun /* WMI_CONNECT_CMDID */ 311*4882a593Smuzhiyun enum wmi_network_type { 312*4882a593Smuzhiyun WMI_NETTYPE_INFRA = 0x01, 313*4882a593Smuzhiyun WMI_NETTYPE_ADHOC = 0x02, 314*4882a593Smuzhiyun WMI_NETTYPE_ADHOC_CREATOR = 0x04, 315*4882a593Smuzhiyun WMI_NETTYPE_AP = 0x10, 316*4882a593Smuzhiyun WMI_NETTYPE_P2P = 0x20, 317*4882a593Smuzhiyun /* PCIE over 60g */ 318*4882a593Smuzhiyun WMI_NETTYPE_WBE = 0x40, 319*4882a593Smuzhiyun }; 320*4882a593Smuzhiyun 321*4882a593Smuzhiyun enum wmi_dot11_auth_mode { 322*4882a593Smuzhiyun WMI_AUTH11_OPEN = 0x01, 323*4882a593Smuzhiyun WMI_AUTH11_SHARED = 0x02, 324*4882a593Smuzhiyun WMI_AUTH11_LEAP = 0x04, 325*4882a593Smuzhiyun WMI_AUTH11_WSC = 0x08, 326*4882a593Smuzhiyun }; 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun enum wmi_auth_mode { 329*4882a593Smuzhiyun WMI_AUTH_NONE = 0x01, 330*4882a593Smuzhiyun WMI_AUTH_WPA = 0x02, 331*4882a593Smuzhiyun WMI_AUTH_WPA2 = 0x04, 332*4882a593Smuzhiyun WMI_AUTH_WPA_PSK = 0x08, 333*4882a593Smuzhiyun WMI_AUTH_WPA2_PSK = 0x10, 334*4882a593Smuzhiyun WMI_AUTH_WPA_CCKM = 0x20, 335*4882a593Smuzhiyun WMI_AUTH_WPA2_CCKM = 0x40, 336*4882a593Smuzhiyun }; 337*4882a593Smuzhiyun 338*4882a593Smuzhiyun enum wmi_crypto_type { 339*4882a593Smuzhiyun WMI_CRYPT_NONE = 0x01, 340*4882a593Smuzhiyun WMI_CRYPT_AES_GCMP = 0x20, 341*4882a593Smuzhiyun }; 342*4882a593Smuzhiyun 343*4882a593Smuzhiyun enum wmi_connect_ctrl_flag_bits { 344*4882a593Smuzhiyun WMI_CONNECT_ASSOC_POLICY_USER = 0x01, 345*4882a593Smuzhiyun WMI_CONNECT_SEND_REASSOC = 0x02, 346*4882a593Smuzhiyun WMI_CONNECT_IGNORE_WPA_GROUP_CIPHER = 0x04, 347*4882a593Smuzhiyun WMI_CONNECT_PROFILE_MATCH_DONE = 0x08, 348*4882a593Smuzhiyun WMI_CONNECT_IGNORE_AAC_BEACON = 0x10, 349*4882a593Smuzhiyun WMI_CONNECT_CSA_FOLLOW_BSS = 0x20, 350*4882a593Smuzhiyun WMI_CONNECT_DO_WPA_OFFLOAD = 0x40, 351*4882a593Smuzhiyun WMI_CONNECT_DO_NOT_DEAUTH = 0x80, 352*4882a593Smuzhiyun }; 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun #define WMI_MAX_SSID_LEN (32) 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun enum wmi_channel { 357*4882a593Smuzhiyun WMI_CHANNEL_1 = 0x00, 358*4882a593Smuzhiyun WMI_CHANNEL_2 = 0x01, 359*4882a593Smuzhiyun WMI_CHANNEL_3 = 0x02, 360*4882a593Smuzhiyun WMI_CHANNEL_4 = 0x03, 361*4882a593Smuzhiyun WMI_CHANNEL_5 = 0x04, 362*4882a593Smuzhiyun WMI_CHANNEL_6 = 0x05, 363*4882a593Smuzhiyun WMI_CHANNEL_9 = 0x06, 364*4882a593Smuzhiyun WMI_CHANNEL_10 = 0x07, 365*4882a593Smuzhiyun WMI_CHANNEL_11 = 0x08, 366*4882a593Smuzhiyun WMI_CHANNEL_12 = 0x09, 367*4882a593Smuzhiyun }; 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun /* WMI_CONNECT_CMDID */ 370*4882a593Smuzhiyun struct wmi_connect_cmd { 371*4882a593Smuzhiyun u8 network_type; 372*4882a593Smuzhiyun u8 dot11_auth_mode; 373*4882a593Smuzhiyun u8 auth_mode; 374*4882a593Smuzhiyun u8 pairwise_crypto_type; 375*4882a593Smuzhiyun u8 pairwise_crypto_len; 376*4882a593Smuzhiyun u8 group_crypto_type; 377*4882a593Smuzhiyun u8 group_crypto_len; 378*4882a593Smuzhiyun u8 ssid_len; 379*4882a593Smuzhiyun u8 ssid[WMI_MAX_SSID_LEN]; 380*4882a593Smuzhiyun /* enum wmi_channel WMI_CHANNEL_1..WMI_CHANNEL_6; for EDMG this is 381*4882a593Smuzhiyun * the primary channel number 382*4882a593Smuzhiyun */ 383*4882a593Smuzhiyun u8 channel; 384*4882a593Smuzhiyun /* enum wmi_channel WMI_CHANNEL_9..WMI_CHANNEL_12 */ 385*4882a593Smuzhiyun u8 edmg_channel; 386*4882a593Smuzhiyun u8 bssid[WMI_MAC_LEN]; 387*4882a593Smuzhiyun __le32 ctrl_flags; 388*4882a593Smuzhiyun u8 dst_mac[WMI_MAC_LEN]; 389*4882a593Smuzhiyun u8 reserved1[2]; 390*4882a593Smuzhiyun } __packed; 391*4882a593Smuzhiyun 392*4882a593Smuzhiyun /* WMI_DISCONNECT_STA_CMDID */ 393*4882a593Smuzhiyun struct wmi_disconnect_sta_cmd { 394*4882a593Smuzhiyun u8 dst_mac[WMI_MAC_LEN]; 395*4882a593Smuzhiyun __le16 disconnect_reason; 396*4882a593Smuzhiyun } __packed; 397*4882a593Smuzhiyun 398*4882a593Smuzhiyun #define WMI_MAX_KEY_INDEX (3) 399*4882a593Smuzhiyun #define WMI_MAX_KEY_LEN (32) 400*4882a593Smuzhiyun #define WMI_PASSPHRASE_LEN (64) 401*4882a593Smuzhiyun 402*4882a593Smuzhiyun /* WMI_SET_PASSPHRASE_CMDID */ 403*4882a593Smuzhiyun struct wmi_set_passphrase_cmd { 404*4882a593Smuzhiyun u8 ssid[WMI_MAX_SSID_LEN]; 405*4882a593Smuzhiyun u8 passphrase[WMI_PASSPHRASE_LEN]; 406*4882a593Smuzhiyun u8 ssid_len; 407*4882a593Smuzhiyun u8 passphrase_len; 408*4882a593Smuzhiyun } __packed; 409*4882a593Smuzhiyun 410*4882a593Smuzhiyun /* WMI_ADD_CIPHER_KEY_CMDID */ 411*4882a593Smuzhiyun enum wmi_key_usage { 412*4882a593Smuzhiyun WMI_KEY_USE_PAIRWISE = 0x00, 413*4882a593Smuzhiyun WMI_KEY_USE_RX_GROUP = 0x01, 414*4882a593Smuzhiyun WMI_KEY_USE_TX_GROUP = 0x02, 415*4882a593Smuzhiyun WMI_KEY_USE_STORE_PTK = 0x03, 416*4882a593Smuzhiyun WMI_KEY_USE_APPLY_PTK = 0x04, 417*4882a593Smuzhiyun }; 418*4882a593Smuzhiyun 419*4882a593Smuzhiyun struct wmi_add_cipher_key_cmd { 420*4882a593Smuzhiyun u8 key_index; 421*4882a593Smuzhiyun u8 key_type; 422*4882a593Smuzhiyun /* enum wmi_key_usage */ 423*4882a593Smuzhiyun u8 key_usage; 424*4882a593Smuzhiyun u8 key_len; 425*4882a593Smuzhiyun /* key replay sequence counter */ 426*4882a593Smuzhiyun u8 key_rsc[8]; 427*4882a593Smuzhiyun u8 key[WMI_MAX_KEY_LEN]; 428*4882a593Smuzhiyun /* Additional Key Control information */ 429*4882a593Smuzhiyun u8 key_op_ctrl; 430*4882a593Smuzhiyun u8 mac[WMI_MAC_LEN]; 431*4882a593Smuzhiyun } __packed; 432*4882a593Smuzhiyun 433*4882a593Smuzhiyun /* WMI_DELETE_CIPHER_KEY_CMDID */ 434*4882a593Smuzhiyun struct wmi_delete_cipher_key_cmd { 435*4882a593Smuzhiyun u8 key_index; 436*4882a593Smuzhiyun u8 mac[WMI_MAC_LEN]; 437*4882a593Smuzhiyun } __packed; 438*4882a593Smuzhiyun 439*4882a593Smuzhiyun /* WMI_START_SCAN_CMDID 440*4882a593Smuzhiyun * 441*4882a593Smuzhiyun * Start L1 scan operation 442*4882a593Smuzhiyun * 443*4882a593Smuzhiyun * Returned events: 444*4882a593Smuzhiyun * - WMI_RX_MGMT_PACKET_EVENTID - for every probe resp. 445*4882a593Smuzhiyun * - WMI_SCAN_COMPLETE_EVENTID 446*4882a593Smuzhiyun */ 447*4882a593Smuzhiyun enum wmi_scan_type { 448*4882a593Smuzhiyun WMI_ACTIVE_SCAN = 0x00, 449*4882a593Smuzhiyun WMI_SHORT_SCAN = 0x01, 450*4882a593Smuzhiyun WMI_PASSIVE_SCAN = 0x02, 451*4882a593Smuzhiyun WMI_DIRECT_SCAN = 0x03, 452*4882a593Smuzhiyun WMI_LONG_SCAN = 0x04, 453*4882a593Smuzhiyun }; 454*4882a593Smuzhiyun 455*4882a593Smuzhiyun /* WMI_START_SCAN_CMDID */ 456*4882a593Smuzhiyun struct wmi_start_scan_cmd { 457*4882a593Smuzhiyun u8 direct_scan_mac_addr[WMI_MAC_LEN]; 458*4882a593Smuzhiyun /* run scan with discovery beacon. Relevant for ACTIVE scan only. */ 459*4882a593Smuzhiyun u8 discovery_mode; 460*4882a593Smuzhiyun u8 reserved; 461*4882a593Smuzhiyun /* Max duration in the home channel(ms) */ 462*4882a593Smuzhiyun __le32 dwell_time; 463*4882a593Smuzhiyun /* Time interval between scans (ms) */ 464*4882a593Smuzhiyun __le32 force_scan_interval; 465*4882a593Smuzhiyun /* enum wmi_scan_type */ 466*4882a593Smuzhiyun u8 scan_type; 467*4882a593Smuzhiyun /* how many channels follow */ 468*4882a593Smuzhiyun u8 num_channels; 469*4882a593Smuzhiyun /* channels ID's: 470*4882a593Smuzhiyun * 0 - 58320 MHz 471*4882a593Smuzhiyun * 1 - 60480 MHz 472*4882a593Smuzhiyun * 2 - 62640 MHz 473*4882a593Smuzhiyun */ 474*4882a593Smuzhiyun struct { 475*4882a593Smuzhiyun u8 channel; 476*4882a593Smuzhiyun u8 reserved; 477*4882a593Smuzhiyun } channel_list[]; 478*4882a593Smuzhiyun } __packed; 479*4882a593Smuzhiyun 480*4882a593Smuzhiyun #define WMI_MAX_PNO_SSID_NUM (16) 481*4882a593Smuzhiyun #define WMI_MAX_CHANNEL_NUM (6) 482*4882a593Smuzhiyun #define WMI_MAX_PLANS_NUM (2) 483*4882a593Smuzhiyun 484*4882a593Smuzhiyun /* WMI_START_SCHED_SCAN_CMDID */ 485*4882a593Smuzhiyun struct wmi_sched_scan_ssid_match { 486*4882a593Smuzhiyun u8 ssid_len; 487*4882a593Smuzhiyun u8 ssid[WMI_MAX_SSID_LEN]; 488*4882a593Smuzhiyun s8 rssi_threshold; 489*4882a593Smuzhiyun /* boolean */ 490*4882a593Smuzhiyun u8 add_ssid_to_probe; 491*4882a593Smuzhiyun u8 reserved; 492*4882a593Smuzhiyun } __packed; 493*4882a593Smuzhiyun 494*4882a593Smuzhiyun /* WMI_START_SCHED_SCAN_CMDID */ 495*4882a593Smuzhiyun struct wmi_sched_scan_plan { 496*4882a593Smuzhiyun __le16 interval_sec; 497*4882a593Smuzhiyun __le16 num_of_iterations; 498*4882a593Smuzhiyun } __packed; 499*4882a593Smuzhiyun 500*4882a593Smuzhiyun /* WMI_START_SCHED_SCAN_CMDID */ 501*4882a593Smuzhiyun struct wmi_start_sched_scan_cmd { 502*4882a593Smuzhiyun struct wmi_sched_scan_ssid_match ssid_for_match[WMI_MAX_PNO_SSID_NUM]; 503*4882a593Smuzhiyun u8 num_of_ssids; 504*4882a593Smuzhiyun s8 min_rssi_threshold; 505*4882a593Smuzhiyun u8 channel_list[WMI_MAX_CHANNEL_NUM]; 506*4882a593Smuzhiyun u8 num_of_channels; 507*4882a593Smuzhiyun u8 reserved; 508*4882a593Smuzhiyun __le16 initial_delay_sec; 509*4882a593Smuzhiyun struct wmi_sched_scan_plan scan_plans[WMI_MAX_PLANS_NUM]; 510*4882a593Smuzhiyun } __packed; 511*4882a593Smuzhiyun 512*4882a593Smuzhiyun /* WMI_FT_AUTH_CMDID */ 513*4882a593Smuzhiyun struct wmi_ft_auth_cmd { 514*4882a593Smuzhiyun u8 bssid[WMI_MAC_LEN]; 515*4882a593Smuzhiyun /* enum wmi_channel */ 516*4882a593Smuzhiyun u8 channel; 517*4882a593Smuzhiyun /* enum wmi_channel */ 518*4882a593Smuzhiyun u8 edmg_channel; 519*4882a593Smuzhiyun u8 reserved[4]; 520*4882a593Smuzhiyun } __packed; 521*4882a593Smuzhiyun 522*4882a593Smuzhiyun /* WMI_FT_REASSOC_CMDID */ 523*4882a593Smuzhiyun struct wmi_ft_reassoc_cmd { 524*4882a593Smuzhiyun u8 bssid[WMI_MAC_LEN]; 525*4882a593Smuzhiyun u8 reserved[2]; 526*4882a593Smuzhiyun } __packed; 527*4882a593Smuzhiyun 528*4882a593Smuzhiyun /* WMI_UPDATE_FT_IES_CMDID */ 529*4882a593Smuzhiyun struct wmi_update_ft_ies_cmd { 530*4882a593Smuzhiyun /* Length of the FT IEs */ 531*4882a593Smuzhiyun __le16 ie_len; 532*4882a593Smuzhiyun u8 reserved[2]; 533*4882a593Smuzhiyun u8 ie_info[]; 534*4882a593Smuzhiyun } __packed; 535*4882a593Smuzhiyun 536*4882a593Smuzhiyun /* WMI_SET_PROBED_SSID_CMDID */ 537*4882a593Smuzhiyun #define MAX_PROBED_SSID_INDEX (3) 538*4882a593Smuzhiyun 539*4882a593Smuzhiyun enum wmi_ssid_flag { 540*4882a593Smuzhiyun /* disables entry */ 541*4882a593Smuzhiyun WMI_SSID_FLAG_DISABLE = 0x00, 542*4882a593Smuzhiyun /* probes specified ssid */ 543*4882a593Smuzhiyun WMI_SSID_FLAG_SPECIFIC = 0x01, 544*4882a593Smuzhiyun /* probes for any ssid */ 545*4882a593Smuzhiyun WMI_SSID_FLAG_ANY = 0x02, 546*4882a593Smuzhiyun }; 547*4882a593Smuzhiyun 548*4882a593Smuzhiyun struct wmi_probed_ssid_cmd { 549*4882a593Smuzhiyun /* 0 to MAX_PROBED_SSID_INDEX */ 550*4882a593Smuzhiyun u8 entry_index; 551*4882a593Smuzhiyun /* enum wmi_ssid_flag */ 552*4882a593Smuzhiyun u8 flag; 553*4882a593Smuzhiyun u8 ssid_len; 554*4882a593Smuzhiyun u8 ssid[WMI_MAX_SSID_LEN]; 555*4882a593Smuzhiyun } __packed; 556*4882a593Smuzhiyun 557*4882a593Smuzhiyun /* WMI_SET_APPIE_CMDID 558*4882a593Smuzhiyun * Add Application specified IE to a management frame 559*4882a593Smuzhiyun */ 560*4882a593Smuzhiyun #define WMI_MAX_IE_LEN (1024) 561*4882a593Smuzhiyun 562*4882a593Smuzhiyun /* Frame Types */ 563*4882a593Smuzhiyun enum wmi_mgmt_frame_type { 564*4882a593Smuzhiyun WMI_FRAME_BEACON = 0x00, 565*4882a593Smuzhiyun WMI_FRAME_PROBE_REQ = 0x01, 566*4882a593Smuzhiyun WMI_FRAME_PROBE_RESP = 0x02, 567*4882a593Smuzhiyun WMI_FRAME_ASSOC_REQ = 0x03, 568*4882a593Smuzhiyun WMI_FRAME_ASSOC_RESP = 0x04, 569*4882a593Smuzhiyun WMI_NUM_MGMT_FRAME = 0x05, 570*4882a593Smuzhiyun }; 571*4882a593Smuzhiyun 572*4882a593Smuzhiyun struct wmi_set_appie_cmd { 573*4882a593Smuzhiyun /* enum wmi_mgmt_frame_type */ 574*4882a593Smuzhiyun u8 mgmt_frm_type; 575*4882a593Smuzhiyun u8 reserved; 576*4882a593Smuzhiyun /* Length of the IE to be added to MGMT frame */ 577*4882a593Smuzhiyun __le16 ie_len; 578*4882a593Smuzhiyun u8 ie_info[]; 579*4882a593Smuzhiyun } __packed; 580*4882a593Smuzhiyun 581*4882a593Smuzhiyun /* WMI_PXMT_RANGE_CFG_CMDID */ 582*4882a593Smuzhiyun struct wmi_pxmt_range_cfg_cmd { 583*4882a593Smuzhiyun u8 dst_mac[WMI_MAC_LEN]; 584*4882a593Smuzhiyun __le16 range; 585*4882a593Smuzhiyun } __packed; 586*4882a593Smuzhiyun 587*4882a593Smuzhiyun /* WMI_PXMT_SNR2_RANGE_CFG_CMDID */ 588*4882a593Smuzhiyun struct wmi_pxmt_snr2_range_cfg_cmd { 589*4882a593Smuzhiyun s8 snr2range_arr[2]; 590*4882a593Smuzhiyun } __packed; 591*4882a593Smuzhiyun 592*4882a593Smuzhiyun /* WMI_RADAR_GENERAL_CONFIG_CMDID */ 593*4882a593Smuzhiyun struct wmi_radar_general_config_cmd { 594*4882a593Smuzhiyun /* Number of pulses (CIRs) in FW FIFO to initiate pulses transfer 595*4882a593Smuzhiyun * from FW to Host 596*4882a593Smuzhiyun */ 597*4882a593Smuzhiyun __le32 fifo_watermark; 598*4882a593Smuzhiyun /* In unit of us, in the range [100, 1000000] */ 599*4882a593Smuzhiyun __le32 t_burst; 600*4882a593Smuzhiyun /* Valid in the range [1, 32768], 0xFFFF means infinite */ 601*4882a593Smuzhiyun __le32 n_bursts; 602*4882a593Smuzhiyun /* In unit of 330Mhz clk, in the range [4, 2000]*330 */ 603*4882a593Smuzhiyun __le32 t_pulse; 604*4882a593Smuzhiyun /* In the range of [1,4096] */ 605*4882a593Smuzhiyun __le16 n_pulses; 606*4882a593Smuzhiyun /* Number of taps after cTap per CIR */ 607*4882a593Smuzhiyun __le16 n_samples; 608*4882a593Smuzhiyun /* Offset from the main tap (0 = zero-distance). In the range of [0, 609*4882a593Smuzhiyun * 255] 610*4882a593Smuzhiyun */ 611*4882a593Smuzhiyun u8 first_sample_offset; 612*4882a593Smuzhiyun /* Number of Pulses to average, 1, 2, 4, 8 */ 613*4882a593Smuzhiyun u8 pulses_to_avg; 614*4882a593Smuzhiyun /* Number of adjacent taps to average, 1, 2, 4, 8 */ 615*4882a593Smuzhiyun u8 samples_to_avg; 616*4882a593Smuzhiyun /* The index to config general params */ 617*4882a593Smuzhiyun u8 general_index; 618*4882a593Smuzhiyun u8 reserved[4]; 619*4882a593Smuzhiyun } __packed; 620*4882a593Smuzhiyun 621*4882a593Smuzhiyun /* WMI_RADAR_CONFIG_SELECT_CMDID */ 622*4882a593Smuzhiyun struct wmi_radar_config_select_cmd { 623*4882a593Smuzhiyun /* Select the general params index to use */ 624*4882a593Smuzhiyun u8 general_index; 625*4882a593Smuzhiyun u8 reserved[3]; 626*4882a593Smuzhiyun /* 0 means don't update burst_active_vector */ 627*4882a593Smuzhiyun __le32 burst_active_vector; 628*4882a593Smuzhiyun /* 0 means don't update pulse_active_vector */ 629*4882a593Smuzhiyun __le32 pulse_active_vector; 630*4882a593Smuzhiyun } __packed; 631*4882a593Smuzhiyun 632*4882a593Smuzhiyun /* WMI_RADAR_PARAMS_CONFIG_CMDID */ 633*4882a593Smuzhiyun struct wmi_radar_params_config_cmd { 634*4882a593Smuzhiyun /* The burst index selected to config */ 635*4882a593Smuzhiyun u8 burst_index; 636*4882a593Smuzhiyun /* 0-not active, 1-active */ 637*4882a593Smuzhiyun u8 burst_en; 638*4882a593Smuzhiyun /* The pulse index selected to config */ 639*4882a593Smuzhiyun u8 pulse_index; 640*4882a593Smuzhiyun /* 0-not active, 1-active */ 641*4882a593Smuzhiyun u8 pulse_en; 642*4882a593Smuzhiyun /* TX RF to use on current pulse */ 643*4882a593Smuzhiyun u8 tx_rfc_idx; 644*4882a593Smuzhiyun u8 tx_sector; 645*4882a593Smuzhiyun /* Offset from calibrated value.(expected to be 0)(value is row in 646*4882a593Smuzhiyun * Gain-LUT, not dB) 647*4882a593Smuzhiyun */ 648*4882a593Smuzhiyun s8 tx_rf_gain_comp; 649*4882a593Smuzhiyun /* expected to be 0 */ 650*4882a593Smuzhiyun s8 tx_bb_gain_comp; 651*4882a593Smuzhiyun /* RX RF to use on current pulse */ 652*4882a593Smuzhiyun u8 rx_rfc_idx; 653*4882a593Smuzhiyun u8 rx_sector; 654*4882a593Smuzhiyun /* Offset from calibrated value.(expected to be 0)(value is row in 655*4882a593Smuzhiyun * Gain-LUT, not dB) 656*4882a593Smuzhiyun */ 657*4882a593Smuzhiyun s8 rx_rf_gain_comp; 658*4882a593Smuzhiyun /* Value in dB.(expected to be 0) */ 659*4882a593Smuzhiyun s8 rx_bb_gain_comp; 660*4882a593Smuzhiyun /* Offset from calibrated value.(expected to be 0) */ 661*4882a593Smuzhiyun s8 rx_timing_offset; 662*4882a593Smuzhiyun u8 reserved[3]; 663*4882a593Smuzhiyun } __packed; 664*4882a593Smuzhiyun 665*4882a593Smuzhiyun /* WMI_RADAR_SET_MODE_CMDID */ 666*4882a593Smuzhiyun struct wmi_radar_set_mode_cmd { 667*4882a593Smuzhiyun /* 0-disable/1-enable */ 668*4882a593Smuzhiyun u8 enable; 669*4882a593Smuzhiyun /* enum wmi_channel */ 670*4882a593Smuzhiyun u8 channel; 671*4882a593Smuzhiyun /* In the range of [0,7], 0xff means use default */ 672*4882a593Smuzhiyun u8 tx_rfc_idx; 673*4882a593Smuzhiyun /* In the range of [0,7], 0xff means use default */ 674*4882a593Smuzhiyun u8 rx_rfc_idx; 675*4882a593Smuzhiyun } __packed; 676*4882a593Smuzhiyun 677*4882a593Smuzhiyun /* WMI_RADAR_CONTROL_CMDID */ 678*4882a593Smuzhiyun struct wmi_radar_control_cmd { 679*4882a593Smuzhiyun /* 0-stop/1-start */ 680*4882a593Smuzhiyun u8 start; 681*4882a593Smuzhiyun u8 reserved[3]; 682*4882a593Smuzhiyun } __packed; 683*4882a593Smuzhiyun 684*4882a593Smuzhiyun /* WMI_RADAR_PCI_CONTROL_CMDID */ 685*4882a593Smuzhiyun struct wmi_radar_pci_control_cmd { 686*4882a593Smuzhiyun /* pcie host buffer start address */ 687*4882a593Smuzhiyun __le64 base_addr; 688*4882a593Smuzhiyun /* pcie host control block address */ 689*4882a593Smuzhiyun __le64 control_block_addr; 690*4882a593Smuzhiyun /* pcie host buffer size */ 691*4882a593Smuzhiyun __le32 buffer_size; 692*4882a593Smuzhiyun __le32 reserved; 693*4882a593Smuzhiyun } __packed; 694*4882a593Smuzhiyun 695*4882a593Smuzhiyun /* WMI_RF_MGMT_CMDID */ 696*4882a593Smuzhiyun enum wmi_rf_mgmt_type { 697*4882a593Smuzhiyun WMI_RF_MGMT_W_DISABLE = 0x00, 698*4882a593Smuzhiyun WMI_RF_MGMT_W_ENABLE = 0x01, 699*4882a593Smuzhiyun WMI_RF_MGMT_GET_STATUS = 0x02, 700*4882a593Smuzhiyun }; 701*4882a593Smuzhiyun 702*4882a593Smuzhiyun /* WMI_BF_CONTROL_CMDID */ 703*4882a593Smuzhiyun enum wmi_bf_triggers { 704*4882a593Smuzhiyun WMI_BF_TRIGGER_RS_MCS1_TH_FAILURE = 0x01, 705*4882a593Smuzhiyun WMI_BF_TRIGGER_RS_MCS1_NO_BACK_FAILURE = 0x02, 706*4882a593Smuzhiyun WMI_BF_TRIGGER_MAX_CTS_FAILURE_IN_TXOP = 0x04, 707*4882a593Smuzhiyun WMI_BF_TRIGGER_MAX_BACK_FAILURE = 0x08, 708*4882a593Smuzhiyun WMI_BF_TRIGGER_FW = 0x10, 709*4882a593Smuzhiyun WMI_BF_TRIGGER_MAX_CTS_FAILURE_IN_KEEP_ALIVE = 0x20, 710*4882a593Smuzhiyun WMI_BF_TRIGGER_AOA = 0x40, 711*4882a593Smuzhiyun WMI_BF_TRIGGER_MAX_CTS_FAILURE_IN_UPM = 0x80, 712*4882a593Smuzhiyun }; 713*4882a593Smuzhiyun 714*4882a593Smuzhiyun /* WMI_RF_MGMT_CMDID */ 715*4882a593Smuzhiyun struct wmi_rf_mgmt_cmd { 716*4882a593Smuzhiyun __le32 rf_mgmt_type; 717*4882a593Smuzhiyun } __packed; 718*4882a593Smuzhiyun 719*4882a593Smuzhiyun /* WMI_CORR_MEASURE_CMDID */ 720*4882a593Smuzhiyun struct wmi_corr_measure_cmd { 721*4882a593Smuzhiyun __le32 freq_mhz; 722*4882a593Smuzhiyun __le32 length_samples; 723*4882a593Smuzhiyun __le32 iterations; 724*4882a593Smuzhiyun } __packed; 725*4882a593Smuzhiyun 726*4882a593Smuzhiyun /* WMI_SET_SSID_CMDID */ 727*4882a593Smuzhiyun struct wmi_set_ssid_cmd { 728*4882a593Smuzhiyun __le32 ssid_len; 729*4882a593Smuzhiyun u8 ssid[WMI_MAX_SSID_LEN]; 730*4882a593Smuzhiyun } __packed; 731*4882a593Smuzhiyun 732*4882a593Smuzhiyun /* WMI_SET_PCP_CHANNEL_CMDID */ 733*4882a593Smuzhiyun struct wmi_set_pcp_channel_cmd { 734*4882a593Smuzhiyun u8 channel; 735*4882a593Smuzhiyun u8 reserved[3]; 736*4882a593Smuzhiyun } __packed; 737*4882a593Smuzhiyun 738*4882a593Smuzhiyun /* WMI_BCON_CTRL_CMDID */ 739*4882a593Smuzhiyun struct wmi_bcon_ctrl_cmd { 740*4882a593Smuzhiyun __le16 bcon_interval; 741*4882a593Smuzhiyun __le16 frag_num; 742*4882a593Smuzhiyun __le64 ss_mask; 743*4882a593Smuzhiyun u8 network_type; 744*4882a593Smuzhiyun u8 pcp_max_assoc_sta; 745*4882a593Smuzhiyun u8 disable_sec_offload; 746*4882a593Smuzhiyun u8 disable_sec; 747*4882a593Smuzhiyun u8 hidden_ssid; 748*4882a593Smuzhiyun u8 is_go; 749*4882a593Smuzhiyun /* A-BFT length override if non-0 */ 750*4882a593Smuzhiyun u8 abft_len; 751*4882a593Smuzhiyun u8 reserved; 752*4882a593Smuzhiyun } __packed; 753*4882a593Smuzhiyun 754*4882a593Smuzhiyun /* WMI_PORT_ALLOCATE_CMDID */ 755*4882a593Smuzhiyun enum wmi_port_role { 756*4882a593Smuzhiyun WMI_PORT_STA = 0x00, 757*4882a593Smuzhiyun WMI_PORT_PCP = 0x01, 758*4882a593Smuzhiyun WMI_PORT_AP = 0x02, 759*4882a593Smuzhiyun WMI_PORT_P2P_DEV = 0x03, 760*4882a593Smuzhiyun WMI_PORT_P2P_CLIENT = 0x04, 761*4882a593Smuzhiyun WMI_PORT_P2P_GO = 0x05, 762*4882a593Smuzhiyun }; 763*4882a593Smuzhiyun 764*4882a593Smuzhiyun /* WMI_PORT_ALLOCATE_CMDID */ 765*4882a593Smuzhiyun struct wmi_port_allocate_cmd { 766*4882a593Smuzhiyun u8 mac[WMI_MAC_LEN]; 767*4882a593Smuzhiyun u8 port_role; 768*4882a593Smuzhiyun u8 mid; 769*4882a593Smuzhiyun } __packed; 770*4882a593Smuzhiyun 771*4882a593Smuzhiyun /* WMI_PORT_DELETE_CMDID */ 772*4882a593Smuzhiyun struct wmi_port_delete_cmd { 773*4882a593Smuzhiyun u8 mid; 774*4882a593Smuzhiyun u8 reserved[3]; 775*4882a593Smuzhiyun } __packed; 776*4882a593Smuzhiyun 777*4882a593Smuzhiyun /* WMI_TRAFFIC_SUSPEND_CMD wakeup trigger bit mask values */ 778*4882a593Smuzhiyun enum wmi_wakeup_trigger { 779*4882a593Smuzhiyun WMI_WAKEUP_TRIGGER_UCAST = 0x01, 780*4882a593Smuzhiyun WMI_WAKEUP_TRIGGER_BCAST = 0x02, 781*4882a593Smuzhiyun }; 782*4882a593Smuzhiyun 783*4882a593Smuzhiyun /* WMI_TRAFFIC_SUSPEND_CMDID */ 784*4882a593Smuzhiyun struct wmi_traffic_suspend_cmd { 785*4882a593Smuzhiyun /* Bit vector: bit[0] - wake on Unicast, bit[1] - wake on Broadcast */ 786*4882a593Smuzhiyun u8 wakeup_trigger; 787*4882a593Smuzhiyun } __packed; 788*4882a593Smuzhiyun 789*4882a593Smuzhiyun /* WMI_P2P_CFG_CMDID */ 790*4882a593Smuzhiyun enum wmi_discovery_mode { 791*4882a593Smuzhiyun WMI_DISCOVERY_MODE_NON_OFFLOAD = 0x00, 792*4882a593Smuzhiyun WMI_DISCOVERY_MODE_OFFLOAD = 0x01, 793*4882a593Smuzhiyun WMI_DISCOVERY_MODE_PEER2PEER = 0x02, 794*4882a593Smuzhiyun }; 795*4882a593Smuzhiyun 796*4882a593Smuzhiyun struct wmi_p2p_cfg_cmd { 797*4882a593Smuzhiyun /* enum wmi_discovery_mode */ 798*4882a593Smuzhiyun u8 discovery_mode; 799*4882a593Smuzhiyun u8 channel; 800*4882a593Smuzhiyun /* base to listen/search duration calculation */ 801*4882a593Smuzhiyun __le16 bcon_interval; 802*4882a593Smuzhiyun } __packed; 803*4882a593Smuzhiyun 804*4882a593Smuzhiyun /* WMI_POWER_MGMT_CFG_CMDID */ 805*4882a593Smuzhiyun enum wmi_power_source_type { 806*4882a593Smuzhiyun WMI_POWER_SOURCE_BATTERY = 0x00, 807*4882a593Smuzhiyun WMI_POWER_SOURCE_OTHER = 0x01, 808*4882a593Smuzhiyun }; 809*4882a593Smuzhiyun 810*4882a593Smuzhiyun struct wmi_power_mgmt_cfg_cmd { 811*4882a593Smuzhiyun /* enum wmi_power_source_type */ 812*4882a593Smuzhiyun u8 power_source; 813*4882a593Smuzhiyun u8 reserved[3]; 814*4882a593Smuzhiyun } __packed; 815*4882a593Smuzhiyun 816*4882a593Smuzhiyun /* WMI_PCP_START_CMDID */ 817*4882a593Smuzhiyun enum wmi_ap_sme_offload_mode { 818*4882a593Smuzhiyun /* Full AP SME in FW */ 819*4882a593Smuzhiyun WMI_AP_SME_OFFLOAD_FULL = 0x00, 820*4882a593Smuzhiyun /* Probe AP SME in FW */ 821*4882a593Smuzhiyun WMI_AP_SME_OFFLOAD_PARTIAL = 0x01, 822*4882a593Smuzhiyun /* AP SME in host */ 823*4882a593Smuzhiyun WMI_AP_SME_OFFLOAD_NONE = 0x02, 824*4882a593Smuzhiyun }; 825*4882a593Smuzhiyun 826*4882a593Smuzhiyun /* WMI_PCP_START_CMDID */ 827*4882a593Smuzhiyun struct wmi_pcp_start_cmd { 828*4882a593Smuzhiyun __le16 bcon_interval; 829*4882a593Smuzhiyun u8 pcp_max_assoc_sta; 830*4882a593Smuzhiyun u8 hidden_ssid; 831*4882a593Smuzhiyun u8 is_go; 832*4882a593Smuzhiyun /* enum wmi_channel WMI_CHANNEL_9..WMI_CHANNEL_12 */ 833*4882a593Smuzhiyun u8 edmg_channel; 834*4882a593Smuzhiyun u8 raw_mode; 835*4882a593Smuzhiyun u8 reserved[3]; 836*4882a593Smuzhiyun /* A-BFT length override if non-0 */ 837*4882a593Smuzhiyun u8 abft_len; 838*4882a593Smuzhiyun /* enum wmi_ap_sme_offload_mode_e */ 839*4882a593Smuzhiyun u8 ap_sme_offload_mode; 840*4882a593Smuzhiyun u8 network_type; 841*4882a593Smuzhiyun /* enum wmi_channel WMI_CHANNEL_1..WMI_CHANNEL_6; for EDMG this is 842*4882a593Smuzhiyun * the primary channel number 843*4882a593Smuzhiyun */ 844*4882a593Smuzhiyun u8 channel; 845*4882a593Smuzhiyun u8 disable_sec_offload; 846*4882a593Smuzhiyun u8 disable_sec; 847*4882a593Smuzhiyun } __packed; 848*4882a593Smuzhiyun 849*4882a593Smuzhiyun /* WMI_SW_TX_REQ_CMDID */ 850*4882a593Smuzhiyun struct wmi_sw_tx_req_cmd { 851*4882a593Smuzhiyun u8 dst_mac[WMI_MAC_LEN]; 852*4882a593Smuzhiyun __le16 len; 853*4882a593Smuzhiyun u8 payload[]; 854*4882a593Smuzhiyun } __packed; 855*4882a593Smuzhiyun 856*4882a593Smuzhiyun /* WMI_SW_TX_REQ_EXT_CMDID */ 857*4882a593Smuzhiyun struct wmi_sw_tx_req_ext_cmd { 858*4882a593Smuzhiyun u8 dst_mac[WMI_MAC_LEN]; 859*4882a593Smuzhiyun __le16 len; 860*4882a593Smuzhiyun __le16 duration_ms; 861*4882a593Smuzhiyun /* Channel to use, 0xFF for currently active channel */ 862*4882a593Smuzhiyun u8 channel; 863*4882a593Smuzhiyun u8 reserved[5]; 864*4882a593Smuzhiyun u8 payload[]; 865*4882a593Smuzhiyun } __packed; 866*4882a593Smuzhiyun 867*4882a593Smuzhiyun /* WMI_VRING_SWITCH_TIMING_CONFIG_CMDID */ 868*4882a593Smuzhiyun struct wmi_vring_switch_timing_config_cmd { 869*4882a593Smuzhiyun /* Set vring timing configuration: 870*4882a593Smuzhiyun * 871*4882a593Smuzhiyun * defined interval for vring switch 872*4882a593Smuzhiyun */ 873*4882a593Smuzhiyun __le32 interval_usec; 874*4882a593Smuzhiyun /* vring inactivity threshold */ 875*4882a593Smuzhiyun __le32 idle_th_usec; 876*4882a593Smuzhiyun } __packed; 877*4882a593Smuzhiyun 878*4882a593Smuzhiyun struct wmi_sw_ring_cfg { 879*4882a593Smuzhiyun __le64 ring_mem_base; 880*4882a593Smuzhiyun __le16 ring_size; 881*4882a593Smuzhiyun __le16 max_mpdu_size; 882*4882a593Smuzhiyun } __packed; 883*4882a593Smuzhiyun 884*4882a593Smuzhiyun /* wmi_vring_cfg_schd */ 885*4882a593Smuzhiyun struct wmi_vring_cfg_schd { 886*4882a593Smuzhiyun __le16 priority; 887*4882a593Smuzhiyun __le16 timeslot_us; 888*4882a593Smuzhiyun } __packed; 889*4882a593Smuzhiyun 890*4882a593Smuzhiyun enum wmi_vring_cfg_encap_trans_type { 891*4882a593Smuzhiyun WMI_VRING_ENC_TYPE_802_3 = 0x00, 892*4882a593Smuzhiyun WMI_VRING_ENC_TYPE_NATIVE_WIFI = 0x01, 893*4882a593Smuzhiyun WMI_VRING_ENC_TYPE_NONE = 0x02, 894*4882a593Smuzhiyun }; 895*4882a593Smuzhiyun 896*4882a593Smuzhiyun enum wmi_vring_cfg_ds_cfg { 897*4882a593Smuzhiyun WMI_VRING_DS_PBSS = 0x00, 898*4882a593Smuzhiyun WMI_VRING_DS_STATION = 0x01, 899*4882a593Smuzhiyun WMI_VRING_DS_AP = 0x02, 900*4882a593Smuzhiyun WMI_VRING_DS_ADDR4 = 0x03, 901*4882a593Smuzhiyun }; 902*4882a593Smuzhiyun 903*4882a593Smuzhiyun enum wmi_vring_cfg_nwifi_ds_trans_type { 904*4882a593Smuzhiyun WMI_NWIFI_TX_TRANS_MODE_NO = 0x00, 905*4882a593Smuzhiyun WMI_NWIFI_TX_TRANS_MODE_AP2PBSS = 0x01, 906*4882a593Smuzhiyun WMI_NWIFI_TX_TRANS_MODE_STA2PBSS = 0x02, 907*4882a593Smuzhiyun }; 908*4882a593Smuzhiyun 909*4882a593Smuzhiyun enum wmi_vring_cfg_schd_params_priority { 910*4882a593Smuzhiyun WMI_SCH_PRIO_REGULAR = 0x00, 911*4882a593Smuzhiyun WMI_SCH_PRIO_HIGH = 0x01, 912*4882a593Smuzhiyun }; 913*4882a593Smuzhiyun 914*4882a593Smuzhiyun #define CIDXTID_EXTENDED_CID_TID (0xFF) 915*4882a593Smuzhiyun #define CIDXTID_CID_POS (0) 916*4882a593Smuzhiyun #define CIDXTID_CID_LEN (4) 917*4882a593Smuzhiyun #define CIDXTID_CID_MSK (0xF) 918*4882a593Smuzhiyun #define CIDXTID_TID_POS (4) 919*4882a593Smuzhiyun #define CIDXTID_TID_LEN (4) 920*4882a593Smuzhiyun #define CIDXTID_TID_MSK (0xF0) 921*4882a593Smuzhiyun #define VRING_CFG_MAC_CTRL_LIFETIME_EN_POS (0) 922*4882a593Smuzhiyun #define VRING_CFG_MAC_CTRL_LIFETIME_EN_LEN (1) 923*4882a593Smuzhiyun #define VRING_CFG_MAC_CTRL_LIFETIME_EN_MSK (0x1) 924*4882a593Smuzhiyun #define VRING_CFG_MAC_CTRL_AGGR_EN_POS (1) 925*4882a593Smuzhiyun #define VRING_CFG_MAC_CTRL_AGGR_EN_LEN (1) 926*4882a593Smuzhiyun #define VRING_CFG_MAC_CTRL_AGGR_EN_MSK (0x2) 927*4882a593Smuzhiyun #define VRING_CFG_TO_RESOLUTION_VALUE_POS (0) 928*4882a593Smuzhiyun #define VRING_CFG_TO_RESOLUTION_VALUE_LEN (6) 929*4882a593Smuzhiyun #define VRING_CFG_TO_RESOLUTION_VALUE_MSK (0x3F) 930*4882a593Smuzhiyun 931*4882a593Smuzhiyun struct wmi_vring_cfg { 932*4882a593Smuzhiyun struct wmi_sw_ring_cfg tx_sw_ring; 933*4882a593Smuzhiyun /* 0-23 vrings */ 934*4882a593Smuzhiyun u8 ringid; 935*4882a593Smuzhiyun /* Used for cid less than 8. For higher cid set 936*4882a593Smuzhiyun * CIDXTID_EXTENDED_CID_TID here and use cid and tid members instead 937*4882a593Smuzhiyun */ 938*4882a593Smuzhiyun u8 cidxtid; 939*4882a593Smuzhiyun u8 encap_trans_type; 940*4882a593Smuzhiyun /* 802.3 DS cfg */ 941*4882a593Smuzhiyun u8 ds_cfg; 942*4882a593Smuzhiyun u8 nwifi_ds_trans_type; 943*4882a593Smuzhiyun u8 mac_ctrl; 944*4882a593Smuzhiyun u8 to_resolution; 945*4882a593Smuzhiyun u8 agg_max_wsize; 946*4882a593Smuzhiyun struct wmi_vring_cfg_schd schd_params; 947*4882a593Smuzhiyun /* Used when cidxtid = CIDXTID_EXTENDED_CID_TID */ 948*4882a593Smuzhiyun u8 cid; 949*4882a593Smuzhiyun /* Used when cidxtid = CIDXTID_EXTENDED_CID_TID */ 950*4882a593Smuzhiyun u8 tid; 951*4882a593Smuzhiyun /* Update the vring's priority for Qos purpose. Set to 952*4882a593Smuzhiyun * WMI_QOS_DEFAULT_PRIORITY to use MID's QoS priority 953*4882a593Smuzhiyun */ 954*4882a593Smuzhiyun u8 qos_priority; 955*4882a593Smuzhiyun u8 reserved; 956*4882a593Smuzhiyun } __packed; 957*4882a593Smuzhiyun 958*4882a593Smuzhiyun enum wmi_vring_cfg_cmd_action { 959*4882a593Smuzhiyun WMI_VRING_CMD_ADD = 0x00, 960*4882a593Smuzhiyun WMI_VRING_CMD_MODIFY = 0x01, 961*4882a593Smuzhiyun WMI_VRING_CMD_DELETE = 0x02, 962*4882a593Smuzhiyun }; 963*4882a593Smuzhiyun 964*4882a593Smuzhiyun /* WMI_VRING_CFG_CMDID */ 965*4882a593Smuzhiyun struct wmi_vring_cfg_cmd { 966*4882a593Smuzhiyun __le32 action; 967*4882a593Smuzhiyun struct wmi_vring_cfg vring_cfg; 968*4882a593Smuzhiyun } __packed; 969*4882a593Smuzhiyun 970*4882a593Smuzhiyun struct wmi_bcast_vring_cfg { 971*4882a593Smuzhiyun struct wmi_sw_ring_cfg tx_sw_ring; 972*4882a593Smuzhiyun /* 0-23 vrings */ 973*4882a593Smuzhiyun u8 ringid; 974*4882a593Smuzhiyun u8 encap_trans_type; 975*4882a593Smuzhiyun /* 802.3 DS cfg */ 976*4882a593Smuzhiyun u8 ds_cfg; 977*4882a593Smuzhiyun u8 nwifi_ds_trans_type; 978*4882a593Smuzhiyun } __packed; 979*4882a593Smuzhiyun 980*4882a593Smuzhiyun /* WMI_BCAST_VRING_CFG_CMDID */ 981*4882a593Smuzhiyun struct wmi_bcast_vring_cfg_cmd { 982*4882a593Smuzhiyun __le32 action; 983*4882a593Smuzhiyun struct wmi_bcast_vring_cfg vring_cfg; 984*4882a593Smuzhiyun } __packed; 985*4882a593Smuzhiyun 986*4882a593Smuzhiyun struct wmi_edma_ring_cfg { 987*4882a593Smuzhiyun __le64 ring_mem_base; 988*4882a593Smuzhiyun /* size in number of items */ 989*4882a593Smuzhiyun __le16 ring_size; 990*4882a593Smuzhiyun u8 ring_id; 991*4882a593Smuzhiyun u8 reserved; 992*4882a593Smuzhiyun } __packed; 993*4882a593Smuzhiyun 994*4882a593Smuzhiyun enum wmi_rx_msg_type { 995*4882a593Smuzhiyun WMI_RX_MSG_TYPE_COMPRESSED = 0x00, 996*4882a593Smuzhiyun WMI_RX_MSG_TYPE_EXTENDED = 0x01, 997*4882a593Smuzhiyun }; 998*4882a593Smuzhiyun 999*4882a593Smuzhiyun enum wmi_ring_add_irq_mode { 1000*4882a593Smuzhiyun /* Backwards compatibility 1001*4882a593Smuzhiyun * for DESC ring - interrupt disabled 1002*4882a593Smuzhiyun * for STATUS ring - interrupt enabled 1003*4882a593Smuzhiyun */ 1004*4882a593Smuzhiyun WMI_RING_ADD_IRQ_MODE_BWC = 0x00, 1005*4882a593Smuzhiyun WMI_RING_ADD_IRQ_MODE_DISABLE = 0x01, 1006*4882a593Smuzhiyun WMI_RING_ADD_IRQ_MODE_ENABLE = 0x02, 1007*4882a593Smuzhiyun }; 1008*4882a593Smuzhiyun 1009*4882a593Smuzhiyun struct wmi_tx_status_ring_add_cmd { 1010*4882a593Smuzhiyun struct wmi_edma_ring_cfg ring_cfg; 1011*4882a593Smuzhiyun u8 irq_index; 1012*4882a593Smuzhiyun /* wmi_ring_add_irq_mode */ 1013*4882a593Smuzhiyun u8 irq_mode; 1014*4882a593Smuzhiyun u8 reserved[2]; 1015*4882a593Smuzhiyun } __packed; 1016*4882a593Smuzhiyun 1017*4882a593Smuzhiyun struct wmi_rx_status_ring_add_cmd { 1018*4882a593Smuzhiyun struct wmi_edma_ring_cfg ring_cfg; 1019*4882a593Smuzhiyun u8 irq_index; 1020*4882a593Smuzhiyun /* wmi_rx_msg_type */ 1021*4882a593Smuzhiyun u8 rx_msg_type; 1022*4882a593Smuzhiyun u8 reserved[2]; 1023*4882a593Smuzhiyun } __packed; 1024*4882a593Smuzhiyun 1025*4882a593Smuzhiyun struct wmi_cfg_def_rx_offload_cmd { 1026*4882a593Smuzhiyun __le16 max_msdu_size; 1027*4882a593Smuzhiyun __le16 max_rx_pl_per_desc; 1028*4882a593Smuzhiyun u8 decap_trans_type; 1029*4882a593Smuzhiyun u8 l2_802_3_offload_ctrl; 1030*4882a593Smuzhiyun u8 l2_nwifi_offload_ctrl; 1031*4882a593Smuzhiyun u8 vlan_id; 1032*4882a593Smuzhiyun u8 nwifi_ds_trans_type; 1033*4882a593Smuzhiyun u8 l3_l4_ctrl; 1034*4882a593Smuzhiyun u8 reserved[6]; 1035*4882a593Smuzhiyun } __packed; 1036*4882a593Smuzhiyun 1037*4882a593Smuzhiyun struct wmi_tx_desc_ring_add_cmd { 1038*4882a593Smuzhiyun struct wmi_edma_ring_cfg ring_cfg; 1039*4882a593Smuzhiyun __le16 max_msdu_size; 1040*4882a593Smuzhiyun /* Correlated status ring (0-63) */ 1041*4882a593Smuzhiyun u8 status_ring_id; 1042*4882a593Smuzhiyun u8 cid; 1043*4882a593Smuzhiyun u8 tid; 1044*4882a593Smuzhiyun u8 encap_trans_type; 1045*4882a593Smuzhiyun u8 mac_ctrl; 1046*4882a593Smuzhiyun u8 to_resolution; 1047*4882a593Smuzhiyun u8 agg_max_wsize; 1048*4882a593Smuzhiyun u8 irq_index; 1049*4882a593Smuzhiyun /* wmi_ring_add_irq_mode */ 1050*4882a593Smuzhiyun u8 irq_mode; 1051*4882a593Smuzhiyun u8 reserved; 1052*4882a593Smuzhiyun struct wmi_vring_cfg_schd schd_params; 1053*4882a593Smuzhiyun } __packed; 1054*4882a593Smuzhiyun 1055*4882a593Smuzhiyun struct wmi_rx_desc_ring_add_cmd { 1056*4882a593Smuzhiyun struct wmi_edma_ring_cfg ring_cfg; 1057*4882a593Smuzhiyun u8 irq_index; 1058*4882a593Smuzhiyun /* 0-63 status rings */ 1059*4882a593Smuzhiyun u8 status_ring_id; 1060*4882a593Smuzhiyun u8 reserved[2]; 1061*4882a593Smuzhiyun __le64 sw_tail_host_addr; 1062*4882a593Smuzhiyun } __packed; 1063*4882a593Smuzhiyun 1064*4882a593Smuzhiyun struct wmi_bcast_desc_ring_add_cmd { 1065*4882a593Smuzhiyun struct wmi_edma_ring_cfg ring_cfg; 1066*4882a593Smuzhiyun __le16 max_msdu_size; 1067*4882a593Smuzhiyun /* Correlated status ring (0-63) */ 1068*4882a593Smuzhiyun u8 status_ring_id; 1069*4882a593Smuzhiyun u8 encap_trans_type; 1070*4882a593Smuzhiyun u8 reserved[4]; 1071*4882a593Smuzhiyun } __packed; 1072*4882a593Smuzhiyun 1073*4882a593Smuzhiyun /* WMI_LO_POWER_CALIB_FROM_OTP_CMDID */ 1074*4882a593Smuzhiyun struct wmi_lo_power_calib_from_otp_cmd { 1075*4882a593Smuzhiyun /* index to read from OTP. zero based */ 1076*4882a593Smuzhiyun u8 index; 1077*4882a593Smuzhiyun u8 reserved[3]; 1078*4882a593Smuzhiyun } __packed; 1079*4882a593Smuzhiyun 1080*4882a593Smuzhiyun /* WMI_LO_POWER_CALIB_FROM_OTP_EVENTID */ 1081*4882a593Smuzhiyun struct wmi_lo_power_calib_from_otp_event { 1082*4882a593Smuzhiyun /* wmi_fw_status */ 1083*4882a593Smuzhiyun u8 status; 1084*4882a593Smuzhiyun u8 reserved[3]; 1085*4882a593Smuzhiyun } __packed; 1086*4882a593Smuzhiyun 1087*4882a593Smuzhiyun /* WMI_RING_BA_EN_CMDID */ 1088*4882a593Smuzhiyun struct wmi_ring_ba_en_cmd { 1089*4882a593Smuzhiyun u8 ring_id; 1090*4882a593Smuzhiyun u8 agg_max_wsize; 1091*4882a593Smuzhiyun __le16 ba_timeout; 1092*4882a593Smuzhiyun u8 amsdu; 1093*4882a593Smuzhiyun u8 reserved[3]; 1094*4882a593Smuzhiyun } __packed; 1095*4882a593Smuzhiyun 1096*4882a593Smuzhiyun /* WMI_RING_BA_DIS_CMDID */ 1097*4882a593Smuzhiyun struct wmi_ring_ba_dis_cmd { 1098*4882a593Smuzhiyun u8 ring_id; 1099*4882a593Smuzhiyun u8 reserved; 1100*4882a593Smuzhiyun __le16 reason; 1101*4882a593Smuzhiyun } __packed; 1102*4882a593Smuzhiyun 1103*4882a593Smuzhiyun /* WMI_NOTIFY_REQ_CMDID */ 1104*4882a593Smuzhiyun struct wmi_notify_req_cmd { 1105*4882a593Smuzhiyun u8 cid; 1106*4882a593Smuzhiyun u8 year; 1107*4882a593Smuzhiyun u8 month; 1108*4882a593Smuzhiyun u8 day; 1109*4882a593Smuzhiyun __le32 interval_usec; 1110*4882a593Smuzhiyun u8 hour; 1111*4882a593Smuzhiyun u8 minute; 1112*4882a593Smuzhiyun u8 second; 1113*4882a593Smuzhiyun u8 miliseconds; 1114*4882a593Smuzhiyun } __packed; 1115*4882a593Smuzhiyun 1116*4882a593Smuzhiyun /* WMI_CFG_RX_CHAIN_CMDID */ 1117*4882a593Smuzhiyun enum wmi_sniffer_cfg_mode { 1118*4882a593Smuzhiyun WMI_SNIFFER_OFF = 0x00, 1119*4882a593Smuzhiyun WMI_SNIFFER_ON = 0x01, 1120*4882a593Smuzhiyun }; 1121*4882a593Smuzhiyun 1122*4882a593Smuzhiyun /* WMI_SILENT_RSSI_TABLE */ 1123*4882a593Smuzhiyun enum wmi_silent_rssi_table { 1124*4882a593Smuzhiyun RF_TEMPERATURE_CALIB_DEFAULT_DB = 0x00, 1125*4882a593Smuzhiyun RF_TEMPERATURE_CALIB_HIGH_POWER_DB = 0x01, 1126*4882a593Smuzhiyun }; 1127*4882a593Smuzhiyun 1128*4882a593Smuzhiyun /* WMI_SILENT_RSSI_STATUS */ 1129*4882a593Smuzhiyun enum wmi_silent_rssi_status { 1130*4882a593Smuzhiyun SILENT_RSSI_SUCCESS = 0x00, 1131*4882a593Smuzhiyun SILENT_RSSI_FAILURE = 0x01, 1132*4882a593Smuzhiyun }; 1133*4882a593Smuzhiyun 1134*4882a593Smuzhiyun /* WMI_SET_ACTIVE_SILENT_RSSI_TABLE_CMDID */ 1135*4882a593Smuzhiyun struct wmi_set_active_silent_rssi_table_cmd { 1136*4882a593Smuzhiyun /* enum wmi_silent_rssi_table */ 1137*4882a593Smuzhiyun __le32 table; 1138*4882a593Smuzhiyun } __packed; 1139*4882a593Smuzhiyun 1140*4882a593Smuzhiyun enum wmi_sniffer_cfg_phy_info_mode { 1141*4882a593Smuzhiyun WMI_SNIFFER_PHY_INFO_DISABLED = 0x00, 1142*4882a593Smuzhiyun WMI_SNIFFER_PHY_INFO_ENABLED = 0x01, 1143*4882a593Smuzhiyun }; 1144*4882a593Smuzhiyun 1145*4882a593Smuzhiyun enum wmi_sniffer_cfg_phy_support { 1146*4882a593Smuzhiyun WMI_SNIFFER_CP = 0x00, 1147*4882a593Smuzhiyun WMI_SNIFFER_DP = 0x01, 1148*4882a593Smuzhiyun WMI_SNIFFER_BOTH_PHYS = 0x02, 1149*4882a593Smuzhiyun }; 1150*4882a593Smuzhiyun 1151*4882a593Smuzhiyun /* wmi_sniffer_cfg */ 1152*4882a593Smuzhiyun struct wmi_sniffer_cfg { 1153*4882a593Smuzhiyun /* enum wmi_sniffer_cfg_mode */ 1154*4882a593Smuzhiyun __le32 mode; 1155*4882a593Smuzhiyun /* enum wmi_sniffer_cfg_phy_info_mode */ 1156*4882a593Smuzhiyun __le32 phy_info_mode; 1157*4882a593Smuzhiyun /* enum wmi_sniffer_cfg_phy_support */ 1158*4882a593Smuzhiyun __le32 phy_support; 1159*4882a593Smuzhiyun u8 channel; 1160*4882a593Smuzhiyun u8 reserved[3]; 1161*4882a593Smuzhiyun } __packed; 1162*4882a593Smuzhiyun 1163*4882a593Smuzhiyun enum wmi_cfg_rx_chain_cmd_action { 1164*4882a593Smuzhiyun WMI_RX_CHAIN_ADD = 0x00, 1165*4882a593Smuzhiyun WMI_RX_CHAIN_DEL = 0x01, 1166*4882a593Smuzhiyun }; 1167*4882a593Smuzhiyun 1168*4882a593Smuzhiyun enum wmi_cfg_rx_chain_cmd_decap_trans_type { 1169*4882a593Smuzhiyun WMI_DECAP_TYPE_802_3 = 0x00, 1170*4882a593Smuzhiyun WMI_DECAP_TYPE_NATIVE_WIFI = 0x01, 1171*4882a593Smuzhiyun WMI_DECAP_TYPE_NONE = 0x02, 1172*4882a593Smuzhiyun }; 1173*4882a593Smuzhiyun 1174*4882a593Smuzhiyun enum wmi_cfg_rx_chain_cmd_nwifi_ds_trans_type { 1175*4882a593Smuzhiyun WMI_NWIFI_RX_TRANS_MODE_NO = 0x00, 1176*4882a593Smuzhiyun WMI_NWIFI_RX_TRANS_MODE_PBSS2AP = 0x01, 1177*4882a593Smuzhiyun WMI_NWIFI_RX_TRANS_MODE_PBSS2STA = 0x02, 1178*4882a593Smuzhiyun }; 1179*4882a593Smuzhiyun 1180*4882a593Smuzhiyun enum wmi_cfg_rx_chain_cmd_reorder_type { 1181*4882a593Smuzhiyun WMI_RX_HW_REORDER = 0x00, 1182*4882a593Smuzhiyun WMI_RX_SW_REORDER = 0x01, 1183*4882a593Smuzhiyun }; 1184*4882a593Smuzhiyun 1185*4882a593Smuzhiyun #define L2_802_3_OFFLOAD_CTRL_VLAN_TAG_INSERTION_POS (0) 1186*4882a593Smuzhiyun #define L2_802_3_OFFLOAD_CTRL_VLAN_TAG_INSERTION_LEN (1) 1187*4882a593Smuzhiyun #define L2_802_3_OFFLOAD_CTRL_VLAN_TAG_INSERTION_MSK (0x1) 1188*4882a593Smuzhiyun #define L2_802_3_OFFLOAD_CTRL_SNAP_KEEP_POS (1) 1189*4882a593Smuzhiyun #define L2_802_3_OFFLOAD_CTRL_SNAP_KEEP_LEN (1) 1190*4882a593Smuzhiyun #define L2_802_3_OFFLOAD_CTRL_SNAP_KEEP_MSK (0x2) 1191*4882a593Smuzhiyun #define L2_NWIFI_OFFLOAD_CTRL_REMOVE_QOS_POS (0) 1192*4882a593Smuzhiyun #define L2_NWIFI_OFFLOAD_CTRL_REMOVE_QOS_LEN (1) 1193*4882a593Smuzhiyun #define L2_NWIFI_OFFLOAD_CTRL_REMOVE_QOS_MSK (0x1) 1194*4882a593Smuzhiyun #define L2_NWIFI_OFFLOAD_CTRL_REMOVE_PN_POS (1) 1195*4882a593Smuzhiyun #define L2_NWIFI_OFFLOAD_CTRL_REMOVE_PN_LEN (1) 1196*4882a593Smuzhiyun #define L2_NWIFI_OFFLOAD_CTRL_REMOVE_PN_MSK (0x2) 1197*4882a593Smuzhiyun #define L3_L4_CTRL_IPV4_CHECKSUM_EN_POS (0) 1198*4882a593Smuzhiyun #define L3_L4_CTRL_IPV4_CHECKSUM_EN_LEN (1) 1199*4882a593Smuzhiyun #define L3_L4_CTRL_IPV4_CHECKSUM_EN_MSK (0x1) 1200*4882a593Smuzhiyun #define L3_L4_CTRL_TCPIP_CHECKSUM_EN_POS (1) 1201*4882a593Smuzhiyun #define L3_L4_CTRL_TCPIP_CHECKSUM_EN_LEN (1) 1202*4882a593Smuzhiyun #define L3_L4_CTRL_TCPIP_CHECKSUM_EN_MSK (0x2) 1203*4882a593Smuzhiyun #define RING_CTRL_OVERRIDE_PREFETCH_THRSH_POS (0) 1204*4882a593Smuzhiyun #define RING_CTRL_OVERRIDE_PREFETCH_THRSH_LEN (1) 1205*4882a593Smuzhiyun #define RING_CTRL_OVERRIDE_PREFETCH_THRSH_MSK (0x1) 1206*4882a593Smuzhiyun #define RING_CTRL_OVERRIDE_WB_THRSH_POS (1) 1207*4882a593Smuzhiyun #define RING_CTRL_OVERRIDE_WB_THRSH_LEN (1) 1208*4882a593Smuzhiyun #define RING_CTRL_OVERRIDE_WB_THRSH_MSK (0x2) 1209*4882a593Smuzhiyun #define RING_CTRL_OVERRIDE_ITR_THRSH_POS (2) 1210*4882a593Smuzhiyun #define RING_CTRL_OVERRIDE_ITR_THRSH_LEN (1) 1211*4882a593Smuzhiyun #define RING_CTRL_OVERRIDE_ITR_THRSH_MSK (0x4) 1212*4882a593Smuzhiyun #define RING_CTRL_OVERRIDE_HOST_THRSH_POS (3) 1213*4882a593Smuzhiyun #define RING_CTRL_OVERRIDE_HOST_THRSH_LEN (1) 1214*4882a593Smuzhiyun #define RING_CTRL_OVERRIDE_HOST_THRSH_MSK (0x8) 1215*4882a593Smuzhiyun 1216*4882a593Smuzhiyun /* WMI_CFG_RX_CHAIN_CMDID */ 1217*4882a593Smuzhiyun struct wmi_cfg_rx_chain_cmd { 1218*4882a593Smuzhiyun __le32 action; 1219*4882a593Smuzhiyun struct wmi_sw_ring_cfg rx_sw_ring; 1220*4882a593Smuzhiyun u8 mid; 1221*4882a593Smuzhiyun u8 decap_trans_type; 1222*4882a593Smuzhiyun u8 l2_802_3_offload_ctrl; 1223*4882a593Smuzhiyun u8 l2_nwifi_offload_ctrl; 1224*4882a593Smuzhiyun u8 vlan_id; 1225*4882a593Smuzhiyun u8 nwifi_ds_trans_type; 1226*4882a593Smuzhiyun u8 l3_l4_ctrl; 1227*4882a593Smuzhiyun u8 ring_ctrl; 1228*4882a593Smuzhiyun __le16 prefetch_thrsh; 1229*4882a593Smuzhiyun __le16 wb_thrsh; 1230*4882a593Smuzhiyun __le32 itr_value; 1231*4882a593Smuzhiyun __le16 host_thrsh; 1232*4882a593Smuzhiyun u8 reorder_type; 1233*4882a593Smuzhiyun u8 reserved; 1234*4882a593Smuzhiyun struct wmi_sniffer_cfg sniffer_cfg; 1235*4882a593Smuzhiyun __le16 max_rx_pl_per_desc; 1236*4882a593Smuzhiyun } __packed; 1237*4882a593Smuzhiyun 1238*4882a593Smuzhiyun /* WMI_RCP_ADDBA_RESP_CMDID */ 1239*4882a593Smuzhiyun struct wmi_rcp_addba_resp_cmd { 1240*4882a593Smuzhiyun /* Used for cid less than 8. For higher cid set 1241*4882a593Smuzhiyun * CIDXTID_EXTENDED_CID_TID here and use cid and tid members instead 1242*4882a593Smuzhiyun */ 1243*4882a593Smuzhiyun u8 cidxtid; 1244*4882a593Smuzhiyun u8 dialog_token; 1245*4882a593Smuzhiyun __le16 status_code; 1246*4882a593Smuzhiyun /* ieee80211_ba_parameterset field to send */ 1247*4882a593Smuzhiyun __le16 ba_param_set; 1248*4882a593Smuzhiyun __le16 ba_timeout; 1249*4882a593Smuzhiyun /* Used when cidxtid = CIDXTID_EXTENDED_CID_TID */ 1250*4882a593Smuzhiyun u8 cid; 1251*4882a593Smuzhiyun /* Used when cidxtid = CIDXTID_EXTENDED_CID_TID */ 1252*4882a593Smuzhiyun u8 tid; 1253*4882a593Smuzhiyun u8 reserved[2]; 1254*4882a593Smuzhiyun } __packed; 1255*4882a593Smuzhiyun 1256*4882a593Smuzhiyun /* WMI_RCP_ADDBA_RESP_EDMA_CMDID */ 1257*4882a593Smuzhiyun struct wmi_rcp_addba_resp_edma_cmd { 1258*4882a593Smuzhiyun u8 cid; 1259*4882a593Smuzhiyun u8 tid; 1260*4882a593Smuzhiyun u8 dialog_token; 1261*4882a593Smuzhiyun u8 reserved; 1262*4882a593Smuzhiyun __le16 status_code; 1263*4882a593Smuzhiyun /* ieee80211_ba_parameterset field to send */ 1264*4882a593Smuzhiyun __le16 ba_param_set; 1265*4882a593Smuzhiyun __le16 ba_timeout; 1266*4882a593Smuzhiyun u8 status_ring_id; 1267*4882a593Smuzhiyun /* wmi_cfg_rx_chain_cmd_reorder_type */ 1268*4882a593Smuzhiyun u8 reorder_type; 1269*4882a593Smuzhiyun } __packed; 1270*4882a593Smuzhiyun 1271*4882a593Smuzhiyun /* WMI_RCP_DELBA_CMDID */ 1272*4882a593Smuzhiyun struct wmi_rcp_delba_cmd { 1273*4882a593Smuzhiyun /* Used for cid less than 8. For higher cid set 1274*4882a593Smuzhiyun * CIDXTID_EXTENDED_CID_TID here and use cid and tid members instead 1275*4882a593Smuzhiyun */ 1276*4882a593Smuzhiyun u8 cidxtid; 1277*4882a593Smuzhiyun u8 reserved; 1278*4882a593Smuzhiyun __le16 reason; 1279*4882a593Smuzhiyun /* Used when cidxtid = CIDXTID_EXTENDED_CID_TID */ 1280*4882a593Smuzhiyun u8 cid; 1281*4882a593Smuzhiyun /* Used when cidxtid = CIDXTID_EXTENDED_CID_TID */ 1282*4882a593Smuzhiyun u8 tid; 1283*4882a593Smuzhiyun u8 reserved2[2]; 1284*4882a593Smuzhiyun } __packed; 1285*4882a593Smuzhiyun 1286*4882a593Smuzhiyun /* WMI_RCP_ADDBA_REQ_CMDID */ 1287*4882a593Smuzhiyun struct wmi_rcp_addba_req_cmd { 1288*4882a593Smuzhiyun /* Used for cid less than 8. For higher cid set 1289*4882a593Smuzhiyun * CIDXTID_EXTENDED_CID_TID here and use cid and tid members instead 1290*4882a593Smuzhiyun */ 1291*4882a593Smuzhiyun u8 cidxtid; 1292*4882a593Smuzhiyun u8 dialog_token; 1293*4882a593Smuzhiyun /* ieee80211_ba_parameterset field as it received */ 1294*4882a593Smuzhiyun __le16 ba_param_set; 1295*4882a593Smuzhiyun __le16 ba_timeout; 1296*4882a593Smuzhiyun /* ieee80211_ba_seqstrl field as it received */ 1297*4882a593Smuzhiyun __le16 ba_seq_ctrl; 1298*4882a593Smuzhiyun /* Used when cidxtid = CIDXTID_EXTENDED_CID_TID */ 1299*4882a593Smuzhiyun u8 cid; 1300*4882a593Smuzhiyun /* Used when cidxtid = CIDXTID_EXTENDED_CID_TID */ 1301*4882a593Smuzhiyun u8 tid; 1302*4882a593Smuzhiyun u8 reserved[2]; 1303*4882a593Smuzhiyun } __packed; 1304*4882a593Smuzhiyun 1305*4882a593Smuzhiyun /* WMI_SET_MAC_ADDRESS_CMDID */ 1306*4882a593Smuzhiyun struct wmi_set_mac_address_cmd { 1307*4882a593Smuzhiyun u8 mac[WMI_MAC_LEN]; 1308*4882a593Smuzhiyun u8 reserved[2]; 1309*4882a593Smuzhiyun } __packed; 1310*4882a593Smuzhiyun 1311*4882a593Smuzhiyun /* WMI_ECHO_CMDID 1312*4882a593Smuzhiyun * Check FW is alive 1313*4882a593Smuzhiyun * Returned event: WMI_ECHO_RSP_EVENTID 1314*4882a593Smuzhiyun */ 1315*4882a593Smuzhiyun struct wmi_echo_cmd { 1316*4882a593Smuzhiyun __le32 value; 1317*4882a593Smuzhiyun } __packed; 1318*4882a593Smuzhiyun 1319*4882a593Smuzhiyun /* WMI_DEEP_ECHO_CMDID 1320*4882a593Smuzhiyun * Check FW and uCode is alive 1321*4882a593Smuzhiyun * Returned event: WMI_DEEP_ECHO_RSP_EVENTID 1322*4882a593Smuzhiyun */ 1323*4882a593Smuzhiyun struct wmi_deep_echo_cmd { 1324*4882a593Smuzhiyun __le32 value; 1325*4882a593Smuzhiyun } __packed; 1326*4882a593Smuzhiyun 1327*4882a593Smuzhiyun /* WMI_RF_PWR_ON_DELAY_CMDID 1328*4882a593Smuzhiyun * set FW time parameters used through RF resetting 1329*4882a593Smuzhiyun * RF reset consists of bringing its power down for a period of time, then 1330*4882a593Smuzhiyun * bringing the power up 1331*4882a593Smuzhiyun * Returned event: WMI_RF_PWR_ON_DELAY_RSP_EVENTID 1332*4882a593Smuzhiyun */ 1333*4882a593Smuzhiyun struct wmi_rf_pwr_on_delay_cmd { 1334*4882a593Smuzhiyun /* time in usec the FW waits after bringing the RF PWR down, 1335*4882a593Smuzhiyun * set 0 for default 1336*4882a593Smuzhiyun */ 1337*4882a593Smuzhiyun __le16 down_delay_usec; 1338*4882a593Smuzhiyun /* time in usec the FW waits after bringing the RF PWR up, 1339*4882a593Smuzhiyun * set 0 for default 1340*4882a593Smuzhiyun */ 1341*4882a593Smuzhiyun __le16 up_delay_usec; 1342*4882a593Smuzhiyun } __packed; 1343*4882a593Smuzhiyun 1344*4882a593Smuzhiyun /* WMI_SET_HIGH_POWER_TABLE_PARAMS_CMDID 1345*4882a593Smuzhiyun * This API controls the Tx and Rx gain over temperature. 1346*4882a593Smuzhiyun * It controls the Tx D-type, Rx D-type and Rx E-type amplifiers. 1347*4882a593Smuzhiyun * It also controls the Tx gain index, by controlling the Rx to Tx gain index 1348*4882a593Smuzhiyun * offset. 1349*4882a593Smuzhiyun * The control is divided by 3 temperature values to 4 temperature ranges. 1350*4882a593Smuzhiyun * Each parameter uses its own temperature values. 1351*4882a593Smuzhiyun * Returned event: WMI_SET_HIGH_POWER_TABLE_PARAMS_EVENTID 1352*4882a593Smuzhiyun */ 1353*4882a593Smuzhiyun struct wmi_set_high_power_table_params_cmd { 1354*4882a593Smuzhiyun /* Temperature range for Tx D-type parameters */ 1355*4882a593Smuzhiyun u8 tx_dtype_temp[WMI_RF_DTYPE_LENGTH]; 1356*4882a593Smuzhiyun u8 reserved0; 1357*4882a593Smuzhiyun /* Tx D-type values to be used for each temperature range */ 1358*4882a593Smuzhiyun __le32 tx_dtype_conf[WMI_RF_DTYPE_CONF_LENGTH]; 1359*4882a593Smuzhiyun /* Temperature range for Tx E-type parameters */ 1360*4882a593Smuzhiyun u8 tx_etype_temp[WMI_RF_ETYPE_LENGTH]; 1361*4882a593Smuzhiyun u8 reserved1; 1362*4882a593Smuzhiyun /* Tx E-type values to be used for each temperature range. 1363*4882a593Smuzhiyun * The last 4 values of any range are the first 4 values of the next 1364*4882a593Smuzhiyun * range and so on 1365*4882a593Smuzhiyun */ 1366*4882a593Smuzhiyun __le32 tx_etype_conf[WMI_RF_ETYPE_CONF_LENGTH]; 1367*4882a593Smuzhiyun /* Temperature range for Rx D-type parameters */ 1368*4882a593Smuzhiyun u8 rx_dtype_temp[WMI_RF_DTYPE_LENGTH]; 1369*4882a593Smuzhiyun u8 reserved2; 1370*4882a593Smuzhiyun /* Rx D-type values to be used for each temperature range */ 1371*4882a593Smuzhiyun __le32 rx_dtype_conf[WMI_RF_DTYPE_CONF_LENGTH]; 1372*4882a593Smuzhiyun /* Temperature range for Rx E-type parameters */ 1373*4882a593Smuzhiyun u8 rx_etype_temp[WMI_RF_ETYPE_LENGTH]; 1374*4882a593Smuzhiyun u8 reserved3; 1375*4882a593Smuzhiyun /* Rx E-type values to be used for each temperature range. 1376*4882a593Smuzhiyun * The last 4 values of any range are the first 4 values of the next 1377*4882a593Smuzhiyun * range and so on 1378*4882a593Smuzhiyun */ 1379*4882a593Smuzhiyun __le32 rx_etype_conf[WMI_RF_ETYPE_CONF_LENGTH]; 1380*4882a593Smuzhiyun /* Temperature range for rx_2_tx_offs parameters */ 1381*4882a593Smuzhiyun u8 rx_2_tx_temp[WMI_RF_RX2TX_LENGTH]; 1382*4882a593Smuzhiyun u8 reserved4; 1383*4882a593Smuzhiyun /* Rx to Tx gain index offset */ 1384*4882a593Smuzhiyun s8 rx_2_tx_offs[WMI_RF_RX2TX_CONF_LENGTH]; 1385*4882a593Smuzhiyun } __packed; 1386*4882a593Smuzhiyun 1387*4882a593Smuzhiyun /* WMI_FIXED_SCHEDULING_UL_CONFIG_CMDID 1388*4882a593Smuzhiyun * This API sets rd parameter per mcs. 1389*4882a593Smuzhiyun * Relevant only in Fixed Scheduling mode. 1390*4882a593Smuzhiyun * Returned event: WMI_FIXED_SCHEDULING_UL_CONFIG_EVENTID 1391*4882a593Smuzhiyun */ 1392*4882a593Smuzhiyun struct wmi_fixed_scheduling_ul_config_cmd { 1393*4882a593Smuzhiyun /* Use mcs -1 to set for every mcs */ 1394*4882a593Smuzhiyun s8 mcs; 1395*4882a593Smuzhiyun /* Number of frames with rd bit set in a single virtual slot */ 1396*4882a593Smuzhiyun u8 rd_count_per_slot; 1397*4882a593Smuzhiyun u8 reserved[2]; 1398*4882a593Smuzhiyun } __packed; 1399*4882a593Smuzhiyun 1400*4882a593Smuzhiyun /* CMD: WMI_RF_XPM_READ_CMDID */ 1401*4882a593Smuzhiyun struct wmi_rf_xpm_read_cmd { 1402*4882a593Smuzhiyun u8 rf_id; 1403*4882a593Smuzhiyun u8 reserved[3]; 1404*4882a593Smuzhiyun /* XPM bit start address in range [0,8191]bits - rounded by FW to 1405*4882a593Smuzhiyun * multiple of 8bits 1406*4882a593Smuzhiyun */ 1407*4882a593Smuzhiyun __le32 xpm_bit_address; 1408*4882a593Smuzhiyun __le32 num_bytes; 1409*4882a593Smuzhiyun } __packed; 1410*4882a593Smuzhiyun 1411*4882a593Smuzhiyun /* CMD: WMI_RF_XPM_WRITE_CMDID */ 1412*4882a593Smuzhiyun struct wmi_rf_xpm_write_cmd { 1413*4882a593Smuzhiyun u8 rf_id; 1414*4882a593Smuzhiyun u8 reserved0[3]; 1415*4882a593Smuzhiyun /* XPM bit start address in range [0,8191]bits - rounded by FW to 1416*4882a593Smuzhiyun * multiple of 8bits 1417*4882a593Smuzhiyun */ 1418*4882a593Smuzhiyun __le32 xpm_bit_address; 1419*4882a593Smuzhiyun __le32 num_bytes; 1420*4882a593Smuzhiyun /* boolean flag indicating whether FW should verify the write 1421*4882a593Smuzhiyun * operation 1422*4882a593Smuzhiyun */ 1423*4882a593Smuzhiyun u8 verify; 1424*4882a593Smuzhiyun u8 reserved1[3]; 1425*4882a593Smuzhiyun /* actual size=num_bytes */ 1426*4882a593Smuzhiyun u8 data_bytes[]; 1427*4882a593Smuzhiyun } __packed; 1428*4882a593Smuzhiyun 1429*4882a593Smuzhiyun /* Possible modes for temperature measurement */ 1430*4882a593Smuzhiyun enum wmi_temperature_measure_mode { 1431*4882a593Smuzhiyun TEMPERATURE_USE_OLD_VALUE = 0x01, 1432*4882a593Smuzhiyun TEMPERATURE_MEASURE_NOW = 0x02, 1433*4882a593Smuzhiyun }; 1434*4882a593Smuzhiyun 1435*4882a593Smuzhiyun /* WMI_TEMP_SENSE_CMDID */ 1436*4882a593Smuzhiyun struct wmi_temp_sense_cmd { 1437*4882a593Smuzhiyun __le32 measure_baseband_en; 1438*4882a593Smuzhiyun __le32 measure_rf_en; 1439*4882a593Smuzhiyun __le32 measure_mode; 1440*4882a593Smuzhiyun } __packed; 1441*4882a593Smuzhiyun 1442*4882a593Smuzhiyun enum wmi_pmc_op { 1443*4882a593Smuzhiyun WMI_PMC_ALLOCATE = 0x00, 1444*4882a593Smuzhiyun WMI_PMC_RELEASE = 0x01, 1445*4882a593Smuzhiyun }; 1446*4882a593Smuzhiyun 1447*4882a593Smuzhiyun /* WMI_PMC_CMDID */ 1448*4882a593Smuzhiyun struct wmi_pmc_cmd { 1449*4882a593Smuzhiyun /* enum wmi_pmc_cmd_op_type */ 1450*4882a593Smuzhiyun u8 op; 1451*4882a593Smuzhiyun u8 reserved; 1452*4882a593Smuzhiyun __le16 ring_size; 1453*4882a593Smuzhiyun __le64 mem_base; 1454*4882a593Smuzhiyun } __packed; 1455*4882a593Smuzhiyun 1456*4882a593Smuzhiyun enum wmi_aoa_meas_type { 1457*4882a593Smuzhiyun WMI_AOA_PHASE_MEAS = 0x00, 1458*4882a593Smuzhiyun WMI_AOA_PHASE_AMP_MEAS = 0x01, 1459*4882a593Smuzhiyun }; 1460*4882a593Smuzhiyun 1461*4882a593Smuzhiyun /* WMI_AOA_MEAS_CMDID */ 1462*4882a593Smuzhiyun struct wmi_aoa_meas_cmd { 1463*4882a593Smuzhiyun u8 mac_addr[WMI_MAC_LEN]; 1464*4882a593Smuzhiyun /* channels IDs: 1465*4882a593Smuzhiyun * 0 - 58320 MHz 1466*4882a593Smuzhiyun * 1 - 60480 MHz 1467*4882a593Smuzhiyun * 2 - 62640 MHz 1468*4882a593Smuzhiyun */ 1469*4882a593Smuzhiyun u8 channel; 1470*4882a593Smuzhiyun /* enum wmi_aoa_meas_type */ 1471*4882a593Smuzhiyun u8 aoa_meas_type; 1472*4882a593Smuzhiyun __le32 meas_rf_mask; 1473*4882a593Smuzhiyun } __packed; 1474*4882a593Smuzhiyun 1475*4882a593Smuzhiyun /* WMI_SET_MGMT_RETRY_LIMIT_CMDID */ 1476*4882a593Smuzhiyun struct wmi_set_mgmt_retry_limit_cmd { 1477*4882a593Smuzhiyun /* MAC retransmit limit for mgmt frames */ 1478*4882a593Smuzhiyun u8 mgmt_retry_limit; 1479*4882a593Smuzhiyun /* alignment to 32b */ 1480*4882a593Smuzhiyun u8 reserved[3]; 1481*4882a593Smuzhiyun } __packed; 1482*4882a593Smuzhiyun 1483*4882a593Smuzhiyun /* Zones: HIGH, MAX, CRITICAL */ 1484*4882a593Smuzhiyun #define WMI_NUM_OF_TT_ZONES (3) 1485*4882a593Smuzhiyun 1486*4882a593Smuzhiyun struct wmi_tt_zone_limits { 1487*4882a593Smuzhiyun /* Above this temperature this zone is active */ 1488*4882a593Smuzhiyun u8 temperature_high; 1489*4882a593Smuzhiyun /* Below this temperature the adjacent lower zone is active */ 1490*4882a593Smuzhiyun u8 temperature_low; 1491*4882a593Smuzhiyun u8 reserved[2]; 1492*4882a593Smuzhiyun } __packed; 1493*4882a593Smuzhiyun 1494*4882a593Smuzhiyun /* Struct used for both configuration and status commands of thermal 1495*4882a593Smuzhiyun * throttling 1496*4882a593Smuzhiyun */ 1497*4882a593Smuzhiyun struct wmi_tt_data { 1498*4882a593Smuzhiyun /* Enable/Disable TT algorithm for baseband */ 1499*4882a593Smuzhiyun u8 bb_enabled; 1500*4882a593Smuzhiyun u8 reserved0[3]; 1501*4882a593Smuzhiyun /* Define zones for baseband */ 1502*4882a593Smuzhiyun struct wmi_tt_zone_limits bb_zones[WMI_NUM_OF_TT_ZONES]; 1503*4882a593Smuzhiyun /* Enable/Disable TT algorithm for radio */ 1504*4882a593Smuzhiyun u8 rf_enabled; 1505*4882a593Smuzhiyun u8 reserved1[3]; 1506*4882a593Smuzhiyun /* Define zones for all radio chips */ 1507*4882a593Smuzhiyun struct wmi_tt_zone_limits rf_zones[WMI_NUM_OF_TT_ZONES]; 1508*4882a593Smuzhiyun } __packed; 1509*4882a593Smuzhiyun 1510*4882a593Smuzhiyun /* WMI_SET_THERMAL_THROTTLING_CFG_CMDID */ 1511*4882a593Smuzhiyun struct wmi_set_thermal_throttling_cfg_cmd { 1512*4882a593Smuzhiyun /* Command data */ 1513*4882a593Smuzhiyun struct wmi_tt_data tt_data; 1514*4882a593Smuzhiyun } __packed; 1515*4882a593Smuzhiyun 1516*4882a593Smuzhiyun /* WMI_NEW_STA_CMDID */ 1517*4882a593Smuzhiyun struct wmi_new_sta_cmd { 1518*4882a593Smuzhiyun u8 dst_mac[WMI_MAC_LEN]; 1519*4882a593Smuzhiyun u8 aid; 1520*4882a593Smuzhiyun } __packed; 1521*4882a593Smuzhiyun 1522*4882a593Smuzhiyun /* WMI_DEL_STA_CMDID */ 1523*4882a593Smuzhiyun struct wmi_del_sta_cmd { 1524*4882a593Smuzhiyun u8 dst_mac[WMI_MAC_LEN]; 1525*4882a593Smuzhiyun __le16 disconnect_reason; 1526*4882a593Smuzhiyun } __packed; 1527*4882a593Smuzhiyun 1528*4882a593Smuzhiyun enum wmi_tof_burst_duration { 1529*4882a593Smuzhiyun WMI_TOF_BURST_DURATION_250_USEC = 2, 1530*4882a593Smuzhiyun WMI_TOF_BURST_DURATION_500_USEC = 3, 1531*4882a593Smuzhiyun WMI_TOF_BURST_DURATION_1_MSEC = 4, 1532*4882a593Smuzhiyun WMI_TOF_BURST_DURATION_2_MSEC = 5, 1533*4882a593Smuzhiyun WMI_TOF_BURST_DURATION_4_MSEC = 6, 1534*4882a593Smuzhiyun WMI_TOF_BURST_DURATION_8_MSEC = 7, 1535*4882a593Smuzhiyun WMI_TOF_BURST_DURATION_16_MSEC = 8, 1536*4882a593Smuzhiyun WMI_TOF_BURST_DURATION_32_MSEC = 9, 1537*4882a593Smuzhiyun WMI_TOF_BURST_DURATION_64_MSEC = 10, 1538*4882a593Smuzhiyun WMI_TOF_BURST_DURATION_128_MSEC = 11, 1539*4882a593Smuzhiyun WMI_TOF_BURST_DURATION_NO_PREFERENCES = 15, 1540*4882a593Smuzhiyun }; 1541*4882a593Smuzhiyun 1542*4882a593Smuzhiyun enum wmi_tof_session_start_flags { 1543*4882a593Smuzhiyun WMI_TOF_SESSION_START_FLAG_SECURED = 0x1, 1544*4882a593Smuzhiyun WMI_TOF_SESSION_START_FLAG_ASAP = 0x2, 1545*4882a593Smuzhiyun WMI_TOF_SESSION_START_FLAG_LCI_REQ = 0x4, 1546*4882a593Smuzhiyun WMI_TOF_SESSION_START_FLAG_LCR_REQ = 0x8, 1547*4882a593Smuzhiyun }; 1548*4882a593Smuzhiyun 1549*4882a593Smuzhiyun /* WMI_TOF_SESSION_START_CMDID */ 1550*4882a593Smuzhiyun struct wmi_ftm_dest_info { 1551*4882a593Smuzhiyun u8 channel; 1552*4882a593Smuzhiyun /* wmi_tof_session_start_flags_e */ 1553*4882a593Smuzhiyun u8 flags; 1554*4882a593Smuzhiyun u8 initial_token; 1555*4882a593Smuzhiyun u8 num_of_ftm_per_burst; 1556*4882a593Smuzhiyun u8 num_of_bursts_exp; 1557*4882a593Smuzhiyun /* wmi_tof_burst_duration_e */ 1558*4882a593Smuzhiyun u8 burst_duration; 1559*4882a593Smuzhiyun /* Burst Period indicate interval between two consecutive burst 1560*4882a593Smuzhiyun * instances, in units of 100 ms 1561*4882a593Smuzhiyun */ 1562*4882a593Smuzhiyun __le16 burst_period; 1563*4882a593Smuzhiyun u8 dst_mac[WMI_MAC_LEN]; 1564*4882a593Smuzhiyun u8 reserved; 1565*4882a593Smuzhiyun u8 num_burst_per_aoa_meas; 1566*4882a593Smuzhiyun } __packed; 1567*4882a593Smuzhiyun 1568*4882a593Smuzhiyun /* WMI_TOF_SESSION_START_CMDID */ 1569*4882a593Smuzhiyun struct wmi_tof_session_start_cmd { 1570*4882a593Smuzhiyun __le32 session_id; 1571*4882a593Smuzhiyun u8 reserved1; 1572*4882a593Smuzhiyun u8 aoa_type; 1573*4882a593Smuzhiyun __le16 num_of_dest; 1574*4882a593Smuzhiyun u8 reserved[4]; 1575*4882a593Smuzhiyun struct wmi_ftm_dest_info ftm_dest_info[]; 1576*4882a593Smuzhiyun } __packed; 1577*4882a593Smuzhiyun 1578*4882a593Smuzhiyun /* WMI_TOF_CFG_RESPONDER_CMDID */ 1579*4882a593Smuzhiyun struct wmi_tof_cfg_responder_cmd { 1580*4882a593Smuzhiyun u8 enable; 1581*4882a593Smuzhiyun u8 reserved[3]; 1582*4882a593Smuzhiyun } __packed; 1583*4882a593Smuzhiyun 1584*4882a593Smuzhiyun enum wmi_tof_channel_info_report_type { 1585*4882a593Smuzhiyun WMI_TOF_CHANNEL_INFO_TYPE_CIR = 0x1, 1586*4882a593Smuzhiyun WMI_TOF_CHANNEL_INFO_TYPE_RSSI = 0x2, 1587*4882a593Smuzhiyun WMI_TOF_CHANNEL_INFO_TYPE_SNR = 0x4, 1588*4882a593Smuzhiyun WMI_TOF_CHANNEL_INFO_TYPE_DEBUG_DATA = 0x8, 1589*4882a593Smuzhiyun WMI_TOF_CHANNEL_INFO_TYPE_VENDOR_SPECIFIC = 0x10, 1590*4882a593Smuzhiyun }; 1591*4882a593Smuzhiyun 1592*4882a593Smuzhiyun /* WMI_TOF_CHANNEL_INFO_CMDID */ 1593*4882a593Smuzhiyun struct wmi_tof_channel_info_cmd { 1594*4882a593Smuzhiyun /* wmi_tof_channel_info_report_type_e */ 1595*4882a593Smuzhiyun __le32 channel_info_report_request; 1596*4882a593Smuzhiyun } __packed; 1597*4882a593Smuzhiyun 1598*4882a593Smuzhiyun /* WMI_TOF_SET_TX_RX_OFFSET_CMDID */ 1599*4882a593Smuzhiyun struct wmi_tof_set_tx_rx_offset_cmd { 1600*4882a593Smuzhiyun /* TX delay offset */ 1601*4882a593Smuzhiyun __le32 tx_offset; 1602*4882a593Smuzhiyun /* RX delay offset */ 1603*4882a593Smuzhiyun __le32 rx_offset; 1604*4882a593Smuzhiyun /* Mask to define which RFs to configure. 0 means all RFs */ 1605*4882a593Smuzhiyun __le32 rf_mask; 1606*4882a593Smuzhiyun /* Offset to strongest tap of CIR */ 1607*4882a593Smuzhiyun __le32 precursor; 1608*4882a593Smuzhiyun } __packed; 1609*4882a593Smuzhiyun 1610*4882a593Smuzhiyun /* WMI_TOF_GET_TX_RX_OFFSET_CMDID */ 1611*4882a593Smuzhiyun struct wmi_tof_get_tx_rx_offset_cmd { 1612*4882a593Smuzhiyun /* rf index to read offsets from */ 1613*4882a593Smuzhiyun u8 rf_index; 1614*4882a593Smuzhiyun u8 reserved[3]; 1615*4882a593Smuzhiyun } __packed; 1616*4882a593Smuzhiyun 1617*4882a593Smuzhiyun /* WMI_FIXED_SCHEDULING_CONFIG_CMDID */ 1618*4882a593Smuzhiyun struct wmi_map_mcs_to_schd_params { 1619*4882a593Smuzhiyun u8 mcs; 1620*4882a593Smuzhiyun /* time in usec from start slot to start tx flow - default 15 */ 1621*4882a593Smuzhiyun u8 time_in_usec_before_initiate_tx; 1622*4882a593Smuzhiyun /* RD enable - if yes consider RD according to STA mcs */ 1623*4882a593Smuzhiyun u8 rd_enabled; 1624*4882a593Smuzhiyun u8 reserved; 1625*4882a593Smuzhiyun /* time in usec from start slot to stop vring */ 1626*4882a593Smuzhiyun __le16 time_in_usec_to_stop_vring; 1627*4882a593Smuzhiyun /* timeout to force flush from start of slot */ 1628*4882a593Smuzhiyun __le16 flush_to_in_usec; 1629*4882a593Smuzhiyun /* per mcs the mac buffer limit size in bytes */ 1630*4882a593Smuzhiyun __le32 mac_buff_size_in_bytes; 1631*4882a593Smuzhiyun } __packed; 1632*4882a593Smuzhiyun 1633*4882a593Smuzhiyun /* WMI_FIXED_SCHEDULING_CONFIG_COMPLETE_EVENTID */ 1634*4882a593Smuzhiyun struct wmi_fixed_scheduling_config_complete_event { 1635*4882a593Smuzhiyun /* wmi_fw_status */ 1636*4882a593Smuzhiyun u8 status; 1637*4882a593Smuzhiyun u8 reserved[3]; 1638*4882a593Smuzhiyun } __packed; 1639*4882a593Smuzhiyun 1640*4882a593Smuzhiyun /* This value exists for backwards compatibility only. 1641*4882a593Smuzhiyun * Do not use it in new commands. 1642*4882a593Smuzhiyun * Use dynamic arrays where possible. 1643*4882a593Smuzhiyun */ 1644*4882a593Smuzhiyun #define WMI_NUM_MCS (13) 1645*4882a593Smuzhiyun 1646*4882a593Smuzhiyun /* WMI_FIXED_SCHEDULING_CONFIG_CMDID */ 1647*4882a593Smuzhiyun struct wmi_fixed_scheduling_config_cmd { 1648*4882a593Smuzhiyun /* defaults in the SAS table */ 1649*4882a593Smuzhiyun struct wmi_map_mcs_to_schd_params mcs_to_schd_params_map[WMI_NUM_MCS]; 1650*4882a593Smuzhiyun /* default 150 uSec */ 1651*4882a593Smuzhiyun __le16 max_sta_rd_ppdu_duration_in_usec; 1652*4882a593Smuzhiyun /* default 300 uSec */ 1653*4882a593Smuzhiyun __le16 max_sta_grant_ppdu_duration_in_usec; 1654*4882a593Smuzhiyun /* default 1000 uSec */ 1655*4882a593Smuzhiyun __le16 assoc_slot_duration_in_usec; 1656*4882a593Smuzhiyun /* default 360 uSec */ 1657*4882a593Smuzhiyun __le16 virtual_slot_duration_in_usec; 1658*4882a593Smuzhiyun /* each this field value slots start with grant frame to the station 1659*4882a593Smuzhiyun * - default 2 1660*4882a593Smuzhiyun */ 1661*4882a593Smuzhiyun u8 number_of_ap_slots_for_initiate_grant; 1662*4882a593Smuzhiyun u8 reserved[3]; 1663*4882a593Smuzhiyun } __packed; 1664*4882a593Smuzhiyun 1665*4882a593Smuzhiyun /* WMI_ENABLE_FIXED_SCHEDULING_CMDID */ 1666*4882a593Smuzhiyun struct wmi_enable_fixed_scheduling_cmd { 1667*4882a593Smuzhiyun __le32 reserved; 1668*4882a593Smuzhiyun } __packed; 1669*4882a593Smuzhiyun 1670*4882a593Smuzhiyun /* WMI_ENABLE_FIXED_SCHEDULING_COMPLETE_EVENTID */ 1671*4882a593Smuzhiyun struct wmi_enable_fixed_scheduling_complete_event { 1672*4882a593Smuzhiyun /* wmi_fw_status */ 1673*4882a593Smuzhiyun u8 status; 1674*4882a593Smuzhiyun u8 reserved[3]; 1675*4882a593Smuzhiyun } __packed; 1676*4882a593Smuzhiyun 1677*4882a593Smuzhiyun /* WMI_SET_MULTI_DIRECTED_OMNIS_CONFIG_CMDID */ 1678*4882a593Smuzhiyun struct wmi_set_multi_directed_omnis_config_cmd { 1679*4882a593Smuzhiyun /* number of directed omnis at destination AP */ 1680*4882a593Smuzhiyun u8 dest_ap_num_directed_omnis; 1681*4882a593Smuzhiyun u8 reserved[3]; 1682*4882a593Smuzhiyun } __packed; 1683*4882a593Smuzhiyun 1684*4882a593Smuzhiyun /* WMI_SET_MULTI_DIRECTED_OMNIS_CONFIG_EVENTID */ 1685*4882a593Smuzhiyun struct wmi_set_multi_directed_omnis_config_event { 1686*4882a593Smuzhiyun /* wmi_fw_status */ 1687*4882a593Smuzhiyun u8 status; 1688*4882a593Smuzhiyun u8 reserved[3]; 1689*4882a593Smuzhiyun } __packed; 1690*4882a593Smuzhiyun 1691*4882a593Smuzhiyun /* WMI_RADAR_GENERAL_CONFIG_EVENTID */ 1692*4882a593Smuzhiyun struct wmi_radar_general_config_event { 1693*4882a593Smuzhiyun /* wmi_fw_status */ 1694*4882a593Smuzhiyun u8 status; 1695*4882a593Smuzhiyun u8 reserved[3]; 1696*4882a593Smuzhiyun } __packed; 1697*4882a593Smuzhiyun 1698*4882a593Smuzhiyun /* WMI_RADAR_CONFIG_SELECT_EVENTID */ 1699*4882a593Smuzhiyun struct wmi_radar_config_select_event { 1700*4882a593Smuzhiyun /* wmi_fw_status */ 1701*4882a593Smuzhiyun u8 status; 1702*4882a593Smuzhiyun u8 reserved[3]; 1703*4882a593Smuzhiyun /* In unit of bytes */ 1704*4882a593Smuzhiyun __le32 fifo_size; 1705*4882a593Smuzhiyun /* In unit of bytes */ 1706*4882a593Smuzhiyun __le32 pulse_size; 1707*4882a593Smuzhiyun } __packed; 1708*4882a593Smuzhiyun 1709*4882a593Smuzhiyun /* WMI_RADAR_PARAMS_CONFIG_EVENTID */ 1710*4882a593Smuzhiyun struct wmi_radar_params_config_event { 1711*4882a593Smuzhiyun /* wmi_fw_status */ 1712*4882a593Smuzhiyun u8 status; 1713*4882a593Smuzhiyun u8 reserved[3]; 1714*4882a593Smuzhiyun } __packed; 1715*4882a593Smuzhiyun 1716*4882a593Smuzhiyun /* WMI_RADAR_SET_MODE_EVENTID */ 1717*4882a593Smuzhiyun struct wmi_radar_set_mode_event { 1718*4882a593Smuzhiyun /* wmi_fw_status */ 1719*4882a593Smuzhiyun u8 status; 1720*4882a593Smuzhiyun u8 reserved[3]; 1721*4882a593Smuzhiyun } __packed; 1722*4882a593Smuzhiyun 1723*4882a593Smuzhiyun /* WMI_RADAR_CONTROL_EVENTID */ 1724*4882a593Smuzhiyun struct wmi_radar_control_event { 1725*4882a593Smuzhiyun /* wmi_fw_status */ 1726*4882a593Smuzhiyun u8 status; 1727*4882a593Smuzhiyun u8 reserved[3]; 1728*4882a593Smuzhiyun } __packed; 1729*4882a593Smuzhiyun 1730*4882a593Smuzhiyun /* WMI_RADAR_PCI_CONTROL_EVENTID */ 1731*4882a593Smuzhiyun struct wmi_radar_pci_control_event { 1732*4882a593Smuzhiyun /* wmi_fw_status */ 1733*4882a593Smuzhiyun u8 status; 1734*4882a593Smuzhiyun u8 reserved[3]; 1735*4882a593Smuzhiyun } __packed; 1736*4882a593Smuzhiyun 1737*4882a593Smuzhiyun /* WMI_SET_LONG_RANGE_CONFIG_CMDID */ 1738*4882a593Smuzhiyun struct wmi_set_long_range_config_cmd { 1739*4882a593Smuzhiyun __le32 reserved; 1740*4882a593Smuzhiyun } __packed; 1741*4882a593Smuzhiyun 1742*4882a593Smuzhiyun /* WMI_SET_LONG_RANGE_CONFIG_COMPLETE_EVENTID */ 1743*4882a593Smuzhiyun struct wmi_set_long_range_config_complete_event { 1744*4882a593Smuzhiyun /* wmi_fw_status */ 1745*4882a593Smuzhiyun u8 status; 1746*4882a593Smuzhiyun u8 reserved[3]; 1747*4882a593Smuzhiyun } __packed; 1748*4882a593Smuzhiyun 1749*4882a593Smuzhiyun /* payload max size is 1024 bytes: max event buffer size (1044) - WMI headers 1750*4882a593Smuzhiyun * (16) - prev struct field size (4) 1751*4882a593Smuzhiyun */ 1752*4882a593Smuzhiyun #define WMI_MAX_IOCTL_PAYLOAD_SIZE (1024) 1753*4882a593Smuzhiyun #define WMI_MAX_IOCTL_REPLY_PAYLOAD_SIZE (1024) 1754*4882a593Smuzhiyun #define WMI_MAX_INTERNAL_EVENT_PAYLOAD_SIZE (1024) 1755*4882a593Smuzhiyun 1756*4882a593Smuzhiyun enum wmi_internal_fw_ioctl_code { 1757*4882a593Smuzhiyun WMI_INTERNAL_FW_CODE_NONE = 0x0, 1758*4882a593Smuzhiyun WMI_INTERNAL_FW_CODE_QCOM = 0x1, 1759*4882a593Smuzhiyun }; 1760*4882a593Smuzhiyun 1761*4882a593Smuzhiyun /* WMI_INTERNAL_FW_IOCTL_CMDID */ 1762*4882a593Smuzhiyun struct wmi_internal_fw_ioctl_cmd { 1763*4882a593Smuzhiyun /* enum wmi_internal_fw_ioctl_code */ 1764*4882a593Smuzhiyun __le16 code; 1765*4882a593Smuzhiyun __le16 length; 1766*4882a593Smuzhiyun /* payload max size is WMI_MAX_IOCTL_PAYLOAD_SIZE 1767*4882a593Smuzhiyun * Must be the last member of the struct 1768*4882a593Smuzhiyun */ 1769*4882a593Smuzhiyun __le32 payload[]; 1770*4882a593Smuzhiyun } __packed; 1771*4882a593Smuzhiyun 1772*4882a593Smuzhiyun /* WMI_INTERNAL_FW_IOCTL_EVENTID */ 1773*4882a593Smuzhiyun struct wmi_internal_fw_ioctl_event { 1774*4882a593Smuzhiyun /* wmi_fw_status */ 1775*4882a593Smuzhiyun u8 status; 1776*4882a593Smuzhiyun u8 reserved; 1777*4882a593Smuzhiyun __le16 length; 1778*4882a593Smuzhiyun /* payload max size is WMI_MAX_IOCTL_REPLY_PAYLOAD_SIZE 1779*4882a593Smuzhiyun * Must be the last member of the struct 1780*4882a593Smuzhiyun */ 1781*4882a593Smuzhiyun __le32 payload[]; 1782*4882a593Smuzhiyun } __packed; 1783*4882a593Smuzhiyun 1784*4882a593Smuzhiyun /* WMI_INTERNAL_FW_EVENT_EVENTID */ 1785*4882a593Smuzhiyun struct wmi_internal_fw_event_event { 1786*4882a593Smuzhiyun __le16 id; 1787*4882a593Smuzhiyun __le16 length; 1788*4882a593Smuzhiyun /* payload max size is WMI_MAX_INTERNAL_EVENT_PAYLOAD_SIZE 1789*4882a593Smuzhiyun * Must be the last member of the struct 1790*4882a593Smuzhiyun */ 1791*4882a593Smuzhiyun __le32 payload[]; 1792*4882a593Smuzhiyun } __packed; 1793*4882a593Smuzhiyun 1794*4882a593Smuzhiyun /* WMI_SET_VRING_PRIORITY_WEIGHT_CMDID */ 1795*4882a593Smuzhiyun struct wmi_set_vring_priority_weight_cmd { 1796*4882a593Smuzhiyun /* Array of weights. Valid values are 1797*4882a593Smuzhiyun * WMI_QOS_MIN_DEFAULT_WEIGHT...WMI_QOS_MAX_WEIGHT. Weight #0 is 1798*4882a593Smuzhiyun * hard-coded WMI_QOS_MIN_WEIGHT. This array provide the weights 1799*4882a593Smuzhiyun * #1..#3 1800*4882a593Smuzhiyun */ 1801*4882a593Smuzhiyun u8 weight[3]; 1802*4882a593Smuzhiyun u8 reserved; 1803*4882a593Smuzhiyun } __packed; 1804*4882a593Smuzhiyun 1805*4882a593Smuzhiyun /* WMI_SET_VRING_PRIORITY_CMDID */ 1806*4882a593Smuzhiyun struct wmi_vring_priority { 1807*4882a593Smuzhiyun u8 vring_idx; 1808*4882a593Smuzhiyun /* Weight index. Valid value is 0-3 */ 1809*4882a593Smuzhiyun u8 priority; 1810*4882a593Smuzhiyun u8 reserved[2]; 1811*4882a593Smuzhiyun } __packed; 1812*4882a593Smuzhiyun 1813*4882a593Smuzhiyun /* WMI_SET_VRING_PRIORITY_CMDID */ 1814*4882a593Smuzhiyun struct wmi_set_vring_priority_cmd { 1815*4882a593Smuzhiyun /* number of entries in vring_priority. Set to 1816*4882a593Smuzhiyun * WMI_QOS_SET_VIF_PRIORITY to update the VIF's priority, and there 1817*4882a593Smuzhiyun * will be only one entry in vring_priority 1818*4882a593Smuzhiyun */ 1819*4882a593Smuzhiyun u8 num_of_vrings; 1820*4882a593Smuzhiyun u8 reserved[3]; 1821*4882a593Smuzhiyun struct wmi_vring_priority vring_priority[]; 1822*4882a593Smuzhiyun } __packed; 1823*4882a593Smuzhiyun 1824*4882a593Smuzhiyun /* WMI_BF_CONTROL_CMDID - deprecated */ 1825*4882a593Smuzhiyun struct wmi_bf_control_cmd { 1826*4882a593Smuzhiyun /* wmi_bf_triggers */ 1827*4882a593Smuzhiyun __le32 triggers; 1828*4882a593Smuzhiyun u8 cid; 1829*4882a593Smuzhiyun /* DISABLED = 0, ENABLED = 1 , DRY_RUN = 2 */ 1830*4882a593Smuzhiyun u8 txss_mode; 1831*4882a593Smuzhiyun /* DISABLED = 0, ENABLED = 1, DRY_RUN = 2 */ 1832*4882a593Smuzhiyun u8 brp_mode; 1833*4882a593Smuzhiyun /* Max cts threshold (correspond to 1834*4882a593Smuzhiyun * WMI_BF_TRIGGER_MAX_CTS_FAILURE_IN_TXOP) 1835*4882a593Smuzhiyun */ 1836*4882a593Smuzhiyun u8 bf_trigger_max_cts_failure_thr; 1837*4882a593Smuzhiyun /* Max cts threshold in dense (correspond to 1838*4882a593Smuzhiyun * WMI_BF_TRIGGER_MAX_CTS_FAILURE_IN_TXOP) 1839*4882a593Smuzhiyun */ 1840*4882a593Smuzhiyun u8 bf_trigger_max_cts_failure_dense_thr; 1841*4882a593Smuzhiyun /* Max b-ack threshold (correspond to 1842*4882a593Smuzhiyun * WMI_BF_TRIGGER_MAX_BACK_FAILURE) 1843*4882a593Smuzhiyun */ 1844*4882a593Smuzhiyun u8 bf_trigger_max_back_failure_thr; 1845*4882a593Smuzhiyun /* Max b-ack threshold in dense (correspond to 1846*4882a593Smuzhiyun * WMI_BF_TRIGGER_MAX_BACK_FAILURE) 1847*4882a593Smuzhiyun */ 1848*4882a593Smuzhiyun u8 bf_trigger_max_back_failure_dense_thr; 1849*4882a593Smuzhiyun u8 reserved0; 1850*4882a593Smuzhiyun /* Wrong sectors threshold */ 1851*4882a593Smuzhiyun __le32 wrong_sector_bis_thr; 1852*4882a593Smuzhiyun /* BOOL to enable/disable long term trigger */ 1853*4882a593Smuzhiyun u8 long_term_enable; 1854*4882a593Smuzhiyun /* 1 = Update long term thresholds from the long_term_mbps_th_tbl and 1855*4882a593Smuzhiyun * long_term_trig_timeout_per_mcs arrays, 0 = Ignore 1856*4882a593Smuzhiyun */ 1857*4882a593Smuzhiyun u8 long_term_update_thr; 1858*4882a593Smuzhiyun /* Long term throughput threshold [Mbps] */ 1859*4882a593Smuzhiyun u8 long_term_mbps_th_tbl[WMI_NUM_MCS]; 1860*4882a593Smuzhiyun u8 reserved1; 1861*4882a593Smuzhiyun /* Long term timeout threshold table [msec] */ 1862*4882a593Smuzhiyun __le16 long_term_trig_timeout_per_mcs[WMI_NUM_MCS]; 1863*4882a593Smuzhiyun u8 reserved2[2]; 1864*4882a593Smuzhiyun } __packed; 1865*4882a593Smuzhiyun 1866*4882a593Smuzhiyun /* BF configuration for each MCS */ 1867*4882a593Smuzhiyun struct wmi_bf_control_ex_mcs { 1868*4882a593Smuzhiyun /* Long term throughput threshold [Mbps] */ 1869*4882a593Smuzhiyun u8 long_term_mbps_th_tbl; 1870*4882a593Smuzhiyun u8 reserved; 1871*4882a593Smuzhiyun /* Long term timeout threshold table [msec] */ 1872*4882a593Smuzhiyun __le16 long_term_trig_timeout_per_mcs; 1873*4882a593Smuzhiyun } __packed; 1874*4882a593Smuzhiyun 1875*4882a593Smuzhiyun /* WMI_BF_CONTROL_EX_CMDID */ 1876*4882a593Smuzhiyun struct wmi_bf_control_ex_cmd { 1877*4882a593Smuzhiyun /* wmi_bf_triggers */ 1878*4882a593Smuzhiyun __le32 triggers; 1879*4882a593Smuzhiyun /* enum wmi_edmg_tx_mode */ 1880*4882a593Smuzhiyun u8 tx_mode; 1881*4882a593Smuzhiyun /* DISABLED = 0, ENABLED = 1 , DRY_RUN = 2 */ 1882*4882a593Smuzhiyun u8 txss_mode; 1883*4882a593Smuzhiyun /* DISABLED = 0, ENABLED = 1, DRY_RUN = 2 */ 1884*4882a593Smuzhiyun u8 brp_mode; 1885*4882a593Smuzhiyun /* Max cts threshold (correspond to 1886*4882a593Smuzhiyun * WMI_BF_TRIGGER_MAX_CTS_FAILURE_IN_TXOP) 1887*4882a593Smuzhiyun */ 1888*4882a593Smuzhiyun u8 bf_trigger_max_cts_failure_thr; 1889*4882a593Smuzhiyun /* Max cts threshold in dense (correspond to 1890*4882a593Smuzhiyun * WMI_BF_TRIGGER_MAX_CTS_FAILURE_IN_TXOP) 1891*4882a593Smuzhiyun */ 1892*4882a593Smuzhiyun u8 bf_trigger_max_cts_failure_dense_thr; 1893*4882a593Smuzhiyun /* Max b-ack threshold (correspond to 1894*4882a593Smuzhiyun * WMI_BF_TRIGGER_MAX_BACK_FAILURE) 1895*4882a593Smuzhiyun */ 1896*4882a593Smuzhiyun u8 bf_trigger_max_back_failure_thr; 1897*4882a593Smuzhiyun /* Max b-ack threshold in dense (correspond to 1898*4882a593Smuzhiyun * WMI_BF_TRIGGER_MAX_BACK_FAILURE) 1899*4882a593Smuzhiyun */ 1900*4882a593Smuzhiyun u8 bf_trigger_max_back_failure_dense_thr; 1901*4882a593Smuzhiyun u8 reserved0; 1902*4882a593Smuzhiyun /* Wrong sectors threshold */ 1903*4882a593Smuzhiyun __le32 wrong_sector_bis_thr; 1904*4882a593Smuzhiyun /* BOOL to enable/disable long term trigger */ 1905*4882a593Smuzhiyun u8 long_term_enable; 1906*4882a593Smuzhiyun /* 1 = Update long term thresholds from the long_term_mbps_th_tbl and 1907*4882a593Smuzhiyun * long_term_trig_timeout_per_mcs arrays, 0 = Ignore 1908*4882a593Smuzhiyun */ 1909*4882a593Smuzhiyun u8 long_term_update_thr; 1910*4882a593Smuzhiyun u8 each_mcs_cfg_size; 1911*4882a593Smuzhiyun u8 reserved1; 1912*4882a593Smuzhiyun /* Configuration for each MCS */ 1913*4882a593Smuzhiyun struct wmi_bf_control_ex_mcs each_mcs_cfg[]; 1914*4882a593Smuzhiyun } __packed; 1915*4882a593Smuzhiyun 1916*4882a593Smuzhiyun /* WMI_LINK_STATS_CMD */ 1917*4882a593Smuzhiyun enum wmi_link_stats_action { 1918*4882a593Smuzhiyun WMI_LINK_STATS_SNAPSHOT = 0x00, 1919*4882a593Smuzhiyun WMI_LINK_STATS_PERIODIC = 0x01, 1920*4882a593Smuzhiyun WMI_LINK_STATS_STOP_PERIODIC = 0x02, 1921*4882a593Smuzhiyun }; 1922*4882a593Smuzhiyun 1923*4882a593Smuzhiyun /* WMI_LINK_STATS_EVENT record identifiers */ 1924*4882a593Smuzhiyun enum wmi_link_stats_record_type { 1925*4882a593Smuzhiyun WMI_LINK_STATS_TYPE_BASIC = 0x01, 1926*4882a593Smuzhiyun WMI_LINK_STATS_TYPE_GLOBAL = 0x02, 1927*4882a593Smuzhiyun }; 1928*4882a593Smuzhiyun 1929*4882a593Smuzhiyun /* WMI_LINK_STATS_CMDID */ 1930*4882a593Smuzhiyun struct wmi_link_stats_cmd { 1931*4882a593Smuzhiyun /* bitmask of required record types 1932*4882a593Smuzhiyun * (wmi_link_stats_record_type_e) 1933*4882a593Smuzhiyun */ 1934*4882a593Smuzhiyun __le32 record_type_mask; 1935*4882a593Smuzhiyun /* 0xff for all cids */ 1936*4882a593Smuzhiyun u8 cid; 1937*4882a593Smuzhiyun /* wmi_link_stats_action_e */ 1938*4882a593Smuzhiyun u8 action; 1939*4882a593Smuzhiyun u8 reserved[6]; 1940*4882a593Smuzhiyun /* range = 100 - 10000 */ 1941*4882a593Smuzhiyun __le32 interval_msec; 1942*4882a593Smuzhiyun } __packed; 1943*4882a593Smuzhiyun 1944*4882a593Smuzhiyun /* WMI_SET_GRANT_MCS_CMDID */ 1945*4882a593Smuzhiyun struct wmi_set_grant_mcs_cmd { 1946*4882a593Smuzhiyun u8 mcs; 1947*4882a593Smuzhiyun u8 reserved[3]; 1948*4882a593Smuzhiyun } __packed; 1949*4882a593Smuzhiyun 1950*4882a593Smuzhiyun /* WMI_SET_AP_SLOT_SIZE_CMDID */ 1951*4882a593Smuzhiyun struct wmi_set_ap_slot_size_cmd { 1952*4882a593Smuzhiyun __le32 slot_size; 1953*4882a593Smuzhiyun } __packed; 1954*4882a593Smuzhiyun 1955*4882a593Smuzhiyun /* WMI_TEMP_SENSE_ALL_CMDID */ 1956*4882a593Smuzhiyun struct wmi_temp_sense_all_cmd { 1957*4882a593Smuzhiyun u8 measure_baseband_en; 1958*4882a593Smuzhiyun u8 measure_rf_en; 1959*4882a593Smuzhiyun u8 measure_mode; 1960*4882a593Smuzhiyun u8 reserved; 1961*4882a593Smuzhiyun } __packed; 1962*4882a593Smuzhiyun 1963*4882a593Smuzhiyun /* WMI Events 1964*4882a593Smuzhiyun * List of Events (target to host) 1965*4882a593Smuzhiyun */ 1966*4882a593Smuzhiyun enum wmi_event_id { 1967*4882a593Smuzhiyun WMI_READY_EVENTID = 0x1001, 1968*4882a593Smuzhiyun WMI_CONNECT_EVENTID = 0x1002, 1969*4882a593Smuzhiyun WMI_DISCONNECT_EVENTID = 0x1003, 1970*4882a593Smuzhiyun WMI_START_SCHED_SCAN_EVENTID = 0x1005, 1971*4882a593Smuzhiyun WMI_STOP_SCHED_SCAN_EVENTID = 0x1006, 1972*4882a593Smuzhiyun WMI_SCHED_SCAN_RESULT_EVENTID = 0x1007, 1973*4882a593Smuzhiyun WMI_SCAN_COMPLETE_EVENTID = 0x100A, 1974*4882a593Smuzhiyun WMI_REPORT_STATISTICS_EVENTID = 0x100B, 1975*4882a593Smuzhiyun WMI_FT_AUTH_STATUS_EVENTID = 0x100C, 1976*4882a593Smuzhiyun WMI_FT_REASSOC_STATUS_EVENTID = 0x100D, 1977*4882a593Smuzhiyun WMI_LINK_MONITOR_EVENTID = 0x100E, 1978*4882a593Smuzhiyun WMI_RADAR_GENERAL_CONFIG_EVENTID = 0x1100, 1979*4882a593Smuzhiyun WMI_RADAR_CONFIG_SELECT_EVENTID = 0x1101, 1980*4882a593Smuzhiyun WMI_RADAR_PARAMS_CONFIG_EVENTID = 0x1102, 1981*4882a593Smuzhiyun WMI_RADAR_SET_MODE_EVENTID = 0x1103, 1982*4882a593Smuzhiyun WMI_RADAR_CONTROL_EVENTID = 0x1104, 1983*4882a593Smuzhiyun WMI_RADAR_PCI_CONTROL_EVENTID = 0x1105, 1984*4882a593Smuzhiyun WMI_RD_MEM_RSP_EVENTID = 0x1800, 1985*4882a593Smuzhiyun WMI_FW_READY_EVENTID = 0x1801, 1986*4882a593Smuzhiyun WMI_EXIT_FAST_MEM_ACC_MODE_EVENTID = 0x200, 1987*4882a593Smuzhiyun WMI_ECHO_RSP_EVENTID = 0x1803, 1988*4882a593Smuzhiyun WMI_DEEP_ECHO_RSP_EVENTID = 0x1804, 1989*4882a593Smuzhiyun /* deprecated */ 1990*4882a593Smuzhiyun WMI_FS_TUNE_DONE_EVENTID = 0x180A, 1991*4882a593Smuzhiyun /* deprecated */ 1992*4882a593Smuzhiyun WMI_CORR_MEASURE_EVENTID = 0x180B, 1993*4882a593Smuzhiyun WMI_READ_RSSI_EVENTID = 0x180C, 1994*4882a593Smuzhiyun WMI_TEMP_SENSE_DONE_EVENTID = 0x180E, 1995*4882a593Smuzhiyun WMI_DC_CALIB_DONE_EVENTID = 0x180F, 1996*4882a593Smuzhiyun /* deprecated */ 1997*4882a593Smuzhiyun WMI_IQ_TX_CALIB_DONE_EVENTID = 0x1811, 1998*4882a593Smuzhiyun /* deprecated */ 1999*4882a593Smuzhiyun WMI_IQ_RX_CALIB_DONE_EVENTID = 0x1812, 2000*4882a593Smuzhiyun WMI_SET_WORK_MODE_DONE_EVENTID = 0x1815, 2001*4882a593Smuzhiyun WMI_LO_LEAKAGE_CALIB_DONE_EVENTID = 0x1816, 2002*4882a593Smuzhiyun WMI_LO_POWER_CALIB_FROM_OTP_EVENTID = 0x1817, 2003*4882a593Smuzhiyun WMI_SILENT_RSSI_CALIB_DONE_EVENTID = 0x181D, 2004*4882a593Smuzhiyun /* deprecated */ 2005*4882a593Smuzhiyun WMI_RF_RX_TEST_DONE_EVENTID = 0x181E, 2006*4882a593Smuzhiyun WMI_CFG_RX_CHAIN_DONE_EVENTID = 0x1820, 2007*4882a593Smuzhiyun WMI_VRING_CFG_DONE_EVENTID = 0x1821, 2008*4882a593Smuzhiyun WMI_BA_STATUS_EVENTID = 0x1823, 2009*4882a593Smuzhiyun WMI_RCP_ADDBA_REQ_EVENTID = 0x1824, 2010*4882a593Smuzhiyun WMI_RCP_ADDBA_RESP_SENT_EVENTID = 0x1825, 2011*4882a593Smuzhiyun WMI_DELBA_EVENTID = 0x1826, 2012*4882a593Smuzhiyun WMI_GET_SSID_EVENTID = 0x1828, 2013*4882a593Smuzhiyun WMI_GET_PCP_CHANNEL_EVENTID = 0x182A, 2014*4882a593Smuzhiyun /* Event is shared between WMI_SW_TX_REQ_CMDID and 2015*4882a593Smuzhiyun * WMI_SW_TX_REQ_EXT_CMDID 2016*4882a593Smuzhiyun */ 2017*4882a593Smuzhiyun WMI_SW_TX_COMPLETE_EVENTID = 0x182B, 2018*4882a593Smuzhiyun WMI_BEAMFORMING_MGMT_DONE_EVENTID = 0x1836, 2019*4882a593Smuzhiyun WMI_BF_TXSS_MGMT_DONE_EVENTID = 0x1837, 2020*4882a593Smuzhiyun WMI_BF_RXSS_MGMT_DONE_EVENTID = 0x1839, 2021*4882a593Smuzhiyun WMI_BF_TRIG_EVENTID = 0x183A, 2022*4882a593Smuzhiyun WMI_RS_MGMT_DONE_EVENTID = 0x1852, 2023*4882a593Smuzhiyun WMI_RF_MGMT_STATUS_EVENTID = 0x1853, 2024*4882a593Smuzhiyun WMI_BF_SM_MGMT_DONE_EVENTID = 0x1838, 2025*4882a593Smuzhiyun WMI_RX_MGMT_PACKET_EVENTID = 0x1840, 2026*4882a593Smuzhiyun WMI_TX_MGMT_PACKET_EVENTID = 0x1841, 2027*4882a593Smuzhiyun WMI_LINK_MAINTAIN_CFG_WRITE_DONE_EVENTID = 0x1842, 2028*4882a593Smuzhiyun WMI_LINK_MAINTAIN_CFG_READ_DONE_EVENTID = 0x1843, 2029*4882a593Smuzhiyun WMI_SET_LINK_MONITOR_EVENTID = 0x1845, 2030*4882a593Smuzhiyun WMI_RF_XPM_READ_RESULT_EVENTID = 0x1856, 2031*4882a593Smuzhiyun WMI_RF_XPM_WRITE_RESULT_EVENTID = 0x1857, 2032*4882a593Smuzhiyun WMI_LED_CFG_DONE_EVENTID = 0x1858, 2033*4882a593Smuzhiyun WMI_SET_SILENT_RSSI_TABLE_DONE_EVENTID = 0x185C, 2034*4882a593Smuzhiyun WMI_RF_PWR_ON_DELAY_RSP_EVENTID = 0x185D, 2035*4882a593Smuzhiyun WMI_SET_HIGH_POWER_TABLE_PARAMS_EVENTID = 0x185E, 2036*4882a593Smuzhiyun WMI_FIXED_SCHEDULING_UL_CONFIG_EVENTID = 0x185F, 2037*4882a593Smuzhiyun /* Performance monitoring events */ 2038*4882a593Smuzhiyun WMI_DATA_PORT_OPEN_EVENTID = 0x1860, 2039*4882a593Smuzhiyun WMI_WBE_LINK_DOWN_EVENTID = 0x1861, 2040*4882a593Smuzhiyun WMI_BF_CTRL_DONE_EVENTID = 0x1862, 2041*4882a593Smuzhiyun WMI_NOTIFY_REQ_DONE_EVENTID = 0x1863, 2042*4882a593Smuzhiyun WMI_GET_STATUS_DONE_EVENTID = 0x1864, 2043*4882a593Smuzhiyun WMI_RING_EN_EVENTID = 0x1865, 2044*4882a593Smuzhiyun WMI_GET_RF_STATUS_EVENTID = 0x1866, 2045*4882a593Smuzhiyun WMI_GET_BASEBAND_TYPE_EVENTID = 0x1867, 2046*4882a593Smuzhiyun WMI_VRING_SWITCH_TIMING_CONFIG_EVENTID = 0x1868, 2047*4882a593Smuzhiyun WMI_UNIT_TEST_EVENTID = 0x1900, 2048*4882a593Smuzhiyun WMI_FLASH_READ_DONE_EVENTID = 0x1902, 2049*4882a593Smuzhiyun WMI_FLASH_WRITE_DONE_EVENTID = 0x1903, 2050*4882a593Smuzhiyun /* Power management */ 2051*4882a593Smuzhiyun WMI_TRAFFIC_SUSPEND_EVENTID = 0x1904, 2052*4882a593Smuzhiyun WMI_TRAFFIC_RESUME_EVENTID = 0x1905, 2053*4882a593Smuzhiyun /* P2P */ 2054*4882a593Smuzhiyun WMI_P2P_CFG_DONE_EVENTID = 0x1910, 2055*4882a593Smuzhiyun WMI_PORT_ALLOCATED_EVENTID = 0x1911, 2056*4882a593Smuzhiyun WMI_PORT_DELETED_EVENTID = 0x1912, 2057*4882a593Smuzhiyun WMI_LISTEN_STARTED_EVENTID = 0x1914, 2058*4882a593Smuzhiyun WMI_SEARCH_STARTED_EVENTID = 0x1915, 2059*4882a593Smuzhiyun WMI_DISCOVERY_STARTED_EVENTID = 0x1916, 2060*4882a593Smuzhiyun WMI_DISCOVERY_STOPPED_EVENTID = 0x1917, 2061*4882a593Smuzhiyun WMI_PCP_STARTED_EVENTID = 0x1918, 2062*4882a593Smuzhiyun WMI_PCP_STOPPED_EVENTID = 0x1919, 2063*4882a593Smuzhiyun WMI_PCP_FACTOR_EVENTID = 0x191A, 2064*4882a593Smuzhiyun /* Power Save Configuration Events */ 2065*4882a593Smuzhiyun WMI_PS_DEV_PROFILE_CFG_EVENTID = 0x191C, 2066*4882a593Smuzhiyun WMI_RS_ENABLE_EVENTID = 0x191E, 2067*4882a593Smuzhiyun WMI_RS_CFG_EX_EVENTID = 0x191F, 2068*4882a593Smuzhiyun WMI_GET_DETAILED_RS_RES_EX_EVENTID = 0x1920, 2069*4882a593Smuzhiyun /* deprecated */ 2070*4882a593Smuzhiyun WMI_RS_CFG_DONE_EVENTID = 0x1921, 2071*4882a593Smuzhiyun /* deprecated */ 2072*4882a593Smuzhiyun WMI_GET_DETAILED_RS_RES_EVENTID = 0x1922, 2073*4882a593Smuzhiyun WMI_AOA_MEAS_EVENTID = 0x1923, 2074*4882a593Smuzhiyun WMI_BRP_SET_ANT_LIMIT_EVENTID = 0x1924, 2075*4882a593Smuzhiyun WMI_SET_MGMT_RETRY_LIMIT_EVENTID = 0x1930, 2076*4882a593Smuzhiyun WMI_GET_MGMT_RETRY_LIMIT_EVENTID = 0x1931, 2077*4882a593Smuzhiyun WMI_SET_THERMAL_THROTTLING_CFG_EVENTID = 0x1940, 2078*4882a593Smuzhiyun WMI_GET_THERMAL_THROTTLING_CFG_EVENTID = 0x1941, 2079*4882a593Smuzhiyun /* return the Power Save profile */ 2080*4882a593Smuzhiyun WMI_PS_DEV_PROFILE_CFG_READ_EVENTID = 0x1942, 2081*4882a593Smuzhiyun WMI_TSF_SYNC_STATUS_EVENTID = 0x1973, 2082*4882a593Smuzhiyun WMI_TOF_SESSION_END_EVENTID = 0x1991, 2083*4882a593Smuzhiyun WMI_TOF_GET_CAPABILITIES_EVENTID = 0x1992, 2084*4882a593Smuzhiyun WMI_TOF_SET_LCR_EVENTID = 0x1993, 2085*4882a593Smuzhiyun WMI_TOF_SET_LCI_EVENTID = 0x1994, 2086*4882a593Smuzhiyun WMI_TOF_FTM_PER_DEST_RES_EVENTID = 0x1995, 2087*4882a593Smuzhiyun WMI_TOF_CFG_RESPONDER_EVENTID = 0x1996, 2088*4882a593Smuzhiyun WMI_TOF_SET_TX_RX_OFFSET_EVENTID = 0x1997, 2089*4882a593Smuzhiyun WMI_TOF_GET_TX_RX_OFFSET_EVENTID = 0x1998, 2090*4882a593Smuzhiyun WMI_TOF_CHANNEL_INFO_EVENTID = 0x1999, 2091*4882a593Smuzhiyun WMI_GET_RF_SECTOR_PARAMS_DONE_EVENTID = 0x19A0, 2092*4882a593Smuzhiyun WMI_SET_RF_SECTOR_PARAMS_DONE_EVENTID = 0x19A1, 2093*4882a593Smuzhiyun WMI_GET_SELECTED_RF_SECTOR_INDEX_DONE_EVENTID = 0x19A2, 2094*4882a593Smuzhiyun WMI_SET_SELECTED_RF_SECTOR_INDEX_DONE_EVENTID = 0x19A3, 2095*4882a593Smuzhiyun WMI_SET_RF_SECTOR_ON_DONE_EVENTID = 0x19A4, 2096*4882a593Smuzhiyun WMI_PRIO_TX_SECTORS_ORDER_EVENTID = 0x19A5, 2097*4882a593Smuzhiyun WMI_PRIO_TX_SECTORS_NUMBER_EVENTID = 0x19A6, 2098*4882a593Smuzhiyun WMI_PRIO_TX_SECTORS_SET_DEFAULT_CFG_EVENTID = 0x19A7, 2099*4882a593Smuzhiyun /* deprecated */ 2100*4882a593Smuzhiyun WMI_BF_CONTROL_EVENTID = 0x19AA, 2101*4882a593Smuzhiyun WMI_BF_CONTROL_EX_EVENTID = 0x19AB, 2102*4882a593Smuzhiyun WMI_TX_STATUS_RING_CFG_DONE_EVENTID = 0x19C0, 2103*4882a593Smuzhiyun WMI_RX_STATUS_RING_CFG_DONE_EVENTID = 0x19C1, 2104*4882a593Smuzhiyun WMI_TX_DESC_RING_CFG_DONE_EVENTID = 0x19C2, 2105*4882a593Smuzhiyun WMI_RX_DESC_RING_CFG_DONE_EVENTID = 0x19C3, 2106*4882a593Smuzhiyun WMI_CFG_DEF_RX_OFFLOAD_DONE_EVENTID = 0x19C5, 2107*4882a593Smuzhiyun WMI_SCHEDULING_SCHEME_EVENTID = 0x1A01, 2108*4882a593Smuzhiyun WMI_FIXED_SCHEDULING_CONFIG_COMPLETE_EVENTID = 0x1A02, 2109*4882a593Smuzhiyun WMI_ENABLE_FIXED_SCHEDULING_COMPLETE_EVENTID = 0x1A03, 2110*4882a593Smuzhiyun WMI_SET_MULTI_DIRECTED_OMNIS_CONFIG_EVENTID = 0x1A04, 2111*4882a593Smuzhiyun WMI_SET_LONG_RANGE_CONFIG_COMPLETE_EVENTID = 0x1A05, 2112*4882a593Smuzhiyun WMI_GET_ASSOC_LIST_RES_EVENTID = 0x1A06, 2113*4882a593Smuzhiyun WMI_GET_CCA_INDICATIONS_EVENTID = 0x1A07, 2114*4882a593Smuzhiyun WMI_SET_CCA_INDICATIONS_BI_AVG_NUM_EVENTID = 0x1A08, 2115*4882a593Smuzhiyun WMI_INTERNAL_FW_EVENT_EVENTID = 0x1A0A, 2116*4882a593Smuzhiyun WMI_INTERNAL_FW_IOCTL_EVENTID = 0x1A0B, 2117*4882a593Smuzhiyun WMI_LINK_STATS_CONFIG_DONE_EVENTID = 0x1A0C, 2118*4882a593Smuzhiyun WMI_LINK_STATS_EVENTID = 0x1A0D, 2119*4882a593Smuzhiyun WMI_SET_GRANT_MCS_EVENTID = 0x1A0E, 2120*4882a593Smuzhiyun WMI_SET_AP_SLOT_SIZE_EVENTID = 0x1A0F, 2121*4882a593Smuzhiyun WMI_SET_VRING_PRIORITY_WEIGHT_EVENTID = 0x1A10, 2122*4882a593Smuzhiyun WMI_SET_VRING_PRIORITY_EVENTID = 0x1A11, 2123*4882a593Smuzhiyun WMI_RBUFCAP_CFG_EVENTID = 0x1A12, 2124*4882a593Smuzhiyun WMI_TEMP_SENSE_ALL_DONE_EVENTID = 0x1A13, 2125*4882a593Smuzhiyun WMI_SET_CHANNEL_EVENTID = 0x9000, 2126*4882a593Smuzhiyun WMI_ASSOC_REQ_EVENTID = 0x9001, 2127*4882a593Smuzhiyun WMI_EAPOL_RX_EVENTID = 0x9002, 2128*4882a593Smuzhiyun WMI_MAC_ADDR_RESP_EVENTID = 0x9003, 2129*4882a593Smuzhiyun WMI_FW_VER_EVENTID = 0x9004, 2130*4882a593Smuzhiyun WMI_ACS_PASSIVE_SCAN_COMPLETE_EVENTID = 0x9005, 2131*4882a593Smuzhiyun WMI_INTERNAL_FW_SET_CHANNEL = 0x9006, 2132*4882a593Smuzhiyun WMI_COMMAND_NOT_SUPPORTED_EVENTID = 0xFFFF, 2133*4882a593Smuzhiyun }; 2134*4882a593Smuzhiyun 2135*4882a593Smuzhiyun /* Events data structures */ 2136*4882a593Smuzhiyun enum wmi_fw_status { 2137*4882a593Smuzhiyun WMI_FW_STATUS_SUCCESS = 0x00, 2138*4882a593Smuzhiyun WMI_FW_STATUS_FAILURE = 0x01, 2139*4882a593Smuzhiyun }; 2140*4882a593Smuzhiyun 2141*4882a593Smuzhiyun /* WMI_RF_MGMT_STATUS_EVENTID */ 2142*4882a593Smuzhiyun enum wmi_rf_status { 2143*4882a593Smuzhiyun WMI_RF_ENABLED = 0x00, 2144*4882a593Smuzhiyun WMI_RF_DISABLED_HW = 0x01, 2145*4882a593Smuzhiyun WMI_RF_DISABLED_SW = 0x02, 2146*4882a593Smuzhiyun WMI_RF_DISABLED_HW_SW = 0x03, 2147*4882a593Smuzhiyun }; 2148*4882a593Smuzhiyun 2149*4882a593Smuzhiyun /* WMI_RF_MGMT_STATUS_EVENTID */ 2150*4882a593Smuzhiyun struct wmi_rf_mgmt_status_event { 2151*4882a593Smuzhiyun __le32 rf_status; 2152*4882a593Smuzhiyun } __packed; 2153*4882a593Smuzhiyun 2154*4882a593Smuzhiyun /* WMI_GET_STATUS_DONE_EVENTID */ 2155*4882a593Smuzhiyun struct wmi_get_status_done_event { 2156*4882a593Smuzhiyun __le32 is_associated; 2157*4882a593Smuzhiyun u8 cid; 2158*4882a593Smuzhiyun u8 reserved0[3]; 2159*4882a593Smuzhiyun u8 bssid[WMI_MAC_LEN]; 2160*4882a593Smuzhiyun u8 channel; 2161*4882a593Smuzhiyun u8 reserved1; 2162*4882a593Smuzhiyun u8 network_type; 2163*4882a593Smuzhiyun u8 reserved2[3]; 2164*4882a593Smuzhiyun __le32 ssid_len; 2165*4882a593Smuzhiyun u8 ssid[WMI_MAX_SSID_LEN]; 2166*4882a593Smuzhiyun __le32 rf_status; 2167*4882a593Smuzhiyun __le32 is_secured; 2168*4882a593Smuzhiyun } __packed; 2169*4882a593Smuzhiyun 2170*4882a593Smuzhiyun /* WMI_FW_VER_EVENTID */ 2171*4882a593Smuzhiyun struct wmi_fw_ver_event { 2172*4882a593Smuzhiyun /* FW image version */ 2173*4882a593Smuzhiyun __le32 fw_major; 2174*4882a593Smuzhiyun __le32 fw_minor; 2175*4882a593Smuzhiyun __le32 fw_subminor; 2176*4882a593Smuzhiyun __le32 fw_build; 2177*4882a593Smuzhiyun /* FW image build time stamp */ 2178*4882a593Smuzhiyun __le32 hour; 2179*4882a593Smuzhiyun __le32 minute; 2180*4882a593Smuzhiyun __le32 second; 2181*4882a593Smuzhiyun __le32 day; 2182*4882a593Smuzhiyun __le32 month; 2183*4882a593Smuzhiyun __le32 year; 2184*4882a593Smuzhiyun /* Boot Loader image version */ 2185*4882a593Smuzhiyun __le32 bl_major; 2186*4882a593Smuzhiyun __le32 bl_minor; 2187*4882a593Smuzhiyun __le32 bl_subminor; 2188*4882a593Smuzhiyun __le32 bl_build; 2189*4882a593Smuzhiyun /* The number of entries in the FW capabilities array */ 2190*4882a593Smuzhiyun u8 fw_capabilities_len; 2191*4882a593Smuzhiyun u8 reserved[3]; 2192*4882a593Smuzhiyun /* FW capabilities info 2193*4882a593Smuzhiyun * Must be the last member of the struct 2194*4882a593Smuzhiyun */ 2195*4882a593Smuzhiyun __le32 fw_capabilities[]; 2196*4882a593Smuzhiyun } __packed; 2197*4882a593Smuzhiyun 2198*4882a593Smuzhiyun /* WMI_GET_RF_STATUS_EVENTID */ 2199*4882a593Smuzhiyun enum rf_type { 2200*4882a593Smuzhiyun RF_UNKNOWN = 0x00, 2201*4882a593Smuzhiyun RF_MARLON = 0x01, 2202*4882a593Smuzhiyun RF_SPARROW = 0x02, 2203*4882a593Smuzhiyun RF_TALYNA1 = 0x03, 2204*4882a593Smuzhiyun RF_TALYNA2 = 0x04, 2205*4882a593Smuzhiyun }; 2206*4882a593Smuzhiyun 2207*4882a593Smuzhiyun /* WMI_GET_RF_STATUS_EVENTID */ 2208*4882a593Smuzhiyun enum board_file_rf_type { 2209*4882a593Smuzhiyun BF_RF_MARLON = 0x00, 2210*4882a593Smuzhiyun BF_RF_SPARROW = 0x01, 2211*4882a593Smuzhiyun BF_RF_TALYNA1 = 0x02, 2212*4882a593Smuzhiyun BF_RF_TALYNA2 = 0x03, 2213*4882a593Smuzhiyun }; 2214*4882a593Smuzhiyun 2215*4882a593Smuzhiyun /* WMI_GET_RF_STATUS_EVENTID */ 2216*4882a593Smuzhiyun enum rf_status { 2217*4882a593Smuzhiyun RF_OK = 0x00, 2218*4882a593Smuzhiyun RF_NO_COMM = 0x01, 2219*4882a593Smuzhiyun RF_WRONG_BOARD_FILE = 0x02, 2220*4882a593Smuzhiyun }; 2221*4882a593Smuzhiyun 2222*4882a593Smuzhiyun /* WMI_GET_RF_STATUS_EVENTID */ 2223*4882a593Smuzhiyun struct wmi_get_rf_status_event { 2224*4882a593Smuzhiyun /* enum rf_type */ 2225*4882a593Smuzhiyun __le32 rf_type; 2226*4882a593Smuzhiyun /* attached RFs bit vector */ 2227*4882a593Smuzhiyun __le32 attached_rf_vector; 2228*4882a593Smuzhiyun /* enabled RFs bit vector */ 2229*4882a593Smuzhiyun __le32 enabled_rf_vector; 2230*4882a593Smuzhiyun /* enum rf_status, refers to enabled RFs */ 2231*4882a593Smuzhiyun u8 rf_status[32]; 2232*4882a593Smuzhiyun /* enum board file RF type */ 2233*4882a593Smuzhiyun __le32 board_file_rf_type; 2234*4882a593Smuzhiyun /* board file platform type */ 2235*4882a593Smuzhiyun __le32 board_file_platform_type; 2236*4882a593Smuzhiyun /* board file version */ 2237*4882a593Smuzhiyun __le32 board_file_version; 2238*4882a593Smuzhiyun /* enabled XIFs bit vector */ 2239*4882a593Smuzhiyun __le32 enabled_xif_vector; 2240*4882a593Smuzhiyun __le32 reserved; 2241*4882a593Smuzhiyun } __packed; 2242*4882a593Smuzhiyun 2243*4882a593Smuzhiyun /* WMI_GET_BASEBAND_TYPE_EVENTID */ 2244*4882a593Smuzhiyun enum baseband_type { 2245*4882a593Smuzhiyun BASEBAND_UNKNOWN = 0x00, 2246*4882a593Smuzhiyun BASEBAND_SPARROW_M_A0 = 0x03, 2247*4882a593Smuzhiyun BASEBAND_SPARROW_M_A1 = 0x04, 2248*4882a593Smuzhiyun BASEBAND_SPARROW_M_B0 = 0x05, 2249*4882a593Smuzhiyun BASEBAND_SPARROW_M_C0 = 0x06, 2250*4882a593Smuzhiyun BASEBAND_SPARROW_M_D0 = 0x07, 2251*4882a593Smuzhiyun BASEBAND_TALYN_M_A0 = 0x08, 2252*4882a593Smuzhiyun BASEBAND_TALYN_M_B0 = 0x09, 2253*4882a593Smuzhiyun }; 2254*4882a593Smuzhiyun 2255*4882a593Smuzhiyun /* WMI_GET_BASEBAND_TYPE_EVENTID */ 2256*4882a593Smuzhiyun struct wmi_get_baseband_type_event { 2257*4882a593Smuzhiyun /* enum baseband_type */ 2258*4882a593Smuzhiyun __le32 baseband_type; 2259*4882a593Smuzhiyun } __packed; 2260*4882a593Smuzhiyun 2261*4882a593Smuzhiyun /* WMI_MAC_ADDR_RESP_EVENTID */ 2262*4882a593Smuzhiyun struct wmi_mac_addr_resp_event { 2263*4882a593Smuzhiyun u8 mac[WMI_MAC_LEN]; 2264*4882a593Smuzhiyun u8 auth_mode; 2265*4882a593Smuzhiyun u8 crypt_mode; 2266*4882a593Smuzhiyun __le32 offload_mode; 2267*4882a593Smuzhiyun } __packed; 2268*4882a593Smuzhiyun 2269*4882a593Smuzhiyun /* WMI_EAPOL_RX_EVENTID */ 2270*4882a593Smuzhiyun struct wmi_eapol_rx_event { 2271*4882a593Smuzhiyun u8 src_mac[WMI_MAC_LEN]; 2272*4882a593Smuzhiyun __le16 eapol_len; 2273*4882a593Smuzhiyun u8 eapol[]; 2274*4882a593Smuzhiyun } __packed; 2275*4882a593Smuzhiyun 2276*4882a593Smuzhiyun /* WMI_READY_EVENTID */ 2277*4882a593Smuzhiyun enum wmi_phy_capability { 2278*4882a593Smuzhiyun WMI_11A_CAPABILITY = 0x01, 2279*4882a593Smuzhiyun WMI_11G_CAPABILITY = 0x02, 2280*4882a593Smuzhiyun WMI_11AG_CAPABILITY = 0x03, 2281*4882a593Smuzhiyun WMI_11NA_CAPABILITY = 0x04, 2282*4882a593Smuzhiyun WMI_11NG_CAPABILITY = 0x05, 2283*4882a593Smuzhiyun WMI_11NAG_CAPABILITY = 0x06, 2284*4882a593Smuzhiyun WMI_11AD_CAPABILITY = 0x07, 2285*4882a593Smuzhiyun WMI_11N_CAPABILITY_OFFSET = 0x03, 2286*4882a593Smuzhiyun }; 2287*4882a593Smuzhiyun 2288*4882a593Smuzhiyun struct wmi_ready_event { 2289*4882a593Smuzhiyun __le32 sw_version; 2290*4882a593Smuzhiyun __le32 abi_version; 2291*4882a593Smuzhiyun u8 mac[WMI_MAC_LEN]; 2292*4882a593Smuzhiyun /* enum wmi_phy_capability */ 2293*4882a593Smuzhiyun u8 phy_capability; 2294*4882a593Smuzhiyun u8 numof_additional_mids; 2295*4882a593Smuzhiyun /* rfc read calibration result. 5..15 */ 2296*4882a593Smuzhiyun u8 rfc_read_calib_result; 2297*4882a593Smuzhiyun /* Max associated STAs supported by FW in AP mode (default 0 means 8 2298*4882a593Smuzhiyun * STA) 2299*4882a593Smuzhiyun */ 2300*4882a593Smuzhiyun u8 max_assoc_sta; 2301*4882a593Smuzhiyun u8 reserved[2]; 2302*4882a593Smuzhiyun } __packed; 2303*4882a593Smuzhiyun 2304*4882a593Smuzhiyun /* WMI_NOTIFY_REQ_DONE_EVENTID */ 2305*4882a593Smuzhiyun struct wmi_notify_req_done_event { 2306*4882a593Smuzhiyun /* beamforming status, 0: fail; 1: OK; 2: retrying */ 2307*4882a593Smuzhiyun __le32 status; 2308*4882a593Smuzhiyun __le64 tsf; 2309*4882a593Smuzhiyun s8 rssi; 2310*4882a593Smuzhiyun /* enum wmi_edmg_tx_mode */ 2311*4882a593Smuzhiyun u8 tx_mode; 2312*4882a593Smuzhiyun u8 reserved0[2]; 2313*4882a593Smuzhiyun __le32 tx_tpt; 2314*4882a593Smuzhiyun __le32 tx_goodput; 2315*4882a593Smuzhiyun __le32 rx_goodput; 2316*4882a593Smuzhiyun __le16 bf_mcs; 2317*4882a593Smuzhiyun __le16 my_rx_sector; 2318*4882a593Smuzhiyun __le16 my_tx_sector; 2319*4882a593Smuzhiyun __le16 other_rx_sector; 2320*4882a593Smuzhiyun __le16 other_tx_sector; 2321*4882a593Smuzhiyun __le16 range; 2322*4882a593Smuzhiyun u8 sqi; 2323*4882a593Smuzhiyun u8 reserved[3]; 2324*4882a593Smuzhiyun } __packed; 2325*4882a593Smuzhiyun 2326*4882a593Smuzhiyun /* WMI_CONNECT_EVENTID */ 2327*4882a593Smuzhiyun struct wmi_connect_event { 2328*4882a593Smuzhiyun /* enum wmi_channel WMI_CHANNEL_1..WMI_CHANNEL_6; for EDMG this is 2329*4882a593Smuzhiyun * the primary channel number 2330*4882a593Smuzhiyun */ 2331*4882a593Smuzhiyun u8 channel; 2332*4882a593Smuzhiyun /* enum wmi_channel WMI_CHANNEL_9..WMI_CHANNEL_12 */ 2333*4882a593Smuzhiyun u8 edmg_channel; 2334*4882a593Smuzhiyun u8 bssid[WMI_MAC_LEN]; 2335*4882a593Smuzhiyun __le16 listen_interval; 2336*4882a593Smuzhiyun __le16 beacon_interval; 2337*4882a593Smuzhiyun u8 network_type; 2338*4882a593Smuzhiyun u8 reserved1[3]; 2339*4882a593Smuzhiyun u8 beacon_ie_len; 2340*4882a593Smuzhiyun u8 assoc_req_len; 2341*4882a593Smuzhiyun u8 assoc_resp_len; 2342*4882a593Smuzhiyun u8 cid; 2343*4882a593Smuzhiyun u8 aid; 2344*4882a593Smuzhiyun u8 reserved2[2]; 2345*4882a593Smuzhiyun /* not in use */ 2346*4882a593Smuzhiyun u8 assoc_info[]; 2347*4882a593Smuzhiyun } __packed; 2348*4882a593Smuzhiyun 2349*4882a593Smuzhiyun /* disconnect_reason */ 2350*4882a593Smuzhiyun enum wmi_disconnect_reason { 2351*4882a593Smuzhiyun WMI_DIS_REASON_NO_NETWORK_AVAIL = 0x01, 2352*4882a593Smuzhiyun /* bmiss */ 2353*4882a593Smuzhiyun WMI_DIS_REASON_LOST_LINK = 0x02, 2354*4882a593Smuzhiyun WMI_DIS_REASON_DISCONNECT_CMD = 0x03, 2355*4882a593Smuzhiyun WMI_DIS_REASON_BSS_DISCONNECTED = 0x04, 2356*4882a593Smuzhiyun WMI_DIS_REASON_AUTH_FAILED = 0x05, 2357*4882a593Smuzhiyun WMI_DIS_REASON_ASSOC_FAILED = 0x06, 2358*4882a593Smuzhiyun WMI_DIS_REASON_NO_RESOURCES_AVAIL = 0x07, 2359*4882a593Smuzhiyun WMI_DIS_REASON_CSERV_DISCONNECT = 0x08, 2360*4882a593Smuzhiyun WMI_DIS_REASON_INVALID_PROFILE = 0x0A, 2361*4882a593Smuzhiyun WMI_DIS_REASON_DOT11H_CHANNEL_SWITCH = 0x0B, 2362*4882a593Smuzhiyun WMI_DIS_REASON_PROFILE_MISMATCH = 0x0C, 2363*4882a593Smuzhiyun WMI_DIS_REASON_CONNECTION_EVICTED = 0x0D, 2364*4882a593Smuzhiyun WMI_DIS_REASON_IBSS_MERGE = 0x0E, 2365*4882a593Smuzhiyun WMI_DIS_REASON_HIGH_TEMPERATURE = 0x0F, 2366*4882a593Smuzhiyun }; 2367*4882a593Smuzhiyun 2368*4882a593Smuzhiyun /* WMI_DISCONNECT_EVENTID */ 2369*4882a593Smuzhiyun struct wmi_disconnect_event { 2370*4882a593Smuzhiyun /* reason code, see 802.11 spec. */ 2371*4882a593Smuzhiyun __le16 protocol_reason_status; 2372*4882a593Smuzhiyun /* set if known */ 2373*4882a593Smuzhiyun u8 bssid[WMI_MAC_LEN]; 2374*4882a593Smuzhiyun /* see enum wmi_disconnect_reason */ 2375*4882a593Smuzhiyun u8 disconnect_reason; 2376*4882a593Smuzhiyun /* last assoc req may passed to host - not in used */ 2377*4882a593Smuzhiyun u8 assoc_resp_len; 2378*4882a593Smuzhiyun /* last assoc req may passed to host - not in used */ 2379*4882a593Smuzhiyun u8 assoc_info[]; 2380*4882a593Smuzhiyun } __packed; 2381*4882a593Smuzhiyun 2382*4882a593Smuzhiyun /* WMI_SCAN_COMPLETE_EVENTID */ 2383*4882a593Smuzhiyun enum scan_status { 2384*4882a593Smuzhiyun WMI_SCAN_SUCCESS = 0x00, 2385*4882a593Smuzhiyun WMI_SCAN_FAILED = 0x01, 2386*4882a593Smuzhiyun WMI_SCAN_ABORTED = 0x02, 2387*4882a593Smuzhiyun WMI_SCAN_REJECTED = 0x03, 2388*4882a593Smuzhiyun WMI_SCAN_ABORT_REJECTED = 0x04, 2389*4882a593Smuzhiyun }; 2390*4882a593Smuzhiyun 2391*4882a593Smuzhiyun struct wmi_scan_complete_event { 2392*4882a593Smuzhiyun /* enum scan_status */ 2393*4882a593Smuzhiyun __le32 status; 2394*4882a593Smuzhiyun } __packed; 2395*4882a593Smuzhiyun 2396*4882a593Smuzhiyun /* WMI_FT_AUTH_STATUS_EVENTID */ 2397*4882a593Smuzhiyun struct wmi_ft_auth_status_event { 2398*4882a593Smuzhiyun /* enum wmi_fw_status */ 2399*4882a593Smuzhiyun u8 status; 2400*4882a593Smuzhiyun u8 reserved[3]; 2401*4882a593Smuzhiyun u8 mac_addr[WMI_MAC_LEN]; 2402*4882a593Smuzhiyun __le16 ie_len; 2403*4882a593Smuzhiyun u8 ie_info[]; 2404*4882a593Smuzhiyun } __packed; 2405*4882a593Smuzhiyun 2406*4882a593Smuzhiyun /* WMI_FT_REASSOC_STATUS_EVENTID */ 2407*4882a593Smuzhiyun struct wmi_ft_reassoc_status_event { 2408*4882a593Smuzhiyun /* enum wmi_fw_status */ 2409*4882a593Smuzhiyun u8 status; 2410*4882a593Smuzhiyun /* association id received from new AP */ 2411*4882a593Smuzhiyun u8 aid; 2412*4882a593Smuzhiyun /* enum wmi_channel */ 2413*4882a593Smuzhiyun u8 channel; 2414*4882a593Smuzhiyun /* enum wmi_channel */ 2415*4882a593Smuzhiyun u8 edmg_channel; 2416*4882a593Smuzhiyun u8 mac_addr[WMI_MAC_LEN]; 2417*4882a593Smuzhiyun __le16 beacon_ie_len; 2418*4882a593Smuzhiyun __le16 reassoc_req_ie_len; 2419*4882a593Smuzhiyun __le16 reassoc_resp_ie_len; 2420*4882a593Smuzhiyun u8 reserved[4]; 2421*4882a593Smuzhiyun u8 ie_info[]; 2422*4882a593Smuzhiyun } __packed; 2423*4882a593Smuzhiyun 2424*4882a593Smuzhiyun /* wmi_rx_mgmt_info */ 2425*4882a593Smuzhiyun struct wmi_rx_mgmt_info { 2426*4882a593Smuzhiyun u8 mcs; 2427*4882a593Smuzhiyun s8 rssi; 2428*4882a593Smuzhiyun u8 range; 2429*4882a593Smuzhiyun u8 sqi; 2430*4882a593Smuzhiyun __le16 stype; 2431*4882a593Smuzhiyun __le16 status; 2432*4882a593Smuzhiyun __le32 len; 2433*4882a593Smuzhiyun /* Not resolved when == 0xFFFFFFFF == > Broadcast to all MIDS */ 2434*4882a593Smuzhiyun u8 qid; 2435*4882a593Smuzhiyun /* Not resolved when == 0xFFFFFFFF == > Broadcast to all MIDS */ 2436*4882a593Smuzhiyun u8 mid; 2437*4882a593Smuzhiyun u8 cid; 2438*4882a593Smuzhiyun /* From Radio MNGR */ 2439*4882a593Smuzhiyun u8 channel; 2440*4882a593Smuzhiyun } __packed; 2441*4882a593Smuzhiyun 2442*4882a593Smuzhiyun /* WMI_START_SCHED_SCAN_EVENTID */ 2443*4882a593Smuzhiyun enum wmi_pno_result { 2444*4882a593Smuzhiyun WMI_PNO_SUCCESS = 0x00, 2445*4882a593Smuzhiyun WMI_PNO_REJECT = 0x01, 2446*4882a593Smuzhiyun WMI_PNO_INVALID_PARAMETERS = 0x02, 2447*4882a593Smuzhiyun WMI_PNO_NOT_ENABLED = 0x03, 2448*4882a593Smuzhiyun }; 2449*4882a593Smuzhiyun 2450*4882a593Smuzhiyun struct wmi_start_sched_scan_event { 2451*4882a593Smuzhiyun /* wmi_pno_result */ 2452*4882a593Smuzhiyun u8 result; 2453*4882a593Smuzhiyun u8 reserved[3]; 2454*4882a593Smuzhiyun } __packed; 2455*4882a593Smuzhiyun 2456*4882a593Smuzhiyun struct wmi_stop_sched_scan_event { 2457*4882a593Smuzhiyun /* wmi_pno_result */ 2458*4882a593Smuzhiyun u8 result; 2459*4882a593Smuzhiyun u8 reserved[3]; 2460*4882a593Smuzhiyun } __packed; 2461*4882a593Smuzhiyun 2462*4882a593Smuzhiyun struct wmi_sched_scan_result_event { 2463*4882a593Smuzhiyun struct wmi_rx_mgmt_info info; 2464*4882a593Smuzhiyun u8 payload[]; 2465*4882a593Smuzhiyun } __packed; 2466*4882a593Smuzhiyun 2467*4882a593Smuzhiyun /* WMI_ACS_PASSIVE_SCAN_COMPLETE_EVENT */ 2468*4882a593Smuzhiyun enum wmi_acs_info_bitmask { 2469*4882a593Smuzhiyun WMI_ACS_INFO_BITMASK_BEACON_FOUND = 0x01, 2470*4882a593Smuzhiyun WMI_ACS_INFO_BITMASK_BUSY_TIME = 0x02, 2471*4882a593Smuzhiyun WMI_ACS_INFO_BITMASK_TX_TIME = 0x04, 2472*4882a593Smuzhiyun WMI_ACS_INFO_BITMASK_RX_TIME = 0x08, 2473*4882a593Smuzhiyun WMI_ACS_INFO_BITMASK_NOISE = 0x10, 2474*4882a593Smuzhiyun }; 2475*4882a593Smuzhiyun 2476*4882a593Smuzhiyun struct scan_acs_info { 2477*4882a593Smuzhiyun u8 channel; 2478*4882a593Smuzhiyun u8 beacon_found; 2479*4882a593Smuzhiyun /* msec */ 2480*4882a593Smuzhiyun __le16 busy_time; 2481*4882a593Smuzhiyun __le16 tx_time; 2482*4882a593Smuzhiyun __le16 rx_time; 2483*4882a593Smuzhiyun u8 noise; 2484*4882a593Smuzhiyun u8 reserved[3]; 2485*4882a593Smuzhiyun } __packed; 2486*4882a593Smuzhiyun 2487*4882a593Smuzhiyun struct wmi_acs_passive_scan_complete_event { 2488*4882a593Smuzhiyun __le32 dwell_time; 2489*4882a593Smuzhiyun /* valid fields within channel info according to 2490*4882a593Smuzhiyun * their appearance in struct order 2491*4882a593Smuzhiyun */ 2492*4882a593Smuzhiyun __le16 filled; 2493*4882a593Smuzhiyun u8 num_scanned_channels; 2494*4882a593Smuzhiyun u8 reserved; 2495*4882a593Smuzhiyun struct scan_acs_info scan_info_list[]; 2496*4882a593Smuzhiyun } __packed; 2497*4882a593Smuzhiyun 2498*4882a593Smuzhiyun /* WMI_BA_STATUS_EVENTID */ 2499*4882a593Smuzhiyun enum wmi_vring_ba_status { 2500*4882a593Smuzhiyun WMI_BA_AGREED = 0x00, 2501*4882a593Smuzhiyun WMI_BA_NON_AGREED = 0x01, 2502*4882a593Smuzhiyun /* BA_EN in middle of teardown flow */ 2503*4882a593Smuzhiyun WMI_BA_TD_WIP = 0x02, 2504*4882a593Smuzhiyun /* BA_DIS or BA_EN in middle of BA SETUP flow */ 2505*4882a593Smuzhiyun WMI_BA_SETUP_WIP = 0x03, 2506*4882a593Smuzhiyun /* BA_EN when the BA session is already active */ 2507*4882a593Smuzhiyun WMI_BA_SESSION_ACTIVE = 0x04, 2508*4882a593Smuzhiyun /* BA_DIS when the BA session is not active */ 2509*4882a593Smuzhiyun WMI_BA_SESSION_NOT_ACTIVE = 0x05, 2510*4882a593Smuzhiyun }; 2511*4882a593Smuzhiyun 2512*4882a593Smuzhiyun struct wmi_ba_status_event { 2513*4882a593Smuzhiyun /* enum wmi_vring_ba_status */ 2514*4882a593Smuzhiyun __le16 status; 2515*4882a593Smuzhiyun u8 reserved[2]; 2516*4882a593Smuzhiyun u8 ringid; 2517*4882a593Smuzhiyun u8 agg_wsize; 2518*4882a593Smuzhiyun __le16 ba_timeout; 2519*4882a593Smuzhiyun u8 amsdu; 2520*4882a593Smuzhiyun } __packed; 2521*4882a593Smuzhiyun 2522*4882a593Smuzhiyun /* WMI_DELBA_EVENTID */ 2523*4882a593Smuzhiyun struct wmi_delba_event { 2524*4882a593Smuzhiyun /* Used for cid less than 8. For higher cid set 2525*4882a593Smuzhiyun * CIDXTID_EXTENDED_CID_TID here and use cid and tid members instead 2526*4882a593Smuzhiyun */ 2527*4882a593Smuzhiyun u8 cidxtid; 2528*4882a593Smuzhiyun u8 from_initiator; 2529*4882a593Smuzhiyun __le16 reason; 2530*4882a593Smuzhiyun /* Used when cidxtid = CIDXTID_EXTENDED_CID_TID */ 2531*4882a593Smuzhiyun u8 cid; 2532*4882a593Smuzhiyun /* Used when cidxtid = CIDXTID_EXTENDED_CID_TID */ 2533*4882a593Smuzhiyun u8 tid; 2534*4882a593Smuzhiyun u8 reserved[2]; 2535*4882a593Smuzhiyun } __packed; 2536*4882a593Smuzhiyun 2537*4882a593Smuzhiyun /* WMI_VRING_CFG_DONE_EVENTID */ 2538*4882a593Smuzhiyun struct wmi_vring_cfg_done_event { 2539*4882a593Smuzhiyun u8 ringid; 2540*4882a593Smuzhiyun u8 status; 2541*4882a593Smuzhiyun u8 reserved[2]; 2542*4882a593Smuzhiyun __le32 tx_vring_tail_ptr; 2543*4882a593Smuzhiyun } __packed; 2544*4882a593Smuzhiyun 2545*4882a593Smuzhiyun /* WMI_RCP_ADDBA_RESP_SENT_EVENTID */ 2546*4882a593Smuzhiyun struct wmi_rcp_addba_resp_sent_event { 2547*4882a593Smuzhiyun /* Used for cid less than 8. For higher cid set 2548*4882a593Smuzhiyun * CIDXTID_EXTENDED_CID_TID here and use cid and tid members instead 2549*4882a593Smuzhiyun */ 2550*4882a593Smuzhiyun u8 cidxtid; 2551*4882a593Smuzhiyun u8 reserved; 2552*4882a593Smuzhiyun __le16 status; 2553*4882a593Smuzhiyun /* Used when cidxtid = CIDXTID_EXTENDED_CID_TID */ 2554*4882a593Smuzhiyun u8 cid; 2555*4882a593Smuzhiyun /* Used when cidxtid = CIDXTID_EXTENDED_CID_TID */ 2556*4882a593Smuzhiyun u8 tid; 2557*4882a593Smuzhiyun u8 reserved2[2]; 2558*4882a593Smuzhiyun } __packed; 2559*4882a593Smuzhiyun 2560*4882a593Smuzhiyun /* WMI_TX_STATUS_RING_CFG_DONE_EVENTID */ 2561*4882a593Smuzhiyun struct wmi_tx_status_ring_cfg_done_event { 2562*4882a593Smuzhiyun u8 ring_id; 2563*4882a593Smuzhiyun /* wmi_fw_status */ 2564*4882a593Smuzhiyun u8 status; 2565*4882a593Smuzhiyun u8 reserved[2]; 2566*4882a593Smuzhiyun __le32 ring_tail_ptr; 2567*4882a593Smuzhiyun } __packed; 2568*4882a593Smuzhiyun 2569*4882a593Smuzhiyun /* WMI_RX_STATUS_RING_CFG_DONE_EVENTID */ 2570*4882a593Smuzhiyun struct wmi_rx_status_ring_cfg_done_event { 2571*4882a593Smuzhiyun u8 ring_id; 2572*4882a593Smuzhiyun /* wmi_fw_status */ 2573*4882a593Smuzhiyun u8 status; 2574*4882a593Smuzhiyun u8 reserved[2]; 2575*4882a593Smuzhiyun __le32 ring_tail_ptr; 2576*4882a593Smuzhiyun } __packed; 2577*4882a593Smuzhiyun 2578*4882a593Smuzhiyun /* WMI_CFG_DEF_RX_OFFLOAD_DONE_EVENTID */ 2579*4882a593Smuzhiyun struct wmi_cfg_def_rx_offload_done_event { 2580*4882a593Smuzhiyun /* wmi_fw_status */ 2581*4882a593Smuzhiyun u8 status; 2582*4882a593Smuzhiyun u8 reserved[3]; 2583*4882a593Smuzhiyun } __packed; 2584*4882a593Smuzhiyun 2585*4882a593Smuzhiyun /* WMI_TX_DESC_RING_CFG_DONE_EVENTID */ 2586*4882a593Smuzhiyun struct wmi_tx_desc_ring_cfg_done_event { 2587*4882a593Smuzhiyun u8 ring_id; 2588*4882a593Smuzhiyun /* wmi_fw_status */ 2589*4882a593Smuzhiyun u8 status; 2590*4882a593Smuzhiyun u8 reserved[2]; 2591*4882a593Smuzhiyun __le32 ring_tail_ptr; 2592*4882a593Smuzhiyun } __packed; 2593*4882a593Smuzhiyun 2594*4882a593Smuzhiyun /* WMI_RX_DESC_RING_CFG_DONE_EVENTID */ 2595*4882a593Smuzhiyun struct wmi_rx_desc_ring_cfg_done_event { 2596*4882a593Smuzhiyun u8 ring_id; 2597*4882a593Smuzhiyun /* wmi_fw_status */ 2598*4882a593Smuzhiyun u8 status; 2599*4882a593Smuzhiyun u8 reserved[2]; 2600*4882a593Smuzhiyun __le32 ring_tail_ptr; 2601*4882a593Smuzhiyun } __packed; 2602*4882a593Smuzhiyun 2603*4882a593Smuzhiyun /* WMI_RCP_ADDBA_REQ_EVENTID */ 2604*4882a593Smuzhiyun struct wmi_rcp_addba_req_event { 2605*4882a593Smuzhiyun /* Used for cid less than 8. For higher cid set 2606*4882a593Smuzhiyun * CIDXTID_EXTENDED_CID_TID here and use cid and tid members instead 2607*4882a593Smuzhiyun */ 2608*4882a593Smuzhiyun u8 cidxtid; 2609*4882a593Smuzhiyun u8 dialog_token; 2610*4882a593Smuzhiyun /* ieee80211_ba_parameterset as it received */ 2611*4882a593Smuzhiyun __le16 ba_param_set; 2612*4882a593Smuzhiyun __le16 ba_timeout; 2613*4882a593Smuzhiyun /* ieee80211_ba_seqstrl field as it received */ 2614*4882a593Smuzhiyun __le16 ba_seq_ctrl; 2615*4882a593Smuzhiyun /* Used when cidxtid = CIDXTID_EXTENDED_CID_TID */ 2616*4882a593Smuzhiyun u8 cid; 2617*4882a593Smuzhiyun /* Used when cidxtid = CIDXTID_EXTENDED_CID_TID */ 2618*4882a593Smuzhiyun u8 tid; 2619*4882a593Smuzhiyun u8 reserved[2]; 2620*4882a593Smuzhiyun } __packed; 2621*4882a593Smuzhiyun 2622*4882a593Smuzhiyun /* WMI_CFG_RX_CHAIN_DONE_EVENTID */ 2623*4882a593Smuzhiyun enum wmi_cfg_rx_chain_done_event_status { 2624*4882a593Smuzhiyun WMI_CFG_RX_CHAIN_SUCCESS = 0x01, 2625*4882a593Smuzhiyun }; 2626*4882a593Smuzhiyun 2627*4882a593Smuzhiyun struct wmi_cfg_rx_chain_done_event { 2628*4882a593Smuzhiyun /* V-Ring Tail pointer */ 2629*4882a593Smuzhiyun __le32 rx_ring_tail_ptr; 2630*4882a593Smuzhiyun __le32 status; 2631*4882a593Smuzhiyun } __packed; 2632*4882a593Smuzhiyun 2633*4882a593Smuzhiyun /* WMI_WBE_LINK_DOWN_EVENTID */ 2634*4882a593Smuzhiyun enum wmi_wbe_link_down_event_reason { 2635*4882a593Smuzhiyun WMI_WBE_REASON_USER_REQUEST = 0x00, 2636*4882a593Smuzhiyun WMI_WBE_REASON_RX_DISASSOC = 0x01, 2637*4882a593Smuzhiyun WMI_WBE_REASON_BAD_PHY_LINK = 0x02, 2638*4882a593Smuzhiyun }; 2639*4882a593Smuzhiyun 2640*4882a593Smuzhiyun /* WMI_WBE_LINK_DOWN_EVENTID */ 2641*4882a593Smuzhiyun struct wmi_wbe_link_down_event { 2642*4882a593Smuzhiyun u8 cid; 2643*4882a593Smuzhiyun u8 reserved[3]; 2644*4882a593Smuzhiyun __le32 reason; 2645*4882a593Smuzhiyun } __packed; 2646*4882a593Smuzhiyun 2647*4882a593Smuzhiyun /* WMI_DATA_PORT_OPEN_EVENTID */ 2648*4882a593Smuzhiyun struct wmi_data_port_open_event { 2649*4882a593Smuzhiyun u8 cid; 2650*4882a593Smuzhiyun u8 reserved[3]; 2651*4882a593Smuzhiyun } __packed; 2652*4882a593Smuzhiyun 2653*4882a593Smuzhiyun /* WMI_RING_EN_EVENTID */ 2654*4882a593Smuzhiyun struct wmi_ring_en_event { 2655*4882a593Smuzhiyun u8 ring_index; 2656*4882a593Smuzhiyun u8 reserved[3]; 2657*4882a593Smuzhiyun } __packed; 2658*4882a593Smuzhiyun 2659*4882a593Smuzhiyun /* WMI_GET_PCP_CHANNEL_EVENTID */ 2660*4882a593Smuzhiyun struct wmi_get_pcp_channel_event { 2661*4882a593Smuzhiyun u8 channel; 2662*4882a593Smuzhiyun u8 reserved[3]; 2663*4882a593Smuzhiyun } __packed; 2664*4882a593Smuzhiyun 2665*4882a593Smuzhiyun /* WMI_P2P_CFG_DONE_EVENTID */ 2666*4882a593Smuzhiyun struct wmi_p2p_cfg_done_event { 2667*4882a593Smuzhiyun /* wmi_fw_status */ 2668*4882a593Smuzhiyun u8 status; 2669*4882a593Smuzhiyun u8 reserved[3]; 2670*4882a593Smuzhiyun } __packed; 2671*4882a593Smuzhiyun 2672*4882a593Smuzhiyun /* WMI_PORT_ALLOCATED_EVENTID */ 2673*4882a593Smuzhiyun struct wmi_port_allocated_event { 2674*4882a593Smuzhiyun /* wmi_fw_status */ 2675*4882a593Smuzhiyun u8 status; 2676*4882a593Smuzhiyun u8 reserved[3]; 2677*4882a593Smuzhiyun } __packed; 2678*4882a593Smuzhiyun 2679*4882a593Smuzhiyun /* WMI_PORT_DELETED_EVENTID */ 2680*4882a593Smuzhiyun struct wmi_port_deleted_event { 2681*4882a593Smuzhiyun /* wmi_fw_status */ 2682*4882a593Smuzhiyun u8 status; 2683*4882a593Smuzhiyun u8 reserved[3]; 2684*4882a593Smuzhiyun } __packed; 2685*4882a593Smuzhiyun 2686*4882a593Smuzhiyun /* WMI_LISTEN_STARTED_EVENTID */ 2687*4882a593Smuzhiyun struct wmi_listen_started_event { 2688*4882a593Smuzhiyun /* wmi_fw_status */ 2689*4882a593Smuzhiyun u8 status; 2690*4882a593Smuzhiyun u8 reserved[3]; 2691*4882a593Smuzhiyun } __packed; 2692*4882a593Smuzhiyun 2693*4882a593Smuzhiyun /* WMI_SEARCH_STARTED_EVENTID */ 2694*4882a593Smuzhiyun struct wmi_search_started_event { 2695*4882a593Smuzhiyun /* wmi_fw_status */ 2696*4882a593Smuzhiyun u8 status; 2697*4882a593Smuzhiyun u8 reserved[3]; 2698*4882a593Smuzhiyun } __packed; 2699*4882a593Smuzhiyun 2700*4882a593Smuzhiyun /* WMI_PCP_STARTED_EVENTID */ 2701*4882a593Smuzhiyun struct wmi_pcp_started_event { 2702*4882a593Smuzhiyun /* wmi_fw_status */ 2703*4882a593Smuzhiyun u8 status; 2704*4882a593Smuzhiyun u8 reserved[3]; 2705*4882a593Smuzhiyun } __packed; 2706*4882a593Smuzhiyun 2707*4882a593Smuzhiyun /* WMI_PCP_FACTOR_EVENTID */ 2708*4882a593Smuzhiyun struct wmi_pcp_factor_event { 2709*4882a593Smuzhiyun __le32 pcp_factor; 2710*4882a593Smuzhiyun } __packed; 2711*4882a593Smuzhiyun 2712*4882a593Smuzhiyun enum wmi_sw_tx_status { 2713*4882a593Smuzhiyun WMI_TX_SW_STATUS_SUCCESS = 0x00, 2714*4882a593Smuzhiyun WMI_TX_SW_STATUS_FAILED_NO_RESOURCES = 0x01, 2715*4882a593Smuzhiyun WMI_TX_SW_STATUS_FAILED_TX = 0x02, 2716*4882a593Smuzhiyun }; 2717*4882a593Smuzhiyun 2718*4882a593Smuzhiyun /* WMI_SW_TX_COMPLETE_EVENTID */ 2719*4882a593Smuzhiyun struct wmi_sw_tx_complete_event { 2720*4882a593Smuzhiyun /* enum wmi_sw_tx_status */ 2721*4882a593Smuzhiyun u8 status; 2722*4882a593Smuzhiyun u8 reserved[3]; 2723*4882a593Smuzhiyun } __packed; 2724*4882a593Smuzhiyun 2725*4882a593Smuzhiyun /* WMI_CORR_MEASURE_EVENTID - deprecated */ 2726*4882a593Smuzhiyun struct wmi_corr_measure_event { 2727*4882a593Smuzhiyun /* signed */ 2728*4882a593Smuzhiyun __le32 i; 2729*4882a593Smuzhiyun /* signed */ 2730*4882a593Smuzhiyun __le32 q; 2731*4882a593Smuzhiyun /* signed */ 2732*4882a593Smuzhiyun __le32 image_i; 2733*4882a593Smuzhiyun /* signed */ 2734*4882a593Smuzhiyun __le32 image_q; 2735*4882a593Smuzhiyun } __packed; 2736*4882a593Smuzhiyun 2737*4882a593Smuzhiyun /* WMI_READ_RSSI_EVENTID */ 2738*4882a593Smuzhiyun struct wmi_read_rssi_event { 2739*4882a593Smuzhiyun __le32 ina_rssi_adc_dbm; 2740*4882a593Smuzhiyun } __packed; 2741*4882a593Smuzhiyun 2742*4882a593Smuzhiyun /* WMI_GET_SSID_EVENTID */ 2743*4882a593Smuzhiyun struct wmi_get_ssid_event { 2744*4882a593Smuzhiyun __le32 ssid_len; 2745*4882a593Smuzhiyun u8 ssid[WMI_MAX_SSID_LEN]; 2746*4882a593Smuzhiyun } __packed; 2747*4882a593Smuzhiyun 2748*4882a593Smuzhiyun /* EVENT: WMI_RF_XPM_READ_RESULT_EVENTID */ 2749*4882a593Smuzhiyun struct wmi_rf_xpm_read_result_event { 2750*4882a593Smuzhiyun /* enum wmi_fw_status_e - success=0 or fail=1 */ 2751*4882a593Smuzhiyun u8 status; 2752*4882a593Smuzhiyun u8 reserved[3]; 2753*4882a593Smuzhiyun /* requested num_bytes of data */ 2754*4882a593Smuzhiyun u8 data_bytes[]; 2755*4882a593Smuzhiyun } __packed; 2756*4882a593Smuzhiyun 2757*4882a593Smuzhiyun /* EVENT: WMI_RF_XPM_WRITE_RESULT_EVENTID */ 2758*4882a593Smuzhiyun struct wmi_rf_xpm_write_result_event { 2759*4882a593Smuzhiyun /* enum wmi_fw_status_e - success=0 or fail=1 */ 2760*4882a593Smuzhiyun u8 status; 2761*4882a593Smuzhiyun u8 reserved[3]; 2762*4882a593Smuzhiyun } __packed; 2763*4882a593Smuzhiyun 2764*4882a593Smuzhiyun /* WMI_TX_MGMT_PACKET_EVENTID */ 2765*4882a593Smuzhiyun struct wmi_tx_mgmt_packet_event { 2766*4882a593Smuzhiyun u8 payload[0]; 2767*4882a593Smuzhiyun } __packed; 2768*4882a593Smuzhiyun 2769*4882a593Smuzhiyun /* WMI_RX_MGMT_PACKET_EVENTID */ 2770*4882a593Smuzhiyun struct wmi_rx_mgmt_packet_event { 2771*4882a593Smuzhiyun struct wmi_rx_mgmt_info info; 2772*4882a593Smuzhiyun u8 payload[]; 2773*4882a593Smuzhiyun } __packed; 2774*4882a593Smuzhiyun 2775*4882a593Smuzhiyun /* WMI_ECHO_RSP_EVENTID */ 2776*4882a593Smuzhiyun struct wmi_echo_rsp_event { 2777*4882a593Smuzhiyun __le32 echoed_value; 2778*4882a593Smuzhiyun } __packed; 2779*4882a593Smuzhiyun 2780*4882a593Smuzhiyun /* WMI_DEEP_ECHO_RSP_EVENTID */ 2781*4882a593Smuzhiyun struct wmi_deep_echo_rsp_event { 2782*4882a593Smuzhiyun __le32 echoed_value; 2783*4882a593Smuzhiyun } __packed; 2784*4882a593Smuzhiyun 2785*4882a593Smuzhiyun /* WMI_RF_PWR_ON_DELAY_RSP_EVENTID */ 2786*4882a593Smuzhiyun struct wmi_rf_pwr_on_delay_rsp_event { 2787*4882a593Smuzhiyun /* wmi_fw_status */ 2788*4882a593Smuzhiyun u8 status; 2789*4882a593Smuzhiyun u8 reserved[3]; 2790*4882a593Smuzhiyun } __packed; 2791*4882a593Smuzhiyun 2792*4882a593Smuzhiyun /* WMI_SET_HIGH_POWER_TABLE_PARAMS_EVENTID */ 2793*4882a593Smuzhiyun struct wmi_set_high_power_table_params_event { 2794*4882a593Smuzhiyun /* wmi_fw_status */ 2795*4882a593Smuzhiyun u8 status; 2796*4882a593Smuzhiyun u8 reserved[3]; 2797*4882a593Smuzhiyun } __packed; 2798*4882a593Smuzhiyun 2799*4882a593Smuzhiyun /* WMI_FIXED_SCHEDULING_UL_CONFIG_EVENTID */ 2800*4882a593Smuzhiyun struct wmi_fixed_scheduling_ul_config_event { 2801*4882a593Smuzhiyun /* wmi_fw_status */ 2802*4882a593Smuzhiyun u8 status; 2803*4882a593Smuzhiyun u8 reserved[3]; 2804*4882a593Smuzhiyun } __packed; 2805*4882a593Smuzhiyun 2806*4882a593Smuzhiyun /* WMI_TEMP_SENSE_DONE_EVENTID 2807*4882a593Smuzhiyun * 2808*4882a593Smuzhiyun * Measure MAC and radio temperatures 2809*4882a593Smuzhiyun */ 2810*4882a593Smuzhiyun struct wmi_temp_sense_done_event { 2811*4882a593Smuzhiyun /* Temperature times 1000 (actual temperature will be achieved by 2812*4882a593Smuzhiyun * dividing the value by 1000). When temperature cannot be read from 2813*4882a593Smuzhiyun * device return WMI_INVALID_TEMPERATURE 2814*4882a593Smuzhiyun */ 2815*4882a593Smuzhiyun __le32 baseband_t1000; 2816*4882a593Smuzhiyun /* Temperature times 1000 (actual temperature will be achieved by 2817*4882a593Smuzhiyun * dividing the value by 1000). When temperature cannot be read from 2818*4882a593Smuzhiyun * device return WMI_INVALID_TEMPERATURE 2819*4882a593Smuzhiyun */ 2820*4882a593Smuzhiyun __le32 rf_t1000; 2821*4882a593Smuzhiyun } __packed; 2822*4882a593Smuzhiyun 2823*4882a593Smuzhiyun #define WMI_SCAN_DWELL_TIME_MS (100) 2824*4882a593Smuzhiyun #define WMI_SURVEY_TIMEOUT_MS (10000) 2825*4882a593Smuzhiyun 2826*4882a593Smuzhiyun enum wmi_hidden_ssid { 2827*4882a593Smuzhiyun WMI_HIDDEN_SSID_DISABLED = 0x00, 2828*4882a593Smuzhiyun WMI_HIDDEN_SSID_SEND_EMPTY = 0x10, 2829*4882a593Smuzhiyun WMI_HIDDEN_SSID_CLEAR = 0xFE, 2830*4882a593Smuzhiyun }; 2831*4882a593Smuzhiyun 2832*4882a593Smuzhiyun /* WMI_LED_CFG_CMDID 2833*4882a593Smuzhiyun * 2834*4882a593Smuzhiyun * Configure LED On\Off\Blinking operation 2835*4882a593Smuzhiyun * 2836*4882a593Smuzhiyun * Returned events: 2837*4882a593Smuzhiyun * - WMI_LED_CFG_DONE_EVENTID 2838*4882a593Smuzhiyun */ 2839*4882a593Smuzhiyun enum led_mode { 2840*4882a593Smuzhiyun LED_DISABLE = 0x00, 2841*4882a593Smuzhiyun LED_ENABLE = 0x01, 2842*4882a593Smuzhiyun }; 2843*4882a593Smuzhiyun 2844*4882a593Smuzhiyun /* The names of the led as 2845*4882a593Smuzhiyun * described on HW schemes. 2846*4882a593Smuzhiyun */ 2847*4882a593Smuzhiyun enum wmi_led_id { 2848*4882a593Smuzhiyun WMI_LED_WLAN = 0x00, 2849*4882a593Smuzhiyun WMI_LED_WPAN = 0x01, 2850*4882a593Smuzhiyun WMI_LED_WWAN = 0x02, 2851*4882a593Smuzhiyun }; 2852*4882a593Smuzhiyun 2853*4882a593Smuzhiyun /* Led polarity mode. */ 2854*4882a593Smuzhiyun enum wmi_led_polarity { 2855*4882a593Smuzhiyun LED_POLARITY_HIGH_ACTIVE = 0x00, 2856*4882a593Smuzhiyun LED_POLARITY_LOW_ACTIVE = 0x01, 2857*4882a593Smuzhiyun }; 2858*4882a593Smuzhiyun 2859*4882a593Smuzhiyun /* Combination of on and off 2860*4882a593Smuzhiyun * creates the blinking period 2861*4882a593Smuzhiyun */ 2862*4882a593Smuzhiyun struct wmi_led_blink_mode { 2863*4882a593Smuzhiyun __le32 blink_on; 2864*4882a593Smuzhiyun __le32 blink_off; 2865*4882a593Smuzhiyun } __packed; 2866*4882a593Smuzhiyun 2867*4882a593Smuzhiyun /* WMI_LED_CFG_CMDID */ 2868*4882a593Smuzhiyun struct wmi_led_cfg_cmd { 2869*4882a593Smuzhiyun /* enum led_mode_e */ 2870*4882a593Smuzhiyun u8 led_mode; 2871*4882a593Smuzhiyun /* enum wmi_led_id_e */ 2872*4882a593Smuzhiyun u8 id; 2873*4882a593Smuzhiyun /* slow speed blinking combination */ 2874*4882a593Smuzhiyun struct wmi_led_blink_mode slow_blink_cfg; 2875*4882a593Smuzhiyun /* medium speed blinking combination */ 2876*4882a593Smuzhiyun struct wmi_led_blink_mode medium_blink_cfg; 2877*4882a593Smuzhiyun /* high speed blinking combination */ 2878*4882a593Smuzhiyun struct wmi_led_blink_mode fast_blink_cfg; 2879*4882a593Smuzhiyun /* polarity of the led */ 2880*4882a593Smuzhiyun u8 led_polarity; 2881*4882a593Smuzhiyun /* reserved */ 2882*4882a593Smuzhiyun u8 reserved; 2883*4882a593Smuzhiyun } __packed; 2884*4882a593Smuzhiyun 2885*4882a593Smuzhiyun /* \WMI_SET_CONNECT_SNR_THR_CMDID */ 2886*4882a593Smuzhiyun struct wmi_set_connect_snr_thr_cmd { 2887*4882a593Smuzhiyun u8 enable; 2888*4882a593Smuzhiyun u8 reserved; 2889*4882a593Smuzhiyun /* 1/4 Db units */ 2890*4882a593Smuzhiyun __le16 omni_snr_thr; 2891*4882a593Smuzhiyun /* 1/4 Db units */ 2892*4882a593Smuzhiyun __le16 direct_snr_thr; 2893*4882a593Smuzhiyun } __packed; 2894*4882a593Smuzhiyun 2895*4882a593Smuzhiyun /* WMI_LED_CFG_DONE_EVENTID */ 2896*4882a593Smuzhiyun struct wmi_led_cfg_done_event { 2897*4882a593Smuzhiyun /* led config status */ 2898*4882a593Smuzhiyun __le32 status; 2899*4882a593Smuzhiyun } __packed; 2900*4882a593Smuzhiyun 2901*4882a593Smuzhiyun /* Rate search parameters configuration per connection */ 2902*4882a593Smuzhiyun struct wmi_rs_cfg { 2903*4882a593Smuzhiyun /* The maximal allowed PER for each MCS 2904*4882a593Smuzhiyun * MCS will be considered as failed if PER during RS is higher 2905*4882a593Smuzhiyun */ 2906*4882a593Smuzhiyun u8 per_threshold[WMI_NUM_MCS]; 2907*4882a593Smuzhiyun /* Number of MPDUs for each MCS 2908*4882a593Smuzhiyun * this is the minimal statistic required to make an educated 2909*4882a593Smuzhiyun * decision 2910*4882a593Smuzhiyun */ 2911*4882a593Smuzhiyun u8 min_frame_cnt[WMI_NUM_MCS]; 2912*4882a593Smuzhiyun /* stop threshold [0-100] */ 2913*4882a593Smuzhiyun u8 stop_th; 2914*4882a593Smuzhiyun /* MCS1 stop threshold [0-100] */ 2915*4882a593Smuzhiyun u8 mcs1_fail_th; 2916*4882a593Smuzhiyun u8 max_back_failure_th; 2917*4882a593Smuzhiyun /* Debug feature for disabling internal RS trigger (which is 2918*4882a593Smuzhiyun * currently triggered by BF Done) 2919*4882a593Smuzhiyun */ 2920*4882a593Smuzhiyun u8 dbg_disable_internal_trigger; 2921*4882a593Smuzhiyun __le32 back_failure_mask; 2922*4882a593Smuzhiyun __le32 mcs_en_vec; 2923*4882a593Smuzhiyun } __packed; 2924*4882a593Smuzhiyun 2925*4882a593Smuzhiyun enum wmi_edmg_tx_mode { 2926*4882a593Smuzhiyun WMI_TX_MODE_DMG = 0x0, 2927*4882a593Smuzhiyun WMI_TX_MODE_EDMG_CB1 = 0x1, 2928*4882a593Smuzhiyun WMI_TX_MODE_EDMG_CB2 = 0x2, 2929*4882a593Smuzhiyun WMI_TX_MODE_EDMG_CB1_LONG_LDPC = 0x3, 2930*4882a593Smuzhiyun WMI_TX_MODE_EDMG_CB2_LONG_LDPC = 0x4, 2931*4882a593Smuzhiyun WMI_TX_MODE_MAX, 2932*4882a593Smuzhiyun }; 2933*4882a593Smuzhiyun 2934*4882a593Smuzhiyun /* Rate search parameters common configuration */ 2935*4882a593Smuzhiyun struct wmi_rs_cfg_ex_common { 2936*4882a593Smuzhiyun /* enum wmi_edmg_tx_mode */ 2937*4882a593Smuzhiyun u8 mode; 2938*4882a593Smuzhiyun /* stop threshold [0-100] */ 2939*4882a593Smuzhiyun u8 stop_th; 2940*4882a593Smuzhiyun /* MCS1 stop threshold [0-100] */ 2941*4882a593Smuzhiyun u8 mcs1_fail_th; 2942*4882a593Smuzhiyun u8 max_back_failure_th; 2943*4882a593Smuzhiyun /* Debug feature for disabling internal RS trigger (which is 2944*4882a593Smuzhiyun * currently triggered by BF Done) 2945*4882a593Smuzhiyun */ 2946*4882a593Smuzhiyun u8 dbg_disable_internal_trigger; 2947*4882a593Smuzhiyun u8 reserved[3]; 2948*4882a593Smuzhiyun __le32 back_failure_mask; 2949*4882a593Smuzhiyun } __packed; 2950*4882a593Smuzhiyun 2951*4882a593Smuzhiyun /* Rate search parameters configuration per MCS */ 2952*4882a593Smuzhiyun struct wmi_rs_cfg_ex_mcs { 2953*4882a593Smuzhiyun /* The maximal allowed PER for each MCS 2954*4882a593Smuzhiyun * MCS will be considered as failed if PER during RS is higher 2955*4882a593Smuzhiyun */ 2956*4882a593Smuzhiyun u8 per_threshold; 2957*4882a593Smuzhiyun /* Number of MPDUs for each MCS 2958*4882a593Smuzhiyun * this is the minimal statistic required to make an educated 2959*4882a593Smuzhiyun * decision 2960*4882a593Smuzhiyun */ 2961*4882a593Smuzhiyun u8 min_frame_cnt; 2962*4882a593Smuzhiyun u8 reserved[2]; 2963*4882a593Smuzhiyun } __packed; 2964*4882a593Smuzhiyun 2965*4882a593Smuzhiyun /* WMI_RS_CFG_EX_CMDID */ 2966*4882a593Smuzhiyun struct wmi_rs_cfg_ex_cmd { 2967*4882a593Smuzhiyun /* Configuration for all MCSs */ 2968*4882a593Smuzhiyun struct wmi_rs_cfg_ex_common common_cfg; 2969*4882a593Smuzhiyun u8 each_mcs_cfg_size; 2970*4882a593Smuzhiyun u8 reserved[3]; 2971*4882a593Smuzhiyun /* Configuration for each MCS */ 2972*4882a593Smuzhiyun struct wmi_rs_cfg_ex_mcs each_mcs_cfg[]; 2973*4882a593Smuzhiyun } __packed; 2974*4882a593Smuzhiyun 2975*4882a593Smuzhiyun /* WMI_RS_CFG_EX_EVENTID */ 2976*4882a593Smuzhiyun struct wmi_rs_cfg_ex_event { 2977*4882a593Smuzhiyun /* enum wmi_edmg_tx_mode */ 2978*4882a593Smuzhiyun u8 mode; 2979*4882a593Smuzhiyun /* enum wmi_fw_status */ 2980*4882a593Smuzhiyun u8 status; 2981*4882a593Smuzhiyun u8 reserved[2]; 2982*4882a593Smuzhiyun } __packed; 2983*4882a593Smuzhiyun 2984*4882a593Smuzhiyun /* WMI_RS_ENABLE_CMDID */ 2985*4882a593Smuzhiyun struct wmi_rs_enable_cmd { 2986*4882a593Smuzhiyun u8 cid; 2987*4882a593Smuzhiyun /* enable or disable rate search */ 2988*4882a593Smuzhiyun u8 rs_enable; 2989*4882a593Smuzhiyun u8 reserved[2]; 2990*4882a593Smuzhiyun __le32 mcs_en_vec; 2991*4882a593Smuzhiyun } __packed; 2992*4882a593Smuzhiyun 2993*4882a593Smuzhiyun /* WMI_RS_ENABLE_EVENTID */ 2994*4882a593Smuzhiyun struct wmi_rs_enable_event { 2995*4882a593Smuzhiyun /* enum wmi_fw_status */ 2996*4882a593Smuzhiyun u8 status; 2997*4882a593Smuzhiyun u8 reserved[3]; 2998*4882a593Smuzhiyun } __packed; 2999*4882a593Smuzhiyun 3000*4882a593Smuzhiyun /* Slot types */ 3001*4882a593Smuzhiyun enum wmi_sched_scheme_slot_type { 3002*4882a593Smuzhiyun WMI_SCHED_SLOT_SP = 0x0, 3003*4882a593Smuzhiyun WMI_SCHED_SLOT_CBAP = 0x1, 3004*4882a593Smuzhiyun WMI_SCHED_SLOT_IDLE = 0x2, 3005*4882a593Smuzhiyun WMI_SCHED_SLOT_ANNOUNCE_NO_ACK = 0x3, 3006*4882a593Smuzhiyun WMI_SCHED_SLOT_DISCOVERY = 0x4, 3007*4882a593Smuzhiyun }; 3008*4882a593Smuzhiyun 3009*4882a593Smuzhiyun enum wmi_sched_scheme_slot_flags { 3010*4882a593Smuzhiyun WMI_SCHED_SCHEME_SLOT_PERIODIC = 0x1, 3011*4882a593Smuzhiyun }; 3012*4882a593Smuzhiyun 3013*4882a593Smuzhiyun struct wmi_sched_scheme_slot { 3014*4882a593Smuzhiyun /* in microsecond */ 3015*4882a593Smuzhiyun __le32 tbtt_offset; 3016*4882a593Smuzhiyun /* wmi_sched_scheme_slot_flags */ 3017*4882a593Smuzhiyun u8 flags; 3018*4882a593Smuzhiyun /* wmi_sched_scheme_slot_type */ 3019*4882a593Smuzhiyun u8 type; 3020*4882a593Smuzhiyun /* in microsecond */ 3021*4882a593Smuzhiyun __le16 duration; 3022*4882a593Smuzhiyun /* frame_exchange_sequence_duration */ 3023*4882a593Smuzhiyun __le16 tx_op; 3024*4882a593Smuzhiyun /* time in microseconds between two consecutive slots 3025*4882a593Smuzhiyun * relevant only if flag WMI_SCHED_SCHEME_SLOT_PERIODIC set 3026*4882a593Smuzhiyun */ 3027*4882a593Smuzhiyun __le16 period; 3028*4882a593Smuzhiyun /* relevant only if flag WMI_SCHED_SCHEME_SLOT_PERIODIC set 3029*4882a593Smuzhiyun * number of times to repeat allocation 3030*4882a593Smuzhiyun */ 3031*4882a593Smuzhiyun u8 num_of_blocks; 3032*4882a593Smuzhiyun /* relevant only if flag WMI_SCHED_SCHEME_SLOT_PERIODIC set 3033*4882a593Smuzhiyun * every idle_period allocation will be idle 3034*4882a593Smuzhiyun */ 3035*4882a593Smuzhiyun u8 idle_period; 3036*4882a593Smuzhiyun u8 src_aid; 3037*4882a593Smuzhiyun u8 dest_aid; 3038*4882a593Smuzhiyun __le32 reserved; 3039*4882a593Smuzhiyun } __packed; 3040*4882a593Smuzhiyun 3041*4882a593Smuzhiyun enum wmi_sched_scheme_flags { 3042*4882a593Smuzhiyun /* should not be set when clearing scheduling scheme */ 3043*4882a593Smuzhiyun WMI_SCHED_SCHEME_ENABLE = 0x01, 3044*4882a593Smuzhiyun WMI_SCHED_PROTECTED_SP = 0x02, 3045*4882a593Smuzhiyun /* should be set only on first WMI fragment of scheme */ 3046*4882a593Smuzhiyun WMI_SCHED_FIRST = 0x04, 3047*4882a593Smuzhiyun /* should be set only on last WMI fragment of scheme */ 3048*4882a593Smuzhiyun WMI_SCHED_LAST = 0x08, 3049*4882a593Smuzhiyun WMI_SCHED_IMMEDIATE_START = 0x10, 3050*4882a593Smuzhiyun }; 3051*4882a593Smuzhiyun 3052*4882a593Smuzhiyun enum wmi_sched_scheme_advertisment { 3053*4882a593Smuzhiyun /* ESE is not advertised at all, STA has to be configured with WMI 3054*4882a593Smuzhiyun * also 3055*4882a593Smuzhiyun */ 3056*4882a593Smuzhiyun WMI_ADVERTISE_ESE_DISABLED = 0x0, 3057*4882a593Smuzhiyun WMI_ADVERTISE_ESE_IN_BEACON = 0x1, 3058*4882a593Smuzhiyun WMI_ADVERTISE_ESE_IN_ANNOUNCE_FRAME = 0x2, 3059*4882a593Smuzhiyun }; 3060*4882a593Smuzhiyun 3061*4882a593Smuzhiyun /* WMI_SCHEDULING_SCHEME_CMD */ 3062*4882a593Smuzhiyun struct wmi_scheduling_scheme_cmd { 3063*4882a593Smuzhiyun u8 serial_num; 3064*4882a593Smuzhiyun /* wmi_sched_scheme_advertisment */ 3065*4882a593Smuzhiyun u8 ese_advertisment; 3066*4882a593Smuzhiyun /* wmi_sched_scheme_flags */ 3067*4882a593Smuzhiyun __le16 flags; 3068*4882a593Smuzhiyun u8 num_allocs; 3069*4882a593Smuzhiyun u8 reserved[3]; 3070*4882a593Smuzhiyun __le64 start_tbtt; 3071*4882a593Smuzhiyun /* allocations list */ 3072*4882a593Smuzhiyun struct wmi_sched_scheme_slot allocs[WMI_SCHED_MAX_ALLOCS_PER_CMD]; 3073*4882a593Smuzhiyun } __packed; 3074*4882a593Smuzhiyun 3075*4882a593Smuzhiyun enum wmi_sched_scheme_failure_type { 3076*4882a593Smuzhiyun WMI_SCHED_SCHEME_FAILURE_NO_ERROR = 0x00, 3077*4882a593Smuzhiyun WMI_SCHED_SCHEME_FAILURE_OLD_START_TSF_ERR = 0x01, 3078*4882a593Smuzhiyun }; 3079*4882a593Smuzhiyun 3080*4882a593Smuzhiyun /* WMI_SCHEDULING_SCHEME_EVENTID */ 3081*4882a593Smuzhiyun struct wmi_scheduling_scheme_event { 3082*4882a593Smuzhiyun /* wmi_fw_status_e */ 3083*4882a593Smuzhiyun u8 status; 3084*4882a593Smuzhiyun /* serial number given in command */ 3085*4882a593Smuzhiyun u8 serial_num; 3086*4882a593Smuzhiyun /* wmi_sched_scheme_failure_type */ 3087*4882a593Smuzhiyun u8 failure_type; 3088*4882a593Smuzhiyun /* alignment to 32b */ 3089*4882a593Smuzhiyun u8 reserved[1]; 3090*4882a593Smuzhiyun } __packed; 3091*4882a593Smuzhiyun 3092*4882a593Smuzhiyun /* WMI_RS_CFG_CMDID - deprecated */ 3093*4882a593Smuzhiyun struct wmi_rs_cfg_cmd { 3094*4882a593Smuzhiyun /* connection id */ 3095*4882a593Smuzhiyun u8 cid; 3096*4882a593Smuzhiyun /* enable or disable rate search */ 3097*4882a593Smuzhiyun u8 rs_enable; 3098*4882a593Smuzhiyun /* rate search configuration */ 3099*4882a593Smuzhiyun struct wmi_rs_cfg rs_cfg; 3100*4882a593Smuzhiyun } __packed; 3101*4882a593Smuzhiyun 3102*4882a593Smuzhiyun /* WMI_RS_CFG_DONE_EVENTID - deprecated */ 3103*4882a593Smuzhiyun struct wmi_rs_cfg_done_event { 3104*4882a593Smuzhiyun u8 cid; 3105*4882a593Smuzhiyun /* enum wmi_fw_status */ 3106*4882a593Smuzhiyun u8 status; 3107*4882a593Smuzhiyun u8 reserved[2]; 3108*4882a593Smuzhiyun } __packed; 3109*4882a593Smuzhiyun 3110*4882a593Smuzhiyun /* WMI_GET_DETAILED_RS_RES_CMDID - deprecated */ 3111*4882a593Smuzhiyun struct wmi_get_detailed_rs_res_cmd { 3112*4882a593Smuzhiyun /* connection id */ 3113*4882a593Smuzhiyun u8 cid; 3114*4882a593Smuzhiyun u8 reserved[3]; 3115*4882a593Smuzhiyun } __packed; 3116*4882a593Smuzhiyun 3117*4882a593Smuzhiyun /* RS results status */ 3118*4882a593Smuzhiyun enum wmi_rs_results_status { 3119*4882a593Smuzhiyun WMI_RS_RES_VALID = 0x00, 3120*4882a593Smuzhiyun WMI_RS_RES_INVALID = 0x01, 3121*4882a593Smuzhiyun }; 3122*4882a593Smuzhiyun 3123*4882a593Smuzhiyun /* Rate search results */ 3124*4882a593Smuzhiyun struct wmi_rs_results { 3125*4882a593Smuzhiyun /* number of sent MPDUs */ 3126*4882a593Smuzhiyun u8 num_of_tx_pkt[WMI_NUM_MCS]; 3127*4882a593Smuzhiyun /* number of non-acked MPDUs */ 3128*4882a593Smuzhiyun u8 num_of_non_acked_pkt[WMI_NUM_MCS]; 3129*4882a593Smuzhiyun /* RS timestamp */ 3130*4882a593Smuzhiyun __le32 tsf; 3131*4882a593Smuzhiyun /* RS selected MCS */ 3132*4882a593Smuzhiyun u8 mcs; 3133*4882a593Smuzhiyun } __packed; 3134*4882a593Smuzhiyun 3135*4882a593Smuzhiyun /* WMI_GET_DETAILED_RS_RES_EVENTID - deprecated */ 3136*4882a593Smuzhiyun struct wmi_get_detailed_rs_res_event { 3137*4882a593Smuzhiyun u8 cid; 3138*4882a593Smuzhiyun /* enum wmi_rs_results_status */ 3139*4882a593Smuzhiyun u8 status; 3140*4882a593Smuzhiyun /* detailed rs results */ 3141*4882a593Smuzhiyun struct wmi_rs_results rs_results; 3142*4882a593Smuzhiyun u8 reserved[3]; 3143*4882a593Smuzhiyun } __packed; 3144*4882a593Smuzhiyun 3145*4882a593Smuzhiyun /* WMI_GET_DETAILED_RS_RES_EX_CMDID */ 3146*4882a593Smuzhiyun struct wmi_get_detailed_rs_res_ex_cmd { 3147*4882a593Smuzhiyun u8 cid; 3148*4882a593Smuzhiyun u8 reserved[3]; 3149*4882a593Smuzhiyun } __packed; 3150*4882a593Smuzhiyun 3151*4882a593Smuzhiyun /* Rate search results */ 3152*4882a593Smuzhiyun struct wmi_rs_results_ex_common { 3153*4882a593Smuzhiyun /* RS timestamp */ 3154*4882a593Smuzhiyun __le32 tsf; 3155*4882a593Smuzhiyun /* RS selected MCS */ 3156*4882a593Smuzhiyun u8 mcs; 3157*4882a593Smuzhiyun /* enum wmi_edmg_tx_mode */ 3158*4882a593Smuzhiyun u8 mode; 3159*4882a593Smuzhiyun u8 reserved[2]; 3160*4882a593Smuzhiyun } __packed; 3161*4882a593Smuzhiyun 3162*4882a593Smuzhiyun /* Rate search results */ 3163*4882a593Smuzhiyun struct wmi_rs_results_ex_mcs { 3164*4882a593Smuzhiyun /* number of sent MPDUs */ 3165*4882a593Smuzhiyun u8 num_of_tx_pkt; 3166*4882a593Smuzhiyun /* number of non-acked MPDUs */ 3167*4882a593Smuzhiyun u8 num_of_non_acked_pkt; 3168*4882a593Smuzhiyun u8 reserved[2]; 3169*4882a593Smuzhiyun } __packed; 3170*4882a593Smuzhiyun 3171*4882a593Smuzhiyun /* WMI_GET_DETAILED_RS_RES_EX_EVENTID */ 3172*4882a593Smuzhiyun struct wmi_get_detailed_rs_res_ex_event { 3173*4882a593Smuzhiyun u8 cid; 3174*4882a593Smuzhiyun /* enum wmi_rs_results_status */ 3175*4882a593Smuzhiyun u8 status; 3176*4882a593Smuzhiyun u8 reserved0[2]; 3177*4882a593Smuzhiyun struct wmi_rs_results_ex_common common_rs_results; 3178*4882a593Smuzhiyun u8 each_mcs_results_size; 3179*4882a593Smuzhiyun u8 reserved1[3]; 3180*4882a593Smuzhiyun /* Results for each MCS */ 3181*4882a593Smuzhiyun struct wmi_rs_results_ex_mcs each_mcs_results[]; 3182*4882a593Smuzhiyun } __packed; 3183*4882a593Smuzhiyun 3184*4882a593Smuzhiyun /* BRP antenna limit mode */ 3185*4882a593Smuzhiyun enum wmi_brp_ant_limit_mode { 3186*4882a593Smuzhiyun /* Disable BRP force antenna limit */ 3187*4882a593Smuzhiyun WMI_BRP_ANT_LIMIT_MODE_DISABLE = 0x00, 3188*4882a593Smuzhiyun /* Define maximal antennas limit. Only effective antennas will be 3189*4882a593Smuzhiyun * actually used 3190*4882a593Smuzhiyun */ 3191*4882a593Smuzhiyun WMI_BRP_ANT_LIMIT_MODE_EFFECTIVE = 0x01, 3192*4882a593Smuzhiyun /* Force a specific number of antennas */ 3193*4882a593Smuzhiyun WMI_BRP_ANT_LIMIT_MODE_FORCE = 0x02, 3194*4882a593Smuzhiyun /* number of BRP antenna limit modes */ 3195*4882a593Smuzhiyun WMI_BRP_ANT_LIMIT_MODES_NUM = 0x03, 3196*4882a593Smuzhiyun }; 3197*4882a593Smuzhiyun 3198*4882a593Smuzhiyun /* WMI_BRP_SET_ANT_LIMIT_CMDID */ 3199*4882a593Smuzhiyun struct wmi_brp_set_ant_limit_cmd { 3200*4882a593Smuzhiyun /* connection id */ 3201*4882a593Smuzhiyun u8 cid; 3202*4882a593Smuzhiyun /* enum wmi_brp_ant_limit_mode */ 3203*4882a593Smuzhiyun u8 limit_mode; 3204*4882a593Smuzhiyun /* antenna limit count, 1-27 3205*4882a593Smuzhiyun * disable_mode - ignored 3206*4882a593Smuzhiyun * effective_mode - upper limit to number of antennas to be used 3207*4882a593Smuzhiyun * force_mode - exact number of antennas to be used 3208*4882a593Smuzhiyun */ 3209*4882a593Smuzhiyun u8 ant_limit; 3210*4882a593Smuzhiyun u8 reserved; 3211*4882a593Smuzhiyun } __packed; 3212*4882a593Smuzhiyun 3213*4882a593Smuzhiyun /* WMI_BRP_SET_ANT_LIMIT_EVENTID */ 3214*4882a593Smuzhiyun struct wmi_brp_set_ant_limit_event { 3215*4882a593Smuzhiyun /* wmi_fw_status */ 3216*4882a593Smuzhiyun u8 status; 3217*4882a593Smuzhiyun u8 reserved[3]; 3218*4882a593Smuzhiyun } __packed; 3219*4882a593Smuzhiyun 3220*4882a593Smuzhiyun enum wmi_bf_type { 3221*4882a593Smuzhiyun WMI_BF_TYPE_SLS = 0x00, 3222*4882a593Smuzhiyun WMI_BF_TYPE_BRP_RX = 0x01, 3223*4882a593Smuzhiyun }; 3224*4882a593Smuzhiyun 3225*4882a593Smuzhiyun /* WMI_BF_TRIG_CMDID */ 3226*4882a593Smuzhiyun struct wmi_bf_trig_cmd { 3227*4882a593Smuzhiyun /* enum wmi_bf_type - type of requested beamforming */ 3228*4882a593Smuzhiyun u8 bf_type; 3229*4882a593Smuzhiyun /* used only for WMI_BF_TYPE_BRP_RX */ 3230*4882a593Smuzhiyun u8 cid; 3231*4882a593Smuzhiyun /* used only for WMI_BF_TYPE_SLS */ 3232*4882a593Smuzhiyun u8 dst_mac[WMI_MAC_LEN]; 3233*4882a593Smuzhiyun u8 reserved[4]; 3234*4882a593Smuzhiyun } __packed; 3235*4882a593Smuzhiyun 3236*4882a593Smuzhiyun /* WMI_BF_TRIG_EVENTID */ 3237*4882a593Smuzhiyun struct wmi_bf_trig_event { 3238*4882a593Smuzhiyun /* enum wmi_fw_status */ 3239*4882a593Smuzhiyun u8 status; 3240*4882a593Smuzhiyun u8 cid; 3241*4882a593Smuzhiyun u8 reserved[2]; 3242*4882a593Smuzhiyun } __packed; 3243*4882a593Smuzhiyun 3244*4882a593Smuzhiyun /* broadcast connection ID */ 3245*4882a593Smuzhiyun #define WMI_LINK_MAINTAIN_CFG_CID_BROADCAST (0xFFFFFFFF) 3246*4882a593Smuzhiyun 3247*4882a593Smuzhiyun /* Types wmi_link_maintain_cfg presets for WMI_LINK_MAINTAIN_CFG_WRITE_CMD */ 3248*4882a593Smuzhiyun enum wmi_link_maintain_cfg_type { 3249*4882a593Smuzhiyun /* AP/PCP default normal (non-FST) configuration settings */ 3250*4882a593Smuzhiyun WMI_LINK_MAINTAIN_CFG_TYPE_DEFAULT_NORMAL_AP = 0x00, 3251*4882a593Smuzhiyun /* AP/PCP default FST configuration settings */ 3252*4882a593Smuzhiyun WMI_LINK_MAINTAIN_CFG_TYPE_DEFAULT_FST_AP = 0x01, 3253*4882a593Smuzhiyun /* STA default normal (non-FST) configuration settings */ 3254*4882a593Smuzhiyun WMI_LINK_MAINTAIN_CFG_TYPE_DEFAULT_NORMAL_STA = 0x02, 3255*4882a593Smuzhiyun /* STA default FST configuration settings */ 3256*4882a593Smuzhiyun WMI_LINK_MAINTAIN_CFG_TYPE_DEFAULT_FST_STA = 0x03, 3257*4882a593Smuzhiyun /* custom configuration settings */ 3258*4882a593Smuzhiyun WMI_LINK_MAINTAIN_CFG_TYPE_CUSTOM = 0x04, 3259*4882a593Smuzhiyun /* number of defined configuration types */ 3260*4882a593Smuzhiyun WMI_LINK_MAINTAIN_CFG_TYPES_NUM = 0x05, 3261*4882a593Smuzhiyun }; 3262*4882a593Smuzhiyun 3263*4882a593Smuzhiyun /* Response status codes for WMI_LINK_MAINTAIN_CFG_WRITE/READ commands */ 3264*4882a593Smuzhiyun enum wmi_link_maintain_cfg_response_status { 3265*4882a593Smuzhiyun /* WMI_LINK_MAINTAIN_CFG_WRITE/READ command successfully accomplished 3266*4882a593Smuzhiyun */ 3267*4882a593Smuzhiyun WMI_LINK_MAINTAIN_CFG_RESPONSE_STATUS_OK = 0x00, 3268*4882a593Smuzhiyun /* ERROR due to bad argument in WMI_LINK_MAINTAIN_CFG_WRITE/READ 3269*4882a593Smuzhiyun * command request 3270*4882a593Smuzhiyun */ 3271*4882a593Smuzhiyun WMI_LINK_MAINTAIN_CFG_RESPONSE_STATUS_BAD_ARGUMENT = 0x01, 3272*4882a593Smuzhiyun }; 3273*4882a593Smuzhiyun 3274*4882a593Smuzhiyun /* Link Loss and Keep Alive configuration */ 3275*4882a593Smuzhiyun struct wmi_link_maintain_cfg { 3276*4882a593Smuzhiyun /* link_loss_enable_detectors_vec */ 3277*4882a593Smuzhiyun __le32 link_loss_enable_detectors_vec; 3278*4882a593Smuzhiyun /* detectors check period usec */ 3279*4882a593Smuzhiyun __le32 check_link_loss_period_usec; 3280*4882a593Smuzhiyun /* max allowed tx ageing */ 3281*4882a593Smuzhiyun __le32 tx_ageing_threshold_usec; 3282*4882a593Smuzhiyun /* keep alive period for high SNR */ 3283*4882a593Smuzhiyun __le32 keep_alive_period_usec_high_snr; 3284*4882a593Smuzhiyun /* keep alive period for low SNR */ 3285*4882a593Smuzhiyun __le32 keep_alive_period_usec_low_snr; 3286*4882a593Smuzhiyun /* lower snr limit for keep alive period update */ 3287*4882a593Smuzhiyun __le32 keep_alive_snr_threshold_low_db; 3288*4882a593Smuzhiyun /* upper snr limit for keep alive period update */ 3289*4882a593Smuzhiyun __le32 keep_alive_snr_threshold_high_db; 3290*4882a593Smuzhiyun /* num of successive bad bcons causing link-loss */ 3291*4882a593Smuzhiyun __le32 bad_beacons_num_threshold; 3292*4882a593Smuzhiyun /* SNR limit for bad_beacons_detector */ 3293*4882a593Smuzhiyun __le32 bad_beacons_snr_threshold_db; 3294*4882a593Smuzhiyun /* timeout for disassoc response frame in uSec */ 3295*4882a593Smuzhiyun __le32 disconnect_timeout; 3296*4882a593Smuzhiyun } __packed; 3297*4882a593Smuzhiyun 3298*4882a593Smuzhiyun /* WMI_LINK_MAINTAIN_CFG_WRITE_CMDID */ 3299*4882a593Smuzhiyun struct wmi_link_maintain_cfg_write_cmd { 3300*4882a593Smuzhiyun /* enum wmi_link_maintain_cfg_type_e - type of requested default 3301*4882a593Smuzhiyun * configuration to be applied 3302*4882a593Smuzhiyun */ 3303*4882a593Smuzhiyun __le32 cfg_type; 3304*4882a593Smuzhiyun /* requested connection ID or WMI_LINK_MAINTAIN_CFG_CID_BROADCAST */ 3305*4882a593Smuzhiyun __le32 cid; 3306*4882a593Smuzhiyun /* custom configuration settings to be applied (relevant only if 3307*4882a593Smuzhiyun * cfg_type==WMI_LINK_MAINTAIN_CFG_TYPE_CUSTOM) 3308*4882a593Smuzhiyun */ 3309*4882a593Smuzhiyun struct wmi_link_maintain_cfg lm_cfg; 3310*4882a593Smuzhiyun } __packed; 3311*4882a593Smuzhiyun 3312*4882a593Smuzhiyun /* WMI_LINK_MAINTAIN_CFG_READ_CMDID */ 3313*4882a593Smuzhiyun struct wmi_link_maintain_cfg_read_cmd { 3314*4882a593Smuzhiyun /* connection ID which configuration settings are requested */ 3315*4882a593Smuzhiyun __le32 cid; 3316*4882a593Smuzhiyun } __packed; 3317*4882a593Smuzhiyun 3318*4882a593Smuzhiyun /* WMI_SET_LINK_MONITOR_CMDID */ 3319*4882a593Smuzhiyun struct wmi_set_link_monitor_cmd { 3320*4882a593Smuzhiyun u8 rssi_hyst; 3321*4882a593Smuzhiyun u8 reserved[12]; 3322*4882a593Smuzhiyun u8 rssi_thresholds_list_size; 3323*4882a593Smuzhiyun s8 rssi_thresholds_list[]; 3324*4882a593Smuzhiyun } __packed; 3325*4882a593Smuzhiyun 3326*4882a593Smuzhiyun /* wmi_link_monitor_event_type */ 3327*4882a593Smuzhiyun enum wmi_link_monitor_event_type { 3328*4882a593Smuzhiyun WMI_LINK_MONITOR_NOTIF_RSSI_THRESHOLD_EVT = 0x00, 3329*4882a593Smuzhiyun WMI_LINK_MONITOR_NOTIF_TX_ERR_EVT = 0x01, 3330*4882a593Smuzhiyun WMI_LINK_MONITOR_NOTIF_THERMAL_EVT = 0x02, 3331*4882a593Smuzhiyun }; 3332*4882a593Smuzhiyun 3333*4882a593Smuzhiyun /* WMI_SET_LINK_MONITOR_EVENTID */ 3334*4882a593Smuzhiyun struct wmi_set_link_monitor_event { 3335*4882a593Smuzhiyun /* wmi_fw_status */ 3336*4882a593Smuzhiyun u8 status; 3337*4882a593Smuzhiyun u8 reserved[3]; 3338*4882a593Smuzhiyun } __packed; 3339*4882a593Smuzhiyun 3340*4882a593Smuzhiyun /* WMI_LINK_MONITOR_EVENTID */ 3341*4882a593Smuzhiyun struct wmi_link_monitor_event { 3342*4882a593Smuzhiyun /* link_monitor_event_type */ 3343*4882a593Smuzhiyun u8 type; 3344*4882a593Smuzhiyun s8 rssi_level; 3345*4882a593Smuzhiyun u8 reserved[2]; 3346*4882a593Smuzhiyun } __packed; 3347*4882a593Smuzhiyun 3348*4882a593Smuzhiyun /* WMI_LINK_MAINTAIN_CFG_WRITE_DONE_EVENTID */ 3349*4882a593Smuzhiyun struct wmi_link_maintain_cfg_write_done_event { 3350*4882a593Smuzhiyun /* requested connection ID */ 3351*4882a593Smuzhiyun __le32 cid; 3352*4882a593Smuzhiyun /* wmi_link_maintain_cfg_response_status_e - write status */ 3353*4882a593Smuzhiyun __le32 status; 3354*4882a593Smuzhiyun } __packed; 3355*4882a593Smuzhiyun 3356*4882a593Smuzhiyun /* \WMI_LINK_MAINTAIN_CFG_READ_DONE_EVENT */ 3357*4882a593Smuzhiyun struct wmi_link_maintain_cfg_read_done_event { 3358*4882a593Smuzhiyun /* requested connection ID */ 3359*4882a593Smuzhiyun __le32 cid; 3360*4882a593Smuzhiyun /* wmi_link_maintain_cfg_response_status_e - read status */ 3361*4882a593Smuzhiyun __le32 status; 3362*4882a593Smuzhiyun /* Retrieved configuration settings */ 3363*4882a593Smuzhiyun struct wmi_link_maintain_cfg lm_cfg; 3364*4882a593Smuzhiyun } __packed; 3365*4882a593Smuzhiyun 3366*4882a593Smuzhiyun enum wmi_traffic_suspend_status { 3367*4882a593Smuzhiyun WMI_TRAFFIC_SUSPEND_APPROVED = 0x0, 3368*4882a593Smuzhiyun WMI_TRAFFIC_SUSPEND_REJECTED_LINK_NOT_IDLE = 0x1, 3369*4882a593Smuzhiyun WMI_TRAFFIC_SUSPEND_REJECTED_DISCONNECT = 0x2, 3370*4882a593Smuzhiyun WMI_TRAFFIC_SUSPEND_REJECTED_OTHER = 0x3, 3371*4882a593Smuzhiyun }; 3372*4882a593Smuzhiyun 3373*4882a593Smuzhiyun /* WMI_TRAFFIC_SUSPEND_EVENTID */ 3374*4882a593Smuzhiyun struct wmi_traffic_suspend_event { 3375*4882a593Smuzhiyun /* enum wmi_traffic_suspend_status_e */ 3376*4882a593Smuzhiyun u8 status; 3377*4882a593Smuzhiyun } __packed; 3378*4882a593Smuzhiyun 3379*4882a593Smuzhiyun enum wmi_traffic_resume_status { 3380*4882a593Smuzhiyun WMI_TRAFFIC_RESUME_SUCCESS = 0x0, 3381*4882a593Smuzhiyun WMI_TRAFFIC_RESUME_FAILED = 0x1, 3382*4882a593Smuzhiyun }; 3383*4882a593Smuzhiyun 3384*4882a593Smuzhiyun enum wmi_resume_trigger { 3385*4882a593Smuzhiyun WMI_RESUME_TRIGGER_UNKNOWN = 0x0, 3386*4882a593Smuzhiyun WMI_RESUME_TRIGGER_HOST = 0x1, 3387*4882a593Smuzhiyun WMI_RESUME_TRIGGER_UCAST_RX = 0x2, 3388*4882a593Smuzhiyun WMI_RESUME_TRIGGER_BCAST_RX = 0x4, 3389*4882a593Smuzhiyun WMI_RESUME_TRIGGER_WMI_EVT = 0x8, 3390*4882a593Smuzhiyun WMI_RESUME_TRIGGER_DISCONNECT = 0x10, 3391*4882a593Smuzhiyun }; 3392*4882a593Smuzhiyun 3393*4882a593Smuzhiyun /* WMI_TRAFFIC_RESUME_EVENTID */ 3394*4882a593Smuzhiyun struct wmi_traffic_resume_event { 3395*4882a593Smuzhiyun /* enum wmi_traffic_resume_status */ 3396*4882a593Smuzhiyun u8 status; 3397*4882a593Smuzhiyun u8 reserved[3]; 3398*4882a593Smuzhiyun /* enum wmi_resume_trigger bitmap */ 3399*4882a593Smuzhiyun __le32 resume_triggers; 3400*4882a593Smuzhiyun } __packed; 3401*4882a593Smuzhiyun 3402*4882a593Smuzhiyun /* Power Save command completion status codes */ 3403*4882a593Smuzhiyun enum wmi_ps_cfg_cmd_status { 3404*4882a593Smuzhiyun WMI_PS_CFG_CMD_STATUS_SUCCESS = 0x00, 3405*4882a593Smuzhiyun WMI_PS_CFG_CMD_STATUS_BAD_PARAM = 0x01, 3406*4882a593Smuzhiyun /* other error */ 3407*4882a593Smuzhiyun WMI_PS_CFG_CMD_STATUS_ERROR = 0x02, 3408*4882a593Smuzhiyun }; 3409*4882a593Smuzhiyun 3410*4882a593Smuzhiyun /* Device Power Save Profiles */ 3411*4882a593Smuzhiyun enum wmi_ps_profile_type { 3412*4882a593Smuzhiyun WMI_PS_PROFILE_TYPE_DEFAULT = 0x00, 3413*4882a593Smuzhiyun WMI_PS_PROFILE_TYPE_PS_DISABLED = 0x01, 3414*4882a593Smuzhiyun WMI_PS_PROFILE_TYPE_MAX_PS = 0x02, 3415*4882a593Smuzhiyun WMI_PS_PROFILE_TYPE_LOW_LATENCY_PS = 0x03, 3416*4882a593Smuzhiyun }; 3417*4882a593Smuzhiyun 3418*4882a593Smuzhiyun /* WMI_PS_DEV_PROFILE_CFG_READ_CMDID */ 3419*4882a593Smuzhiyun struct wmi_ps_dev_profile_cfg_read_cmd { 3420*4882a593Smuzhiyun /* reserved */ 3421*4882a593Smuzhiyun __le32 reserved; 3422*4882a593Smuzhiyun } __packed; 3423*4882a593Smuzhiyun 3424*4882a593Smuzhiyun /* WMI_PS_DEV_PROFILE_CFG_READ_EVENTID */ 3425*4882a593Smuzhiyun struct wmi_ps_dev_profile_cfg_read_event { 3426*4882a593Smuzhiyun /* wmi_ps_profile_type_e */ 3427*4882a593Smuzhiyun u8 ps_profile; 3428*4882a593Smuzhiyun u8 reserved[3]; 3429*4882a593Smuzhiyun } __packed; 3430*4882a593Smuzhiyun 3431*4882a593Smuzhiyun /* WMI_PS_DEV_PROFILE_CFG_CMDID 3432*4882a593Smuzhiyun * 3433*4882a593Smuzhiyun * Power save profile to be used by the device 3434*4882a593Smuzhiyun * 3435*4882a593Smuzhiyun * Returned event: 3436*4882a593Smuzhiyun * - WMI_PS_DEV_PROFILE_CFG_EVENTID 3437*4882a593Smuzhiyun */ 3438*4882a593Smuzhiyun struct wmi_ps_dev_profile_cfg_cmd { 3439*4882a593Smuzhiyun /* wmi_ps_profile_type_e */ 3440*4882a593Smuzhiyun u8 ps_profile; 3441*4882a593Smuzhiyun u8 reserved[3]; 3442*4882a593Smuzhiyun } __packed; 3443*4882a593Smuzhiyun 3444*4882a593Smuzhiyun /* WMI_PS_DEV_PROFILE_CFG_EVENTID */ 3445*4882a593Smuzhiyun struct wmi_ps_dev_profile_cfg_event { 3446*4882a593Smuzhiyun /* wmi_ps_cfg_cmd_status_e */ 3447*4882a593Smuzhiyun __le32 status; 3448*4882a593Smuzhiyun } __packed; 3449*4882a593Smuzhiyun 3450*4882a593Smuzhiyun enum wmi_ps_level { 3451*4882a593Smuzhiyun WMI_PS_LEVEL_DEEP_SLEEP = 0x00, 3452*4882a593Smuzhiyun WMI_PS_LEVEL_SHALLOW_SLEEP = 0x01, 3453*4882a593Smuzhiyun /* awake = all PS mechanisms are disabled */ 3454*4882a593Smuzhiyun WMI_PS_LEVEL_AWAKE = 0x02, 3455*4882a593Smuzhiyun }; 3456*4882a593Smuzhiyun 3457*4882a593Smuzhiyun enum wmi_ps_deep_sleep_clk_level { 3458*4882a593Smuzhiyun /* 33k */ 3459*4882a593Smuzhiyun WMI_PS_DEEP_SLEEP_CLK_LEVEL_RTC = 0x00, 3460*4882a593Smuzhiyun /* 10k */ 3461*4882a593Smuzhiyun WMI_PS_DEEP_SLEEP_CLK_LEVEL_OSC = 0x01, 3462*4882a593Smuzhiyun /* @RTC Low latency */ 3463*4882a593Smuzhiyun WMI_PS_DEEP_SLEEP_CLK_LEVEL_RTC_LT = 0x02, 3464*4882a593Smuzhiyun WMI_PS_DEEP_SLEEP_CLK_LEVEL_XTAL = 0x03, 3465*4882a593Smuzhiyun WMI_PS_DEEP_SLEEP_CLK_LEVEL_SYSCLK = 0x04, 3466*4882a593Smuzhiyun /* Not Applicable */ 3467*4882a593Smuzhiyun WMI_PS_DEEP_SLEEP_CLK_LEVEL_N_A = 0xFF, 3468*4882a593Smuzhiyun }; 3469*4882a593Smuzhiyun 3470*4882a593Smuzhiyun /* Response by the FW to a D3 entry request */ 3471*4882a593Smuzhiyun enum wmi_ps_d3_resp_policy { 3472*4882a593Smuzhiyun WMI_PS_D3_RESP_POLICY_DEFAULT = 0x00, 3473*4882a593Smuzhiyun /* debug -D3 req is always denied */ 3474*4882a593Smuzhiyun WMI_PS_D3_RESP_POLICY_DENIED = 0x01, 3475*4882a593Smuzhiyun /* debug -D3 req is always approved */ 3476*4882a593Smuzhiyun WMI_PS_D3_RESP_POLICY_APPROVED = 0x02, 3477*4882a593Smuzhiyun }; 3478*4882a593Smuzhiyun 3479*4882a593Smuzhiyun #define WMI_AOA_MAX_DATA_SIZE (128) 3480*4882a593Smuzhiyun 3481*4882a593Smuzhiyun enum wmi_aoa_meas_status { 3482*4882a593Smuzhiyun WMI_AOA_MEAS_SUCCESS = 0x00, 3483*4882a593Smuzhiyun WMI_AOA_MEAS_PEER_INCAPABLE = 0x01, 3484*4882a593Smuzhiyun WMI_AOA_MEAS_FAILURE = 0x02, 3485*4882a593Smuzhiyun }; 3486*4882a593Smuzhiyun 3487*4882a593Smuzhiyun /* WMI_AOA_MEAS_EVENTID */ 3488*4882a593Smuzhiyun struct wmi_aoa_meas_event { 3489*4882a593Smuzhiyun u8 mac_addr[WMI_MAC_LEN]; 3490*4882a593Smuzhiyun /* channels IDs: 3491*4882a593Smuzhiyun * 0 - 58320 MHz 3492*4882a593Smuzhiyun * 1 - 60480 MHz 3493*4882a593Smuzhiyun * 2 - 62640 MHz 3494*4882a593Smuzhiyun */ 3495*4882a593Smuzhiyun u8 channel; 3496*4882a593Smuzhiyun /* enum wmi_aoa_meas_type */ 3497*4882a593Smuzhiyun u8 aoa_meas_type; 3498*4882a593Smuzhiyun /* Measurments are from RFs, defined by the mask */ 3499*4882a593Smuzhiyun __le32 meas_rf_mask; 3500*4882a593Smuzhiyun /* enum wmi_aoa_meas_status */ 3501*4882a593Smuzhiyun u8 meas_status; 3502*4882a593Smuzhiyun u8 reserved; 3503*4882a593Smuzhiyun /* Length of meas_data in bytes */ 3504*4882a593Smuzhiyun __le16 length; 3505*4882a593Smuzhiyun u8 meas_data[WMI_AOA_MAX_DATA_SIZE]; 3506*4882a593Smuzhiyun } __packed; 3507*4882a593Smuzhiyun 3508*4882a593Smuzhiyun /* WMI_SET_MGMT_RETRY_LIMIT_EVENTID */ 3509*4882a593Smuzhiyun struct wmi_set_mgmt_retry_limit_event { 3510*4882a593Smuzhiyun /* enum wmi_fw_status */ 3511*4882a593Smuzhiyun u8 status; 3512*4882a593Smuzhiyun /* alignment to 32b */ 3513*4882a593Smuzhiyun u8 reserved[3]; 3514*4882a593Smuzhiyun } __packed; 3515*4882a593Smuzhiyun 3516*4882a593Smuzhiyun /* WMI_GET_MGMT_RETRY_LIMIT_EVENTID */ 3517*4882a593Smuzhiyun struct wmi_get_mgmt_retry_limit_event { 3518*4882a593Smuzhiyun /* MAC retransmit limit for mgmt frames */ 3519*4882a593Smuzhiyun u8 mgmt_retry_limit; 3520*4882a593Smuzhiyun /* alignment to 32b */ 3521*4882a593Smuzhiyun u8 reserved[3]; 3522*4882a593Smuzhiyun } __packed; 3523*4882a593Smuzhiyun 3524*4882a593Smuzhiyun /* WMI_TOF_GET_CAPABILITIES_EVENTID */ 3525*4882a593Smuzhiyun struct wmi_tof_get_capabilities_event { 3526*4882a593Smuzhiyun u8 ftm_capability; 3527*4882a593Smuzhiyun /* maximum supported number of destination to start TOF */ 3528*4882a593Smuzhiyun u8 max_num_of_dest; 3529*4882a593Smuzhiyun /* maximum supported number of measurements per burst */ 3530*4882a593Smuzhiyun u8 max_num_of_meas_per_burst; 3531*4882a593Smuzhiyun u8 reserved; 3532*4882a593Smuzhiyun /* maximum supported multi bursts */ 3533*4882a593Smuzhiyun __le16 max_multi_bursts_sessions; 3534*4882a593Smuzhiyun /* maximum supported FTM burst duration , wmi_tof_burst_duration_e */ 3535*4882a593Smuzhiyun __le16 max_ftm_burst_duration; 3536*4882a593Smuzhiyun /* AOA supported types */ 3537*4882a593Smuzhiyun __le32 aoa_supported_types; 3538*4882a593Smuzhiyun } __packed; 3539*4882a593Smuzhiyun 3540*4882a593Smuzhiyun /* WMI_SET_THERMAL_THROTTLING_CFG_EVENTID */ 3541*4882a593Smuzhiyun struct wmi_set_thermal_throttling_cfg_event { 3542*4882a593Smuzhiyun /* wmi_fw_status */ 3543*4882a593Smuzhiyun u8 status; 3544*4882a593Smuzhiyun u8 reserved[3]; 3545*4882a593Smuzhiyun } __packed; 3546*4882a593Smuzhiyun 3547*4882a593Smuzhiyun /* WMI_GET_THERMAL_THROTTLING_CFG_EVENTID */ 3548*4882a593Smuzhiyun struct wmi_get_thermal_throttling_cfg_event { 3549*4882a593Smuzhiyun /* Status data */ 3550*4882a593Smuzhiyun struct wmi_tt_data tt_data; 3551*4882a593Smuzhiyun } __packed; 3552*4882a593Smuzhiyun 3553*4882a593Smuzhiyun enum wmi_tof_session_end_status { 3554*4882a593Smuzhiyun WMI_TOF_SESSION_END_NO_ERROR = 0x00, 3555*4882a593Smuzhiyun WMI_TOF_SESSION_END_FAIL = 0x01, 3556*4882a593Smuzhiyun WMI_TOF_SESSION_END_PARAMS_ERROR = 0x02, 3557*4882a593Smuzhiyun WMI_TOF_SESSION_END_ABORTED = 0x03, 3558*4882a593Smuzhiyun WMI_TOF_SESSION_END_BUSY = 0x04, 3559*4882a593Smuzhiyun }; 3560*4882a593Smuzhiyun 3561*4882a593Smuzhiyun /* WMI_TOF_SESSION_END_EVENTID */ 3562*4882a593Smuzhiyun struct wmi_tof_session_end_event { 3563*4882a593Smuzhiyun /* FTM session ID */ 3564*4882a593Smuzhiyun __le32 session_id; 3565*4882a593Smuzhiyun /* wmi_tof_session_end_status_e */ 3566*4882a593Smuzhiyun u8 status; 3567*4882a593Smuzhiyun u8 reserved[3]; 3568*4882a593Smuzhiyun } __packed; 3569*4882a593Smuzhiyun 3570*4882a593Smuzhiyun /* WMI_TOF_SET_LCI_EVENTID */ 3571*4882a593Smuzhiyun struct wmi_tof_set_lci_event { 3572*4882a593Smuzhiyun /* enum wmi_fw_status */ 3573*4882a593Smuzhiyun u8 status; 3574*4882a593Smuzhiyun u8 reserved[3]; 3575*4882a593Smuzhiyun } __packed; 3576*4882a593Smuzhiyun 3577*4882a593Smuzhiyun /* WMI_TOF_SET_LCR_EVENTID */ 3578*4882a593Smuzhiyun struct wmi_tof_set_lcr_event { 3579*4882a593Smuzhiyun /* enum wmi_fw_status */ 3580*4882a593Smuzhiyun u8 status; 3581*4882a593Smuzhiyun u8 reserved[3]; 3582*4882a593Smuzhiyun } __packed; 3583*4882a593Smuzhiyun 3584*4882a593Smuzhiyun /* Responder FTM Results */ 3585*4882a593Smuzhiyun struct wmi_responder_ftm_res { 3586*4882a593Smuzhiyun u8 t1[6]; 3587*4882a593Smuzhiyun u8 t2[6]; 3588*4882a593Smuzhiyun u8 t3[6]; 3589*4882a593Smuzhiyun u8 t4[6]; 3590*4882a593Smuzhiyun __le16 tod_err; 3591*4882a593Smuzhiyun __le16 toa_err; 3592*4882a593Smuzhiyun __le16 tod_err_initiator; 3593*4882a593Smuzhiyun __le16 toa_err_initiator; 3594*4882a593Smuzhiyun } __packed; 3595*4882a593Smuzhiyun 3596*4882a593Smuzhiyun enum wmi_tof_ftm_per_dest_res_status { 3597*4882a593Smuzhiyun WMI_PER_DEST_RES_NO_ERROR = 0x00, 3598*4882a593Smuzhiyun WMI_PER_DEST_RES_TX_RX_FAIL = 0x01, 3599*4882a593Smuzhiyun WMI_PER_DEST_RES_PARAM_DONT_MATCH = 0x02, 3600*4882a593Smuzhiyun }; 3601*4882a593Smuzhiyun 3602*4882a593Smuzhiyun enum wmi_tof_ftm_per_dest_res_flags { 3603*4882a593Smuzhiyun WMI_PER_DEST_RES_REQ_START = 0x01, 3604*4882a593Smuzhiyun WMI_PER_DEST_RES_BURST_REPORT_END = 0x02, 3605*4882a593Smuzhiyun WMI_PER_DEST_RES_REQ_END = 0x04, 3606*4882a593Smuzhiyun WMI_PER_DEST_RES_PARAM_UPDATE = 0x08, 3607*4882a593Smuzhiyun }; 3608*4882a593Smuzhiyun 3609*4882a593Smuzhiyun /* WMI_TOF_FTM_PER_DEST_RES_EVENTID */ 3610*4882a593Smuzhiyun struct wmi_tof_ftm_per_dest_res_event { 3611*4882a593Smuzhiyun /* FTM session ID */ 3612*4882a593Smuzhiyun __le32 session_id; 3613*4882a593Smuzhiyun /* destination MAC address */ 3614*4882a593Smuzhiyun u8 dst_mac[WMI_MAC_LEN]; 3615*4882a593Smuzhiyun /* wmi_tof_ftm_per_dest_res_flags_e */ 3616*4882a593Smuzhiyun u8 flags; 3617*4882a593Smuzhiyun /* wmi_tof_ftm_per_dest_res_status_e */ 3618*4882a593Smuzhiyun u8 status; 3619*4882a593Smuzhiyun /* responder ASAP */ 3620*4882a593Smuzhiyun u8 responder_asap; 3621*4882a593Smuzhiyun /* responder number of FTM per burst */ 3622*4882a593Smuzhiyun u8 responder_num_ftm_per_burst; 3623*4882a593Smuzhiyun /* responder number of FTM burst exponent */ 3624*4882a593Smuzhiyun u8 responder_num_ftm_bursts_exp; 3625*4882a593Smuzhiyun /* responder burst duration ,wmi_tof_burst_duration_e */ 3626*4882a593Smuzhiyun u8 responder_burst_duration; 3627*4882a593Smuzhiyun /* responder burst period, indicate interval between two consecutive 3628*4882a593Smuzhiyun * burst instances, in units of 100 ms 3629*4882a593Smuzhiyun */ 3630*4882a593Smuzhiyun __le16 responder_burst_period; 3631*4882a593Smuzhiyun /* receive burst counter */ 3632*4882a593Smuzhiyun __le16 bursts_cnt; 3633*4882a593Smuzhiyun /* tsf of responder start burst */ 3634*4882a593Smuzhiyun __le32 tsf_sync; 3635*4882a593Smuzhiyun /* actual received ftm per burst */ 3636*4882a593Smuzhiyun u8 actual_ftm_per_burst; 3637*4882a593Smuzhiyun /* Measurments are from RFs, defined by the mask */ 3638*4882a593Smuzhiyun __le32 meas_rf_mask; 3639*4882a593Smuzhiyun u8 reserved0[3]; 3640*4882a593Smuzhiyun struct wmi_responder_ftm_res responder_ftm_res[]; 3641*4882a593Smuzhiyun } __packed; 3642*4882a593Smuzhiyun 3643*4882a593Smuzhiyun /* WMI_TOF_CFG_RESPONDER_EVENTID */ 3644*4882a593Smuzhiyun struct wmi_tof_cfg_responder_event { 3645*4882a593Smuzhiyun /* enum wmi_fw_status */ 3646*4882a593Smuzhiyun u8 status; 3647*4882a593Smuzhiyun u8 reserved[3]; 3648*4882a593Smuzhiyun } __packed; 3649*4882a593Smuzhiyun 3650*4882a593Smuzhiyun enum wmi_tof_channel_info_type { 3651*4882a593Smuzhiyun WMI_TOF_CHANNEL_INFO_AOA = 0x00, 3652*4882a593Smuzhiyun WMI_TOF_CHANNEL_INFO_LCI = 0x01, 3653*4882a593Smuzhiyun WMI_TOF_CHANNEL_INFO_LCR = 0x02, 3654*4882a593Smuzhiyun WMI_TOF_CHANNEL_INFO_VENDOR_SPECIFIC = 0x03, 3655*4882a593Smuzhiyun WMI_TOF_CHANNEL_INFO_CIR = 0x04, 3656*4882a593Smuzhiyun WMI_TOF_CHANNEL_INFO_RSSI = 0x05, 3657*4882a593Smuzhiyun WMI_TOF_CHANNEL_INFO_SNR = 0x06, 3658*4882a593Smuzhiyun WMI_TOF_CHANNEL_INFO_DEBUG = 0x07, 3659*4882a593Smuzhiyun }; 3660*4882a593Smuzhiyun 3661*4882a593Smuzhiyun /* WMI_TOF_CHANNEL_INFO_EVENTID */ 3662*4882a593Smuzhiyun struct wmi_tof_channel_info_event { 3663*4882a593Smuzhiyun /* FTM session ID */ 3664*4882a593Smuzhiyun __le32 session_id; 3665*4882a593Smuzhiyun /* destination MAC address */ 3666*4882a593Smuzhiyun u8 dst_mac[WMI_MAC_LEN]; 3667*4882a593Smuzhiyun /* wmi_tof_channel_info_type_e */ 3668*4882a593Smuzhiyun u8 type; 3669*4882a593Smuzhiyun /* data report length */ 3670*4882a593Smuzhiyun u8 len; 3671*4882a593Smuzhiyun /* data report payload */ 3672*4882a593Smuzhiyun u8 report[]; 3673*4882a593Smuzhiyun } __packed; 3674*4882a593Smuzhiyun 3675*4882a593Smuzhiyun /* WMI_TOF_SET_TX_RX_OFFSET_EVENTID */ 3676*4882a593Smuzhiyun struct wmi_tof_set_tx_rx_offset_event { 3677*4882a593Smuzhiyun /* enum wmi_fw_status */ 3678*4882a593Smuzhiyun u8 status; 3679*4882a593Smuzhiyun u8 reserved[3]; 3680*4882a593Smuzhiyun } __packed; 3681*4882a593Smuzhiyun 3682*4882a593Smuzhiyun /* WMI_TOF_GET_TX_RX_OFFSET_EVENTID */ 3683*4882a593Smuzhiyun struct wmi_tof_get_tx_rx_offset_event { 3684*4882a593Smuzhiyun /* enum wmi_fw_status */ 3685*4882a593Smuzhiyun u8 status; 3686*4882a593Smuzhiyun /* RF index used to read the offsets */ 3687*4882a593Smuzhiyun u8 rf_index; 3688*4882a593Smuzhiyun u8 reserved1[2]; 3689*4882a593Smuzhiyun /* TX delay offset */ 3690*4882a593Smuzhiyun __le32 tx_offset; 3691*4882a593Smuzhiyun /* RX delay offset */ 3692*4882a593Smuzhiyun __le32 rx_offset; 3693*4882a593Smuzhiyun /* Offset to strongest tap of CIR */ 3694*4882a593Smuzhiyun __le32 precursor; 3695*4882a593Smuzhiyun } __packed; 3696*4882a593Smuzhiyun 3697*4882a593Smuzhiyun /* Result status codes for WMI commands */ 3698*4882a593Smuzhiyun enum wmi_rf_sector_status { 3699*4882a593Smuzhiyun WMI_RF_SECTOR_STATUS_SUCCESS = 0x00, 3700*4882a593Smuzhiyun WMI_RF_SECTOR_STATUS_BAD_PARAMETERS_ERROR = 0x01, 3701*4882a593Smuzhiyun WMI_RF_SECTOR_STATUS_BUSY_ERROR = 0x02, 3702*4882a593Smuzhiyun WMI_RF_SECTOR_STATUS_NOT_SUPPORTED_ERROR = 0x03, 3703*4882a593Smuzhiyun }; 3704*4882a593Smuzhiyun 3705*4882a593Smuzhiyun /* Types of the RF sector (TX,RX) */ 3706*4882a593Smuzhiyun enum wmi_rf_sector_type { 3707*4882a593Smuzhiyun WMI_RF_SECTOR_TYPE_RX = 0x00, 3708*4882a593Smuzhiyun WMI_RF_SECTOR_TYPE_TX = 0x01, 3709*4882a593Smuzhiyun }; 3710*4882a593Smuzhiyun 3711*4882a593Smuzhiyun /* Content of RF Sector (six 32-bits registers) */ 3712*4882a593Smuzhiyun struct wmi_rf_sector_info { 3713*4882a593Smuzhiyun /* Phase values for RF Chains[15-0] (2bits per RF chain) */ 3714*4882a593Smuzhiyun __le32 psh_hi; 3715*4882a593Smuzhiyun /* Phase values for RF Chains[31-16] (2bits per RF chain) */ 3716*4882a593Smuzhiyun __le32 psh_lo; 3717*4882a593Smuzhiyun /* ETYPE Bit0 for all RF chains[31-0] - bit0 of Edge amplifier gain 3718*4882a593Smuzhiyun * index 3719*4882a593Smuzhiyun */ 3720*4882a593Smuzhiyun __le32 etype0; 3721*4882a593Smuzhiyun /* ETYPE Bit1 for all RF chains[31-0] - bit1 of Edge amplifier gain 3722*4882a593Smuzhiyun * index 3723*4882a593Smuzhiyun */ 3724*4882a593Smuzhiyun __le32 etype1; 3725*4882a593Smuzhiyun /* ETYPE Bit2 for all RF chains[31-0] - bit2 of Edge amplifier gain 3726*4882a593Smuzhiyun * index 3727*4882a593Smuzhiyun */ 3728*4882a593Smuzhiyun __le32 etype2; 3729*4882a593Smuzhiyun /* D-Type values (3bits each) for 8 Distribution amplifiers + X16 3730*4882a593Smuzhiyun * switch bits 3731*4882a593Smuzhiyun */ 3732*4882a593Smuzhiyun __le32 dtype_swch_off; 3733*4882a593Smuzhiyun } __packed; 3734*4882a593Smuzhiyun 3735*4882a593Smuzhiyun #define WMI_INVALID_RF_SECTOR_INDEX (0xFFFF) 3736*4882a593Smuzhiyun #define WMI_MAX_RF_MODULES_NUM (8) 3737*4882a593Smuzhiyun 3738*4882a593Smuzhiyun /* WMI_GET_RF_SECTOR_PARAMS_CMD */ 3739*4882a593Smuzhiyun struct wmi_get_rf_sector_params_cmd { 3740*4882a593Smuzhiyun /* Sector number to be retrieved */ 3741*4882a593Smuzhiyun __le16 sector_idx; 3742*4882a593Smuzhiyun /* enum wmi_rf_sector_type - type of requested RF sector */ 3743*4882a593Smuzhiyun u8 sector_type; 3744*4882a593Smuzhiyun /* bitmask vector specifying destination RF modules */ 3745*4882a593Smuzhiyun u8 rf_modules_vec; 3746*4882a593Smuzhiyun } __packed; 3747*4882a593Smuzhiyun 3748*4882a593Smuzhiyun /* \WMI_GET_RF_SECTOR_PARAMS_DONE_EVENT */ 3749*4882a593Smuzhiyun struct wmi_get_rf_sector_params_done_event { 3750*4882a593Smuzhiyun /* result status of WMI_GET_RF_SECTOR_PARAMS_CMD (enum 3751*4882a593Smuzhiyun * wmi_rf_sector_status) 3752*4882a593Smuzhiyun */ 3753*4882a593Smuzhiyun u8 status; 3754*4882a593Smuzhiyun /* align next field to U64 boundary */ 3755*4882a593Smuzhiyun u8 reserved[7]; 3756*4882a593Smuzhiyun /* TSF timestamp when RF sectors where retrieved */ 3757*4882a593Smuzhiyun __le64 tsf; 3758*4882a593Smuzhiyun /* Content of RF sector retrieved from each RF module */ 3759*4882a593Smuzhiyun struct wmi_rf_sector_info sectors_info[WMI_MAX_RF_MODULES_NUM]; 3760*4882a593Smuzhiyun } __packed; 3761*4882a593Smuzhiyun 3762*4882a593Smuzhiyun /* WMI_SET_RF_SECTOR_PARAMS_CMD */ 3763*4882a593Smuzhiyun struct wmi_set_rf_sector_params_cmd { 3764*4882a593Smuzhiyun /* Sector number to be retrieved */ 3765*4882a593Smuzhiyun __le16 sector_idx; 3766*4882a593Smuzhiyun /* enum wmi_rf_sector_type - type of requested RF sector */ 3767*4882a593Smuzhiyun u8 sector_type; 3768*4882a593Smuzhiyun /* bitmask vector specifying destination RF modules */ 3769*4882a593Smuzhiyun u8 rf_modules_vec; 3770*4882a593Smuzhiyun /* Content of RF sector to be written to each RF module */ 3771*4882a593Smuzhiyun struct wmi_rf_sector_info sectors_info[WMI_MAX_RF_MODULES_NUM]; 3772*4882a593Smuzhiyun } __packed; 3773*4882a593Smuzhiyun 3774*4882a593Smuzhiyun /* \WMI_SET_RF_SECTOR_PARAMS_DONE_EVENT */ 3775*4882a593Smuzhiyun struct wmi_set_rf_sector_params_done_event { 3776*4882a593Smuzhiyun /* result status of WMI_SET_RF_SECTOR_PARAMS_CMD (enum 3777*4882a593Smuzhiyun * wmi_rf_sector_status) 3778*4882a593Smuzhiyun */ 3779*4882a593Smuzhiyun u8 status; 3780*4882a593Smuzhiyun } __packed; 3781*4882a593Smuzhiyun 3782*4882a593Smuzhiyun /* WMI_GET_SELECTED_RF_SECTOR_INDEX_CMD - Get RF sector index selected by 3783*4882a593Smuzhiyun * TXSS/BRP for communication with specified CID 3784*4882a593Smuzhiyun */ 3785*4882a593Smuzhiyun struct wmi_get_selected_rf_sector_index_cmd { 3786*4882a593Smuzhiyun /* Connection/Station ID in [0:7] range */ 3787*4882a593Smuzhiyun u8 cid; 3788*4882a593Smuzhiyun /* type of requested RF sector (enum wmi_rf_sector_type) */ 3789*4882a593Smuzhiyun u8 sector_type; 3790*4882a593Smuzhiyun /* align to U32 boundary */ 3791*4882a593Smuzhiyun u8 reserved[2]; 3792*4882a593Smuzhiyun } __packed; 3793*4882a593Smuzhiyun 3794*4882a593Smuzhiyun /* \WMI_GET_SELECTED_RF_SECTOR_INDEX_DONE_EVENT - Returns retrieved RF sector 3795*4882a593Smuzhiyun * index selected by TXSS/BRP for communication with specified CID 3796*4882a593Smuzhiyun */ 3797*4882a593Smuzhiyun struct wmi_get_selected_rf_sector_index_done_event { 3798*4882a593Smuzhiyun /* Retrieved sector index selected in TXSS (for TX sector request) or 3799*4882a593Smuzhiyun * BRP (for RX sector request) 3800*4882a593Smuzhiyun */ 3801*4882a593Smuzhiyun __le16 sector_idx; 3802*4882a593Smuzhiyun /* result status of WMI_GET_SELECTED_RF_SECTOR_INDEX_CMD (enum 3803*4882a593Smuzhiyun * wmi_rf_sector_status) 3804*4882a593Smuzhiyun */ 3805*4882a593Smuzhiyun u8 status; 3806*4882a593Smuzhiyun /* align next field to U64 boundary */ 3807*4882a593Smuzhiyun u8 reserved[5]; 3808*4882a593Smuzhiyun /* TSF timestamp when result was retrieved */ 3809*4882a593Smuzhiyun __le64 tsf; 3810*4882a593Smuzhiyun } __packed; 3811*4882a593Smuzhiyun 3812*4882a593Smuzhiyun /* WMI_SET_SELECTED_RF_SECTOR_INDEX_CMD - Force RF sector index for 3813*4882a593Smuzhiyun * communication with specified CID. Assumes that TXSS/BRP is disabled by 3814*4882a593Smuzhiyun * other command 3815*4882a593Smuzhiyun */ 3816*4882a593Smuzhiyun struct wmi_set_selected_rf_sector_index_cmd { 3817*4882a593Smuzhiyun /* Connection/Station ID in [0:7] range */ 3818*4882a593Smuzhiyun u8 cid; 3819*4882a593Smuzhiyun /* type of requested RF sector (enum wmi_rf_sector_type) */ 3820*4882a593Smuzhiyun u8 sector_type; 3821*4882a593Smuzhiyun /* Forced sector index */ 3822*4882a593Smuzhiyun __le16 sector_idx; 3823*4882a593Smuzhiyun } __packed; 3824*4882a593Smuzhiyun 3825*4882a593Smuzhiyun /* \WMI_SET_SELECTED_RF_SECTOR_INDEX_DONE_EVENT - Success/Fail status for 3826*4882a593Smuzhiyun * WMI_SET_SELECTED_RF_SECTOR_INDEX_CMD 3827*4882a593Smuzhiyun */ 3828*4882a593Smuzhiyun struct wmi_set_selected_rf_sector_index_done_event { 3829*4882a593Smuzhiyun /* result status of WMI_SET_SELECTED_RF_SECTOR_INDEX_CMD (enum 3830*4882a593Smuzhiyun * wmi_rf_sector_status) 3831*4882a593Smuzhiyun */ 3832*4882a593Smuzhiyun u8 status; 3833*4882a593Smuzhiyun /* align to U32 boundary */ 3834*4882a593Smuzhiyun u8 reserved[3]; 3835*4882a593Smuzhiyun } __packed; 3836*4882a593Smuzhiyun 3837*4882a593Smuzhiyun /* WMI_SET_RF_SECTOR_ON_CMD - Activates specified sector for specified rf 3838*4882a593Smuzhiyun * modules 3839*4882a593Smuzhiyun */ 3840*4882a593Smuzhiyun struct wmi_set_rf_sector_on_cmd { 3841*4882a593Smuzhiyun /* Sector index to be activated */ 3842*4882a593Smuzhiyun __le16 sector_idx; 3843*4882a593Smuzhiyun /* type of requested RF sector (enum wmi_rf_sector_type) */ 3844*4882a593Smuzhiyun u8 sector_type; 3845*4882a593Smuzhiyun /* bitmask vector specifying destination RF modules */ 3846*4882a593Smuzhiyun u8 rf_modules_vec; 3847*4882a593Smuzhiyun } __packed; 3848*4882a593Smuzhiyun 3849*4882a593Smuzhiyun /* \WMI_SET_RF_SECTOR_ON_DONE_EVENT - Success/Fail status for 3850*4882a593Smuzhiyun * WMI_SET_RF_SECTOR_ON_CMD 3851*4882a593Smuzhiyun */ 3852*4882a593Smuzhiyun struct wmi_set_rf_sector_on_done_event { 3853*4882a593Smuzhiyun /* result status of WMI_SET_RF_SECTOR_ON_CMD (enum 3854*4882a593Smuzhiyun * wmi_rf_sector_status) 3855*4882a593Smuzhiyun */ 3856*4882a593Smuzhiyun u8 status; 3857*4882a593Smuzhiyun /* align to U32 boundary */ 3858*4882a593Smuzhiyun u8 reserved[3]; 3859*4882a593Smuzhiyun } __packed; 3860*4882a593Smuzhiyun 3861*4882a593Smuzhiyun enum wmi_sector_sweep_type { 3862*4882a593Smuzhiyun WMI_SECTOR_SWEEP_TYPE_TXSS = 0x00, 3863*4882a593Smuzhiyun WMI_SECTOR_SWEEP_TYPE_BCON = 0x01, 3864*4882a593Smuzhiyun WMI_SECTOR_SWEEP_TYPE_TXSS_AND_BCON = 0x02, 3865*4882a593Smuzhiyun WMI_SECTOR_SWEEP_TYPE_NUM = 0x03, 3866*4882a593Smuzhiyun }; 3867*4882a593Smuzhiyun 3868*4882a593Smuzhiyun /* WMI_PRIO_TX_SECTORS_ORDER_CMDID 3869*4882a593Smuzhiyun * 3870*4882a593Smuzhiyun * Set the order of TX sectors in TXSS and/or Beacon(AP). 3871*4882a593Smuzhiyun * 3872*4882a593Smuzhiyun * Returned event: 3873*4882a593Smuzhiyun * - WMI_PRIO_TX_SECTORS_ORDER_EVENTID 3874*4882a593Smuzhiyun */ 3875*4882a593Smuzhiyun struct wmi_prio_tx_sectors_order_cmd { 3876*4882a593Smuzhiyun /* tx sectors order to be applied, 0xFF for end of array */ 3877*4882a593Smuzhiyun u8 tx_sectors_priority_array[MAX_NUM_OF_SECTORS]; 3878*4882a593Smuzhiyun /* enum wmi_sector_sweep_type, TXSS and/or Beacon */ 3879*4882a593Smuzhiyun u8 sector_sweep_type; 3880*4882a593Smuzhiyun /* needed only for TXSS configuration */ 3881*4882a593Smuzhiyun u8 cid; 3882*4882a593Smuzhiyun /* alignment to 32b */ 3883*4882a593Smuzhiyun u8 reserved[2]; 3884*4882a593Smuzhiyun } __packed; 3885*4882a593Smuzhiyun 3886*4882a593Smuzhiyun /* completion status codes */ 3887*4882a593Smuzhiyun enum wmi_prio_tx_sectors_cmd_status { 3888*4882a593Smuzhiyun WMI_PRIO_TX_SECT_CMD_STATUS_SUCCESS = 0x00, 3889*4882a593Smuzhiyun WMI_PRIO_TX_SECT_CMD_STATUS_BAD_PARAM = 0x01, 3890*4882a593Smuzhiyun /* other error */ 3891*4882a593Smuzhiyun WMI_PRIO_TX_SECT_CMD_STATUS_ERROR = 0x02, 3892*4882a593Smuzhiyun }; 3893*4882a593Smuzhiyun 3894*4882a593Smuzhiyun /* WMI_PRIO_TX_SECTORS_ORDER_EVENTID */ 3895*4882a593Smuzhiyun struct wmi_prio_tx_sectors_order_event { 3896*4882a593Smuzhiyun /* enum wmi_prio_tx_sectors_cmd_status */ 3897*4882a593Smuzhiyun u8 status; 3898*4882a593Smuzhiyun /* alignment to 32b */ 3899*4882a593Smuzhiyun u8 reserved[3]; 3900*4882a593Smuzhiyun } __packed; 3901*4882a593Smuzhiyun 3902*4882a593Smuzhiyun struct wmi_prio_tx_sectors_num_cmd { 3903*4882a593Smuzhiyun /* [0-128], 0 = No changes */ 3904*4882a593Smuzhiyun u8 beacon_number_of_sectors; 3905*4882a593Smuzhiyun /* [0-128], 0 = No changes */ 3906*4882a593Smuzhiyun u8 txss_number_of_sectors; 3907*4882a593Smuzhiyun /* [0-8] needed only for TXSS configuration */ 3908*4882a593Smuzhiyun u8 cid; 3909*4882a593Smuzhiyun } __packed; 3910*4882a593Smuzhiyun 3911*4882a593Smuzhiyun /* WMI_PRIO_TX_SECTORS_NUMBER_CMDID 3912*4882a593Smuzhiyun * 3913*4882a593Smuzhiyun * Set the number of active sectors in TXSS and/or Beacon. 3914*4882a593Smuzhiyun * 3915*4882a593Smuzhiyun * Returned event: 3916*4882a593Smuzhiyun * - WMI_PRIO_TX_SECTORS_NUMBER_EVENTID 3917*4882a593Smuzhiyun */ 3918*4882a593Smuzhiyun struct wmi_prio_tx_sectors_number_cmd { 3919*4882a593Smuzhiyun struct wmi_prio_tx_sectors_num_cmd active_sectors_num; 3920*4882a593Smuzhiyun /* alignment to 32b */ 3921*4882a593Smuzhiyun u8 reserved; 3922*4882a593Smuzhiyun } __packed; 3923*4882a593Smuzhiyun 3924*4882a593Smuzhiyun /* WMI_PRIO_TX_SECTORS_NUMBER_EVENTID */ 3925*4882a593Smuzhiyun struct wmi_prio_tx_sectors_number_event { 3926*4882a593Smuzhiyun /* enum wmi_prio_tx_sectors_cmd_status */ 3927*4882a593Smuzhiyun u8 status; 3928*4882a593Smuzhiyun /* alignment to 32b */ 3929*4882a593Smuzhiyun u8 reserved[3]; 3930*4882a593Smuzhiyun } __packed; 3931*4882a593Smuzhiyun 3932*4882a593Smuzhiyun /* WMI_PRIO_TX_SECTORS_SET_DEFAULT_CFG_CMDID 3933*4882a593Smuzhiyun * 3934*4882a593Smuzhiyun * Set default sectors order and number (hard coded in board file) 3935*4882a593Smuzhiyun * in TXSS and/or Beacon. 3936*4882a593Smuzhiyun * 3937*4882a593Smuzhiyun * Returned event: 3938*4882a593Smuzhiyun * - WMI_PRIO_TX_SECTORS_SET_DEFAULT_CFG_EVENTID 3939*4882a593Smuzhiyun */ 3940*4882a593Smuzhiyun struct wmi_prio_tx_sectors_set_default_cfg_cmd { 3941*4882a593Smuzhiyun /* enum wmi_sector_sweep_type, TXSS and/or Beacon */ 3942*4882a593Smuzhiyun u8 sector_sweep_type; 3943*4882a593Smuzhiyun /* needed only for TXSS configuration */ 3944*4882a593Smuzhiyun u8 cid; 3945*4882a593Smuzhiyun /* alignment to 32b */ 3946*4882a593Smuzhiyun u8 reserved[2]; 3947*4882a593Smuzhiyun } __packed; 3948*4882a593Smuzhiyun 3949*4882a593Smuzhiyun /* WMI_PRIO_TX_SECTORS_SET_DEFAULT_CFG_EVENTID */ 3950*4882a593Smuzhiyun struct wmi_prio_tx_sectors_set_default_cfg_event { 3951*4882a593Smuzhiyun /* enum wmi_prio_tx_sectors_cmd_status */ 3952*4882a593Smuzhiyun u8 status; 3953*4882a593Smuzhiyun /* alignment to 32b */ 3954*4882a593Smuzhiyun u8 reserved[3]; 3955*4882a593Smuzhiyun } __packed; 3956*4882a593Smuzhiyun 3957*4882a593Smuzhiyun /* WMI_SET_SILENT_RSSI_TABLE_DONE_EVENTID */ 3958*4882a593Smuzhiyun struct wmi_set_silent_rssi_table_done_event { 3959*4882a593Smuzhiyun /* enum wmi_silent_rssi_status */ 3960*4882a593Smuzhiyun __le32 status; 3961*4882a593Smuzhiyun /* enum wmi_silent_rssi_table */ 3962*4882a593Smuzhiyun __le32 table; 3963*4882a593Smuzhiyun } __packed; 3964*4882a593Smuzhiyun 3965*4882a593Smuzhiyun /* WMI_VRING_SWITCH_TIMING_CONFIG_EVENTID */ 3966*4882a593Smuzhiyun struct wmi_vring_switch_timing_config_event { 3967*4882a593Smuzhiyun /* enum wmi_fw_status */ 3968*4882a593Smuzhiyun u8 status; 3969*4882a593Smuzhiyun u8 reserved[3]; 3970*4882a593Smuzhiyun } __packed; 3971*4882a593Smuzhiyun 3972*4882a593Smuzhiyun /* WMI_GET_ASSOC_LIST_RES_EVENTID */ 3973*4882a593Smuzhiyun struct wmi_assoc_sta_info { 3974*4882a593Smuzhiyun u8 mac[WMI_MAC_LEN]; 3975*4882a593Smuzhiyun u8 omni_index_address; 3976*4882a593Smuzhiyun u8 reserved; 3977*4882a593Smuzhiyun } __packed; 3978*4882a593Smuzhiyun 3979*4882a593Smuzhiyun #define WMI_GET_ASSOC_LIST_SIZE (8) 3980*4882a593Smuzhiyun 3981*4882a593Smuzhiyun /* WMI_GET_ASSOC_LIST_RES_EVENTID 3982*4882a593Smuzhiyun * Returns up to MAX_ASSOC_STA_LIST_SIZE associated STAs 3983*4882a593Smuzhiyun */ 3984*4882a593Smuzhiyun struct wmi_get_assoc_list_res_event { 3985*4882a593Smuzhiyun struct wmi_assoc_sta_info assoc_sta_list[WMI_GET_ASSOC_LIST_SIZE]; 3986*4882a593Smuzhiyun /* STA count */ 3987*4882a593Smuzhiyun u8 count; 3988*4882a593Smuzhiyun u8 reserved[3]; 3989*4882a593Smuzhiyun } __packed; 3990*4882a593Smuzhiyun 3991*4882a593Smuzhiyun /* WMI_BF_CONTROL_EVENTID - deprecated */ 3992*4882a593Smuzhiyun struct wmi_bf_control_event { 3993*4882a593Smuzhiyun /* wmi_fw_status */ 3994*4882a593Smuzhiyun u8 status; 3995*4882a593Smuzhiyun u8 reserved[3]; 3996*4882a593Smuzhiyun } __packed; 3997*4882a593Smuzhiyun 3998*4882a593Smuzhiyun /* WMI_BF_CONTROL_EX_EVENTID */ 3999*4882a593Smuzhiyun struct wmi_bf_control_ex_event { 4000*4882a593Smuzhiyun /* wmi_fw_status */ 4001*4882a593Smuzhiyun u8 status; 4002*4882a593Smuzhiyun u8 reserved[3]; 4003*4882a593Smuzhiyun } __packed; 4004*4882a593Smuzhiyun 4005*4882a593Smuzhiyun /* WMI_COMMAND_NOT_SUPPORTED_EVENTID */ 4006*4882a593Smuzhiyun struct wmi_command_not_supported_event { 4007*4882a593Smuzhiyun /* device id */ 4008*4882a593Smuzhiyun u8 mid; 4009*4882a593Smuzhiyun u8 reserved0; 4010*4882a593Smuzhiyun __le16 command_id; 4011*4882a593Smuzhiyun /* for UT command only, otherwise reserved */ 4012*4882a593Smuzhiyun __le16 command_subtype; 4013*4882a593Smuzhiyun __le16 reserved1; 4014*4882a593Smuzhiyun } __packed; 4015*4882a593Smuzhiyun 4016*4882a593Smuzhiyun /* WMI_TSF_SYNC_CMDID */ 4017*4882a593Smuzhiyun struct wmi_tsf_sync_cmd { 4018*4882a593Smuzhiyun /* The time interval to send announce frame in one BI */ 4019*4882a593Smuzhiyun u8 interval_ms; 4020*4882a593Smuzhiyun /* The mcs to send announce frame */ 4021*4882a593Smuzhiyun u8 mcs; 4022*4882a593Smuzhiyun u8 reserved[6]; 4023*4882a593Smuzhiyun } __packed; 4024*4882a593Smuzhiyun 4025*4882a593Smuzhiyun /* WMI_TSF_SYNC_STATUS_EVENTID */ 4026*4882a593Smuzhiyun enum wmi_tsf_sync_status { 4027*4882a593Smuzhiyun WMI_TSF_SYNC_SUCCESS = 0x00, 4028*4882a593Smuzhiyun WMI_TSF_SYNC_FAILED = 0x01, 4029*4882a593Smuzhiyun WMI_TSF_SYNC_REJECTED = 0x02, 4030*4882a593Smuzhiyun }; 4031*4882a593Smuzhiyun 4032*4882a593Smuzhiyun /* WMI_TSF_SYNC_STATUS_EVENTID */ 4033*4882a593Smuzhiyun struct wmi_tsf_sync_status_event { 4034*4882a593Smuzhiyun /* enum wmi_tsf_sync_status */ 4035*4882a593Smuzhiyun u8 status; 4036*4882a593Smuzhiyun u8 reserved[3]; 4037*4882a593Smuzhiyun } __packed; 4038*4882a593Smuzhiyun 4039*4882a593Smuzhiyun /* WMI_GET_CCA_INDICATIONS_EVENTID */ 4040*4882a593Smuzhiyun struct wmi_get_cca_indications_event { 4041*4882a593Smuzhiyun /* wmi_fw_status */ 4042*4882a593Smuzhiyun u8 status; 4043*4882a593Smuzhiyun /* CCA-Energy Detect in percentage over last BI (0..100) */ 4044*4882a593Smuzhiyun u8 cca_ed_percent; 4045*4882a593Smuzhiyun /* Averaged CCA-Energy Detect in percent over number of BIs (0..100) */ 4046*4882a593Smuzhiyun u8 cca_ed_avg_percent; 4047*4882a593Smuzhiyun /* NAV percent over last BI (0..100) */ 4048*4882a593Smuzhiyun u8 nav_percent; 4049*4882a593Smuzhiyun /* Averaged NAV percent over number of BIs (0..100) */ 4050*4882a593Smuzhiyun u8 nav_avg_percent; 4051*4882a593Smuzhiyun u8 reserved[3]; 4052*4882a593Smuzhiyun } __packed; 4053*4882a593Smuzhiyun 4054*4882a593Smuzhiyun /* WMI_SET_CCA_INDICATIONS_BI_AVG_NUM_CMDID */ 4055*4882a593Smuzhiyun struct wmi_set_cca_indications_bi_avg_num_cmd { 4056*4882a593Smuzhiyun /* set the number of bis to average cca_ed (0..255) */ 4057*4882a593Smuzhiyun u8 bi_number; 4058*4882a593Smuzhiyun u8 reserved[3]; 4059*4882a593Smuzhiyun } __packed; 4060*4882a593Smuzhiyun 4061*4882a593Smuzhiyun /* WMI_SET_CCA_INDICATIONS_BI_AVG_NUM_EVENTID */ 4062*4882a593Smuzhiyun struct wmi_set_cca_indications_bi_avg_num_event { 4063*4882a593Smuzhiyun /* wmi_fw_status */ 4064*4882a593Smuzhiyun u8 status; 4065*4882a593Smuzhiyun u8 reserved[3]; 4066*4882a593Smuzhiyun } __packed; 4067*4882a593Smuzhiyun 4068*4882a593Smuzhiyun /* WMI_INTERNAL_FW_SET_CHANNEL */ 4069*4882a593Smuzhiyun struct wmi_internal_fw_set_channel_event { 4070*4882a593Smuzhiyun u8 channel_num; 4071*4882a593Smuzhiyun u8 reserved[3]; 4072*4882a593Smuzhiyun } __packed; 4073*4882a593Smuzhiyun 4074*4882a593Smuzhiyun /* WMI_LINK_STATS_CONFIG_DONE_EVENTID */ 4075*4882a593Smuzhiyun struct wmi_link_stats_config_done_event { 4076*4882a593Smuzhiyun /* wmi_fw_status_e */ 4077*4882a593Smuzhiyun u8 status; 4078*4882a593Smuzhiyun u8 reserved[3]; 4079*4882a593Smuzhiyun } __packed; 4080*4882a593Smuzhiyun 4081*4882a593Smuzhiyun /* WMI_LINK_STATS_EVENTID */ 4082*4882a593Smuzhiyun struct wmi_link_stats_event { 4083*4882a593Smuzhiyun __le64 tsf; 4084*4882a593Smuzhiyun __le16 payload_size; 4085*4882a593Smuzhiyun u8 has_next; 4086*4882a593Smuzhiyun u8 reserved[5]; 4087*4882a593Smuzhiyun /* a stream of wmi_link_stats_record_s */ 4088*4882a593Smuzhiyun u8 payload[]; 4089*4882a593Smuzhiyun } __packed; 4090*4882a593Smuzhiyun 4091*4882a593Smuzhiyun /* WMI_LINK_STATS_EVENT */ 4092*4882a593Smuzhiyun struct wmi_link_stats_record { 4093*4882a593Smuzhiyun /* wmi_link_stats_record_type_e */ 4094*4882a593Smuzhiyun u8 record_type_id; 4095*4882a593Smuzhiyun u8 reserved; 4096*4882a593Smuzhiyun __le16 record_size; 4097*4882a593Smuzhiyun u8 record[]; 4098*4882a593Smuzhiyun } __packed; 4099*4882a593Smuzhiyun 4100*4882a593Smuzhiyun /* WMI_LINK_STATS_TYPE_BASIC */ 4101*4882a593Smuzhiyun struct wmi_link_stats_basic { 4102*4882a593Smuzhiyun u8 cid; 4103*4882a593Smuzhiyun s8 rssi; 4104*4882a593Smuzhiyun u8 sqi; 4105*4882a593Smuzhiyun u8 bf_mcs; 4106*4882a593Smuzhiyun u8 per_average; 4107*4882a593Smuzhiyun u8 selected_rfc; 4108*4882a593Smuzhiyun u8 rx_effective_ant_num; 4109*4882a593Smuzhiyun u8 my_rx_sector; 4110*4882a593Smuzhiyun u8 my_tx_sector; 4111*4882a593Smuzhiyun u8 other_rx_sector; 4112*4882a593Smuzhiyun u8 other_tx_sector; 4113*4882a593Smuzhiyun u8 reserved[7]; 4114*4882a593Smuzhiyun /* 1/4 Db units */ 4115*4882a593Smuzhiyun __le16 snr; 4116*4882a593Smuzhiyun __le32 tx_tpt; 4117*4882a593Smuzhiyun __le32 tx_goodput; 4118*4882a593Smuzhiyun __le32 rx_goodput; 4119*4882a593Smuzhiyun __le32 bf_count; 4120*4882a593Smuzhiyun __le32 rx_bcast_frames; 4121*4882a593Smuzhiyun } __packed; 4122*4882a593Smuzhiyun 4123*4882a593Smuzhiyun /* WMI_LINK_STATS_TYPE_GLOBAL */ 4124*4882a593Smuzhiyun struct wmi_link_stats_global { 4125*4882a593Smuzhiyun /* all ack-able frames */ 4126*4882a593Smuzhiyun __le32 rx_frames; 4127*4882a593Smuzhiyun /* all ack-able frames */ 4128*4882a593Smuzhiyun __le32 tx_frames; 4129*4882a593Smuzhiyun __le32 rx_ba_frames; 4130*4882a593Smuzhiyun __le32 tx_ba_frames; 4131*4882a593Smuzhiyun __le32 tx_beacons; 4132*4882a593Smuzhiyun __le32 rx_mic_errors; 4133*4882a593Smuzhiyun __le32 rx_crc_errors; 4134*4882a593Smuzhiyun __le32 tx_fail_no_ack; 4135*4882a593Smuzhiyun u8 reserved[8]; 4136*4882a593Smuzhiyun } __packed; 4137*4882a593Smuzhiyun 4138*4882a593Smuzhiyun /* WMI_SET_GRANT_MCS_EVENTID */ 4139*4882a593Smuzhiyun struct wmi_set_grant_mcs_event { 4140*4882a593Smuzhiyun /* wmi_fw_status */ 4141*4882a593Smuzhiyun u8 status; 4142*4882a593Smuzhiyun u8 reserved[3]; 4143*4882a593Smuzhiyun } __packed; 4144*4882a593Smuzhiyun 4145*4882a593Smuzhiyun /* WMI_SET_AP_SLOT_SIZE_EVENTID */ 4146*4882a593Smuzhiyun struct wmi_set_ap_slot_size_event { 4147*4882a593Smuzhiyun /* wmi_fw_status */ 4148*4882a593Smuzhiyun u8 status; 4149*4882a593Smuzhiyun u8 reserved[3]; 4150*4882a593Smuzhiyun } __packed; 4151*4882a593Smuzhiyun 4152*4882a593Smuzhiyun /* WMI_SET_VRING_PRIORITY_WEIGHT_EVENTID */ 4153*4882a593Smuzhiyun struct wmi_set_vring_priority_weight_event { 4154*4882a593Smuzhiyun /* wmi_fw_status */ 4155*4882a593Smuzhiyun u8 status; 4156*4882a593Smuzhiyun u8 reserved[3]; 4157*4882a593Smuzhiyun } __packed; 4158*4882a593Smuzhiyun 4159*4882a593Smuzhiyun /* WMI_SET_VRING_PRIORITY_EVENTID */ 4160*4882a593Smuzhiyun struct wmi_set_vring_priority_event { 4161*4882a593Smuzhiyun /* wmi_fw_status */ 4162*4882a593Smuzhiyun u8 status; 4163*4882a593Smuzhiyun u8 reserved[3]; 4164*4882a593Smuzhiyun } __packed; 4165*4882a593Smuzhiyun 4166*4882a593Smuzhiyun /* WMI_RADAR_PCI_CTRL_BLOCK struct */ 4167*4882a593Smuzhiyun struct wmi_radar_pci_ctrl_block { 4168*4882a593Smuzhiyun /* last fw tail address index */ 4169*4882a593Smuzhiyun __le32 fw_tail_index; 4170*4882a593Smuzhiyun /* last SW head address index known to FW */ 4171*4882a593Smuzhiyun __le32 sw_head_index; 4172*4882a593Smuzhiyun __le32 last_wr_pulse_tsf_low; 4173*4882a593Smuzhiyun __le32 last_wr_pulse_count; 4174*4882a593Smuzhiyun __le32 last_wr_in_bytes; 4175*4882a593Smuzhiyun __le32 last_wr_pulse_id; 4176*4882a593Smuzhiyun __le32 last_wr_burst_id; 4177*4882a593Smuzhiyun /* When pre overflow detected, advance sw head in unit of pulses */ 4178*4882a593Smuzhiyun __le32 sw_head_inc; 4179*4882a593Smuzhiyun __le32 reserved[8]; 4180*4882a593Smuzhiyun } __packed; 4181*4882a593Smuzhiyun 4182*4882a593Smuzhiyun /* WMI_RBUFCAP_CFG_CMD */ 4183*4882a593Smuzhiyun struct wmi_rbufcap_cfg_cmd { 4184*4882a593Smuzhiyun u8 enable; 4185*4882a593Smuzhiyun u8 reserved; 4186*4882a593Smuzhiyun /* RBUFCAP indicates rx space unavailable when number of rx 4187*4882a593Smuzhiyun * descriptors drops below this threshold. Set 0 to use system 4188*4882a593Smuzhiyun * default 4189*4882a593Smuzhiyun */ 4190*4882a593Smuzhiyun __le16 rx_desc_threshold; 4191*4882a593Smuzhiyun } __packed; 4192*4882a593Smuzhiyun 4193*4882a593Smuzhiyun /* WMI_RBUFCAP_CFG_EVENTID */ 4194*4882a593Smuzhiyun struct wmi_rbufcap_cfg_event { 4195*4882a593Smuzhiyun /* enum wmi_fw_status */ 4196*4882a593Smuzhiyun u8 status; 4197*4882a593Smuzhiyun u8 reserved[3]; 4198*4882a593Smuzhiyun } __packed; 4199*4882a593Smuzhiyun 4200*4882a593Smuzhiyun /* WMI_TEMP_SENSE_ALL_DONE_EVENTID 4201*4882a593Smuzhiyun * Measure MAC and all radio temperatures 4202*4882a593Smuzhiyun */ 4203*4882a593Smuzhiyun struct wmi_temp_sense_all_done_event { 4204*4882a593Smuzhiyun /* enum wmi_fw_status */ 4205*4882a593Smuzhiyun u8 status; 4206*4882a593Smuzhiyun /* Bitmap of connected RFs */ 4207*4882a593Smuzhiyun u8 rf_bitmap; 4208*4882a593Smuzhiyun u8 reserved[2]; 4209*4882a593Smuzhiyun /* Temperature times 1000 (actual temperature will be achieved by 4210*4882a593Smuzhiyun * dividing the value by 1000). When temperature cannot be read from 4211*4882a593Smuzhiyun * device return WMI_INVALID_TEMPERATURE 4212*4882a593Smuzhiyun */ 4213*4882a593Smuzhiyun __le32 rf_t1000[WMI_MAX_XIF_PORTS_NUM]; 4214*4882a593Smuzhiyun /* Temperature times 1000 (actual temperature will be achieved by 4215*4882a593Smuzhiyun * dividing the value by 1000). When temperature cannot be read from 4216*4882a593Smuzhiyun * device return WMI_INVALID_TEMPERATURE 4217*4882a593Smuzhiyun */ 4218*4882a593Smuzhiyun __le32 baseband_t1000; 4219*4882a593Smuzhiyun } __packed; 4220*4882a593Smuzhiyun 4221*4882a593Smuzhiyun #endif /* __WILOCITY_WMI_H__ */ 4222