1*4882a593Smuzhiyun // SPDX-License-Identifier: ISC
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2012-2017 Qualcomm Atheros, Inc.
4*4882a593Smuzhiyun * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/moduleparam.h>
8*4882a593Smuzhiyun #include <linux/if_arp.h>
9*4882a593Smuzhiyun #include <linux/etherdevice.h>
10*4882a593Smuzhiyun #include <linux/rtnetlink.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include "wil6210.h"
13*4882a593Smuzhiyun #include "txrx.h"
14*4882a593Smuzhiyun #include "txrx_edma.h"
15*4882a593Smuzhiyun #include "wmi.h"
16*4882a593Smuzhiyun #include "boot_loader.h"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define WAIT_FOR_HALP_VOTE_MS 100
19*4882a593Smuzhiyun #define WAIT_FOR_SCAN_ABORT_MS 1000
20*4882a593Smuzhiyun #define WIL_DEFAULT_NUM_RX_STATUS_RINGS 1
21*4882a593Smuzhiyun #define WIL_BOARD_FILE_MAX_NAMELEN 128
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun bool debug_fw; /* = false; */
24*4882a593Smuzhiyun module_param(debug_fw, bool, 0444);
25*4882a593Smuzhiyun MODULE_PARM_DESC(debug_fw, " do not perform card reset. For FW debug");
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun static u8 oob_mode;
28*4882a593Smuzhiyun module_param(oob_mode, byte, 0444);
29*4882a593Smuzhiyun MODULE_PARM_DESC(oob_mode,
30*4882a593Smuzhiyun " enable out of the box (OOB) mode in FW, for diagnostics and certification");
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun bool no_fw_recovery;
33*4882a593Smuzhiyun module_param(no_fw_recovery, bool, 0644);
34*4882a593Smuzhiyun MODULE_PARM_DESC(no_fw_recovery, " disable automatic FW error recovery");
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* if not set via modparam, will be set to default value of 1/8 of
37*4882a593Smuzhiyun * rx ring size during init flow
38*4882a593Smuzhiyun */
39*4882a593Smuzhiyun unsigned short rx_ring_overflow_thrsh = WIL6210_RX_HIGH_TRSH_INIT;
40*4882a593Smuzhiyun module_param(rx_ring_overflow_thrsh, ushort, 0444);
41*4882a593Smuzhiyun MODULE_PARM_DESC(rx_ring_overflow_thrsh,
42*4882a593Smuzhiyun " RX ring overflow threshold in descriptors.");
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /* We allow allocation of more than 1 page buffers to support large packets.
45*4882a593Smuzhiyun * It is suboptimal behavior performance wise in case MTU above page size.
46*4882a593Smuzhiyun */
47*4882a593Smuzhiyun unsigned int mtu_max = TXRX_BUF_LEN_DEFAULT - WIL_MAX_MPDU_OVERHEAD;
mtu_max_set(const char * val,const struct kernel_param * kp)48*4882a593Smuzhiyun static int mtu_max_set(const char *val, const struct kernel_param *kp)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun int ret;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /* sets mtu_max directly. no need to restore it in case of
53*4882a593Smuzhiyun * illegal value since we assume this will fail insmod
54*4882a593Smuzhiyun */
55*4882a593Smuzhiyun ret = param_set_uint(val, kp);
56*4882a593Smuzhiyun if (ret)
57*4882a593Smuzhiyun return ret;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun if (mtu_max < 68 || mtu_max > WIL_MAX_ETH_MTU)
60*4882a593Smuzhiyun ret = -EINVAL;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun return ret;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun static const struct kernel_param_ops mtu_max_ops = {
66*4882a593Smuzhiyun .set = mtu_max_set,
67*4882a593Smuzhiyun .get = param_get_uint,
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun module_param_cb(mtu_max, &mtu_max_ops, &mtu_max, 0444);
71*4882a593Smuzhiyun MODULE_PARM_DESC(mtu_max, " Max MTU value.");
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun static uint rx_ring_order;
74*4882a593Smuzhiyun static uint tx_ring_order = WIL_TX_RING_SIZE_ORDER_DEFAULT;
75*4882a593Smuzhiyun static uint bcast_ring_order = WIL_BCAST_RING_SIZE_ORDER_DEFAULT;
76*4882a593Smuzhiyun
ring_order_set(const char * val,const struct kernel_param * kp)77*4882a593Smuzhiyun static int ring_order_set(const char *val, const struct kernel_param *kp)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun int ret;
80*4882a593Smuzhiyun uint x;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun ret = kstrtouint(val, 0, &x);
83*4882a593Smuzhiyun if (ret)
84*4882a593Smuzhiyun return ret;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun if ((x < WIL_RING_SIZE_ORDER_MIN) || (x > WIL_RING_SIZE_ORDER_MAX))
87*4882a593Smuzhiyun return -EINVAL;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun *((uint *)kp->arg) = x;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun return 0;
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun static const struct kernel_param_ops ring_order_ops = {
95*4882a593Smuzhiyun .set = ring_order_set,
96*4882a593Smuzhiyun .get = param_get_uint,
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun module_param_cb(rx_ring_order, &ring_order_ops, &rx_ring_order, 0444);
100*4882a593Smuzhiyun MODULE_PARM_DESC(rx_ring_order, " Rx ring order; size = 1 << order");
101*4882a593Smuzhiyun module_param_cb(tx_ring_order, &ring_order_ops, &tx_ring_order, 0444);
102*4882a593Smuzhiyun MODULE_PARM_DESC(tx_ring_order, " Tx ring order; size = 1 << order");
103*4882a593Smuzhiyun module_param_cb(bcast_ring_order, &ring_order_ops, &bcast_ring_order, 0444);
104*4882a593Smuzhiyun MODULE_PARM_DESC(bcast_ring_order, " Bcast ring order; size = 1 << order");
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun enum {
107*4882a593Smuzhiyun WIL_BOOT_ERR,
108*4882a593Smuzhiyun WIL_BOOT_VANILLA,
109*4882a593Smuzhiyun WIL_BOOT_PRODUCTION,
110*4882a593Smuzhiyun WIL_BOOT_DEVELOPMENT,
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun enum {
114*4882a593Smuzhiyun WIL_SIG_STATUS_VANILLA = 0x0,
115*4882a593Smuzhiyun WIL_SIG_STATUS_DEVELOPMENT = 0x1,
116*4882a593Smuzhiyun WIL_SIG_STATUS_PRODUCTION = 0x2,
117*4882a593Smuzhiyun WIL_SIG_STATUS_CORRUPTED_PRODUCTION = 0x3,
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun #define RST_DELAY (20) /* msec, for loop in @wil_wait_device_ready */
121*4882a593Smuzhiyun #define RST_COUNT (1 + 1000/RST_DELAY) /* round up to be above 1 sec total */
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun #define PMU_READY_DELAY_MS (4) /* ms, for sleep in @wil_wait_device_ready */
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun #define OTP_HW_DELAY (200) /* usec, loop in @wil_wait_device_ready_talyn_mb */
126*4882a593Smuzhiyun /* round up to be above 2 ms total */
127*4882a593Smuzhiyun #define OTP_HW_COUNT (1 + 2000 / OTP_HW_DELAY)
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun /*
130*4882a593Smuzhiyun * Due to a hardware issue,
131*4882a593Smuzhiyun * one has to read/write to/from NIC in 32-bit chunks;
132*4882a593Smuzhiyun * regular memcpy_fromio and siblings will
133*4882a593Smuzhiyun * not work on 64-bit platform - it uses 64-bit transactions
134*4882a593Smuzhiyun *
135*4882a593Smuzhiyun * Force 32-bit transactions to enable NIC on 64-bit platforms
136*4882a593Smuzhiyun *
137*4882a593Smuzhiyun * To avoid byte swap on big endian host, __raw_{read|write}l
138*4882a593Smuzhiyun * should be used - {read|write}l would swap bytes to provide
139*4882a593Smuzhiyun * little endian on PCI value in host endianness.
140*4882a593Smuzhiyun */
wil_memcpy_fromio_32(void * dst,const volatile void __iomem * src,size_t count)141*4882a593Smuzhiyun void wil_memcpy_fromio_32(void *dst, const volatile void __iomem *src,
142*4882a593Smuzhiyun size_t count)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun u32 *d = dst;
145*4882a593Smuzhiyun const volatile u32 __iomem *s = src;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun for (; count >= 4; count -= 4)
148*4882a593Smuzhiyun *d++ = __raw_readl(s++);
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun if (unlikely(count)) {
151*4882a593Smuzhiyun /* count can be 1..3 */
152*4882a593Smuzhiyun u32 tmp = __raw_readl(s);
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun memcpy(d, &tmp, count);
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
wil_memcpy_toio_32(volatile void __iomem * dst,const void * src,size_t count)158*4882a593Smuzhiyun void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src,
159*4882a593Smuzhiyun size_t count)
160*4882a593Smuzhiyun {
161*4882a593Smuzhiyun volatile u32 __iomem *d = dst;
162*4882a593Smuzhiyun const u32 *s = src;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun for (; count >= 4; count -= 4)
165*4882a593Smuzhiyun __raw_writel(*s++, d++);
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun if (unlikely(count)) {
168*4882a593Smuzhiyun /* count can be 1..3 */
169*4882a593Smuzhiyun u32 tmp = 0;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun memcpy(&tmp, s, count);
172*4882a593Smuzhiyun __raw_writel(tmp, d);
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun /* Device memory access is prohibited while reset or suspend.
177*4882a593Smuzhiyun * wil_mem_access_lock protects accessing device memory in these cases
178*4882a593Smuzhiyun */
wil_mem_access_lock(struct wil6210_priv * wil)179*4882a593Smuzhiyun int wil_mem_access_lock(struct wil6210_priv *wil)
180*4882a593Smuzhiyun {
181*4882a593Smuzhiyun if (!down_read_trylock(&wil->mem_lock))
182*4882a593Smuzhiyun return -EBUSY;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun if (test_bit(wil_status_suspending, wil->status) ||
185*4882a593Smuzhiyun test_bit(wil_status_suspended, wil->status)) {
186*4882a593Smuzhiyun up_read(&wil->mem_lock);
187*4882a593Smuzhiyun return -EBUSY;
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun return 0;
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun
wil_mem_access_unlock(struct wil6210_priv * wil)193*4882a593Smuzhiyun void wil_mem_access_unlock(struct wil6210_priv *wil)
194*4882a593Smuzhiyun {
195*4882a593Smuzhiyun up_read(&wil->mem_lock);
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun
wil_ring_fini_tx(struct wil6210_priv * wil,int id)198*4882a593Smuzhiyun static void wil_ring_fini_tx(struct wil6210_priv *wil, int id)
199*4882a593Smuzhiyun {
200*4882a593Smuzhiyun struct wil_ring *ring = &wil->ring_tx[id];
201*4882a593Smuzhiyun struct wil_ring_tx_data *txdata = &wil->ring_tx_data[id];
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun lockdep_assert_held(&wil->mutex);
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun if (!ring->va)
206*4882a593Smuzhiyun return;
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun wil_dbg_misc(wil, "vring_fini_tx: id=%d\n", id);
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun spin_lock_bh(&txdata->lock);
211*4882a593Smuzhiyun txdata->dot1x_open = false;
212*4882a593Smuzhiyun txdata->mid = U8_MAX;
213*4882a593Smuzhiyun txdata->enabled = 0; /* no Tx can be in progress or start anew */
214*4882a593Smuzhiyun spin_unlock_bh(&txdata->lock);
215*4882a593Smuzhiyun /* napi_synchronize waits for completion of the current NAPI but will
216*4882a593Smuzhiyun * not prevent the next NAPI run.
217*4882a593Smuzhiyun * Add a memory barrier to guarantee that txdata->enabled is zeroed
218*4882a593Smuzhiyun * before napi_synchronize so that the next scheduled NAPI will not
219*4882a593Smuzhiyun * handle this vring
220*4882a593Smuzhiyun */
221*4882a593Smuzhiyun wmb();
222*4882a593Smuzhiyun /* make sure NAPI won't touch this vring */
223*4882a593Smuzhiyun if (test_bit(wil_status_napi_en, wil->status))
224*4882a593Smuzhiyun napi_synchronize(&wil->napi_tx);
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun wil->txrx_ops.ring_fini_tx(wil, ring);
227*4882a593Smuzhiyun }
228*4882a593Smuzhiyun
wil_vif_is_connected(struct wil6210_priv * wil,u8 mid)229*4882a593Smuzhiyun static bool wil_vif_is_connected(struct wil6210_priv *wil, u8 mid)
230*4882a593Smuzhiyun {
231*4882a593Smuzhiyun int i;
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun for (i = 0; i < wil->max_assoc_sta; i++) {
234*4882a593Smuzhiyun if (wil->sta[i].mid == mid &&
235*4882a593Smuzhiyun wil->sta[i].status == wil_sta_connected)
236*4882a593Smuzhiyun return true;
237*4882a593Smuzhiyun }
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun return false;
240*4882a593Smuzhiyun }
241*4882a593Smuzhiyun
wil_disconnect_cid_complete(struct wil6210_vif * vif,int cid,u16 reason_code)242*4882a593Smuzhiyun static void wil_disconnect_cid_complete(struct wil6210_vif *vif, int cid,
243*4882a593Smuzhiyun u16 reason_code)
244*4882a593Smuzhiyun __acquires(&sta->tid_rx_lock) __releases(&sta->tid_rx_lock)
245*4882a593Smuzhiyun {
246*4882a593Smuzhiyun uint i;
247*4882a593Smuzhiyun struct wil6210_priv *wil = vif_to_wil(vif);
248*4882a593Smuzhiyun struct net_device *ndev = vif_to_ndev(vif);
249*4882a593Smuzhiyun struct wireless_dev *wdev = vif_to_wdev(vif);
250*4882a593Smuzhiyun struct wil_sta_info *sta = &wil->sta[cid];
251*4882a593Smuzhiyun int min_ring_id = wil_get_min_tx_ring_id(wil);
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun might_sleep();
254*4882a593Smuzhiyun wil_dbg_misc(wil,
255*4882a593Smuzhiyun "disconnect_cid_complete: CID %d, MID %d, status %d\n",
256*4882a593Smuzhiyun cid, sta->mid, sta->status);
257*4882a593Smuzhiyun /* inform upper layers */
258*4882a593Smuzhiyun if (sta->status != wil_sta_unused) {
259*4882a593Smuzhiyun if (vif->mid != sta->mid) {
260*4882a593Smuzhiyun wil_err(wil, "STA MID mismatch with VIF MID(%d)\n",
261*4882a593Smuzhiyun vif->mid);
262*4882a593Smuzhiyun }
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun switch (wdev->iftype) {
265*4882a593Smuzhiyun case NL80211_IFTYPE_AP:
266*4882a593Smuzhiyun case NL80211_IFTYPE_P2P_GO:
267*4882a593Smuzhiyun /* AP-like interface */
268*4882a593Smuzhiyun cfg80211_del_sta(ndev, sta->addr, GFP_KERNEL);
269*4882a593Smuzhiyun break;
270*4882a593Smuzhiyun default:
271*4882a593Smuzhiyun break;
272*4882a593Smuzhiyun }
273*4882a593Smuzhiyun sta->status = wil_sta_unused;
274*4882a593Smuzhiyun sta->mid = U8_MAX;
275*4882a593Smuzhiyun }
276*4882a593Smuzhiyun /* reorder buffers */
277*4882a593Smuzhiyun for (i = 0; i < WIL_STA_TID_NUM; i++) {
278*4882a593Smuzhiyun struct wil_tid_ampdu_rx *r;
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun spin_lock_bh(&sta->tid_rx_lock);
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun r = sta->tid_rx[i];
283*4882a593Smuzhiyun sta->tid_rx[i] = NULL;
284*4882a593Smuzhiyun wil_tid_ampdu_rx_free(wil, r);
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun spin_unlock_bh(&sta->tid_rx_lock);
287*4882a593Smuzhiyun }
288*4882a593Smuzhiyun /* crypto context */
289*4882a593Smuzhiyun memset(sta->tid_crypto_rx, 0, sizeof(sta->tid_crypto_rx));
290*4882a593Smuzhiyun memset(&sta->group_crypto_rx, 0, sizeof(sta->group_crypto_rx));
291*4882a593Smuzhiyun /* release vrings */
292*4882a593Smuzhiyun for (i = min_ring_id; i < ARRAY_SIZE(wil->ring_tx); i++) {
293*4882a593Smuzhiyun if (wil->ring2cid_tid[i][0] == cid)
294*4882a593Smuzhiyun wil_ring_fini_tx(wil, i);
295*4882a593Smuzhiyun }
296*4882a593Smuzhiyun /* statistics */
297*4882a593Smuzhiyun memset(&sta->stats, 0, sizeof(sta->stats));
298*4882a593Smuzhiyun sta->stats.tx_latency_min_us = U32_MAX;
299*4882a593Smuzhiyun }
300*4882a593Smuzhiyun
_wil6210_disconnect_complete(struct wil6210_vif * vif,const u8 * bssid,u16 reason_code)301*4882a593Smuzhiyun static void _wil6210_disconnect_complete(struct wil6210_vif *vif,
302*4882a593Smuzhiyun const u8 *bssid, u16 reason_code)
303*4882a593Smuzhiyun {
304*4882a593Smuzhiyun struct wil6210_priv *wil = vif_to_wil(vif);
305*4882a593Smuzhiyun int cid = -ENOENT;
306*4882a593Smuzhiyun struct net_device *ndev;
307*4882a593Smuzhiyun struct wireless_dev *wdev;
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun ndev = vif_to_ndev(vif);
310*4882a593Smuzhiyun wdev = vif_to_wdev(vif);
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun might_sleep();
313*4882a593Smuzhiyun wil_info(wil, "disconnect_complete: bssid=%pM, reason=%d\n",
314*4882a593Smuzhiyun bssid, reason_code);
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun /* Cases are:
317*4882a593Smuzhiyun * - disconnect single STA, still connected
318*4882a593Smuzhiyun * - disconnect single STA, already disconnected
319*4882a593Smuzhiyun * - disconnect all
320*4882a593Smuzhiyun *
321*4882a593Smuzhiyun * For "disconnect all", there are 3 options:
322*4882a593Smuzhiyun * - bssid == NULL
323*4882a593Smuzhiyun * - bssid is broadcast address (ff:ff:ff:ff:ff:ff)
324*4882a593Smuzhiyun * - bssid is our MAC address
325*4882a593Smuzhiyun */
326*4882a593Smuzhiyun if (bssid && !is_broadcast_ether_addr(bssid) &&
327*4882a593Smuzhiyun !ether_addr_equal_unaligned(ndev->dev_addr, bssid)) {
328*4882a593Smuzhiyun cid = wil_find_cid(wil, vif->mid, bssid);
329*4882a593Smuzhiyun wil_dbg_misc(wil,
330*4882a593Smuzhiyun "Disconnect complete %pM, CID=%d, reason=%d\n",
331*4882a593Smuzhiyun bssid, cid, reason_code);
332*4882a593Smuzhiyun if (wil_cid_valid(wil, cid)) /* disconnect 1 peer */
333*4882a593Smuzhiyun wil_disconnect_cid_complete(vif, cid, reason_code);
334*4882a593Smuzhiyun } else { /* all */
335*4882a593Smuzhiyun wil_dbg_misc(wil, "Disconnect complete all\n");
336*4882a593Smuzhiyun for (cid = 0; cid < wil->max_assoc_sta; cid++)
337*4882a593Smuzhiyun wil_disconnect_cid_complete(vif, cid, reason_code);
338*4882a593Smuzhiyun }
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun /* link state */
341*4882a593Smuzhiyun switch (wdev->iftype) {
342*4882a593Smuzhiyun case NL80211_IFTYPE_STATION:
343*4882a593Smuzhiyun case NL80211_IFTYPE_P2P_CLIENT:
344*4882a593Smuzhiyun wil_bcast_fini(vif);
345*4882a593Smuzhiyun wil_update_net_queues_bh(wil, vif, NULL, true);
346*4882a593Smuzhiyun netif_carrier_off(ndev);
347*4882a593Smuzhiyun if (!wil_has_other_active_ifaces(wil, ndev, false, true))
348*4882a593Smuzhiyun wil6210_bus_request(wil, WIL_DEFAULT_BUS_REQUEST_KBPS);
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun if (test_and_clear_bit(wil_vif_fwconnected, vif->status)) {
351*4882a593Smuzhiyun atomic_dec(&wil->connected_vifs);
352*4882a593Smuzhiyun cfg80211_disconnected(ndev, reason_code,
353*4882a593Smuzhiyun NULL, 0,
354*4882a593Smuzhiyun vif->locally_generated_disc,
355*4882a593Smuzhiyun GFP_KERNEL);
356*4882a593Smuzhiyun vif->locally_generated_disc = false;
357*4882a593Smuzhiyun } else if (test_bit(wil_vif_fwconnecting, vif->status)) {
358*4882a593Smuzhiyun cfg80211_connect_result(ndev, bssid, NULL, 0, NULL, 0,
359*4882a593Smuzhiyun WLAN_STATUS_UNSPECIFIED_FAILURE,
360*4882a593Smuzhiyun GFP_KERNEL);
361*4882a593Smuzhiyun vif->bss = NULL;
362*4882a593Smuzhiyun }
363*4882a593Smuzhiyun clear_bit(wil_vif_fwconnecting, vif->status);
364*4882a593Smuzhiyun clear_bit(wil_vif_ft_roam, vif->status);
365*4882a593Smuzhiyun vif->ptk_rekey_state = WIL_REKEY_IDLE;
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun break;
368*4882a593Smuzhiyun case NL80211_IFTYPE_AP:
369*4882a593Smuzhiyun case NL80211_IFTYPE_P2P_GO:
370*4882a593Smuzhiyun if (!wil_vif_is_connected(wil, vif->mid)) {
371*4882a593Smuzhiyun wil_update_net_queues_bh(wil, vif, NULL, true);
372*4882a593Smuzhiyun if (test_and_clear_bit(wil_vif_fwconnected,
373*4882a593Smuzhiyun vif->status))
374*4882a593Smuzhiyun atomic_dec(&wil->connected_vifs);
375*4882a593Smuzhiyun } else {
376*4882a593Smuzhiyun wil_update_net_queues_bh(wil, vif, NULL, false);
377*4882a593Smuzhiyun }
378*4882a593Smuzhiyun break;
379*4882a593Smuzhiyun default:
380*4882a593Smuzhiyun break;
381*4882a593Smuzhiyun }
382*4882a593Smuzhiyun }
383*4882a593Smuzhiyun
wil_disconnect_cid(struct wil6210_vif * vif,int cid,u16 reason_code)384*4882a593Smuzhiyun static int wil_disconnect_cid(struct wil6210_vif *vif, int cid,
385*4882a593Smuzhiyun u16 reason_code)
386*4882a593Smuzhiyun {
387*4882a593Smuzhiyun struct wil6210_priv *wil = vif_to_wil(vif);
388*4882a593Smuzhiyun struct wireless_dev *wdev = vif_to_wdev(vif);
389*4882a593Smuzhiyun struct wil_sta_info *sta = &wil->sta[cid];
390*4882a593Smuzhiyun bool del_sta = false;
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun might_sleep();
393*4882a593Smuzhiyun wil_dbg_misc(wil, "disconnect_cid: CID %d, MID %d, status %d\n",
394*4882a593Smuzhiyun cid, sta->mid, sta->status);
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun if (sta->status == wil_sta_unused)
397*4882a593Smuzhiyun return 0;
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun if (vif->mid != sta->mid) {
400*4882a593Smuzhiyun wil_err(wil, "STA MID mismatch with VIF MID(%d)\n", vif->mid);
401*4882a593Smuzhiyun return -EINVAL;
402*4882a593Smuzhiyun }
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun /* inform lower layers */
405*4882a593Smuzhiyun if (wdev->iftype == NL80211_IFTYPE_AP && disable_ap_sme)
406*4882a593Smuzhiyun del_sta = true;
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun /* disconnect by sending command disconnect/del_sta and wait
409*4882a593Smuzhiyun * synchronously for WMI_DISCONNECT_EVENTID event.
410*4882a593Smuzhiyun */
411*4882a593Smuzhiyun return wmi_disconnect_sta(vif, sta->addr, reason_code, del_sta);
412*4882a593Smuzhiyun }
413*4882a593Smuzhiyun
_wil6210_disconnect(struct wil6210_vif * vif,const u8 * bssid,u16 reason_code)414*4882a593Smuzhiyun static void _wil6210_disconnect(struct wil6210_vif *vif, const u8 *bssid,
415*4882a593Smuzhiyun u16 reason_code)
416*4882a593Smuzhiyun {
417*4882a593Smuzhiyun struct wil6210_priv *wil;
418*4882a593Smuzhiyun struct net_device *ndev;
419*4882a593Smuzhiyun int cid = -ENOENT;
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun if (unlikely(!vif))
422*4882a593Smuzhiyun return;
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun wil = vif_to_wil(vif);
425*4882a593Smuzhiyun ndev = vif_to_ndev(vif);
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun might_sleep();
428*4882a593Smuzhiyun wil_info(wil, "disconnect bssid=%pM, reason=%d\n", bssid, reason_code);
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun /* Cases are:
431*4882a593Smuzhiyun * - disconnect single STA, still connected
432*4882a593Smuzhiyun * - disconnect single STA, already disconnected
433*4882a593Smuzhiyun * - disconnect all
434*4882a593Smuzhiyun *
435*4882a593Smuzhiyun * For "disconnect all", there are 3 options:
436*4882a593Smuzhiyun * - bssid == NULL
437*4882a593Smuzhiyun * - bssid is broadcast address (ff:ff:ff:ff:ff:ff)
438*4882a593Smuzhiyun * - bssid is our MAC address
439*4882a593Smuzhiyun */
440*4882a593Smuzhiyun if (bssid && !is_broadcast_ether_addr(bssid) &&
441*4882a593Smuzhiyun !ether_addr_equal_unaligned(ndev->dev_addr, bssid)) {
442*4882a593Smuzhiyun cid = wil_find_cid(wil, vif->mid, bssid);
443*4882a593Smuzhiyun wil_dbg_misc(wil, "Disconnect %pM, CID=%d, reason=%d\n",
444*4882a593Smuzhiyun bssid, cid, reason_code);
445*4882a593Smuzhiyun if (wil_cid_valid(wil, cid)) /* disconnect 1 peer */
446*4882a593Smuzhiyun wil_disconnect_cid(vif, cid, reason_code);
447*4882a593Smuzhiyun } else { /* all */
448*4882a593Smuzhiyun wil_dbg_misc(wil, "Disconnect all\n");
449*4882a593Smuzhiyun for (cid = 0; cid < wil->max_assoc_sta; cid++)
450*4882a593Smuzhiyun wil_disconnect_cid(vif, cid, reason_code);
451*4882a593Smuzhiyun }
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun /* call event handler manually after processing wmi_call,
454*4882a593Smuzhiyun * to avoid deadlock - disconnect event handler acquires
455*4882a593Smuzhiyun * wil->mutex while it is already held here
456*4882a593Smuzhiyun */
457*4882a593Smuzhiyun _wil6210_disconnect_complete(vif, bssid, reason_code);
458*4882a593Smuzhiyun }
459*4882a593Smuzhiyun
wil_disconnect_worker(struct work_struct * work)460*4882a593Smuzhiyun void wil_disconnect_worker(struct work_struct *work)
461*4882a593Smuzhiyun {
462*4882a593Smuzhiyun struct wil6210_vif *vif = container_of(work,
463*4882a593Smuzhiyun struct wil6210_vif, disconnect_worker);
464*4882a593Smuzhiyun struct wil6210_priv *wil = vif_to_wil(vif);
465*4882a593Smuzhiyun struct net_device *ndev = vif_to_ndev(vif);
466*4882a593Smuzhiyun int rc;
467*4882a593Smuzhiyun struct {
468*4882a593Smuzhiyun struct wmi_cmd_hdr wmi;
469*4882a593Smuzhiyun struct wmi_disconnect_event evt;
470*4882a593Smuzhiyun } __packed reply;
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun if (test_bit(wil_vif_fwconnected, vif->status))
473*4882a593Smuzhiyun /* connect succeeded after all */
474*4882a593Smuzhiyun return;
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun if (!test_bit(wil_vif_fwconnecting, vif->status))
477*4882a593Smuzhiyun /* already disconnected */
478*4882a593Smuzhiyun return;
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun memset(&reply, 0, sizeof(reply));
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun rc = wmi_call(wil, WMI_DISCONNECT_CMDID, vif->mid, NULL, 0,
483*4882a593Smuzhiyun WMI_DISCONNECT_EVENTID, &reply, sizeof(reply),
484*4882a593Smuzhiyun WIL6210_DISCONNECT_TO_MS);
485*4882a593Smuzhiyun if (rc) {
486*4882a593Smuzhiyun wil_err(wil, "disconnect error %d\n", rc);
487*4882a593Smuzhiyun return;
488*4882a593Smuzhiyun }
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun wil_update_net_queues_bh(wil, vif, NULL, true);
491*4882a593Smuzhiyun netif_carrier_off(ndev);
492*4882a593Smuzhiyun cfg80211_connect_result(ndev, NULL, NULL, 0, NULL, 0,
493*4882a593Smuzhiyun WLAN_STATUS_UNSPECIFIED_FAILURE, GFP_KERNEL);
494*4882a593Smuzhiyun clear_bit(wil_vif_fwconnecting, vif->status);
495*4882a593Smuzhiyun }
496*4882a593Smuzhiyun
wil_wait_for_recovery(struct wil6210_priv * wil)497*4882a593Smuzhiyun static int wil_wait_for_recovery(struct wil6210_priv *wil)
498*4882a593Smuzhiyun {
499*4882a593Smuzhiyun if (wait_event_interruptible(wil->wq, wil->recovery_state !=
500*4882a593Smuzhiyun fw_recovery_pending)) {
501*4882a593Smuzhiyun wil_err(wil, "Interrupt, canceling recovery\n");
502*4882a593Smuzhiyun return -ERESTARTSYS;
503*4882a593Smuzhiyun }
504*4882a593Smuzhiyun if (wil->recovery_state != fw_recovery_running) {
505*4882a593Smuzhiyun wil_info(wil, "Recovery cancelled\n");
506*4882a593Smuzhiyun return -EINTR;
507*4882a593Smuzhiyun }
508*4882a593Smuzhiyun wil_info(wil, "Proceed with recovery\n");
509*4882a593Smuzhiyun return 0;
510*4882a593Smuzhiyun }
511*4882a593Smuzhiyun
wil_set_recovery_state(struct wil6210_priv * wil,int state)512*4882a593Smuzhiyun void wil_set_recovery_state(struct wil6210_priv *wil, int state)
513*4882a593Smuzhiyun {
514*4882a593Smuzhiyun wil_dbg_misc(wil, "set_recovery_state: %d -> %d\n",
515*4882a593Smuzhiyun wil->recovery_state, state);
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun wil->recovery_state = state;
518*4882a593Smuzhiyun wake_up_interruptible(&wil->wq);
519*4882a593Smuzhiyun }
520*4882a593Smuzhiyun
wil_is_recovery_blocked(struct wil6210_priv * wil)521*4882a593Smuzhiyun bool wil_is_recovery_blocked(struct wil6210_priv *wil)
522*4882a593Smuzhiyun {
523*4882a593Smuzhiyun return no_fw_recovery && (wil->recovery_state == fw_recovery_pending);
524*4882a593Smuzhiyun }
525*4882a593Smuzhiyun
wil_fw_error_worker(struct work_struct * work)526*4882a593Smuzhiyun static void wil_fw_error_worker(struct work_struct *work)
527*4882a593Smuzhiyun {
528*4882a593Smuzhiyun struct wil6210_priv *wil = container_of(work, struct wil6210_priv,
529*4882a593Smuzhiyun fw_error_worker);
530*4882a593Smuzhiyun struct net_device *ndev = wil->main_ndev;
531*4882a593Smuzhiyun struct wireless_dev *wdev;
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun wil_dbg_misc(wil, "fw error worker\n");
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun if (!ndev || !(ndev->flags & IFF_UP)) {
536*4882a593Smuzhiyun wil_info(wil, "No recovery - interface is down\n");
537*4882a593Smuzhiyun return;
538*4882a593Smuzhiyun }
539*4882a593Smuzhiyun wdev = ndev->ieee80211_ptr;
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun /* increment @recovery_count if less then WIL6210_FW_RECOVERY_TO
542*4882a593Smuzhiyun * passed since last recovery attempt
543*4882a593Smuzhiyun */
544*4882a593Smuzhiyun if (time_is_after_jiffies(wil->last_fw_recovery +
545*4882a593Smuzhiyun WIL6210_FW_RECOVERY_TO))
546*4882a593Smuzhiyun wil->recovery_count++;
547*4882a593Smuzhiyun else
548*4882a593Smuzhiyun wil->recovery_count = 1; /* fw was alive for a long time */
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun if (wil->recovery_count > WIL6210_FW_RECOVERY_RETRIES) {
551*4882a593Smuzhiyun wil_err(wil, "too many recovery attempts (%d), giving up\n",
552*4882a593Smuzhiyun wil->recovery_count);
553*4882a593Smuzhiyun return;
554*4882a593Smuzhiyun }
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun wil->last_fw_recovery = jiffies;
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun wil_info(wil, "fw error recovery requested (try %d)...\n",
559*4882a593Smuzhiyun wil->recovery_count);
560*4882a593Smuzhiyun if (!no_fw_recovery)
561*4882a593Smuzhiyun wil->recovery_state = fw_recovery_running;
562*4882a593Smuzhiyun if (wil_wait_for_recovery(wil) != 0)
563*4882a593Smuzhiyun return;
564*4882a593Smuzhiyun
565*4882a593Smuzhiyun rtnl_lock();
566*4882a593Smuzhiyun mutex_lock(&wil->mutex);
567*4882a593Smuzhiyun /* Needs adaptation for multiple VIFs
568*4882a593Smuzhiyun * need to go over all VIFs and consider the appropriate
569*4882a593Smuzhiyun * recovery because each one can have different iftype.
570*4882a593Smuzhiyun */
571*4882a593Smuzhiyun switch (wdev->iftype) {
572*4882a593Smuzhiyun case NL80211_IFTYPE_STATION:
573*4882a593Smuzhiyun case NL80211_IFTYPE_P2P_CLIENT:
574*4882a593Smuzhiyun case NL80211_IFTYPE_MONITOR:
575*4882a593Smuzhiyun /* silent recovery, upper layers will see disconnect */
576*4882a593Smuzhiyun __wil_down(wil);
577*4882a593Smuzhiyun __wil_up(wil);
578*4882a593Smuzhiyun break;
579*4882a593Smuzhiyun case NL80211_IFTYPE_AP:
580*4882a593Smuzhiyun case NL80211_IFTYPE_P2P_GO:
581*4882a593Smuzhiyun if (no_fw_recovery) /* upper layers do recovery */
582*4882a593Smuzhiyun break;
583*4882a593Smuzhiyun /* silent recovery, upper layers will see disconnect */
584*4882a593Smuzhiyun __wil_down(wil);
585*4882a593Smuzhiyun __wil_up(wil);
586*4882a593Smuzhiyun mutex_unlock(&wil->mutex);
587*4882a593Smuzhiyun wil_cfg80211_ap_recovery(wil);
588*4882a593Smuzhiyun mutex_lock(&wil->mutex);
589*4882a593Smuzhiyun wil_info(wil, "... completed\n");
590*4882a593Smuzhiyun break;
591*4882a593Smuzhiyun default:
592*4882a593Smuzhiyun wil_err(wil, "No recovery - unknown interface type %d\n",
593*4882a593Smuzhiyun wdev->iftype);
594*4882a593Smuzhiyun break;
595*4882a593Smuzhiyun }
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun mutex_unlock(&wil->mutex);
598*4882a593Smuzhiyun rtnl_unlock();
599*4882a593Smuzhiyun }
600*4882a593Smuzhiyun
wil_find_free_ring(struct wil6210_priv * wil)601*4882a593Smuzhiyun static int wil_find_free_ring(struct wil6210_priv *wil)
602*4882a593Smuzhiyun {
603*4882a593Smuzhiyun int i;
604*4882a593Smuzhiyun int min_ring_id = wil_get_min_tx_ring_id(wil);
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun for (i = min_ring_id; i < WIL6210_MAX_TX_RINGS; i++) {
607*4882a593Smuzhiyun if (!wil->ring_tx[i].va)
608*4882a593Smuzhiyun return i;
609*4882a593Smuzhiyun }
610*4882a593Smuzhiyun return -EINVAL;
611*4882a593Smuzhiyun }
612*4882a593Smuzhiyun
wil_ring_init_tx(struct wil6210_vif * vif,int cid)613*4882a593Smuzhiyun int wil_ring_init_tx(struct wil6210_vif *vif, int cid)
614*4882a593Smuzhiyun {
615*4882a593Smuzhiyun struct wil6210_priv *wil = vif_to_wil(vif);
616*4882a593Smuzhiyun int rc = -EINVAL, ringid;
617*4882a593Smuzhiyun
618*4882a593Smuzhiyun if (cid < 0) {
619*4882a593Smuzhiyun wil_err(wil, "No connection pending\n");
620*4882a593Smuzhiyun goto out;
621*4882a593Smuzhiyun }
622*4882a593Smuzhiyun ringid = wil_find_free_ring(wil);
623*4882a593Smuzhiyun if (ringid < 0) {
624*4882a593Smuzhiyun wil_err(wil, "No free vring found\n");
625*4882a593Smuzhiyun goto out;
626*4882a593Smuzhiyun }
627*4882a593Smuzhiyun
628*4882a593Smuzhiyun wil_dbg_wmi(wil, "Configure for connection CID %d MID %d ring %d\n",
629*4882a593Smuzhiyun cid, vif->mid, ringid);
630*4882a593Smuzhiyun
631*4882a593Smuzhiyun rc = wil->txrx_ops.ring_init_tx(vif, ringid, 1 << tx_ring_order,
632*4882a593Smuzhiyun cid, 0);
633*4882a593Smuzhiyun if (rc)
634*4882a593Smuzhiyun wil_err(wil, "init TX for CID %d MID %d vring %d failed\n",
635*4882a593Smuzhiyun cid, vif->mid, ringid);
636*4882a593Smuzhiyun
637*4882a593Smuzhiyun out:
638*4882a593Smuzhiyun return rc;
639*4882a593Smuzhiyun }
640*4882a593Smuzhiyun
wil_bcast_init(struct wil6210_vif * vif)641*4882a593Smuzhiyun int wil_bcast_init(struct wil6210_vif *vif)
642*4882a593Smuzhiyun {
643*4882a593Smuzhiyun struct wil6210_priv *wil = vif_to_wil(vif);
644*4882a593Smuzhiyun int ri = vif->bcast_ring, rc;
645*4882a593Smuzhiyun
646*4882a593Smuzhiyun if (ri >= 0 && wil->ring_tx[ri].va)
647*4882a593Smuzhiyun return 0;
648*4882a593Smuzhiyun
649*4882a593Smuzhiyun ri = wil_find_free_ring(wil);
650*4882a593Smuzhiyun if (ri < 0)
651*4882a593Smuzhiyun return ri;
652*4882a593Smuzhiyun
653*4882a593Smuzhiyun vif->bcast_ring = ri;
654*4882a593Smuzhiyun rc = wil->txrx_ops.ring_init_bcast(vif, ri, 1 << bcast_ring_order);
655*4882a593Smuzhiyun if (rc)
656*4882a593Smuzhiyun vif->bcast_ring = -1;
657*4882a593Smuzhiyun
658*4882a593Smuzhiyun return rc;
659*4882a593Smuzhiyun }
660*4882a593Smuzhiyun
wil_bcast_fini(struct wil6210_vif * vif)661*4882a593Smuzhiyun void wil_bcast_fini(struct wil6210_vif *vif)
662*4882a593Smuzhiyun {
663*4882a593Smuzhiyun struct wil6210_priv *wil = vif_to_wil(vif);
664*4882a593Smuzhiyun int ri = vif->bcast_ring;
665*4882a593Smuzhiyun
666*4882a593Smuzhiyun if (ri < 0)
667*4882a593Smuzhiyun return;
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun vif->bcast_ring = -1;
670*4882a593Smuzhiyun wil_ring_fini_tx(wil, ri);
671*4882a593Smuzhiyun }
672*4882a593Smuzhiyun
wil_bcast_fini_all(struct wil6210_priv * wil)673*4882a593Smuzhiyun void wil_bcast_fini_all(struct wil6210_priv *wil)
674*4882a593Smuzhiyun {
675*4882a593Smuzhiyun int i;
676*4882a593Smuzhiyun struct wil6210_vif *vif;
677*4882a593Smuzhiyun
678*4882a593Smuzhiyun for (i = 0; i < GET_MAX_VIFS(wil); i++) {
679*4882a593Smuzhiyun vif = wil->vifs[i];
680*4882a593Smuzhiyun if (vif)
681*4882a593Smuzhiyun wil_bcast_fini(vif);
682*4882a593Smuzhiyun }
683*4882a593Smuzhiyun }
684*4882a593Smuzhiyun
wil_priv_init(struct wil6210_priv * wil)685*4882a593Smuzhiyun int wil_priv_init(struct wil6210_priv *wil)
686*4882a593Smuzhiyun {
687*4882a593Smuzhiyun uint i;
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun wil_dbg_misc(wil, "priv_init\n");
690*4882a593Smuzhiyun
691*4882a593Smuzhiyun memset(wil->sta, 0, sizeof(wil->sta));
692*4882a593Smuzhiyun for (i = 0; i < WIL6210_MAX_CID; i++) {
693*4882a593Smuzhiyun spin_lock_init(&wil->sta[i].tid_rx_lock);
694*4882a593Smuzhiyun wil->sta[i].mid = U8_MAX;
695*4882a593Smuzhiyun }
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun for (i = 0; i < WIL6210_MAX_TX_RINGS; i++) {
698*4882a593Smuzhiyun spin_lock_init(&wil->ring_tx_data[i].lock);
699*4882a593Smuzhiyun wil->ring2cid_tid[i][0] = WIL6210_MAX_CID;
700*4882a593Smuzhiyun }
701*4882a593Smuzhiyun
702*4882a593Smuzhiyun mutex_init(&wil->mutex);
703*4882a593Smuzhiyun mutex_init(&wil->vif_mutex);
704*4882a593Smuzhiyun mutex_init(&wil->wmi_mutex);
705*4882a593Smuzhiyun mutex_init(&wil->halp.lock);
706*4882a593Smuzhiyun
707*4882a593Smuzhiyun init_completion(&wil->wmi_ready);
708*4882a593Smuzhiyun init_completion(&wil->wmi_call);
709*4882a593Smuzhiyun init_completion(&wil->halp.comp);
710*4882a593Smuzhiyun
711*4882a593Smuzhiyun INIT_WORK(&wil->wmi_event_worker, wmi_event_worker);
712*4882a593Smuzhiyun INIT_WORK(&wil->fw_error_worker, wil_fw_error_worker);
713*4882a593Smuzhiyun
714*4882a593Smuzhiyun INIT_LIST_HEAD(&wil->pending_wmi_ev);
715*4882a593Smuzhiyun spin_lock_init(&wil->wmi_ev_lock);
716*4882a593Smuzhiyun spin_lock_init(&wil->net_queue_lock);
717*4882a593Smuzhiyun spin_lock_init(&wil->eap_lock);
718*4882a593Smuzhiyun
719*4882a593Smuzhiyun init_waitqueue_head(&wil->wq);
720*4882a593Smuzhiyun init_rwsem(&wil->mem_lock);
721*4882a593Smuzhiyun
722*4882a593Smuzhiyun wil->wmi_wq = create_singlethread_workqueue(WIL_NAME "_wmi");
723*4882a593Smuzhiyun if (!wil->wmi_wq)
724*4882a593Smuzhiyun return -EAGAIN;
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun wil->wq_service = create_singlethread_workqueue(WIL_NAME "_service");
727*4882a593Smuzhiyun if (!wil->wq_service)
728*4882a593Smuzhiyun goto out_wmi_wq;
729*4882a593Smuzhiyun
730*4882a593Smuzhiyun wil->last_fw_recovery = jiffies;
731*4882a593Smuzhiyun wil->tx_interframe_timeout = WIL6210_ITR_TX_INTERFRAME_TIMEOUT_DEFAULT;
732*4882a593Smuzhiyun wil->rx_interframe_timeout = WIL6210_ITR_RX_INTERFRAME_TIMEOUT_DEFAULT;
733*4882a593Smuzhiyun wil->tx_max_burst_duration = WIL6210_ITR_TX_MAX_BURST_DURATION_DEFAULT;
734*4882a593Smuzhiyun wil->rx_max_burst_duration = WIL6210_ITR_RX_MAX_BURST_DURATION_DEFAULT;
735*4882a593Smuzhiyun
736*4882a593Smuzhiyun if (rx_ring_overflow_thrsh == WIL6210_RX_HIGH_TRSH_INIT)
737*4882a593Smuzhiyun rx_ring_overflow_thrsh = WIL6210_RX_HIGH_TRSH_DEFAULT;
738*4882a593Smuzhiyun
739*4882a593Smuzhiyun wil->ps_profile = WMI_PS_PROFILE_TYPE_DEFAULT;
740*4882a593Smuzhiyun
741*4882a593Smuzhiyun wil->wakeup_trigger = WMI_WAKEUP_TRIGGER_UCAST |
742*4882a593Smuzhiyun WMI_WAKEUP_TRIGGER_BCAST;
743*4882a593Smuzhiyun memset(&wil->suspend_stats, 0, sizeof(wil->suspend_stats));
744*4882a593Smuzhiyun wil->ring_idle_trsh = 16;
745*4882a593Smuzhiyun
746*4882a593Smuzhiyun wil->reply_mid = U8_MAX;
747*4882a593Smuzhiyun wil->max_vifs = 1;
748*4882a593Smuzhiyun wil->max_assoc_sta = max_assoc_sta;
749*4882a593Smuzhiyun
750*4882a593Smuzhiyun /* edma configuration can be updated via debugfs before allocation */
751*4882a593Smuzhiyun wil->num_rx_status_rings = WIL_DEFAULT_NUM_RX_STATUS_RINGS;
752*4882a593Smuzhiyun wil->tx_status_ring_order = WIL_TX_SRING_SIZE_ORDER_DEFAULT;
753*4882a593Smuzhiyun
754*4882a593Smuzhiyun /* Rx status ring size should be bigger than the number of RX buffers
755*4882a593Smuzhiyun * in order to prevent backpressure on the status ring, which may
756*4882a593Smuzhiyun * cause HW freeze.
757*4882a593Smuzhiyun */
758*4882a593Smuzhiyun wil->rx_status_ring_order = WIL_RX_SRING_SIZE_ORDER_DEFAULT;
759*4882a593Smuzhiyun /* Number of RX buffer IDs should be bigger than the RX descriptor
760*4882a593Smuzhiyun * ring size as in HW reorder flow, the HW can consume additional
761*4882a593Smuzhiyun * buffers before releasing the previous ones.
762*4882a593Smuzhiyun */
763*4882a593Smuzhiyun wil->rx_buff_id_count = WIL_RX_BUFF_ARR_SIZE_DEFAULT;
764*4882a593Smuzhiyun
765*4882a593Smuzhiyun wil->amsdu_en = true;
766*4882a593Smuzhiyun
767*4882a593Smuzhiyun return 0;
768*4882a593Smuzhiyun
769*4882a593Smuzhiyun out_wmi_wq:
770*4882a593Smuzhiyun destroy_workqueue(wil->wmi_wq);
771*4882a593Smuzhiyun
772*4882a593Smuzhiyun return -EAGAIN;
773*4882a593Smuzhiyun }
774*4882a593Smuzhiyun
wil6210_bus_request(struct wil6210_priv * wil,u32 kbps)775*4882a593Smuzhiyun void wil6210_bus_request(struct wil6210_priv *wil, u32 kbps)
776*4882a593Smuzhiyun {
777*4882a593Smuzhiyun if (wil->platform_ops.bus_request) {
778*4882a593Smuzhiyun wil->bus_request_kbps = kbps;
779*4882a593Smuzhiyun wil->platform_ops.bus_request(wil->platform_handle, kbps);
780*4882a593Smuzhiyun }
781*4882a593Smuzhiyun }
782*4882a593Smuzhiyun
783*4882a593Smuzhiyun /**
784*4882a593Smuzhiyun * wil6210_disconnect - disconnect one connection
785*4882a593Smuzhiyun * @vif: virtual interface context
786*4882a593Smuzhiyun * @bssid: peer to disconnect, NULL to disconnect all
787*4882a593Smuzhiyun * @reason_code: Reason code for the Disassociation frame
788*4882a593Smuzhiyun *
789*4882a593Smuzhiyun * Disconnect and release associated resources. Issue WMI
790*4882a593Smuzhiyun * command(s) to trigger MAC disconnect. When command was issued
791*4882a593Smuzhiyun * successfully, call the wil6210_disconnect_complete function
792*4882a593Smuzhiyun * to handle the event synchronously
793*4882a593Smuzhiyun */
wil6210_disconnect(struct wil6210_vif * vif,const u8 * bssid,u16 reason_code)794*4882a593Smuzhiyun void wil6210_disconnect(struct wil6210_vif *vif, const u8 *bssid,
795*4882a593Smuzhiyun u16 reason_code)
796*4882a593Smuzhiyun {
797*4882a593Smuzhiyun struct wil6210_priv *wil = vif_to_wil(vif);
798*4882a593Smuzhiyun
799*4882a593Smuzhiyun wil_dbg_misc(wil, "disconnecting\n");
800*4882a593Smuzhiyun
801*4882a593Smuzhiyun del_timer_sync(&vif->connect_timer);
802*4882a593Smuzhiyun _wil6210_disconnect(vif, bssid, reason_code);
803*4882a593Smuzhiyun }
804*4882a593Smuzhiyun
805*4882a593Smuzhiyun /**
806*4882a593Smuzhiyun * wil6210_disconnect_complete - handle disconnect event
807*4882a593Smuzhiyun * @vif: virtual interface context
808*4882a593Smuzhiyun * @bssid: peer to disconnect, NULL to disconnect all
809*4882a593Smuzhiyun * @reason_code: Reason code for the Disassociation frame
810*4882a593Smuzhiyun *
811*4882a593Smuzhiyun * Release associated resources and indicate upper layers the
812*4882a593Smuzhiyun * connection is terminated.
813*4882a593Smuzhiyun */
wil6210_disconnect_complete(struct wil6210_vif * vif,const u8 * bssid,u16 reason_code)814*4882a593Smuzhiyun void wil6210_disconnect_complete(struct wil6210_vif *vif, const u8 *bssid,
815*4882a593Smuzhiyun u16 reason_code)
816*4882a593Smuzhiyun {
817*4882a593Smuzhiyun struct wil6210_priv *wil = vif_to_wil(vif);
818*4882a593Smuzhiyun
819*4882a593Smuzhiyun wil_dbg_misc(wil, "got disconnect\n");
820*4882a593Smuzhiyun
821*4882a593Smuzhiyun del_timer_sync(&vif->connect_timer);
822*4882a593Smuzhiyun _wil6210_disconnect_complete(vif, bssid, reason_code);
823*4882a593Smuzhiyun }
824*4882a593Smuzhiyun
wil_priv_deinit(struct wil6210_priv * wil)825*4882a593Smuzhiyun void wil_priv_deinit(struct wil6210_priv *wil)
826*4882a593Smuzhiyun {
827*4882a593Smuzhiyun wil_dbg_misc(wil, "priv_deinit\n");
828*4882a593Smuzhiyun
829*4882a593Smuzhiyun wil_set_recovery_state(wil, fw_recovery_idle);
830*4882a593Smuzhiyun cancel_work_sync(&wil->fw_error_worker);
831*4882a593Smuzhiyun wmi_event_flush(wil);
832*4882a593Smuzhiyun destroy_workqueue(wil->wq_service);
833*4882a593Smuzhiyun destroy_workqueue(wil->wmi_wq);
834*4882a593Smuzhiyun kfree(wil->brd_info);
835*4882a593Smuzhiyun }
836*4882a593Smuzhiyun
wil_shutdown_bl(struct wil6210_priv * wil)837*4882a593Smuzhiyun static void wil_shutdown_bl(struct wil6210_priv *wil)
838*4882a593Smuzhiyun {
839*4882a593Smuzhiyun u32 val;
840*4882a593Smuzhiyun
841*4882a593Smuzhiyun wil_s(wil, RGF_USER_BL +
842*4882a593Smuzhiyun offsetof(struct bl_dedicated_registers_v1,
843*4882a593Smuzhiyun bl_shutdown_handshake), BL_SHUTDOWN_HS_GRTD);
844*4882a593Smuzhiyun
845*4882a593Smuzhiyun usleep_range(100, 150);
846*4882a593Smuzhiyun
847*4882a593Smuzhiyun val = wil_r(wil, RGF_USER_BL +
848*4882a593Smuzhiyun offsetof(struct bl_dedicated_registers_v1,
849*4882a593Smuzhiyun bl_shutdown_handshake));
850*4882a593Smuzhiyun if (val & BL_SHUTDOWN_HS_RTD) {
851*4882a593Smuzhiyun wil_dbg_misc(wil, "BL is ready for halt\n");
852*4882a593Smuzhiyun return;
853*4882a593Smuzhiyun }
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun wil_err(wil, "BL did not report ready for halt\n");
856*4882a593Smuzhiyun }
857*4882a593Smuzhiyun
858*4882a593Smuzhiyun /* this format is used by ARC embedded CPU for instruction memory */
ARC_me_imm32(u32 d)859*4882a593Smuzhiyun static inline u32 ARC_me_imm32(u32 d)
860*4882a593Smuzhiyun {
861*4882a593Smuzhiyun return ((d & 0xffff0000) >> 16) | ((d & 0x0000ffff) << 16);
862*4882a593Smuzhiyun }
863*4882a593Smuzhiyun
864*4882a593Smuzhiyun /* defines access to interrupt vectors for wil_freeze_bl */
865*4882a593Smuzhiyun #define ARC_IRQ_VECTOR_OFFSET(N) ((N) * 8)
866*4882a593Smuzhiyun /* ARC long jump instruction */
867*4882a593Smuzhiyun #define ARC_JAL_INST (0x20200f80)
868*4882a593Smuzhiyun
wil_freeze_bl(struct wil6210_priv * wil)869*4882a593Smuzhiyun static void wil_freeze_bl(struct wil6210_priv *wil)
870*4882a593Smuzhiyun {
871*4882a593Smuzhiyun u32 jal, upc, saved;
872*4882a593Smuzhiyun u32 ivt3 = ARC_IRQ_VECTOR_OFFSET(3);
873*4882a593Smuzhiyun
874*4882a593Smuzhiyun jal = wil_r(wil, wil->iccm_base + ivt3);
875*4882a593Smuzhiyun if (jal != ARC_me_imm32(ARC_JAL_INST)) {
876*4882a593Smuzhiyun wil_dbg_misc(wil, "invalid IVT entry found, skipping\n");
877*4882a593Smuzhiyun return;
878*4882a593Smuzhiyun }
879*4882a593Smuzhiyun
880*4882a593Smuzhiyun /* prevent the target from entering deep sleep
881*4882a593Smuzhiyun * and disabling memory access
882*4882a593Smuzhiyun */
883*4882a593Smuzhiyun saved = wil_r(wil, RGF_USER_USAGE_8);
884*4882a593Smuzhiyun wil_w(wil, RGF_USER_USAGE_8, saved | BIT_USER_PREVENT_DEEP_SLEEP);
885*4882a593Smuzhiyun usleep_range(20, 25); /* let the BL process the bit */
886*4882a593Smuzhiyun
887*4882a593Smuzhiyun /* redirect to endless loop in the INT_L1 context and let it trap */
888*4882a593Smuzhiyun wil_w(wil, wil->iccm_base + ivt3 + 4, ARC_me_imm32(ivt3));
889*4882a593Smuzhiyun usleep_range(20, 25); /* let the BL get into the trap */
890*4882a593Smuzhiyun
891*4882a593Smuzhiyun /* verify the BL is frozen */
892*4882a593Smuzhiyun upc = wil_r(wil, RGF_USER_CPU_PC);
893*4882a593Smuzhiyun if (upc < ivt3 || (upc > (ivt3 + 8)))
894*4882a593Smuzhiyun wil_dbg_misc(wil, "BL freeze failed, PC=0x%08X\n", upc);
895*4882a593Smuzhiyun
896*4882a593Smuzhiyun wil_w(wil, RGF_USER_USAGE_8, saved);
897*4882a593Smuzhiyun }
898*4882a593Smuzhiyun
wil_bl_prepare_halt(struct wil6210_priv * wil)899*4882a593Smuzhiyun static void wil_bl_prepare_halt(struct wil6210_priv *wil)
900*4882a593Smuzhiyun {
901*4882a593Smuzhiyun u32 tmp, ver;
902*4882a593Smuzhiyun
903*4882a593Smuzhiyun /* before halting device CPU driver must make sure BL is not accessing
904*4882a593Smuzhiyun * host memory. This is done differently depending on BL version:
905*4882a593Smuzhiyun * 1. For very old BL versions the procedure is skipped
906*4882a593Smuzhiyun * (not supported).
907*4882a593Smuzhiyun * 2. For old BL version we use a special trick to freeze the BL
908*4882a593Smuzhiyun * 3. For new BL versions we shutdown the BL using handshake procedure.
909*4882a593Smuzhiyun */
910*4882a593Smuzhiyun tmp = wil_r(wil, RGF_USER_BL +
911*4882a593Smuzhiyun offsetof(struct bl_dedicated_registers_v0,
912*4882a593Smuzhiyun boot_loader_struct_version));
913*4882a593Smuzhiyun if (!tmp) {
914*4882a593Smuzhiyun wil_dbg_misc(wil, "old BL, skipping halt preparation\n");
915*4882a593Smuzhiyun return;
916*4882a593Smuzhiyun }
917*4882a593Smuzhiyun
918*4882a593Smuzhiyun tmp = wil_r(wil, RGF_USER_BL +
919*4882a593Smuzhiyun offsetof(struct bl_dedicated_registers_v1,
920*4882a593Smuzhiyun bl_shutdown_handshake));
921*4882a593Smuzhiyun ver = BL_SHUTDOWN_HS_PROT_VER(tmp);
922*4882a593Smuzhiyun
923*4882a593Smuzhiyun if (ver > 0)
924*4882a593Smuzhiyun wil_shutdown_bl(wil);
925*4882a593Smuzhiyun else
926*4882a593Smuzhiyun wil_freeze_bl(wil);
927*4882a593Smuzhiyun }
928*4882a593Smuzhiyun
wil_halt_cpu(struct wil6210_priv * wil)929*4882a593Smuzhiyun static inline void wil_halt_cpu(struct wil6210_priv *wil)
930*4882a593Smuzhiyun {
931*4882a593Smuzhiyun if (wil->hw_version >= HW_VER_TALYN_MB) {
932*4882a593Smuzhiyun wil_w(wil, RGF_USER_USER_CPU_0_TALYN_MB,
933*4882a593Smuzhiyun BIT_USER_USER_CPU_MAN_RST);
934*4882a593Smuzhiyun wil_w(wil, RGF_USER_MAC_CPU_0_TALYN_MB,
935*4882a593Smuzhiyun BIT_USER_MAC_CPU_MAN_RST);
936*4882a593Smuzhiyun } else {
937*4882a593Smuzhiyun wil_w(wil, RGF_USER_USER_CPU_0, BIT_USER_USER_CPU_MAN_RST);
938*4882a593Smuzhiyun wil_w(wil, RGF_USER_MAC_CPU_0, BIT_USER_MAC_CPU_MAN_RST);
939*4882a593Smuzhiyun }
940*4882a593Smuzhiyun }
941*4882a593Smuzhiyun
wil_release_cpu(struct wil6210_priv * wil)942*4882a593Smuzhiyun static inline void wil_release_cpu(struct wil6210_priv *wil)
943*4882a593Smuzhiyun {
944*4882a593Smuzhiyun /* Start CPU */
945*4882a593Smuzhiyun if (wil->hw_version >= HW_VER_TALYN_MB)
946*4882a593Smuzhiyun wil_w(wil, RGF_USER_USER_CPU_0_TALYN_MB, 1);
947*4882a593Smuzhiyun else
948*4882a593Smuzhiyun wil_w(wil, RGF_USER_USER_CPU_0, 1);
949*4882a593Smuzhiyun }
950*4882a593Smuzhiyun
wil_set_oob_mode(struct wil6210_priv * wil,u8 mode)951*4882a593Smuzhiyun static void wil_set_oob_mode(struct wil6210_priv *wil, u8 mode)
952*4882a593Smuzhiyun {
953*4882a593Smuzhiyun wil_info(wil, "oob_mode to %d\n", mode);
954*4882a593Smuzhiyun switch (mode) {
955*4882a593Smuzhiyun case 0:
956*4882a593Smuzhiyun wil_c(wil, RGF_USER_USAGE_6, BIT_USER_OOB_MODE |
957*4882a593Smuzhiyun BIT_USER_OOB_R2_MODE);
958*4882a593Smuzhiyun break;
959*4882a593Smuzhiyun case 1:
960*4882a593Smuzhiyun wil_c(wil, RGF_USER_USAGE_6, BIT_USER_OOB_R2_MODE);
961*4882a593Smuzhiyun wil_s(wil, RGF_USER_USAGE_6, BIT_USER_OOB_MODE);
962*4882a593Smuzhiyun break;
963*4882a593Smuzhiyun case 2:
964*4882a593Smuzhiyun wil_c(wil, RGF_USER_USAGE_6, BIT_USER_OOB_MODE);
965*4882a593Smuzhiyun wil_s(wil, RGF_USER_USAGE_6, BIT_USER_OOB_R2_MODE);
966*4882a593Smuzhiyun break;
967*4882a593Smuzhiyun default:
968*4882a593Smuzhiyun wil_err(wil, "invalid oob_mode: %d\n", mode);
969*4882a593Smuzhiyun }
970*4882a593Smuzhiyun }
971*4882a593Smuzhiyun
wil_wait_device_ready(struct wil6210_priv * wil,int no_flash)972*4882a593Smuzhiyun static int wil_wait_device_ready(struct wil6210_priv *wil, int no_flash)
973*4882a593Smuzhiyun {
974*4882a593Smuzhiyun int delay = 0;
975*4882a593Smuzhiyun u32 x, x1 = 0;
976*4882a593Smuzhiyun
977*4882a593Smuzhiyun /* wait until device ready. */
978*4882a593Smuzhiyun if (no_flash) {
979*4882a593Smuzhiyun msleep(PMU_READY_DELAY_MS);
980*4882a593Smuzhiyun
981*4882a593Smuzhiyun wil_dbg_misc(wil, "Reset completed\n");
982*4882a593Smuzhiyun } else {
983*4882a593Smuzhiyun do {
984*4882a593Smuzhiyun msleep(RST_DELAY);
985*4882a593Smuzhiyun x = wil_r(wil, RGF_USER_BL +
986*4882a593Smuzhiyun offsetof(struct bl_dedicated_registers_v0,
987*4882a593Smuzhiyun boot_loader_ready));
988*4882a593Smuzhiyun if (x1 != x) {
989*4882a593Smuzhiyun wil_dbg_misc(wil, "BL.ready 0x%08x => 0x%08x\n",
990*4882a593Smuzhiyun x1, x);
991*4882a593Smuzhiyun x1 = x;
992*4882a593Smuzhiyun }
993*4882a593Smuzhiyun if (delay++ > RST_COUNT) {
994*4882a593Smuzhiyun wil_err(wil, "Reset not completed, bl.ready 0x%08x\n",
995*4882a593Smuzhiyun x);
996*4882a593Smuzhiyun return -ETIME;
997*4882a593Smuzhiyun }
998*4882a593Smuzhiyun } while (x != BL_READY);
999*4882a593Smuzhiyun
1000*4882a593Smuzhiyun wil_dbg_misc(wil, "Reset completed in %d ms\n",
1001*4882a593Smuzhiyun delay * RST_DELAY);
1002*4882a593Smuzhiyun }
1003*4882a593Smuzhiyun
1004*4882a593Smuzhiyun return 0;
1005*4882a593Smuzhiyun }
1006*4882a593Smuzhiyun
wil_wait_device_ready_talyn_mb(struct wil6210_priv * wil)1007*4882a593Smuzhiyun static int wil_wait_device_ready_talyn_mb(struct wil6210_priv *wil)
1008*4882a593Smuzhiyun {
1009*4882a593Smuzhiyun u32 otp_hw;
1010*4882a593Smuzhiyun u8 signature_status;
1011*4882a593Smuzhiyun bool otp_signature_err;
1012*4882a593Smuzhiyun bool hw_section_done;
1013*4882a593Smuzhiyun u32 otp_qc_secured;
1014*4882a593Smuzhiyun int delay = 0;
1015*4882a593Smuzhiyun
1016*4882a593Smuzhiyun /* Wait for OTP signature test to complete */
1017*4882a593Smuzhiyun usleep_range(2000, 2200);
1018*4882a593Smuzhiyun
1019*4882a593Smuzhiyun wil->boot_config = WIL_BOOT_ERR;
1020*4882a593Smuzhiyun
1021*4882a593Smuzhiyun /* Poll until OTP signature status is valid.
1022*4882a593Smuzhiyun * In vanilla and development modes, when signature test is complete
1023*4882a593Smuzhiyun * HW sets BIT_OTP_SIGNATURE_ERR_TALYN_MB.
1024*4882a593Smuzhiyun * In production mode BIT_OTP_SIGNATURE_ERR_TALYN_MB remains 0, poll
1025*4882a593Smuzhiyun * for signature status change to 2 or 3.
1026*4882a593Smuzhiyun */
1027*4882a593Smuzhiyun do {
1028*4882a593Smuzhiyun otp_hw = wil_r(wil, RGF_USER_OTP_HW_RD_MACHINE_1);
1029*4882a593Smuzhiyun signature_status = WIL_GET_BITS(otp_hw, 8, 9);
1030*4882a593Smuzhiyun otp_signature_err = otp_hw & BIT_OTP_SIGNATURE_ERR_TALYN_MB;
1031*4882a593Smuzhiyun
1032*4882a593Smuzhiyun if (otp_signature_err &&
1033*4882a593Smuzhiyun signature_status == WIL_SIG_STATUS_VANILLA) {
1034*4882a593Smuzhiyun wil->boot_config = WIL_BOOT_VANILLA;
1035*4882a593Smuzhiyun break;
1036*4882a593Smuzhiyun }
1037*4882a593Smuzhiyun if (otp_signature_err &&
1038*4882a593Smuzhiyun signature_status == WIL_SIG_STATUS_DEVELOPMENT) {
1039*4882a593Smuzhiyun wil->boot_config = WIL_BOOT_DEVELOPMENT;
1040*4882a593Smuzhiyun break;
1041*4882a593Smuzhiyun }
1042*4882a593Smuzhiyun if (!otp_signature_err &&
1043*4882a593Smuzhiyun signature_status == WIL_SIG_STATUS_PRODUCTION) {
1044*4882a593Smuzhiyun wil->boot_config = WIL_BOOT_PRODUCTION;
1045*4882a593Smuzhiyun break;
1046*4882a593Smuzhiyun }
1047*4882a593Smuzhiyun if (!otp_signature_err &&
1048*4882a593Smuzhiyun signature_status ==
1049*4882a593Smuzhiyun WIL_SIG_STATUS_CORRUPTED_PRODUCTION) {
1050*4882a593Smuzhiyun /* Unrecognized OTP signature found. Possibly a
1051*4882a593Smuzhiyun * corrupted production signature, access control
1052*4882a593Smuzhiyun * is applied as in production mode, therefore
1053*4882a593Smuzhiyun * do not fail
1054*4882a593Smuzhiyun */
1055*4882a593Smuzhiyun wil->boot_config = WIL_BOOT_PRODUCTION;
1056*4882a593Smuzhiyun break;
1057*4882a593Smuzhiyun }
1058*4882a593Smuzhiyun if (delay++ > OTP_HW_COUNT)
1059*4882a593Smuzhiyun break;
1060*4882a593Smuzhiyun
1061*4882a593Smuzhiyun usleep_range(OTP_HW_DELAY, OTP_HW_DELAY + 10);
1062*4882a593Smuzhiyun } while (!otp_signature_err && signature_status == 0);
1063*4882a593Smuzhiyun
1064*4882a593Smuzhiyun if (wil->boot_config == WIL_BOOT_ERR) {
1065*4882a593Smuzhiyun wil_err(wil,
1066*4882a593Smuzhiyun "invalid boot config, signature_status %d otp_signature_err %d\n",
1067*4882a593Smuzhiyun signature_status, otp_signature_err);
1068*4882a593Smuzhiyun return -ETIME;
1069*4882a593Smuzhiyun }
1070*4882a593Smuzhiyun
1071*4882a593Smuzhiyun wil_dbg_misc(wil,
1072*4882a593Smuzhiyun "signature test done in %d usec, otp_hw 0x%x, boot_config %d\n",
1073*4882a593Smuzhiyun delay * OTP_HW_DELAY, otp_hw, wil->boot_config);
1074*4882a593Smuzhiyun
1075*4882a593Smuzhiyun if (wil->boot_config == WIL_BOOT_VANILLA)
1076*4882a593Smuzhiyun /* Assuming not SPI boot (currently not supported) */
1077*4882a593Smuzhiyun goto out;
1078*4882a593Smuzhiyun
1079*4882a593Smuzhiyun hw_section_done = otp_hw & BIT_OTP_HW_SECTION_DONE_TALYN_MB;
1080*4882a593Smuzhiyun delay = 0;
1081*4882a593Smuzhiyun
1082*4882a593Smuzhiyun while (!hw_section_done) {
1083*4882a593Smuzhiyun msleep(RST_DELAY);
1084*4882a593Smuzhiyun
1085*4882a593Smuzhiyun otp_hw = wil_r(wil, RGF_USER_OTP_HW_RD_MACHINE_1);
1086*4882a593Smuzhiyun hw_section_done = otp_hw & BIT_OTP_HW_SECTION_DONE_TALYN_MB;
1087*4882a593Smuzhiyun
1088*4882a593Smuzhiyun if (delay++ > RST_COUNT) {
1089*4882a593Smuzhiyun wil_err(wil, "TO waiting for hw_section_done\n");
1090*4882a593Smuzhiyun return -ETIME;
1091*4882a593Smuzhiyun }
1092*4882a593Smuzhiyun }
1093*4882a593Smuzhiyun
1094*4882a593Smuzhiyun wil_dbg_misc(wil, "HW section done in %d ms\n", delay * RST_DELAY);
1095*4882a593Smuzhiyun
1096*4882a593Smuzhiyun otp_qc_secured = wil_r(wil, RGF_OTP_QC_SECURED);
1097*4882a593Smuzhiyun wil->secured_boot = otp_qc_secured & BIT_BOOT_FROM_ROM ? 1 : 0;
1098*4882a593Smuzhiyun wil_dbg_misc(wil, "secured boot is %sabled\n",
1099*4882a593Smuzhiyun wil->secured_boot ? "en" : "dis");
1100*4882a593Smuzhiyun
1101*4882a593Smuzhiyun out:
1102*4882a593Smuzhiyun wil_dbg_misc(wil, "Reset completed\n");
1103*4882a593Smuzhiyun
1104*4882a593Smuzhiyun return 0;
1105*4882a593Smuzhiyun }
1106*4882a593Smuzhiyun
wil_target_reset(struct wil6210_priv * wil,int no_flash)1107*4882a593Smuzhiyun static int wil_target_reset(struct wil6210_priv *wil, int no_flash)
1108*4882a593Smuzhiyun {
1109*4882a593Smuzhiyun u32 x;
1110*4882a593Smuzhiyun int rc;
1111*4882a593Smuzhiyun
1112*4882a593Smuzhiyun wil_dbg_misc(wil, "Resetting \"%s\"...\n", wil->hw_name);
1113*4882a593Smuzhiyun
1114*4882a593Smuzhiyun if (wil->hw_version < HW_VER_TALYN) {
1115*4882a593Smuzhiyun /* Clear MAC link up */
1116*4882a593Smuzhiyun wil_s(wil, RGF_HP_CTRL, BIT(15));
1117*4882a593Smuzhiyun wil_s(wil, RGF_USER_CLKS_CTL_SW_RST_MASK_0,
1118*4882a593Smuzhiyun BIT_HPAL_PERST_FROM_PAD);
1119*4882a593Smuzhiyun wil_s(wil, RGF_USER_CLKS_CTL_SW_RST_MASK_0, BIT_CAR_PERST_RST);
1120*4882a593Smuzhiyun }
1121*4882a593Smuzhiyun
1122*4882a593Smuzhiyun wil_halt_cpu(wil);
1123*4882a593Smuzhiyun
1124*4882a593Smuzhiyun if (!no_flash) {
1125*4882a593Smuzhiyun /* clear all boot loader "ready" bits */
1126*4882a593Smuzhiyun wil_w(wil, RGF_USER_BL +
1127*4882a593Smuzhiyun offsetof(struct bl_dedicated_registers_v0,
1128*4882a593Smuzhiyun boot_loader_ready), 0);
1129*4882a593Smuzhiyun /* this should be safe to write even with old BLs */
1130*4882a593Smuzhiyun wil_w(wil, RGF_USER_BL +
1131*4882a593Smuzhiyun offsetof(struct bl_dedicated_registers_v1,
1132*4882a593Smuzhiyun bl_shutdown_handshake), 0);
1133*4882a593Smuzhiyun }
1134*4882a593Smuzhiyun /* Clear Fw Download notification */
1135*4882a593Smuzhiyun wil_c(wil, RGF_USER_USAGE_6, BIT(0));
1136*4882a593Smuzhiyun
1137*4882a593Smuzhiyun wil_s(wil, RGF_CAF_OSC_CONTROL, BIT_CAF_OSC_XTAL_EN);
1138*4882a593Smuzhiyun /* XTAL stabilization should take about 3ms */
1139*4882a593Smuzhiyun usleep_range(5000, 7000);
1140*4882a593Smuzhiyun x = wil_r(wil, RGF_CAF_PLL_LOCK_STATUS);
1141*4882a593Smuzhiyun if (!(x & BIT_CAF_OSC_DIG_XTAL_STABLE)) {
1142*4882a593Smuzhiyun wil_err(wil, "Xtal stabilization timeout\n"
1143*4882a593Smuzhiyun "RGF_CAF_PLL_LOCK_STATUS = 0x%08x\n", x);
1144*4882a593Smuzhiyun return -ETIME;
1145*4882a593Smuzhiyun }
1146*4882a593Smuzhiyun /* switch 10k to XTAL*/
1147*4882a593Smuzhiyun wil_c(wil, RGF_USER_SPARROW_M_4, BIT_SPARROW_M_4_SEL_SLEEP_OR_REF);
1148*4882a593Smuzhiyun /* 40 MHz */
1149*4882a593Smuzhiyun wil_c(wil, RGF_USER_CLKS_CTL_0, BIT_USER_CLKS_CAR_AHB_SW_SEL);
1150*4882a593Smuzhiyun
1151*4882a593Smuzhiyun wil_w(wil, RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0, 0x3ff81f);
1152*4882a593Smuzhiyun wil_w(wil, RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1, 0xf);
1153*4882a593Smuzhiyun
1154*4882a593Smuzhiyun if (wil->hw_version >= HW_VER_TALYN_MB) {
1155*4882a593Smuzhiyun wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0x7e000000);
1156*4882a593Smuzhiyun wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_1, 0x0000003f);
1157*4882a593Smuzhiyun wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0xc00000f0);
1158*4882a593Smuzhiyun wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0xffe7fe00);
1159*4882a593Smuzhiyun } else {
1160*4882a593Smuzhiyun wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0xfe000000);
1161*4882a593Smuzhiyun wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_1, 0x0000003f);
1162*4882a593Smuzhiyun wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0x000000f0);
1163*4882a593Smuzhiyun wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0xffe7fe00);
1164*4882a593Smuzhiyun }
1165*4882a593Smuzhiyun
1166*4882a593Smuzhiyun wil_w(wil, RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0, 0x0);
1167*4882a593Smuzhiyun wil_w(wil, RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1, 0x0);
1168*4882a593Smuzhiyun
1169*4882a593Smuzhiyun wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0);
1170*4882a593Smuzhiyun wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0);
1171*4882a593Smuzhiyun wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_1, 0);
1172*4882a593Smuzhiyun wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0);
1173*4882a593Smuzhiyun
1174*4882a593Smuzhiyun wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0x00000003);
1175*4882a593Smuzhiyun /* reset A2 PCIE AHB */
1176*4882a593Smuzhiyun wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0x00008000);
1177*4882a593Smuzhiyun
1178*4882a593Smuzhiyun wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0);
1179*4882a593Smuzhiyun
1180*4882a593Smuzhiyun if (wil->hw_version == HW_VER_TALYN_MB)
1181*4882a593Smuzhiyun rc = wil_wait_device_ready_talyn_mb(wil);
1182*4882a593Smuzhiyun else
1183*4882a593Smuzhiyun rc = wil_wait_device_ready(wil, no_flash);
1184*4882a593Smuzhiyun if (rc)
1185*4882a593Smuzhiyun return rc;
1186*4882a593Smuzhiyun
1187*4882a593Smuzhiyun wil_c(wil, RGF_USER_CLKS_CTL_0, BIT_USER_CLKS_RST_PWGD);
1188*4882a593Smuzhiyun
1189*4882a593Smuzhiyun /* enable fix for HW bug related to the SA/DA swap in AP Rx */
1190*4882a593Smuzhiyun wil_s(wil, RGF_DMA_OFUL_NID_0, BIT_DMA_OFUL_NID_0_RX_EXT_TR_EN |
1191*4882a593Smuzhiyun BIT_DMA_OFUL_NID_0_RX_EXT_A3_SRC);
1192*4882a593Smuzhiyun
1193*4882a593Smuzhiyun if (wil->hw_version < HW_VER_TALYN_MB && no_flash) {
1194*4882a593Smuzhiyun /* Reset OTP HW vectors to fit 40MHz */
1195*4882a593Smuzhiyun wil_w(wil, RGF_USER_XPM_IFC_RD_TIME1, 0x60001);
1196*4882a593Smuzhiyun wil_w(wil, RGF_USER_XPM_IFC_RD_TIME2, 0x20027);
1197*4882a593Smuzhiyun wil_w(wil, RGF_USER_XPM_IFC_RD_TIME3, 0x1);
1198*4882a593Smuzhiyun wil_w(wil, RGF_USER_XPM_IFC_RD_TIME4, 0x20027);
1199*4882a593Smuzhiyun wil_w(wil, RGF_USER_XPM_IFC_RD_TIME5, 0x30003);
1200*4882a593Smuzhiyun wil_w(wil, RGF_USER_XPM_IFC_RD_TIME6, 0x20002);
1201*4882a593Smuzhiyun wil_w(wil, RGF_USER_XPM_IFC_RD_TIME7, 0x60001);
1202*4882a593Smuzhiyun wil_w(wil, RGF_USER_XPM_IFC_RD_TIME8, 0x60001);
1203*4882a593Smuzhiyun wil_w(wil, RGF_USER_XPM_IFC_RD_TIME9, 0x60001);
1204*4882a593Smuzhiyun wil_w(wil, RGF_USER_XPM_IFC_RD_TIME10, 0x60001);
1205*4882a593Smuzhiyun wil_w(wil, RGF_USER_XPM_RD_DOUT_SAMPLE_TIME, 0x57);
1206*4882a593Smuzhiyun }
1207*4882a593Smuzhiyun
1208*4882a593Smuzhiyun return 0;
1209*4882a593Smuzhiyun }
1210*4882a593Smuzhiyun
wil_collect_fw_info(struct wil6210_priv * wil)1211*4882a593Smuzhiyun static void wil_collect_fw_info(struct wil6210_priv *wil)
1212*4882a593Smuzhiyun {
1213*4882a593Smuzhiyun struct wiphy *wiphy = wil_to_wiphy(wil);
1214*4882a593Smuzhiyun u8 retry_short;
1215*4882a593Smuzhiyun int rc;
1216*4882a593Smuzhiyun
1217*4882a593Smuzhiyun wil_refresh_fw_capabilities(wil);
1218*4882a593Smuzhiyun
1219*4882a593Smuzhiyun rc = wmi_get_mgmt_retry(wil, &retry_short);
1220*4882a593Smuzhiyun if (!rc) {
1221*4882a593Smuzhiyun wiphy->retry_short = retry_short;
1222*4882a593Smuzhiyun wil_dbg_misc(wil, "FW retry_short: %d\n", retry_short);
1223*4882a593Smuzhiyun }
1224*4882a593Smuzhiyun }
1225*4882a593Smuzhiyun
wil_refresh_fw_capabilities(struct wil6210_priv * wil)1226*4882a593Smuzhiyun void wil_refresh_fw_capabilities(struct wil6210_priv *wil)
1227*4882a593Smuzhiyun {
1228*4882a593Smuzhiyun struct wiphy *wiphy = wil_to_wiphy(wil);
1229*4882a593Smuzhiyun int features;
1230*4882a593Smuzhiyun
1231*4882a593Smuzhiyun wil->keep_radio_on_during_sleep =
1232*4882a593Smuzhiyun test_bit(WIL_PLATFORM_CAPA_RADIO_ON_IN_SUSPEND,
1233*4882a593Smuzhiyun wil->platform_capa) &&
1234*4882a593Smuzhiyun test_bit(WMI_FW_CAPABILITY_D3_SUSPEND, wil->fw_capabilities);
1235*4882a593Smuzhiyun
1236*4882a593Smuzhiyun wil_info(wil, "keep_radio_on_during_sleep (%d)\n",
1237*4882a593Smuzhiyun wil->keep_radio_on_during_sleep);
1238*4882a593Smuzhiyun
1239*4882a593Smuzhiyun if (test_bit(WMI_FW_CAPABILITY_RSSI_REPORTING, wil->fw_capabilities))
1240*4882a593Smuzhiyun wiphy->signal_type = CFG80211_SIGNAL_TYPE_MBM;
1241*4882a593Smuzhiyun else
1242*4882a593Smuzhiyun wiphy->signal_type = CFG80211_SIGNAL_TYPE_UNSPEC;
1243*4882a593Smuzhiyun
1244*4882a593Smuzhiyun if (test_bit(WMI_FW_CAPABILITY_PNO, wil->fw_capabilities)) {
1245*4882a593Smuzhiyun wiphy->max_sched_scan_reqs = 1;
1246*4882a593Smuzhiyun wiphy->max_sched_scan_ssids = WMI_MAX_PNO_SSID_NUM;
1247*4882a593Smuzhiyun wiphy->max_match_sets = WMI_MAX_PNO_SSID_NUM;
1248*4882a593Smuzhiyun wiphy->max_sched_scan_ie_len = WMI_MAX_IE_LEN;
1249*4882a593Smuzhiyun wiphy->max_sched_scan_plans = WMI_MAX_PLANS_NUM;
1250*4882a593Smuzhiyun }
1251*4882a593Smuzhiyun
1252*4882a593Smuzhiyun if (test_bit(WMI_FW_CAPABILITY_TX_REQ_EXT, wil->fw_capabilities))
1253*4882a593Smuzhiyun wiphy->flags |= WIPHY_FLAG_OFFCHAN_TX;
1254*4882a593Smuzhiyun
1255*4882a593Smuzhiyun if (wil->platform_ops.set_features) {
1256*4882a593Smuzhiyun features = (test_bit(WMI_FW_CAPABILITY_REF_CLOCK_CONTROL,
1257*4882a593Smuzhiyun wil->fw_capabilities) &&
1258*4882a593Smuzhiyun test_bit(WIL_PLATFORM_CAPA_EXT_CLK,
1259*4882a593Smuzhiyun wil->platform_capa)) ?
1260*4882a593Smuzhiyun BIT(WIL_PLATFORM_FEATURE_FW_EXT_CLK_CONTROL) : 0;
1261*4882a593Smuzhiyun
1262*4882a593Smuzhiyun if (wil->n_msi == 3)
1263*4882a593Smuzhiyun features |= BIT(WIL_PLATFORM_FEATURE_TRIPLE_MSI);
1264*4882a593Smuzhiyun
1265*4882a593Smuzhiyun wil->platform_ops.set_features(wil->platform_handle, features);
1266*4882a593Smuzhiyun }
1267*4882a593Smuzhiyun
1268*4882a593Smuzhiyun if (test_bit(WMI_FW_CAPABILITY_BACK_WIN_SIZE_64,
1269*4882a593Smuzhiyun wil->fw_capabilities)) {
1270*4882a593Smuzhiyun wil->max_agg_wsize = WIL_MAX_AGG_WSIZE_64;
1271*4882a593Smuzhiyun wil->max_ampdu_size = WIL_MAX_AMPDU_SIZE_128;
1272*4882a593Smuzhiyun } else {
1273*4882a593Smuzhiyun wil->max_agg_wsize = WIL_MAX_AGG_WSIZE;
1274*4882a593Smuzhiyun wil->max_ampdu_size = WIL_MAX_AMPDU_SIZE;
1275*4882a593Smuzhiyun }
1276*4882a593Smuzhiyun
1277*4882a593Smuzhiyun update_supported_bands(wil);
1278*4882a593Smuzhiyun }
1279*4882a593Smuzhiyun
wil_mbox_ring_le2cpus(struct wil6210_mbox_ring * r)1280*4882a593Smuzhiyun void wil_mbox_ring_le2cpus(struct wil6210_mbox_ring *r)
1281*4882a593Smuzhiyun {
1282*4882a593Smuzhiyun le32_to_cpus(&r->base);
1283*4882a593Smuzhiyun le16_to_cpus(&r->entry_size);
1284*4882a593Smuzhiyun le16_to_cpus(&r->size);
1285*4882a593Smuzhiyun le32_to_cpus(&r->tail);
1286*4882a593Smuzhiyun le32_to_cpus(&r->head);
1287*4882a593Smuzhiyun }
1288*4882a593Smuzhiyun
1289*4882a593Smuzhiyun /* construct actual board file name to use */
wil_get_board_file(struct wil6210_priv * wil,char * buf,size_t len)1290*4882a593Smuzhiyun void wil_get_board_file(struct wil6210_priv *wil, char *buf, size_t len)
1291*4882a593Smuzhiyun {
1292*4882a593Smuzhiyun const char *board_file;
1293*4882a593Smuzhiyun const char *wil_talyn_fw_name = ftm_mode ? WIL_FW_NAME_FTM_TALYN :
1294*4882a593Smuzhiyun WIL_FW_NAME_TALYN;
1295*4882a593Smuzhiyun
1296*4882a593Smuzhiyun if (wil->board_file) {
1297*4882a593Smuzhiyun board_file = wil->board_file;
1298*4882a593Smuzhiyun } else {
1299*4882a593Smuzhiyun /* If specific FW file is used for Talyn,
1300*4882a593Smuzhiyun * use specific board file
1301*4882a593Smuzhiyun */
1302*4882a593Smuzhiyun if (strcmp(wil->wil_fw_name, wil_talyn_fw_name) == 0)
1303*4882a593Smuzhiyun board_file = WIL_BRD_NAME_TALYN;
1304*4882a593Smuzhiyun else
1305*4882a593Smuzhiyun board_file = WIL_BOARD_FILE_NAME;
1306*4882a593Smuzhiyun }
1307*4882a593Smuzhiyun
1308*4882a593Smuzhiyun strlcpy(buf, board_file, len);
1309*4882a593Smuzhiyun }
1310*4882a593Smuzhiyun
wil_get_bl_info(struct wil6210_priv * wil)1311*4882a593Smuzhiyun static int wil_get_bl_info(struct wil6210_priv *wil)
1312*4882a593Smuzhiyun {
1313*4882a593Smuzhiyun struct net_device *ndev = wil->main_ndev;
1314*4882a593Smuzhiyun struct wiphy *wiphy = wil_to_wiphy(wil);
1315*4882a593Smuzhiyun union {
1316*4882a593Smuzhiyun struct bl_dedicated_registers_v0 bl0;
1317*4882a593Smuzhiyun struct bl_dedicated_registers_v1 bl1;
1318*4882a593Smuzhiyun } bl;
1319*4882a593Smuzhiyun u32 bl_ver;
1320*4882a593Smuzhiyun u8 *mac;
1321*4882a593Smuzhiyun u16 rf_status;
1322*4882a593Smuzhiyun
1323*4882a593Smuzhiyun wil_memcpy_fromio_32(&bl, wil->csr + HOSTADDR(RGF_USER_BL),
1324*4882a593Smuzhiyun sizeof(bl));
1325*4882a593Smuzhiyun bl_ver = le32_to_cpu(bl.bl0.boot_loader_struct_version);
1326*4882a593Smuzhiyun mac = bl.bl0.mac_address;
1327*4882a593Smuzhiyun
1328*4882a593Smuzhiyun if (bl_ver == 0) {
1329*4882a593Smuzhiyun le32_to_cpus(&bl.bl0.rf_type);
1330*4882a593Smuzhiyun le32_to_cpus(&bl.bl0.baseband_type);
1331*4882a593Smuzhiyun rf_status = 0; /* actually, unknown */
1332*4882a593Smuzhiyun wil_info(wil,
1333*4882a593Smuzhiyun "Boot Loader struct v%d: MAC = %pM RF = 0x%08x bband = 0x%08x\n",
1334*4882a593Smuzhiyun bl_ver, mac,
1335*4882a593Smuzhiyun bl.bl0.rf_type, bl.bl0.baseband_type);
1336*4882a593Smuzhiyun wil_info(wil, "Boot Loader build unknown for struct v0\n");
1337*4882a593Smuzhiyun } else {
1338*4882a593Smuzhiyun le16_to_cpus(&bl.bl1.rf_type);
1339*4882a593Smuzhiyun rf_status = le16_to_cpu(bl.bl1.rf_status);
1340*4882a593Smuzhiyun le32_to_cpus(&bl.bl1.baseband_type);
1341*4882a593Smuzhiyun le16_to_cpus(&bl.bl1.bl_version_subminor);
1342*4882a593Smuzhiyun le16_to_cpus(&bl.bl1.bl_version_build);
1343*4882a593Smuzhiyun wil_info(wil,
1344*4882a593Smuzhiyun "Boot Loader struct v%d: MAC = %pM RF = 0x%04x (status 0x%04x) bband = 0x%08x\n",
1345*4882a593Smuzhiyun bl_ver, mac,
1346*4882a593Smuzhiyun bl.bl1.rf_type, rf_status,
1347*4882a593Smuzhiyun bl.bl1.baseband_type);
1348*4882a593Smuzhiyun wil_info(wil, "Boot Loader build %d.%d.%d.%d\n",
1349*4882a593Smuzhiyun bl.bl1.bl_version_major, bl.bl1.bl_version_minor,
1350*4882a593Smuzhiyun bl.bl1.bl_version_subminor, bl.bl1.bl_version_build);
1351*4882a593Smuzhiyun }
1352*4882a593Smuzhiyun
1353*4882a593Smuzhiyun if (!is_valid_ether_addr(mac)) {
1354*4882a593Smuzhiyun wil_err(wil, "BL: Invalid MAC %pM\n", mac);
1355*4882a593Smuzhiyun return -EINVAL;
1356*4882a593Smuzhiyun }
1357*4882a593Smuzhiyun
1358*4882a593Smuzhiyun ether_addr_copy(ndev->perm_addr, mac);
1359*4882a593Smuzhiyun ether_addr_copy(wiphy->perm_addr, mac);
1360*4882a593Smuzhiyun if (!is_valid_ether_addr(ndev->dev_addr))
1361*4882a593Smuzhiyun ether_addr_copy(ndev->dev_addr, mac);
1362*4882a593Smuzhiyun
1363*4882a593Smuzhiyun if (rf_status) {/* bad RF cable? */
1364*4882a593Smuzhiyun wil_err(wil, "RF communication error 0x%04x",
1365*4882a593Smuzhiyun rf_status);
1366*4882a593Smuzhiyun return -EAGAIN;
1367*4882a593Smuzhiyun }
1368*4882a593Smuzhiyun
1369*4882a593Smuzhiyun return 0;
1370*4882a593Smuzhiyun }
1371*4882a593Smuzhiyun
wil_bl_crash_info(struct wil6210_priv * wil,bool is_err)1372*4882a593Smuzhiyun static void wil_bl_crash_info(struct wil6210_priv *wil, bool is_err)
1373*4882a593Smuzhiyun {
1374*4882a593Smuzhiyun u32 bl_assert_code, bl_assert_blink, bl_magic_number;
1375*4882a593Smuzhiyun u32 bl_ver = wil_r(wil, RGF_USER_BL +
1376*4882a593Smuzhiyun offsetof(struct bl_dedicated_registers_v0,
1377*4882a593Smuzhiyun boot_loader_struct_version));
1378*4882a593Smuzhiyun
1379*4882a593Smuzhiyun if (bl_ver < 2)
1380*4882a593Smuzhiyun return;
1381*4882a593Smuzhiyun
1382*4882a593Smuzhiyun bl_assert_code = wil_r(wil, RGF_USER_BL +
1383*4882a593Smuzhiyun offsetof(struct bl_dedicated_registers_v1,
1384*4882a593Smuzhiyun bl_assert_code));
1385*4882a593Smuzhiyun bl_assert_blink = wil_r(wil, RGF_USER_BL +
1386*4882a593Smuzhiyun offsetof(struct bl_dedicated_registers_v1,
1387*4882a593Smuzhiyun bl_assert_blink));
1388*4882a593Smuzhiyun bl_magic_number = wil_r(wil, RGF_USER_BL +
1389*4882a593Smuzhiyun offsetof(struct bl_dedicated_registers_v1,
1390*4882a593Smuzhiyun bl_magic_number));
1391*4882a593Smuzhiyun
1392*4882a593Smuzhiyun if (is_err) {
1393*4882a593Smuzhiyun wil_err(wil,
1394*4882a593Smuzhiyun "BL assert code 0x%08x blink 0x%08x magic 0x%08x\n",
1395*4882a593Smuzhiyun bl_assert_code, bl_assert_blink, bl_magic_number);
1396*4882a593Smuzhiyun } else {
1397*4882a593Smuzhiyun wil_dbg_misc(wil,
1398*4882a593Smuzhiyun "BL assert code 0x%08x blink 0x%08x magic 0x%08x\n",
1399*4882a593Smuzhiyun bl_assert_code, bl_assert_blink, bl_magic_number);
1400*4882a593Smuzhiyun }
1401*4882a593Smuzhiyun }
1402*4882a593Smuzhiyun
wil_get_otp_info(struct wil6210_priv * wil)1403*4882a593Smuzhiyun static int wil_get_otp_info(struct wil6210_priv *wil)
1404*4882a593Smuzhiyun {
1405*4882a593Smuzhiyun struct net_device *ndev = wil->main_ndev;
1406*4882a593Smuzhiyun struct wiphy *wiphy = wil_to_wiphy(wil);
1407*4882a593Smuzhiyun u8 mac[8];
1408*4882a593Smuzhiyun int mac_addr;
1409*4882a593Smuzhiyun
1410*4882a593Smuzhiyun /* OEM MAC has precedence */
1411*4882a593Smuzhiyun mac_addr = RGF_OTP_OEM_MAC;
1412*4882a593Smuzhiyun wil_memcpy_fromio_32(mac, wil->csr + HOSTADDR(mac_addr), sizeof(mac));
1413*4882a593Smuzhiyun
1414*4882a593Smuzhiyun if (is_valid_ether_addr(mac)) {
1415*4882a593Smuzhiyun wil_info(wil, "using OEM MAC %pM\n", mac);
1416*4882a593Smuzhiyun } else {
1417*4882a593Smuzhiyun if (wil->hw_version >= HW_VER_TALYN_MB)
1418*4882a593Smuzhiyun mac_addr = RGF_OTP_MAC_TALYN_MB;
1419*4882a593Smuzhiyun else
1420*4882a593Smuzhiyun mac_addr = RGF_OTP_MAC;
1421*4882a593Smuzhiyun
1422*4882a593Smuzhiyun wil_memcpy_fromio_32(mac, wil->csr + HOSTADDR(mac_addr),
1423*4882a593Smuzhiyun sizeof(mac));
1424*4882a593Smuzhiyun }
1425*4882a593Smuzhiyun
1426*4882a593Smuzhiyun if (!is_valid_ether_addr(mac)) {
1427*4882a593Smuzhiyun wil_err(wil, "Invalid MAC %pM\n", mac);
1428*4882a593Smuzhiyun return -EINVAL;
1429*4882a593Smuzhiyun }
1430*4882a593Smuzhiyun
1431*4882a593Smuzhiyun ether_addr_copy(ndev->perm_addr, mac);
1432*4882a593Smuzhiyun ether_addr_copy(wiphy->perm_addr, mac);
1433*4882a593Smuzhiyun if (!is_valid_ether_addr(ndev->dev_addr))
1434*4882a593Smuzhiyun ether_addr_copy(ndev->dev_addr, mac);
1435*4882a593Smuzhiyun
1436*4882a593Smuzhiyun return 0;
1437*4882a593Smuzhiyun }
1438*4882a593Smuzhiyun
wil_wait_for_fw_ready(struct wil6210_priv * wil)1439*4882a593Smuzhiyun static int wil_wait_for_fw_ready(struct wil6210_priv *wil)
1440*4882a593Smuzhiyun {
1441*4882a593Smuzhiyun ulong to = msecs_to_jiffies(2000);
1442*4882a593Smuzhiyun ulong left = wait_for_completion_timeout(&wil->wmi_ready, to);
1443*4882a593Smuzhiyun
1444*4882a593Smuzhiyun if (0 == left) {
1445*4882a593Smuzhiyun wil_err(wil, "Firmware not ready\n");
1446*4882a593Smuzhiyun return -ETIME;
1447*4882a593Smuzhiyun } else {
1448*4882a593Smuzhiyun wil_info(wil, "FW ready after %d ms. HW version 0x%08x\n",
1449*4882a593Smuzhiyun jiffies_to_msecs(to-left), wil->hw_version);
1450*4882a593Smuzhiyun }
1451*4882a593Smuzhiyun return 0;
1452*4882a593Smuzhiyun }
1453*4882a593Smuzhiyun
wil_abort_scan(struct wil6210_vif * vif,bool sync)1454*4882a593Smuzhiyun void wil_abort_scan(struct wil6210_vif *vif, bool sync)
1455*4882a593Smuzhiyun {
1456*4882a593Smuzhiyun struct wil6210_priv *wil = vif_to_wil(vif);
1457*4882a593Smuzhiyun int rc;
1458*4882a593Smuzhiyun struct cfg80211_scan_info info = {
1459*4882a593Smuzhiyun .aborted = true,
1460*4882a593Smuzhiyun };
1461*4882a593Smuzhiyun
1462*4882a593Smuzhiyun lockdep_assert_held(&wil->vif_mutex);
1463*4882a593Smuzhiyun
1464*4882a593Smuzhiyun if (!vif->scan_request)
1465*4882a593Smuzhiyun return;
1466*4882a593Smuzhiyun
1467*4882a593Smuzhiyun wil_dbg_misc(wil, "Abort scan_request 0x%p\n", vif->scan_request);
1468*4882a593Smuzhiyun del_timer_sync(&vif->scan_timer);
1469*4882a593Smuzhiyun mutex_unlock(&wil->vif_mutex);
1470*4882a593Smuzhiyun rc = wmi_abort_scan(vif);
1471*4882a593Smuzhiyun if (!rc && sync)
1472*4882a593Smuzhiyun wait_event_interruptible_timeout(wil->wq, !vif->scan_request,
1473*4882a593Smuzhiyun msecs_to_jiffies(
1474*4882a593Smuzhiyun WAIT_FOR_SCAN_ABORT_MS));
1475*4882a593Smuzhiyun
1476*4882a593Smuzhiyun mutex_lock(&wil->vif_mutex);
1477*4882a593Smuzhiyun if (vif->scan_request) {
1478*4882a593Smuzhiyun cfg80211_scan_done(vif->scan_request, &info);
1479*4882a593Smuzhiyun vif->scan_request = NULL;
1480*4882a593Smuzhiyun }
1481*4882a593Smuzhiyun }
1482*4882a593Smuzhiyun
wil_abort_scan_all_vifs(struct wil6210_priv * wil,bool sync)1483*4882a593Smuzhiyun void wil_abort_scan_all_vifs(struct wil6210_priv *wil, bool sync)
1484*4882a593Smuzhiyun {
1485*4882a593Smuzhiyun int i;
1486*4882a593Smuzhiyun
1487*4882a593Smuzhiyun lockdep_assert_held(&wil->vif_mutex);
1488*4882a593Smuzhiyun
1489*4882a593Smuzhiyun for (i = 0; i < GET_MAX_VIFS(wil); i++) {
1490*4882a593Smuzhiyun struct wil6210_vif *vif = wil->vifs[i];
1491*4882a593Smuzhiyun
1492*4882a593Smuzhiyun if (vif)
1493*4882a593Smuzhiyun wil_abort_scan(vif, sync);
1494*4882a593Smuzhiyun }
1495*4882a593Smuzhiyun }
1496*4882a593Smuzhiyun
wil_ps_update(struct wil6210_priv * wil,enum wmi_ps_profile_type ps_profile)1497*4882a593Smuzhiyun int wil_ps_update(struct wil6210_priv *wil, enum wmi_ps_profile_type ps_profile)
1498*4882a593Smuzhiyun {
1499*4882a593Smuzhiyun int rc;
1500*4882a593Smuzhiyun
1501*4882a593Smuzhiyun if (!test_bit(WMI_FW_CAPABILITY_PS_CONFIG, wil->fw_capabilities)) {
1502*4882a593Smuzhiyun wil_err(wil, "set_power_mgmt not supported\n");
1503*4882a593Smuzhiyun return -EOPNOTSUPP;
1504*4882a593Smuzhiyun }
1505*4882a593Smuzhiyun
1506*4882a593Smuzhiyun rc = wmi_ps_dev_profile_cfg(wil, ps_profile);
1507*4882a593Smuzhiyun if (rc)
1508*4882a593Smuzhiyun wil_err(wil, "wmi_ps_dev_profile_cfg failed (%d)\n", rc);
1509*4882a593Smuzhiyun else
1510*4882a593Smuzhiyun wil->ps_profile = ps_profile;
1511*4882a593Smuzhiyun
1512*4882a593Smuzhiyun return rc;
1513*4882a593Smuzhiyun }
1514*4882a593Smuzhiyun
wil_pre_fw_config(struct wil6210_priv * wil)1515*4882a593Smuzhiyun static void wil_pre_fw_config(struct wil6210_priv *wil)
1516*4882a593Smuzhiyun {
1517*4882a593Smuzhiyun wil_clear_fw_log_addr(wil);
1518*4882a593Smuzhiyun /* Mark FW as loaded from host */
1519*4882a593Smuzhiyun wil_s(wil, RGF_USER_USAGE_6, 1);
1520*4882a593Smuzhiyun
1521*4882a593Smuzhiyun /* clear any interrupts which on-card-firmware
1522*4882a593Smuzhiyun * may have set
1523*4882a593Smuzhiyun */
1524*4882a593Smuzhiyun wil6210_clear_irq(wil);
1525*4882a593Smuzhiyun /* CAF_ICR - clear and mask */
1526*4882a593Smuzhiyun /* it is W1C, clear by writing back same value */
1527*4882a593Smuzhiyun if (wil->hw_version < HW_VER_TALYN_MB) {
1528*4882a593Smuzhiyun wil_s(wil, RGF_CAF_ICR + offsetof(struct RGF_ICR, ICR), 0);
1529*4882a593Smuzhiyun wil_w(wil, RGF_CAF_ICR + offsetof(struct RGF_ICR, IMV), ~0);
1530*4882a593Smuzhiyun }
1531*4882a593Smuzhiyun /* clear PAL_UNIT_ICR (potential D0->D3 leftover)
1532*4882a593Smuzhiyun * In Talyn-MB host cannot access this register due to
1533*4882a593Smuzhiyun * access control, hence PAL_UNIT_ICR is cleared by the FW
1534*4882a593Smuzhiyun */
1535*4882a593Smuzhiyun if (wil->hw_version < HW_VER_TALYN_MB)
1536*4882a593Smuzhiyun wil_s(wil, RGF_PAL_UNIT_ICR + offsetof(struct RGF_ICR, ICR),
1537*4882a593Smuzhiyun 0);
1538*4882a593Smuzhiyun
1539*4882a593Smuzhiyun if (wil->fw_calib_result > 0) {
1540*4882a593Smuzhiyun __le32 val = cpu_to_le32(wil->fw_calib_result |
1541*4882a593Smuzhiyun (CALIB_RESULT_SIGNATURE << 8));
1542*4882a593Smuzhiyun wil_w(wil, RGF_USER_FW_CALIB_RESULT, (u32 __force)val);
1543*4882a593Smuzhiyun }
1544*4882a593Smuzhiyun }
1545*4882a593Smuzhiyun
wil_restore_vifs(struct wil6210_priv * wil)1546*4882a593Smuzhiyun static int wil_restore_vifs(struct wil6210_priv *wil)
1547*4882a593Smuzhiyun {
1548*4882a593Smuzhiyun struct wil6210_vif *vif;
1549*4882a593Smuzhiyun struct net_device *ndev;
1550*4882a593Smuzhiyun struct wireless_dev *wdev;
1551*4882a593Smuzhiyun int i, rc;
1552*4882a593Smuzhiyun
1553*4882a593Smuzhiyun for (i = 0; i < GET_MAX_VIFS(wil); i++) {
1554*4882a593Smuzhiyun vif = wil->vifs[i];
1555*4882a593Smuzhiyun if (!vif)
1556*4882a593Smuzhiyun continue;
1557*4882a593Smuzhiyun vif->ap_isolate = 0;
1558*4882a593Smuzhiyun if (vif->mid) {
1559*4882a593Smuzhiyun ndev = vif_to_ndev(vif);
1560*4882a593Smuzhiyun wdev = vif_to_wdev(vif);
1561*4882a593Smuzhiyun rc = wmi_port_allocate(wil, vif->mid, ndev->dev_addr,
1562*4882a593Smuzhiyun wdev->iftype);
1563*4882a593Smuzhiyun if (rc) {
1564*4882a593Smuzhiyun wil_err(wil, "fail to restore VIF %d type %d, rc %d\n",
1565*4882a593Smuzhiyun i, wdev->iftype, rc);
1566*4882a593Smuzhiyun return rc;
1567*4882a593Smuzhiyun }
1568*4882a593Smuzhiyun }
1569*4882a593Smuzhiyun }
1570*4882a593Smuzhiyun
1571*4882a593Smuzhiyun return 0;
1572*4882a593Smuzhiyun }
1573*4882a593Smuzhiyun
1574*4882a593Smuzhiyun /*
1575*4882a593Smuzhiyun * Clear FW and ucode log start addr to indicate FW log is not ready. The host
1576*4882a593Smuzhiyun * driver clears the addresses before FW starts and FW initializes the address
1577*4882a593Smuzhiyun * when it is ready to send logs.
1578*4882a593Smuzhiyun */
wil_clear_fw_log_addr(struct wil6210_priv * wil)1579*4882a593Smuzhiyun void wil_clear_fw_log_addr(struct wil6210_priv *wil)
1580*4882a593Smuzhiyun {
1581*4882a593Smuzhiyun /* FW log addr */
1582*4882a593Smuzhiyun wil_w(wil, RGF_USER_USAGE_1, 0);
1583*4882a593Smuzhiyun /* ucode log addr */
1584*4882a593Smuzhiyun wil_w(wil, RGF_USER_USAGE_2, 0);
1585*4882a593Smuzhiyun wil_dbg_misc(wil, "Cleared FW and ucode log address");
1586*4882a593Smuzhiyun }
1587*4882a593Smuzhiyun
1588*4882a593Smuzhiyun /*
1589*4882a593Smuzhiyun * We reset all the structures, and we reset the UMAC.
1590*4882a593Smuzhiyun * After calling this routine, you're expected to reload
1591*4882a593Smuzhiyun * the firmware.
1592*4882a593Smuzhiyun */
wil_reset(struct wil6210_priv * wil,bool load_fw)1593*4882a593Smuzhiyun int wil_reset(struct wil6210_priv *wil, bool load_fw)
1594*4882a593Smuzhiyun {
1595*4882a593Smuzhiyun int rc, i;
1596*4882a593Smuzhiyun unsigned long status_flags = BIT(wil_status_resetting);
1597*4882a593Smuzhiyun int no_flash;
1598*4882a593Smuzhiyun struct wil6210_vif *vif;
1599*4882a593Smuzhiyun
1600*4882a593Smuzhiyun wil_dbg_misc(wil, "reset\n");
1601*4882a593Smuzhiyun
1602*4882a593Smuzhiyun WARN_ON(!mutex_is_locked(&wil->mutex));
1603*4882a593Smuzhiyun WARN_ON(test_bit(wil_status_napi_en, wil->status));
1604*4882a593Smuzhiyun
1605*4882a593Smuzhiyun if (debug_fw) {
1606*4882a593Smuzhiyun static const u8 mac[ETH_ALEN] = {
1607*4882a593Smuzhiyun 0x00, 0xde, 0xad, 0x12, 0x34, 0x56,
1608*4882a593Smuzhiyun };
1609*4882a593Smuzhiyun struct net_device *ndev = wil->main_ndev;
1610*4882a593Smuzhiyun
1611*4882a593Smuzhiyun ether_addr_copy(ndev->perm_addr, mac);
1612*4882a593Smuzhiyun ether_addr_copy(ndev->dev_addr, ndev->perm_addr);
1613*4882a593Smuzhiyun return 0;
1614*4882a593Smuzhiyun }
1615*4882a593Smuzhiyun
1616*4882a593Smuzhiyun if (wil->hw_version == HW_VER_UNKNOWN)
1617*4882a593Smuzhiyun return -ENODEV;
1618*4882a593Smuzhiyun
1619*4882a593Smuzhiyun if (test_bit(WIL_PLATFORM_CAPA_T_PWR_ON_0, wil->platform_capa) &&
1620*4882a593Smuzhiyun wil->hw_version < HW_VER_TALYN_MB) {
1621*4882a593Smuzhiyun wil_dbg_misc(wil, "Notify FW to set T_POWER_ON=0\n");
1622*4882a593Smuzhiyun wil_s(wil, RGF_USER_USAGE_8, BIT_USER_SUPPORT_T_POWER_ON_0);
1623*4882a593Smuzhiyun }
1624*4882a593Smuzhiyun
1625*4882a593Smuzhiyun if (test_bit(WIL_PLATFORM_CAPA_EXT_CLK, wil->platform_capa)) {
1626*4882a593Smuzhiyun wil_dbg_misc(wil, "Notify FW on ext clock configuration\n");
1627*4882a593Smuzhiyun wil_s(wil, RGF_USER_USAGE_8, BIT_USER_EXT_CLK);
1628*4882a593Smuzhiyun }
1629*4882a593Smuzhiyun
1630*4882a593Smuzhiyun if (wil->platform_ops.notify) {
1631*4882a593Smuzhiyun rc = wil->platform_ops.notify(wil->platform_handle,
1632*4882a593Smuzhiyun WIL_PLATFORM_EVT_PRE_RESET);
1633*4882a593Smuzhiyun if (rc)
1634*4882a593Smuzhiyun wil_err(wil, "PRE_RESET platform notify failed, rc %d\n",
1635*4882a593Smuzhiyun rc);
1636*4882a593Smuzhiyun }
1637*4882a593Smuzhiyun
1638*4882a593Smuzhiyun set_bit(wil_status_resetting, wil->status);
1639*4882a593Smuzhiyun mutex_lock(&wil->vif_mutex);
1640*4882a593Smuzhiyun wil_abort_scan_all_vifs(wil, false);
1641*4882a593Smuzhiyun mutex_unlock(&wil->vif_mutex);
1642*4882a593Smuzhiyun
1643*4882a593Smuzhiyun for (i = 0; i < GET_MAX_VIFS(wil); i++) {
1644*4882a593Smuzhiyun vif = wil->vifs[i];
1645*4882a593Smuzhiyun if (vif) {
1646*4882a593Smuzhiyun cancel_work_sync(&vif->disconnect_worker);
1647*4882a593Smuzhiyun wil6210_disconnect(vif, NULL,
1648*4882a593Smuzhiyun WLAN_REASON_DEAUTH_LEAVING);
1649*4882a593Smuzhiyun vif->ptk_rekey_state = WIL_REKEY_IDLE;
1650*4882a593Smuzhiyun }
1651*4882a593Smuzhiyun }
1652*4882a593Smuzhiyun wil_bcast_fini_all(wil);
1653*4882a593Smuzhiyun
1654*4882a593Smuzhiyun /* Disable device led before reset*/
1655*4882a593Smuzhiyun wmi_led_cfg(wil, false);
1656*4882a593Smuzhiyun
1657*4882a593Smuzhiyun down_write(&wil->mem_lock);
1658*4882a593Smuzhiyun
1659*4882a593Smuzhiyun /* prevent NAPI from being scheduled and prevent wmi commands */
1660*4882a593Smuzhiyun mutex_lock(&wil->wmi_mutex);
1661*4882a593Smuzhiyun if (test_bit(wil_status_suspending, wil->status))
1662*4882a593Smuzhiyun status_flags |= BIT(wil_status_suspending);
1663*4882a593Smuzhiyun bitmap_and(wil->status, wil->status, &status_flags,
1664*4882a593Smuzhiyun wil_status_last);
1665*4882a593Smuzhiyun wil_dbg_misc(wil, "wil->status (0x%lx)\n", *wil->status);
1666*4882a593Smuzhiyun mutex_unlock(&wil->wmi_mutex);
1667*4882a593Smuzhiyun
1668*4882a593Smuzhiyun wil_mask_irq(wil);
1669*4882a593Smuzhiyun
1670*4882a593Smuzhiyun wmi_event_flush(wil);
1671*4882a593Smuzhiyun
1672*4882a593Smuzhiyun flush_workqueue(wil->wq_service);
1673*4882a593Smuzhiyun flush_workqueue(wil->wmi_wq);
1674*4882a593Smuzhiyun
1675*4882a593Smuzhiyun no_flash = test_bit(hw_capa_no_flash, wil->hw_capa);
1676*4882a593Smuzhiyun if (!no_flash)
1677*4882a593Smuzhiyun wil_bl_crash_info(wil, false);
1678*4882a593Smuzhiyun wil_disable_irq(wil);
1679*4882a593Smuzhiyun rc = wil_target_reset(wil, no_flash);
1680*4882a593Smuzhiyun wil6210_clear_irq(wil);
1681*4882a593Smuzhiyun wil_enable_irq(wil);
1682*4882a593Smuzhiyun wil->txrx_ops.rx_fini(wil);
1683*4882a593Smuzhiyun wil->txrx_ops.tx_fini(wil);
1684*4882a593Smuzhiyun if (rc) {
1685*4882a593Smuzhiyun if (!no_flash)
1686*4882a593Smuzhiyun wil_bl_crash_info(wil, true);
1687*4882a593Smuzhiyun goto out;
1688*4882a593Smuzhiyun }
1689*4882a593Smuzhiyun
1690*4882a593Smuzhiyun if (no_flash) {
1691*4882a593Smuzhiyun rc = wil_get_otp_info(wil);
1692*4882a593Smuzhiyun } else {
1693*4882a593Smuzhiyun rc = wil_get_bl_info(wil);
1694*4882a593Smuzhiyun if (rc == -EAGAIN && !load_fw)
1695*4882a593Smuzhiyun /* ignore RF error if not going up */
1696*4882a593Smuzhiyun rc = 0;
1697*4882a593Smuzhiyun }
1698*4882a593Smuzhiyun if (rc)
1699*4882a593Smuzhiyun goto out;
1700*4882a593Smuzhiyun
1701*4882a593Smuzhiyun wil_set_oob_mode(wil, oob_mode);
1702*4882a593Smuzhiyun if (load_fw) {
1703*4882a593Smuzhiyun char board_file[WIL_BOARD_FILE_MAX_NAMELEN];
1704*4882a593Smuzhiyun
1705*4882a593Smuzhiyun if (wil->secured_boot) {
1706*4882a593Smuzhiyun wil_err(wil, "secured boot is not supported\n");
1707*4882a593Smuzhiyun up_write(&wil->mem_lock);
1708*4882a593Smuzhiyun return -ENOTSUPP;
1709*4882a593Smuzhiyun }
1710*4882a593Smuzhiyun
1711*4882a593Smuzhiyun board_file[0] = '\0';
1712*4882a593Smuzhiyun wil_get_board_file(wil, board_file, sizeof(board_file));
1713*4882a593Smuzhiyun wil_info(wil, "Use firmware <%s> + board <%s>\n",
1714*4882a593Smuzhiyun wil->wil_fw_name, board_file);
1715*4882a593Smuzhiyun
1716*4882a593Smuzhiyun if (!no_flash)
1717*4882a593Smuzhiyun wil_bl_prepare_halt(wil);
1718*4882a593Smuzhiyun
1719*4882a593Smuzhiyun wil_halt_cpu(wil);
1720*4882a593Smuzhiyun memset(wil->fw_version, 0, sizeof(wil->fw_version));
1721*4882a593Smuzhiyun /* Loading f/w from the file */
1722*4882a593Smuzhiyun rc = wil_request_firmware(wil, wil->wil_fw_name, true);
1723*4882a593Smuzhiyun if (rc)
1724*4882a593Smuzhiyun goto out;
1725*4882a593Smuzhiyun if (wil->num_of_brd_entries)
1726*4882a593Smuzhiyun rc = wil_request_board(wil, board_file);
1727*4882a593Smuzhiyun else
1728*4882a593Smuzhiyun rc = wil_request_firmware(wil, board_file, true);
1729*4882a593Smuzhiyun if (rc)
1730*4882a593Smuzhiyun goto out;
1731*4882a593Smuzhiyun
1732*4882a593Smuzhiyun wil_pre_fw_config(wil);
1733*4882a593Smuzhiyun wil_release_cpu(wil);
1734*4882a593Smuzhiyun }
1735*4882a593Smuzhiyun
1736*4882a593Smuzhiyun /* init after reset */
1737*4882a593Smuzhiyun reinit_completion(&wil->wmi_ready);
1738*4882a593Smuzhiyun reinit_completion(&wil->wmi_call);
1739*4882a593Smuzhiyun reinit_completion(&wil->halp.comp);
1740*4882a593Smuzhiyun
1741*4882a593Smuzhiyun clear_bit(wil_status_resetting, wil->status);
1742*4882a593Smuzhiyun
1743*4882a593Smuzhiyun up_write(&wil->mem_lock);
1744*4882a593Smuzhiyun
1745*4882a593Smuzhiyun if (load_fw) {
1746*4882a593Smuzhiyun wil_unmask_irq(wil);
1747*4882a593Smuzhiyun
1748*4882a593Smuzhiyun /* we just started MAC, wait for FW ready */
1749*4882a593Smuzhiyun rc = wil_wait_for_fw_ready(wil);
1750*4882a593Smuzhiyun if (rc)
1751*4882a593Smuzhiyun return rc;
1752*4882a593Smuzhiyun
1753*4882a593Smuzhiyun /* check FW is responsive */
1754*4882a593Smuzhiyun rc = wmi_echo(wil);
1755*4882a593Smuzhiyun if (rc) {
1756*4882a593Smuzhiyun wil_err(wil, "wmi_echo failed, rc %d\n", rc);
1757*4882a593Smuzhiyun return rc;
1758*4882a593Smuzhiyun }
1759*4882a593Smuzhiyun
1760*4882a593Smuzhiyun wil->txrx_ops.configure_interrupt_moderation(wil);
1761*4882a593Smuzhiyun
1762*4882a593Smuzhiyun /* Enable OFU rdy valid bug fix, to prevent hang in oful34_rx
1763*4882a593Smuzhiyun * while there is back-pressure from Host during RX
1764*4882a593Smuzhiyun */
1765*4882a593Smuzhiyun if (wil->hw_version >= HW_VER_TALYN_MB)
1766*4882a593Smuzhiyun wil_s(wil, RGF_DMA_MISC_CTL,
1767*4882a593Smuzhiyun BIT_OFUL34_RDY_VALID_BUG_FIX_EN);
1768*4882a593Smuzhiyun
1769*4882a593Smuzhiyun rc = wil_restore_vifs(wil);
1770*4882a593Smuzhiyun if (rc) {
1771*4882a593Smuzhiyun wil_err(wil, "failed to restore vifs, rc %d\n", rc);
1772*4882a593Smuzhiyun return rc;
1773*4882a593Smuzhiyun }
1774*4882a593Smuzhiyun
1775*4882a593Smuzhiyun wil_collect_fw_info(wil);
1776*4882a593Smuzhiyun
1777*4882a593Smuzhiyun if (wil->ps_profile != WMI_PS_PROFILE_TYPE_DEFAULT)
1778*4882a593Smuzhiyun wil_ps_update(wil, wil->ps_profile);
1779*4882a593Smuzhiyun
1780*4882a593Smuzhiyun if (wil->platform_ops.notify) {
1781*4882a593Smuzhiyun rc = wil->platform_ops.notify(wil->platform_handle,
1782*4882a593Smuzhiyun WIL_PLATFORM_EVT_FW_RDY);
1783*4882a593Smuzhiyun if (rc) {
1784*4882a593Smuzhiyun wil_err(wil, "FW_RDY notify failed, rc %d\n",
1785*4882a593Smuzhiyun rc);
1786*4882a593Smuzhiyun rc = 0;
1787*4882a593Smuzhiyun }
1788*4882a593Smuzhiyun }
1789*4882a593Smuzhiyun }
1790*4882a593Smuzhiyun
1791*4882a593Smuzhiyun return rc;
1792*4882a593Smuzhiyun
1793*4882a593Smuzhiyun out:
1794*4882a593Smuzhiyun up_write(&wil->mem_lock);
1795*4882a593Smuzhiyun clear_bit(wil_status_resetting, wil->status);
1796*4882a593Smuzhiyun return rc;
1797*4882a593Smuzhiyun }
1798*4882a593Smuzhiyun
wil_fw_error_recovery(struct wil6210_priv * wil)1799*4882a593Smuzhiyun void wil_fw_error_recovery(struct wil6210_priv *wil)
1800*4882a593Smuzhiyun {
1801*4882a593Smuzhiyun wil_dbg_misc(wil, "starting fw error recovery\n");
1802*4882a593Smuzhiyun
1803*4882a593Smuzhiyun if (test_bit(wil_status_resetting, wil->status)) {
1804*4882a593Smuzhiyun wil_info(wil, "Reset already in progress\n");
1805*4882a593Smuzhiyun return;
1806*4882a593Smuzhiyun }
1807*4882a593Smuzhiyun
1808*4882a593Smuzhiyun wil->recovery_state = fw_recovery_pending;
1809*4882a593Smuzhiyun schedule_work(&wil->fw_error_worker);
1810*4882a593Smuzhiyun }
1811*4882a593Smuzhiyun
__wil_up(struct wil6210_priv * wil)1812*4882a593Smuzhiyun int __wil_up(struct wil6210_priv *wil)
1813*4882a593Smuzhiyun {
1814*4882a593Smuzhiyun struct net_device *ndev = wil->main_ndev;
1815*4882a593Smuzhiyun struct wireless_dev *wdev = ndev->ieee80211_ptr;
1816*4882a593Smuzhiyun int rc;
1817*4882a593Smuzhiyun
1818*4882a593Smuzhiyun WARN_ON(!mutex_is_locked(&wil->mutex));
1819*4882a593Smuzhiyun
1820*4882a593Smuzhiyun rc = wil_reset(wil, true);
1821*4882a593Smuzhiyun if (rc)
1822*4882a593Smuzhiyun return rc;
1823*4882a593Smuzhiyun
1824*4882a593Smuzhiyun /* Rx RING. After MAC and beacon */
1825*4882a593Smuzhiyun if (rx_ring_order == 0)
1826*4882a593Smuzhiyun rx_ring_order = wil->hw_version < HW_VER_TALYN_MB ?
1827*4882a593Smuzhiyun WIL_RX_RING_SIZE_ORDER_DEFAULT :
1828*4882a593Smuzhiyun WIL_RX_RING_SIZE_ORDER_TALYN_DEFAULT;
1829*4882a593Smuzhiyun
1830*4882a593Smuzhiyun rc = wil->txrx_ops.rx_init(wil, rx_ring_order);
1831*4882a593Smuzhiyun if (rc)
1832*4882a593Smuzhiyun return rc;
1833*4882a593Smuzhiyun
1834*4882a593Smuzhiyun rc = wil->txrx_ops.tx_init(wil);
1835*4882a593Smuzhiyun if (rc)
1836*4882a593Smuzhiyun return rc;
1837*4882a593Smuzhiyun
1838*4882a593Smuzhiyun switch (wdev->iftype) {
1839*4882a593Smuzhiyun case NL80211_IFTYPE_STATION:
1840*4882a593Smuzhiyun wil_dbg_misc(wil, "type: STATION\n");
1841*4882a593Smuzhiyun ndev->type = ARPHRD_ETHER;
1842*4882a593Smuzhiyun break;
1843*4882a593Smuzhiyun case NL80211_IFTYPE_AP:
1844*4882a593Smuzhiyun wil_dbg_misc(wil, "type: AP\n");
1845*4882a593Smuzhiyun ndev->type = ARPHRD_ETHER;
1846*4882a593Smuzhiyun break;
1847*4882a593Smuzhiyun case NL80211_IFTYPE_P2P_CLIENT:
1848*4882a593Smuzhiyun wil_dbg_misc(wil, "type: P2P_CLIENT\n");
1849*4882a593Smuzhiyun ndev->type = ARPHRD_ETHER;
1850*4882a593Smuzhiyun break;
1851*4882a593Smuzhiyun case NL80211_IFTYPE_P2P_GO:
1852*4882a593Smuzhiyun wil_dbg_misc(wil, "type: P2P_GO\n");
1853*4882a593Smuzhiyun ndev->type = ARPHRD_ETHER;
1854*4882a593Smuzhiyun break;
1855*4882a593Smuzhiyun case NL80211_IFTYPE_MONITOR:
1856*4882a593Smuzhiyun wil_dbg_misc(wil, "type: Monitor\n");
1857*4882a593Smuzhiyun ndev->type = ARPHRD_IEEE80211_RADIOTAP;
1858*4882a593Smuzhiyun /* ARPHRD_IEEE80211 or ARPHRD_IEEE80211_RADIOTAP ? */
1859*4882a593Smuzhiyun break;
1860*4882a593Smuzhiyun default:
1861*4882a593Smuzhiyun return -EOPNOTSUPP;
1862*4882a593Smuzhiyun }
1863*4882a593Smuzhiyun
1864*4882a593Smuzhiyun /* MAC address - pre-requisite for other commands */
1865*4882a593Smuzhiyun wmi_set_mac_address(wil, ndev->dev_addr);
1866*4882a593Smuzhiyun
1867*4882a593Smuzhiyun wil_dbg_misc(wil, "NAPI enable\n");
1868*4882a593Smuzhiyun napi_enable(&wil->napi_rx);
1869*4882a593Smuzhiyun napi_enable(&wil->napi_tx);
1870*4882a593Smuzhiyun set_bit(wil_status_napi_en, wil->status);
1871*4882a593Smuzhiyun
1872*4882a593Smuzhiyun wil6210_bus_request(wil, WIL_DEFAULT_BUS_REQUEST_KBPS);
1873*4882a593Smuzhiyun
1874*4882a593Smuzhiyun return 0;
1875*4882a593Smuzhiyun }
1876*4882a593Smuzhiyun
wil_up(struct wil6210_priv * wil)1877*4882a593Smuzhiyun int wil_up(struct wil6210_priv *wil)
1878*4882a593Smuzhiyun {
1879*4882a593Smuzhiyun int rc;
1880*4882a593Smuzhiyun
1881*4882a593Smuzhiyun wil_dbg_misc(wil, "up\n");
1882*4882a593Smuzhiyun
1883*4882a593Smuzhiyun mutex_lock(&wil->mutex);
1884*4882a593Smuzhiyun rc = __wil_up(wil);
1885*4882a593Smuzhiyun mutex_unlock(&wil->mutex);
1886*4882a593Smuzhiyun
1887*4882a593Smuzhiyun return rc;
1888*4882a593Smuzhiyun }
1889*4882a593Smuzhiyun
__wil_down(struct wil6210_priv * wil)1890*4882a593Smuzhiyun int __wil_down(struct wil6210_priv *wil)
1891*4882a593Smuzhiyun {
1892*4882a593Smuzhiyun int rc;
1893*4882a593Smuzhiyun WARN_ON(!mutex_is_locked(&wil->mutex));
1894*4882a593Smuzhiyun
1895*4882a593Smuzhiyun set_bit(wil_status_resetting, wil->status);
1896*4882a593Smuzhiyun
1897*4882a593Smuzhiyun wil6210_bus_request(wil, 0);
1898*4882a593Smuzhiyun
1899*4882a593Smuzhiyun wil_disable_irq(wil);
1900*4882a593Smuzhiyun if (test_and_clear_bit(wil_status_napi_en, wil->status)) {
1901*4882a593Smuzhiyun napi_disable(&wil->napi_rx);
1902*4882a593Smuzhiyun napi_disable(&wil->napi_tx);
1903*4882a593Smuzhiyun wil_dbg_misc(wil, "NAPI disable\n");
1904*4882a593Smuzhiyun }
1905*4882a593Smuzhiyun wil_enable_irq(wil);
1906*4882a593Smuzhiyun
1907*4882a593Smuzhiyun mutex_lock(&wil->vif_mutex);
1908*4882a593Smuzhiyun wil_p2p_stop_radio_operations(wil);
1909*4882a593Smuzhiyun wil_abort_scan_all_vifs(wil, false);
1910*4882a593Smuzhiyun mutex_unlock(&wil->vif_mutex);
1911*4882a593Smuzhiyun
1912*4882a593Smuzhiyun rc = wil_reset(wil, false);
1913*4882a593Smuzhiyun
1914*4882a593Smuzhiyun return rc;
1915*4882a593Smuzhiyun }
1916*4882a593Smuzhiyun
wil_down(struct wil6210_priv * wil)1917*4882a593Smuzhiyun int wil_down(struct wil6210_priv *wil)
1918*4882a593Smuzhiyun {
1919*4882a593Smuzhiyun int rc;
1920*4882a593Smuzhiyun
1921*4882a593Smuzhiyun wil_dbg_misc(wil, "down\n");
1922*4882a593Smuzhiyun
1923*4882a593Smuzhiyun wil_set_recovery_state(wil, fw_recovery_idle);
1924*4882a593Smuzhiyun mutex_lock(&wil->mutex);
1925*4882a593Smuzhiyun rc = __wil_down(wil);
1926*4882a593Smuzhiyun mutex_unlock(&wil->mutex);
1927*4882a593Smuzhiyun
1928*4882a593Smuzhiyun return rc;
1929*4882a593Smuzhiyun }
1930*4882a593Smuzhiyun
wil_find_cid(struct wil6210_priv * wil,u8 mid,const u8 * mac)1931*4882a593Smuzhiyun int wil_find_cid(struct wil6210_priv *wil, u8 mid, const u8 *mac)
1932*4882a593Smuzhiyun {
1933*4882a593Smuzhiyun int i;
1934*4882a593Smuzhiyun int rc = -ENOENT;
1935*4882a593Smuzhiyun
1936*4882a593Smuzhiyun for (i = 0; i < wil->max_assoc_sta; i++) {
1937*4882a593Smuzhiyun if (wil->sta[i].mid == mid &&
1938*4882a593Smuzhiyun wil->sta[i].status != wil_sta_unused &&
1939*4882a593Smuzhiyun ether_addr_equal(wil->sta[i].addr, mac)) {
1940*4882a593Smuzhiyun rc = i;
1941*4882a593Smuzhiyun break;
1942*4882a593Smuzhiyun }
1943*4882a593Smuzhiyun }
1944*4882a593Smuzhiyun
1945*4882a593Smuzhiyun return rc;
1946*4882a593Smuzhiyun }
1947*4882a593Smuzhiyun
wil_halp_vote(struct wil6210_priv * wil)1948*4882a593Smuzhiyun void wil_halp_vote(struct wil6210_priv *wil)
1949*4882a593Smuzhiyun {
1950*4882a593Smuzhiyun unsigned long rc;
1951*4882a593Smuzhiyun unsigned long to_jiffies = msecs_to_jiffies(WAIT_FOR_HALP_VOTE_MS);
1952*4882a593Smuzhiyun
1953*4882a593Smuzhiyun if (wil->hw_version >= HW_VER_TALYN_MB)
1954*4882a593Smuzhiyun return;
1955*4882a593Smuzhiyun
1956*4882a593Smuzhiyun mutex_lock(&wil->halp.lock);
1957*4882a593Smuzhiyun
1958*4882a593Smuzhiyun wil_dbg_irq(wil, "halp_vote: start, HALP ref_cnt (%d)\n",
1959*4882a593Smuzhiyun wil->halp.ref_cnt);
1960*4882a593Smuzhiyun
1961*4882a593Smuzhiyun if (++wil->halp.ref_cnt == 1) {
1962*4882a593Smuzhiyun reinit_completion(&wil->halp.comp);
1963*4882a593Smuzhiyun /* mark to IRQ context to handle HALP ICR */
1964*4882a593Smuzhiyun wil->halp.handle_icr = true;
1965*4882a593Smuzhiyun wil6210_set_halp(wil);
1966*4882a593Smuzhiyun rc = wait_for_completion_timeout(&wil->halp.comp, to_jiffies);
1967*4882a593Smuzhiyun if (!rc) {
1968*4882a593Smuzhiyun wil_err(wil, "HALP vote timed out\n");
1969*4882a593Smuzhiyun /* Mask HALP as done in case the interrupt is raised */
1970*4882a593Smuzhiyun wil->halp.handle_icr = false;
1971*4882a593Smuzhiyun wil6210_mask_halp(wil);
1972*4882a593Smuzhiyun } else {
1973*4882a593Smuzhiyun wil_dbg_irq(wil,
1974*4882a593Smuzhiyun "halp_vote: HALP vote completed after %d ms\n",
1975*4882a593Smuzhiyun jiffies_to_msecs(to_jiffies - rc));
1976*4882a593Smuzhiyun }
1977*4882a593Smuzhiyun }
1978*4882a593Smuzhiyun
1979*4882a593Smuzhiyun wil_dbg_irq(wil, "halp_vote: end, HALP ref_cnt (%d)\n",
1980*4882a593Smuzhiyun wil->halp.ref_cnt);
1981*4882a593Smuzhiyun
1982*4882a593Smuzhiyun mutex_unlock(&wil->halp.lock);
1983*4882a593Smuzhiyun }
1984*4882a593Smuzhiyun
wil_halp_unvote(struct wil6210_priv * wil)1985*4882a593Smuzhiyun void wil_halp_unvote(struct wil6210_priv *wil)
1986*4882a593Smuzhiyun {
1987*4882a593Smuzhiyun if (wil->hw_version >= HW_VER_TALYN_MB)
1988*4882a593Smuzhiyun return;
1989*4882a593Smuzhiyun
1990*4882a593Smuzhiyun WARN_ON(wil->halp.ref_cnt == 0);
1991*4882a593Smuzhiyun
1992*4882a593Smuzhiyun mutex_lock(&wil->halp.lock);
1993*4882a593Smuzhiyun
1994*4882a593Smuzhiyun wil_dbg_irq(wil, "halp_unvote: start, HALP ref_cnt (%d)\n",
1995*4882a593Smuzhiyun wil->halp.ref_cnt);
1996*4882a593Smuzhiyun
1997*4882a593Smuzhiyun if (--wil->halp.ref_cnt == 0) {
1998*4882a593Smuzhiyun wil6210_clear_halp(wil);
1999*4882a593Smuzhiyun wil_dbg_irq(wil, "HALP unvote\n");
2000*4882a593Smuzhiyun }
2001*4882a593Smuzhiyun
2002*4882a593Smuzhiyun wil_dbg_irq(wil, "halp_unvote:end, HALP ref_cnt (%d)\n",
2003*4882a593Smuzhiyun wil->halp.ref_cnt);
2004*4882a593Smuzhiyun
2005*4882a593Smuzhiyun mutex_unlock(&wil->halp.lock);
2006*4882a593Smuzhiyun }
2007*4882a593Smuzhiyun
wil_init_txrx_ops(struct wil6210_priv * wil)2008*4882a593Smuzhiyun void wil_init_txrx_ops(struct wil6210_priv *wil)
2009*4882a593Smuzhiyun {
2010*4882a593Smuzhiyun if (wil->use_enhanced_dma_hw)
2011*4882a593Smuzhiyun wil_init_txrx_ops_edma(wil);
2012*4882a593Smuzhiyun else
2013*4882a593Smuzhiyun wil_init_txrx_ops_legacy_dma(wil);
2014*4882a593Smuzhiyun }
2015