xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/ath/wcn36xx/wcn36xx.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (c) 2013 Eugene Krasnikov <k.eugene.e@gmail.com>
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Permission to use, copy, modify, and/or distribute this software for any
5*4882a593Smuzhiyun  * purpose with or without fee is hereby granted, provided that the above
6*4882a593Smuzhiyun  * copyright notice and this permission notice appear in all copies.
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9*4882a593Smuzhiyun  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10*4882a593Smuzhiyun  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11*4882a593Smuzhiyun  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12*4882a593Smuzhiyun  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13*4882a593Smuzhiyun  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14*4882a593Smuzhiyun  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15*4882a593Smuzhiyun  */
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #ifndef _WCN36XX_H_
18*4882a593Smuzhiyun #define _WCN36XX_H_
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #include <linux/completion.h>
21*4882a593Smuzhiyun #include <linux/printk.h>
22*4882a593Smuzhiyun #include <linux/spinlock.h>
23*4882a593Smuzhiyun #include <net/mac80211.h>
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #include "hal.h"
26*4882a593Smuzhiyun #include "smd.h"
27*4882a593Smuzhiyun #include "txrx.h"
28*4882a593Smuzhiyun #include "dxe.h"
29*4882a593Smuzhiyun #include "pmc.h"
30*4882a593Smuzhiyun #include "debug.h"
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #define WLAN_NV_FILE               "wlan/prima/WCNSS_qcom_wlan_nv.bin"
33*4882a593Smuzhiyun #define WCN36XX_AGGR_BUFFER_SIZE 64
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun extern unsigned int wcn36xx_dbg_mask;
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun enum wcn36xx_debug_mask {
38*4882a593Smuzhiyun 	WCN36XX_DBG_DXE		= 0x00000001,
39*4882a593Smuzhiyun 	WCN36XX_DBG_DXE_DUMP	= 0x00000002,
40*4882a593Smuzhiyun 	WCN36XX_DBG_SMD		= 0x00000004,
41*4882a593Smuzhiyun 	WCN36XX_DBG_SMD_DUMP	= 0x00000008,
42*4882a593Smuzhiyun 	WCN36XX_DBG_RX		= 0x00000010,
43*4882a593Smuzhiyun 	WCN36XX_DBG_RX_DUMP	= 0x00000020,
44*4882a593Smuzhiyun 	WCN36XX_DBG_TX		= 0x00000040,
45*4882a593Smuzhiyun 	WCN36XX_DBG_TX_DUMP	= 0x00000080,
46*4882a593Smuzhiyun 	WCN36XX_DBG_HAL		= 0x00000100,
47*4882a593Smuzhiyun 	WCN36XX_DBG_HAL_DUMP	= 0x00000200,
48*4882a593Smuzhiyun 	WCN36XX_DBG_MAC		= 0x00000400,
49*4882a593Smuzhiyun 	WCN36XX_DBG_BEACON	= 0x00000800,
50*4882a593Smuzhiyun 	WCN36XX_DBG_BEACON_DUMP	= 0x00001000,
51*4882a593Smuzhiyun 	WCN36XX_DBG_PMC		= 0x00002000,
52*4882a593Smuzhiyun 	WCN36XX_DBG_PMC_DUMP	= 0x00004000,
53*4882a593Smuzhiyun 	WCN36XX_DBG_TESTMODE		= 0x00008000,
54*4882a593Smuzhiyun 	WCN36XX_DBG_TESTMODE_DUMP	= 0x00010000,
55*4882a593Smuzhiyun 	WCN36XX_DBG_ANY		= 0xffffffff,
56*4882a593Smuzhiyun };
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun #define wcn36xx_err(fmt, arg...)				\
59*4882a593Smuzhiyun 	printk(KERN_ERR pr_fmt("ERROR " fmt), ##arg)
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun #define wcn36xx_warn(fmt, arg...)				\
62*4882a593Smuzhiyun 	printk(KERN_WARNING pr_fmt("WARNING " fmt), ##arg)
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun #define wcn36xx_info(fmt, arg...)		\
65*4882a593Smuzhiyun 	printk(KERN_INFO pr_fmt(fmt), ##arg)
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun #define wcn36xx_dbg(mask, fmt, arg...) do {			\
68*4882a593Smuzhiyun 	if (wcn36xx_dbg_mask & mask)					\
69*4882a593Smuzhiyun 		printk(KERN_DEBUG pr_fmt(fmt), ##arg);	\
70*4882a593Smuzhiyun } while (0)
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun #define wcn36xx_dbg_dump(mask, prefix_str, buf, len) do {	\
73*4882a593Smuzhiyun 	if (wcn36xx_dbg_mask & mask)					\
74*4882a593Smuzhiyun 		print_hex_dump(KERN_DEBUG, pr_fmt(prefix_str),	\
75*4882a593Smuzhiyun 			       DUMP_PREFIX_OFFSET, 32, 1,	\
76*4882a593Smuzhiyun 			       buf, len, false);		\
77*4882a593Smuzhiyun } while (0)
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun enum wcn36xx_ampdu_state {
80*4882a593Smuzhiyun 	WCN36XX_AMPDU_NONE,
81*4882a593Smuzhiyun 	WCN36XX_AMPDU_INIT,
82*4882a593Smuzhiyun 	WCN36XX_AMPDU_START,
83*4882a593Smuzhiyun 	WCN36XX_AMPDU_OPERATIONAL,
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun #define HW_VALUE_PHY_SHIFT 8
87*4882a593Smuzhiyun #define HW_VALUE_PHY(hw_value) ((hw_value) >> HW_VALUE_PHY_SHIFT)
88*4882a593Smuzhiyun #define HW_VALUE_CHANNEL(hw_value) ((hw_value) & 0xFF)
89*4882a593Smuzhiyun #define WCN36XX_HW_CHANNEL(__wcn)\
90*4882a593Smuzhiyun 	HW_VALUE_CHANNEL(__wcn->hw->conf.chandef.chan->hw_value)
91*4882a593Smuzhiyun #define WCN36XX_BAND(__wcn) (__wcn->hw->conf.chandef.chan->band)
92*4882a593Smuzhiyun #define WCN36XX_CENTER_FREQ(__wcn) (__wcn->hw->conf.chandef.chan->center_freq)
93*4882a593Smuzhiyun #define WCN36XX_LISTEN_INTERVAL(__wcn) (__wcn->hw->conf.listen_interval)
94*4882a593Smuzhiyun #define WCN36XX_FLAGS(__wcn) (__wcn->hw->flags)
95*4882a593Smuzhiyun #define WCN36XX_MAX_POWER(__wcn) (__wcn->hw->conf.chandef.chan->max_power)
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun #define RF_UNKNOWN	0x0000
98*4882a593Smuzhiyun #define RF_IRIS_WCN3620	0x3620
99*4882a593Smuzhiyun #define RF_IRIS_WCN3660	0x3660
100*4882a593Smuzhiyun #define RF_IRIS_WCN3680	0x3680
101*4882a593Smuzhiyun 
buff_to_be(u32 * buf,size_t len)102*4882a593Smuzhiyun static inline void buff_to_be(u32 *buf, size_t len)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun 	int i;
105*4882a593Smuzhiyun 	for (i = 0; i < len; i++)
106*4882a593Smuzhiyun 		buf[i] = cpu_to_be32(buf[i]);
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun struct nv_data {
110*4882a593Smuzhiyun 	int	is_valid;
111*4882a593Smuzhiyun 	u8	table;
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun /**
115*4882a593Smuzhiyun  * struct wcn36xx_vif - holds VIF related fields
116*4882a593Smuzhiyun  *
117*4882a593Smuzhiyun  * @bss_index: bss_index is initially set to 0xFF. bss_index is received from
118*4882a593Smuzhiyun  * HW after first config_bss call and must be used in delete_bss and
119*4882a593Smuzhiyun  * enter/exit_bmps.
120*4882a593Smuzhiyun  */
121*4882a593Smuzhiyun struct wcn36xx_vif {
122*4882a593Smuzhiyun 	struct list_head list;
123*4882a593Smuzhiyun 	u8 dtim_period;
124*4882a593Smuzhiyun 	enum ani_ed_type encrypt_type;
125*4882a593Smuzhiyun 	bool is_joining;
126*4882a593Smuzhiyun 	bool sta_assoc;
127*4882a593Smuzhiyun 	struct wcn36xx_hal_mac_ssid ssid;
128*4882a593Smuzhiyun 	enum wcn36xx_hal_bss_type bss_type;
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	/* Power management */
131*4882a593Smuzhiyun 	enum wcn36xx_power_state pw_state;
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	u8 bss_index;
134*4882a593Smuzhiyun 	/* Returned from WCN36XX_HAL_ADD_STA_SELF_RSP */
135*4882a593Smuzhiyun 	u8 self_sta_index;
136*4882a593Smuzhiyun 	u8 self_dpu_desc_index;
137*4882a593Smuzhiyun 	u8 self_ucast_dpu_sign;
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	struct list_head sta_list;
140*4882a593Smuzhiyun };
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun /**
143*4882a593Smuzhiyun  * struct wcn36xx_sta - holds STA related fields
144*4882a593Smuzhiyun  *
145*4882a593Smuzhiyun  * @tid: traffic ID that is used during AMPDU and in TX BD.
146*4882a593Smuzhiyun  * @sta_index: STA index is returned from HW after config_sta call and is
147*4882a593Smuzhiyun  * used in both SMD channel and TX BD.
148*4882a593Smuzhiyun  * @dpu_desc_index: DPU descriptor index is returned from HW after config_sta
149*4882a593Smuzhiyun  * call and is used in TX BD.
150*4882a593Smuzhiyun  * @bss_sta_index: STA index is returned from HW after config_bss call and is
151*4882a593Smuzhiyun  * used in both SMD channel and TX BD. See table bellow when it is used.
152*4882a593Smuzhiyun  * @bss_dpu_desc_index: DPU descriptor index is returned from HW after
153*4882a593Smuzhiyun  * config_bss call and is used in TX BD.
154*4882a593Smuzhiyun  * ______________________________________________
155*4882a593Smuzhiyun  * |		  |	STA	|	AP	|
156*4882a593Smuzhiyun  * |______________|_____________|_______________|
157*4882a593Smuzhiyun  * |    TX BD     |bss_sta_index|   sta_index   |
158*4882a593Smuzhiyun  * |______________|_____________|_______________|
159*4882a593Smuzhiyun  * |all SMD calls |bss_sta_index|   sta_index	|
160*4882a593Smuzhiyun  * |______________|_____________|_______________|
161*4882a593Smuzhiyun  * |smd_delete_sta|  sta_index  |   sta_index	|
162*4882a593Smuzhiyun  * |______________|_____________|_______________|
163*4882a593Smuzhiyun  */
164*4882a593Smuzhiyun struct wcn36xx_sta {
165*4882a593Smuzhiyun 	struct list_head list;
166*4882a593Smuzhiyun 	struct wcn36xx_vif *vif;
167*4882a593Smuzhiyun 	u16 aid;
168*4882a593Smuzhiyun 	u16 tid;
169*4882a593Smuzhiyun 	u8 sta_index;
170*4882a593Smuzhiyun 	u8 dpu_desc_index;
171*4882a593Smuzhiyun 	u8 ucast_dpu_sign;
172*4882a593Smuzhiyun 	u8 bss_sta_index;
173*4882a593Smuzhiyun 	u8 bss_dpu_desc_index;
174*4882a593Smuzhiyun 	bool is_data_encrypted;
175*4882a593Smuzhiyun 	/* Rates */
176*4882a593Smuzhiyun 	struct wcn36xx_hal_supported_rates_v1 supported_rates;
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	spinlock_t ampdu_lock;		/* protects next two fields */
179*4882a593Smuzhiyun 	enum wcn36xx_ampdu_state ampdu_state[16];
180*4882a593Smuzhiyun 	int non_agg_frame_ct;
181*4882a593Smuzhiyun };
182*4882a593Smuzhiyun struct wcn36xx_dxe_ch;
183*4882a593Smuzhiyun struct wcn36xx {
184*4882a593Smuzhiyun 	struct ieee80211_hw	*hw;
185*4882a593Smuzhiyun 	struct device		*dev;
186*4882a593Smuzhiyun 	struct list_head	vif_list;
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 	const struct firmware	*nv;
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun 	u8			fw_revision;
191*4882a593Smuzhiyun 	u8			fw_version;
192*4882a593Smuzhiyun 	u8			fw_minor;
193*4882a593Smuzhiyun 	u8			fw_major;
194*4882a593Smuzhiyun 	u32			fw_feat_caps[WCN36XX_HAL_CAPS_SIZE];
195*4882a593Smuzhiyun 	bool			is_pronto;
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun 	/* extra byte for the NULL termination */
198*4882a593Smuzhiyun 	u8			crm_version[WCN36XX_HAL_VERSION_LENGTH + 1];
199*4882a593Smuzhiyun 	u8			wlan_version[WCN36XX_HAL_VERSION_LENGTH + 1];
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun 	bool		first_boot;
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	/* IRQs */
204*4882a593Smuzhiyun 	int			tx_irq;
205*4882a593Smuzhiyun 	int			rx_irq;
206*4882a593Smuzhiyun 	void __iomem		*ccu_base;
207*4882a593Smuzhiyun 	void __iomem		*dxe_base;
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun 	struct rpmsg_endpoint	*smd_channel;
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	struct qcom_smem_state  *tx_enable_state;
212*4882a593Smuzhiyun 	unsigned		tx_enable_state_bit;
213*4882a593Smuzhiyun 	struct qcom_smem_state	*tx_rings_empty_state;
214*4882a593Smuzhiyun 	unsigned		tx_rings_empty_state_bit;
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	/* prevents concurrent FW reconfiguration */
217*4882a593Smuzhiyun 	struct mutex		conf_mutex;
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun 	/*
220*4882a593Smuzhiyun 	 * smd_buf must be protected with smd_mutex to garantee
221*4882a593Smuzhiyun 	 * that all messages are sent one after another
222*4882a593Smuzhiyun 	 */
223*4882a593Smuzhiyun 	u8			*hal_buf;
224*4882a593Smuzhiyun 	size_t			hal_rsp_len;
225*4882a593Smuzhiyun 	struct mutex		hal_mutex;
226*4882a593Smuzhiyun 	struct completion	hal_rsp_compl;
227*4882a593Smuzhiyun 	struct workqueue_struct	*hal_ind_wq;
228*4882a593Smuzhiyun 	struct work_struct	hal_ind_work;
229*4882a593Smuzhiyun 	spinlock_t		hal_ind_lock;
230*4882a593Smuzhiyun 	struct list_head	hal_ind_queue;
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 	struct cfg80211_scan_request *scan_req;
233*4882a593Smuzhiyun 	bool			sw_scan;
234*4882a593Smuzhiyun 	u8			sw_scan_opchannel;
235*4882a593Smuzhiyun 	bool			sw_scan_init;
236*4882a593Smuzhiyun 	u8			sw_scan_channel;
237*4882a593Smuzhiyun 	struct ieee80211_vif	*sw_scan_vif;
238*4882a593Smuzhiyun 	struct mutex		scan_lock;
239*4882a593Smuzhiyun 	bool			scan_aborted;
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun 	/* DXE channels */
242*4882a593Smuzhiyun 	struct wcn36xx_dxe_ch	dxe_tx_l_ch;	/* TX low */
243*4882a593Smuzhiyun 	struct wcn36xx_dxe_ch	dxe_tx_h_ch;	/* TX high */
244*4882a593Smuzhiyun 	struct wcn36xx_dxe_ch	dxe_rx_l_ch;	/* RX low */
245*4882a593Smuzhiyun 	struct wcn36xx_dxe_ch	dxe_rx_h_ch;	/* RX high */
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun 	/* For synchronization of DXE resources from BH, IRQ and WQ contexts */
248*4882a593Smuzhiyun 	spinlock_t	dxe_lock;
249*4882a593Smuzhiyun 	bool                    queues_stopped;
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 	/* Memory pools */
252*4882a593Smuzhiyun 	struct wcn36xx_dxe_mem_pool mgmt_mem_pool;
253*4882a593Smuzhiyun 	struct wcn36xx_dxe_mem_pool data_mem_pool;
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun 	struct sk_buff		*tx_ack_skb;
256*4882a593Smuzhiyun 	struct timer_list	tx_ack_timer;
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun 	/* RF module */
259*4882a593Smuzhiyun 	unsigned		rf_id;
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun #ifdef CONFIG_WCN36XX_DEBUGFS
262*4882a593Smuzhiyun 	/* Debug file system entry */
263*4882a593Smuzhiyun 	struct wcn36xx_dfs_entry    dfs;
264*4882a593Smuzhiyun #endif /* CONFIG_WCN36XX_DEBUGFS */
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun };
267*4882a593Smuzhiyun 
wcn36xx_is_fw_version(struct wcn36xx * wcn,u8 major,u8 minor,u8 version,u8 revision)268*4882a593Smuzhiyun static inline bool wcn36xx_is_fw_version(struct wcn36xx *wcn,
269*4882a593Smuzhiyun 					 u8 major,
270*4882a593Smuzhiyun 					 u8 minor,
271*4882a593Smuzhiyun 					 u8 version,
272*4882a593Smuzhiyun 					 u8 revision)
273*4882a593Smuzhiyun {
274*4882a593Smuzhiyun 	return (wcn->fw_major == major &&
275*4882a593Smuzhiyun 		wcn->fw_minor == minor &&
276*4882a593Smuzhiyun 		wcn->fw_version == version &&
277*4882a593Smuzhiyun 		wcn->fw_revision == revision);
278*4882a593Smuzhiyun }
279*4882a593Smuzhiyun void wcn36xx_set_default_rates(struct wcn36xx_hal_supported_rates *rates);
280*4882a593Smuzhiyun void wcn36xx_set_default_rates_v1(struct wcn36xx_hal_supported_rates_v1 *rates);
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun static inline
wcn36xx_priv_to_sta(struct wcn36xx_sta * sta_priv)283*4882a593Smuzhiyun struct ieee80211_sta *wcn36xx_priv_to_sta(struct wcn36xx_sta *sta_priv)
284*4882a593Smuzhiyun {
285*4882a593Smuzhiyun 	return container_of((void *)sta_priv, struct ieee80211_sta, drv_priv);
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun static inline
wcn36xx_vif_to_priv(struct ieee80211_vif * vif)289*4882a593Smuzhiyun struct wcn36xx_vif *wcn36xx_vif_to_priv(struct ieee80211_vif *vif)
290*4882a593Smuzhiyun {
291*4882a593Smuzhiyun 	return (struct wcn36xx_vif *) vif->drv_priv;
292*4882a593Smuzhiyun }
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun static inline
wcn36xx_priv_to_vif(struct wcn36xx_vif * vif_priv)295*4882a593Smuzhiyun struct ieee80211_vif *wcn36xx_priv_to_vif(struct wcn36xx_vif *vif_priv)
296*4882a593Smuzhiyun {
297*4882a593Smuzhiyun 	return container_of((void *) vif_priv, struct ieee80211_vif, drv_priv);
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun static inline
wcn36xx_sta_to_priv(struct ieee80211_sta * sta)301*4882a593Smuzhiyun struct wcn36xx_sta *wcn36xx_sta_to_priv(struct ieee80211_sta *sta)
302*4882a593Smuzhiyun {
303*4882a593Smuzhiyun 	return (struct wcn36xx_sta *)sta->drv_priv;
304*4882a593Smuzhiyun }
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun #endif	/* _WCN36XX_H_ */
307