1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2013 Eugene Krasnikov <k.eugene.e@gmail.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission to use, copy, modify, and/or distribute this software for any 5*4882a593Smuzhiyun * purpose with or without fee is hereby granted, provided that the above 6*4882a593Smuzhiyun * copyright notice and this permission notice appear in all copies. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*4882a593Smuzhiyun * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*4882a593Smuzhiyun * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11*4882a593Smuzhiyun * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*4882a593Smuzhiyun * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13*4882a593Smuzhiyun * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14*4882a593Smuzhiyun * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef _TXRX_H_ 18*4882a593Smuzhiyun #define _TXRX_H_ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #include <linux/etherdevice.h> 21*4882a593Smuzhiyun #include "wcn36xx.h" 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* TODO describe all properties */ 24*4882a593Smuzhiyun #define WCN36XX_802_11_HEADER_LEN 24 25*4882a593Smuzhiyun #define WCN36XX_BMU_WQ_TX 25 26*4882a593Smuzhiyun #define WCN36XX_TID 7 27*4882a593Smuzhiyun /* broadcast wq ID */ 28*4882a593Smuzhiyun #define WCN36XX_TX_B_WQ_ID 0xA 29*4882a593Smuzhiyun #define WCN36XX_TX_U_WQ_ID 0x9 30*4882a593Smuzhiyun /* bd_rate */ 31*4882a593Smuzhiyun #define WCN36XX_BD_RATE_DATA 0 32*4882a593Smuzhiyun #define WCN36XX_BD_RATE_MGMT 2 33*4882a593Smuzhiyun #define WCN36XX_BD_RATE_CTRL 3 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun enum wcn36xx_txbd_ssn_type { 36*4882a593Smuzhiyun WCN36XX_TXBD_SSN_FILL_HOST = 0, 37*4882a593Smuzhiyun WCN36XX_TXBD_SSN_FILL_DPU_NON_QOS = 1, 38*4882a593Smuzhiyun WCN36XX_TXBD_SSN_FILL_DPU_QOS = 2, 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun struct wcn36xx_pdu { 42*4882a593Smuzhiyun u32 dpu_fb:8; 43*4882a593Smuzhiyun u32 adu_fb:8; 44*4882a593Smuzhiyun u32 pdu_id:16; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* 0x04*/ 47*4882a593Smuzhiyun u32 tail_pdu_idx:16; 48*4882a593Smuzhiyun u32 head_pdu_idx:16; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* 0x08*/ 51*4882a593Smuzhiyun u32 pdu_count:7; 52*4882a593Smuzhiyun u32 mpdu_data_off:9; 53*4882a593Smuzhiyun u32 mpdu_header_off:8; 54*4882a593Smuzhiyun u32 mpdu_header_len:8; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* 0x0c*/ 57*4882a593Smuzhiyun u32 reserved4:8; 58*4882a593Smuzhiyun u32 tid:4; 59*4882a593Smuzhiyun u32 bd_ssn:2; 60*4882a593Smuzhiyun u32 reserved3:2; 61*4882a593Smuzhiyun u32 mpdu_len:16; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun struct wcn36xx_rx_bd { 65*4882a593Smuzhiyun u32 bdt:2; 66*4882a593Smuzhiyun u32 ft:1; 67*4882a593Smuzhiyun u32 dpu_ne:1; 68*4882a593Smuzhiyun u32 rx_key_id:3; 69*4882a593Smuzhiyun u32 ub:1; 70*4882a593Smuzhiyun u32 rmf:1; 71*4882a593Smuzhiyun u32 uma_bypass:1; 72*4882a593Smuzhiyun u32 csr11:1; 73*4882a593Smuzhiyun u32 reserved0:1; 74*4882a593Smuzhiyun u32 scan_learn:1; 75*4882a593Smuzhiyun u32 rx_ch:4; 76*4882a593Smuzhiyun u32 rtsf:1; 77*4882a593Smuzhiyun u32 bsf:1; 78*4882a593Smuzhiyun u32 a2hf:1; 79*4882a593Smuzhiyun u32 st_auf:1; 80*4882a593Smuzhiyun u32 dpu_sign:3; 81*4882a593Smuzhiyun u32 dpu_rf:8; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun struct wcn36xx_pdu pdu; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* 0x14*/ 86*4882a593Smuzhiyun u32 addr3:8; 87*4882a593Smuzhiyun u32 addr2:8; 88*4882a593Smuzhiyun u32 addr1:8; 89*4882a593Smuzhiyun u32 dpu_desc_idx:8; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* 0x18*/ 92*4882a593Smuzhiyun u32 rxp_flags:23; 93*4882a593Smuzhiyun u32 rate_id:9; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun u32 phy_stat0; 96*4882a593Smuzhiyun u32 phy_stat1; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* 0x24 */ 99*4882a593Smuzhiyun u32 rx_times; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun u32 pmi_cmd[6]; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* 0x40 */ 104*4882a593Smuzhiyun u32 reserved7:4; 105*4882a593Smuzhiyun u32 reorder_slot_id:6; 106*4882a593Smuzhiyun u32 reorder_fwd_id:6; 107*4882a593Smuzhiyun u32 reserved6:12; 108*4882a593Smuzhiyun u32 reorder_code:4; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* 0x44 */ 111*4882a593Smuzhiyun u32 exp_seq_num:12; 112*4882a593Smuzhiyun u32 cur_seq_num:12; 113*4882a593Smuzhiyun u32 rf_band:2; 114*4882a593Smuzhiyun u32 fr_type_subtype:6; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun /* 0x48 */ 117*4882a593Smuzhiyun u32 msdu_size:16; 118*4882a593Smuzhiyun u32 sub_fr_id:4; 119*4882a593Smuzhiyun u32 proc_order:4; 120*4882a593Smuzhiyun u32 reserved9:4; 121*4882a593Smuzhiyun u32 aef:1; 122*4882a593Smuzhiyun u32 lsf:1; 123*4882a593Smuzhiyun u32 esf:1; 124*4882a593Smuzhiyun u32 asf:1; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun struct wcn36xx_tx_bd { 128*4882a593Smuzhiyun u32 bdt:2; 129*4882a593Smuzhiyun u32 ft:1; 130*4882a593Smuzhiyun u32 dpu_ne:1; 131*4882a593Smuzhiyun u32 fw_tx_comp:1; 132*4882a593Smuzhiyun u32 tx_comp:1; 133*4882a593Smuzhiyun u32 reserved1:1; 134*4882a593Smuzhiyun u32 ub:1; 135*4882a593Smuzhiyun u32 rmf:1; 136*4882a593Smuzhiyun u32 reserved0:12; 137*4882a593Smuzhiyun u32 dpu_sign:3; 138*4882a593Smuzhiyun u32 dpu_rf:8; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun struct wcn36xx_pdu pdu; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun /* 0x14*/ 143*4882a593Smuzhiyun u32 reserved5:7; 144*4882a593Smuzhiyun u32 queue_id:5; 145*4882a593Smuzhiyun u32 bd_rate:2; 146*4882a593Smuzhiyun u32 ack_policy:2; 147*4882a593Smuzhiyun u32 sta_index:8; 148*4882a593Smuzhiyun u32 dpu_desc_idx:8; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun u32 tx_bd_sign; 151*4882a593Smuzhiyun u32 reserved6; 152*4882a593Smuzhiyun u32 dxe_start_time; 153*4882a593Smuzhiyun u32 dxe_end_time; 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun /*u32 tcp_udp_start_off:10; 156*4882a593Smuzhiyun u32 header_cks:16; 157*4882a593Smuzhiyun u32 reserved7:6;*/ 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun struct wcn36xx_sta; 161*4882a593Smuzhiyun struct wcn36xx; 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun int wcn36xx_rx_skb(struct wcn36xx *wcn, struct sk_buff *skb); 164*4882a593Smuzhiyun int wcn36xx_start_tx(struct wcn36xx *wcn, 165*4882a593Smuzhiyun struct wcn36xx_sta *sta_priv, 166*4882a593Smuzhiyun struct sk_buff *skb); 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun #endif /* _TXRX_H_ */ 169