1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Shared Atheros AR9170 Header 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * EEPROM layout 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright 2008, Johannes Berg <johannes@sipsolutions.net> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 9*4882a593Smuzhiyun * it under the terms of the GNU General Public License as published by 10*4882a593Smuzhiyun * the Free Software Foundation; either version 2 of the License, or 11*4882a593Smuzhiyun * (at your option) any later version. 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, 14*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of 15*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*4882a593Smuzhiyun * GNU General Public License for more details. 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License 19*4882a593Smuzhiyun * along with this program; see the file COPYING. If not, see 20*4882a593Smuzhiyun * http://www.gnu.org/licenses/. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * This file incorporates work covered by the following copyright and 23*4882a593Smuzhiyun * permission notice: 24*4882a593Smuzhiyun * Copyright (c) 2007-2008 Atheros Communications, Inc. 25*4882a593Smuzhiyun * 26*4882a593Smuzhiyun * Permission to use, copy, modify, and/or distribute this software for any 27*4882a593Smuzhiyun * purpose with or without fee is hereby granted, provided that the above 28*4882a593Smuzhiyun * copyright notice and this permission notice appear in all copies. 29*4882a593Smuzhiyun * 30*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 31*4882a593Smuzhiyun * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 32*4882a593Smuzhiyun * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 33*4882a593Smuzhiyun * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 34*4882a593Smuzhiyun * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 35*4882a593Smuzhiyun * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 36*4882a593Smuzhiyun * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun #ifndef __CARL9170_SHARED_EEPROM_H 39*4882a593Smuzhiyun #define __CARL9170_SHARED_EEPROM_H 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define AR9170_EEPROM_START 0x1600 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define AR5416_MAX_CHAINS 2 44*4882a593Smuzhiyun #define AR5416_MODAL_SPURS 5 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun struct ar9170_eeprom_modal { 47*4882a593Smuzhiyun __le32 antCtrlChain[AR5416_MAX_CHAINS]; 48*4882a593Smuzhiyun __le32 antCtrlCommon; 49*4882a593Smuzhiyun s8 antennaGainCh[AR5416_MAX_CHAINS]; 50*4882a593Smuzhiyun u8 switchSettling; 51*4882a593Smuzhiyun u8 txRxAttenCh[AR5416_MAX_CHAINS]; 52*4882a593Smuzhiyun u8 rxTxMarginCh[AR5416_MAX_CHAINS]; 53*4882a593Smuzhiyun s8 adcDesiredSize; 54*4882a593Smuzhiyun s8 pgaDesiredSize; 55*4882a593Smuzhiyun u8 xlnaGainCh[AR5416_MAX_CHAINS]; 56*4882a593Smuzhiyun u8 txEndToXpaOff; 57*4882a593Smuzhiyun u8 txEndToRxOn; 58*4882a593Smuzhiyun u8 txFrameToXpaOn; 59*4882a593Smuzhiyun u8 thresh62; 60*4882a593Smuzhiyun s8 noiseFloorThreshCh[AR5416_MAX_CHAINS]; 61*4882a593Smuzhiyun u8 xpdGain; 62*4882a593Smuzhiyun u8 xpd; 63*4882a593Smuzhiyun s8 iqCalICh[AR5416_MAX_CHAINS]; 64*4882a593Smuzhiyun s8 iqCalQCh[AR5416_MAX_CHAINS]; 65*4882a593Smuzhiyun u8 pdGainOverlap; 66*4882a593Smuzhiyun u8 ob; 67*4882a593Smuzhiyun u8 db; 68*4882a593Smuzhiyun u8 xpaBiasLvl; 69*4882a593Smuzhiyun u8 pwrDecreaseFor2Chain; 70*4882a593Smuzhiyun u8 pwrDecreaseFor3Chain; 71*4882a593Smuzhiyun u8 txFrameToDataStart; 72*4882a593Smuzhiyun u8 txFrameToPaOn; 73*4882a593Smuzhiyun u8 ht40PowerIncForPdadc; 74*4882a593Smuzhiyun u8 bswAtten[AR5416_MAX_CHAINS]; 75*4882a593Smuzhiyun u8 bswMargin[AR5416_MAX_CHAINS]; 76*4882a593Smuzhiyun u8 swSettleHt40; 77*4882a593Smuzhiyun u8 reserved[22]; 78*4882a593Smuzhiyun struct spur_channel { 79*4882a593Smuzhiyun __le16 spurChan; 80*4882a593Smuzhiyun u8 spurRangeLow; 81*4882a593Smuzhiyun u8 spurRangeHigh; 82*4882a593Smuzhiyun } __packed spur_channels[AR5416_MODAL_SPURS]; 83*4882a593Smuzhiyun } __packed; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define AR5416_NUM_PD_GAINS 4 86*4882a593Smuzhiyun #define AR5416_PD_GAIN_ICEPTS 5 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun struct ar9170_calibration_data_per_freq { 89*4882a593Smuzhiyun u8 pwr_pdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 90*4882a593Smuzhiyun u8 vpd_pdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 91*4882a593Smuzhiyun } __packed; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #define AR5416_NUM_5G_CAL_PIERS 8 94*4882a593Smuzhiyun #define AR5416_NUM_2G_CAL_PIERS 4 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #define AR5416_NUM_5G_TARGET_PWRS 8 97*4882a593Smuzhiyun #define AR5416_NUM_2G_CCK_TARGET_PWRS 3 98*4882a593Smuzhiyun #define AR5416_NUM_2G_OFDM_TARGET_PWRS 4 99*4882a593Smuzhiyun #define AR5416_MAX_NUM_TGT_PWRS 8 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun struct ar9170_calibration_target_power_legacy { 102*4882a593Smuzhiyun u8 freq; 103*4882a593Smuzhiyun u8 power[4]; 104*4882a593Smuzhiyun } __packed; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun struct ar9170_calibration_target_power_ht { 107*4882a593Smuzhiyun u8 freq; 108*4882a593Smuzhiyun u8 power[8]; 109*4882a593Smuzhiyun } __packed; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #define AR5416_NUM_CTLS 24 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun struct ar9170_calctl_edges { 114*4882a593Smuzhiyun u8 channel; 115*4882a593Smuzhiyun #define AR9170_CALCTL_EDGE_FLAGS 0xC0 116*4882a593Smuzhiyun u8 power_flags; 117*4882a593Smuzhiyun } __packed; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define AR5416_NUM_BAND_EDGES 8 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun struct ar9170_calctl_data { 122*4882a593Smuzhiyun struct ar9170_calctl_edges 123*4882a593Smuzhiyun control_edges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES]; 124*4882a593Smuzhiyun } __packed; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun struct ar9170_eeprom { 127*4882a593Smuzhiyun __le16 length; 128*4882a593Smuzhiyun __le16 checksum; 129*4882a593Smuzhiyun __le16 version; 130*4882a593Smuzhiyun u8 operating_flags; 131*4882a593Smuzhiyun #define AR9170_OPFLAG_5GHZ 1 132*4882a593Smuzhiyun #define AR9170_OPFLAG_2GHZ 2 133*4882a593Smuzhiyun u8 misc; 134*4882a593Smuzhiyun __le16 reg_domain[2]; 135*4882a593Smuzhiyun u8 mac_address[6]; 136*4882a593Smuzhiyun u8 rx_mask; 137*4882a593Smuzhiyun u8 tx_mask; 138*4882a593Smuzhiyun __le16 rf_silent; 139*4882a593Smuzhiyun __le16 bluetooth_options; 140*4882a593Smuzhiyun __le16 device_capabilities; 141*4882a593Smuzhiyun __le32 build_number; 142*4882a593Smuzhiyun u8 deviceType; 143*4882a593Smuzhiyun u8 reserved[33]; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun u8 customer_data[64]; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun struct ar9170_eeprom_modal 148*4882a593Smuzhiyun modal_header[2]; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun u8 cal_freq_pier_5G[AR5416_NUM_5G_CAL_PIERS]; 151*4882a593Smuzhiyun u8 cal_freq_pier_2G[AR5416_NUM_2G_CAL_PIERS]; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun struct ar9170_calibration_data_per_freq 154*4882a593Smuzhiyun cal_pier_data_5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS], 155*4882a593Smuzhiyun cal_pier_data_2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS]; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun /* power calibration data */ 158*4882a593Smuzhiyun struct ar9170_calibration_target_power_legacy 159*4882a593Smuzhiyun cal_tgt_pwr_5G[AR5416_NUM_5G_TARGET_PWRS]; 160*4882a593Smuzhiyun struct ar9170_calibration_target_power_ht 161*4882a593Smuzhiyun cal_tgt_pwr_5G_ht20[AR5416_NUM_5G_TARGET_PWRS], 162*4882a593Smuzhiyun cal_tgt_pwr_5G_ht40[AR5416_NUM_5G_TARGET_PWRS]; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun struct ar9170_calibration_target_power_legacy 165*4882a593Smuzhiyun cal_tgt_pwr_2G_cck[AR5416_NUM_2G_CCK_TARGET_PWRS], 166*4882a593Smuzhiyun cal_tgt_pwr_2G_ofdm[AR5416_NUM_2G_OFDM_TARGET_PWRS]; 167*4882a593Smuzhiyun struct ar9170_calibration_target_power_ht 168*4882a593Smuzhiyun cal_tgt_pwr_2G_ht20[AR5416_NUM_2G_OFDM_TARGET_PWRS], 169*4882a593Smuzhiyun cal_tgt_pwr_2G_ht40[AR5416_NUM_2G_OFDM_TARGET_PWRS]; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun /* conformance testing limits */ 172*4882a593Smuzhiyun u8 ctl_index[AR5416_NUM_CTLS]; 173*4882a593Smuzhiyun struct ar9170_calctl_data 174*4882a593Smuzhiyun ctl_data[AR5416_NUM_CTLS]; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun u8 pad; 177*4882a593Smuzhiyun __le16 subsystem_id; 178*4882a593Smuzhiyun } __packed; 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun #define AR9170_LED_MODE_POWER_ON 0x0001 181*4882a593Smuzhiyun #define AR9170_LED_MODE_RESERVED 0x0002 182*4882a593Smuzhiyun #define AR9170_LED_MODE_DISABLE_STATE 0x0004 183*4882a593Smuzhiyun #define AR9170_LED_MODE_OFF_IN_PSM 0x0008 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun /* AR9170_LED_MODE BIT is set */ 186*4882a593Smuzhiyun #define AR9170_LED_MODE_FREQUENCY_S 4 187*4882a593Smuzhiyun #define AR9170_LED_MODE_FREQUENCY 0x0030 188*4882a593Smuzhiyun #define AR9170_LED_MODE_FREQUENCY_1HZ 0x0000 189*4882a593Smuzhiyun #define AR9170_LED_MODE_FREQUENCY_0_5HZ 0x0010 190*4882a593Smuzhiyun #define AR9170_LED_MODE_FREQUENCY_0_25HZ 0x0020 191*4882a593Smuzhiyun #define AR9170_LED_MODE_FREQUENCY_0_125HZ 0x0030 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun /* AR9170_LED_MODE BIT is not set */ 194*4882a593Smuzhiyun #define AR9170_LED_MODE_CONN_STATE_S 4 195*4882a593Smuzhiyun #define AR9170_LED_MODE_CONN_STATE 0x0030 196*4882a593Smuzhiyun #define AR9170_LED_MODE_CONN_STATE_FORCE_OFF 0x0000 197*4882a593Smuzhiyun #define AR9170_LED_MODE_CONN_STATE_FORCE_ON 0x0010 198*4882a593Smuzhiyun /* Idle off / Active on */ 199*4882a593Smuzhiyun #define AR9170_LED_MODE_CONN_STATE_IOFF_AON 0x0020 200*4882a593Smuzhiyun /* Idle on / Active off */ 201*4882a593Smuzhiyun #define AR9170_LED_MODE_CONN_STATE_ION_AOFF 0x0010 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun #define AR9170_LED_MODE_MODE 0x0040 204*4882a593Smuzhiyun #define AR9170_LED_MODE_RESERVED2 0x0080 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun #define AR9170_LED_MODE_TON_SCAN_S 8 207*4882a593Smuzhiyun #define AR9170_LED_MODE_TON_SCAN 0x0f00 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun #define AR9170_LED_MODE_TOFF_SCAN_S 12 210*4882a593Smuzhiyun #define AR9170_LED_MODE_TOFF_SCAN 0xf000 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun struct ar9170_led_mode { 213*4882a593Smuzhiyun __le16 led; 214*4882a593Smuzhiyun }; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun #endif /* __CARL9170_SHARED_EEPROM_H */ 217