1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Atheros CARL9170 driver 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * debug header 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright 2010, Christian Lamparter <chunkeey@googlemail.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 9*4882a593Smuzhiyun * it under the terms of the GNU General Public License as published by 10*4882a593Smuzhiyun * the Free Software Foundation; either version 2 of the License, or 11*4882a593Smuzhiyun * (at your option) any later version. 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, 14*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of 15*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*4882a593Smuzhiyun * GNU General Public License for more details. 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License 19*4882a593Smuzhiyun * along with this program; see the file COPYING. If not, see 20*4882a593Smuzhiyun * http://www.gnu.org/licenses/. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * This file incorporates work covered by the following copyright and 23*4882a593Smuzhiyun * permission notice: 24*4882a593Smuzhiyun * Copyright (c) 2007-2008 Atheros Communications, Inc. 25*4882a593Smuzhiyun * 26*4882a593Smuzhiyun * Permission to use, copy, modify, and/or distribute this software for any 27*4882a593Smuzhiyun * purpose with or without fee is hereby granted, provided that the above 28*4882a593Smuzhiyun * copyright notice and this permission notice appear in all copies. 29*4882a593Smuzhiyun * 30*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 31*4882a593Smuzhiyun * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 32*4882a593Smuzhiyun * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 33*4882a593Smuzhiyun * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 34*4882a593Smuzhiyun * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 35*4882a593Smuzhiyun * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 36*4882a593Smuzhiyun * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun #ifndef __DEBUG_H 39*4882a593Smuzhiyun #define __DEBUG_H 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #include "eeprom.h" 42*4882a593Smuzhiyun #include "wlan.h" 43*4882a593Smuzhiyun #include "hw.h" 44*4882a593Smuzhiyun #include "fwdesc.h" 45*4882a593Smuzhiyun #include "fwcmd.h" 46*4882a593Smuzhiyun #include "../regd.h" 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun struct hw_stat_reg_entry { 49*4882a593Smuzhiyun u32 reg; 50*4882a593Smuzhiyun char nreg[32]; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define STAT_MAC_REG(reg) \ 54*4882a593Smuzhiyun { (AR9170_MAC_REG_##reg), #reg } 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define STAT_PTA_REG(reg) \ 57*4882a593Smuzhiyun { (AR9170_PTA_REG_##reg), #reg } 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define STAT_USB_REG(reg) \ 60*4882a593Smuzhiyun { (AR9170_USB_REG_##reg), #reg } 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun static const struct hw_stat_reg_entry hw_rx_tally_regs[] = { 63*4882a593Smuzhiyun STAT_MAC_REG(RX_CRC32), STAT_MAC_REG(RX_CRC16), 64*4882a593Smuzhiyun STAT_MAC_REG(RX_TIMEOUT_COUNT), STAT_MAC_REG(RX_ERR_DECRYPTION_UNI), 65*4882a593Smuzhiyun STAT_MAC_REG(RX_ERR_DECRYPTION_MUL), STAT_MAC_REG(RX_MPDU), 66*4882a593Smuzhiyun STAT_MAC_REG(RX_DROPPED_MPDU), STAT_MAC_REG(RX_DEL_MPDU), 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun static const struct hw_stat_reg_entry hw_phy_errors_regs[] = { 70*4882a593Smuzhiyun STAT_MAC_REG(RX_PHY_MISC_ERROR), STAT_MAC_REG(RX_PHY_XR_ERROR), 71*4882a593Smuzhiyun STAT_MAC_REG(RX_PHY_OFDM_ERROR), STAT_MAC_REG(RX_PHY_CCK_ERROR), 72*4882a593Smuzhiyun STAT_MAC_REG(RX_PHY_HT_ERROR), STAT_MAC_REG(RX_PHY_TOTAL), 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun static const struct hw_stat_reg_entry hw_tx_tally_regs[] = { 76*4882a593Smuzhiyun STAT_MAC_REG(TX_TOTAL), STAT_MAC_REG(TX_UNDERRUN), 77*4882a593Smuzhiyun STAT_MAC_REG(TX_RETRY), 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun static const struct hw_stat_reg_entry hw_wlan_queue_regs[] = { 81*4882a593Smuzhiyun STAT_MAC_REG(DMA_STATUS), STAT_MAC_REG(DMA_TRIGGER), 82*4882a593Smuzhiyun STAT_MAC_REG(DMA_TXQ0_ADDR), STAT_MAC_REG(DMA_TXQ0_CURR_ADDR), 83*4882a593Smuzhiyun STAT_MAC_REG(DMA_TXQ1_ADDR), STAT_MAC_REG(DMA_TXQ1_CURR_ADDR), 84*4882a593Smuzhiyun STAT_MAC_REG(DMA_TXQ2_ADDR), STAT_MAC_REG(DMA_TXQ2_CURR_ADDR), 85*4882a593Smuzhiyun STAT_MAC_REG(DMA_TXQ3_ADDR), STAT_MAC_REG(DMA_TXQ3_CURR_ADDR), 86*4882a593Smuzhiyun STAT_MAC_REG(DMA_RXQ_ADDR), STAT_MAC_REG(DMA_RXQ_CURR_ADDR), 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun static const struct hw_stat_reg_entry hw_ampdu_info_regs[] = { 90*4882a593Smuzhiyun STAT_MAC_REG(AMPDU_DENSITY), STAT_MAC_REG(AMPDU_FACTOR), 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun static const struct hw_stat_reg_entry hw_pta_queue_regs[] = { 94*4882a593Smuzhiyun STAT_PTA_REG(DN_CURR_ADDRH), STAT_PTA_REG(DN_CURR_ADDRL), 95*4882a593Smuzhiyun STAT_PTA_REG(UP_CURR_ADDRH), STAT_PTA_REG(UP_CURR_ADDRL), 96*4882a593Smuzhiyun STAT_PTA_REG(DMA_STATUS), STAT_PTA_REG(DMA_MODE_CTRL), 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #define DEFINE_TALLY(name) \ 100*4882a593Smuzhiyun u32 name##_sum[ARRAY_SIZE(name##_regs)], \ 101*4882a593Smuzhiyun name##_counter[ARRAY_SIZE(name##_regs)] \ 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define DEFINE_STAT(name) \ 104*4882a593Smuzhiyun u32 name##_counter[ARRAY_SIZE(name##_regs)] \ 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun struct ath_stats { 107*4882a593Smuzhiyun DEFINE_TALLY(hw_tx_tally); 108*4882a593Smuzhiyun DEFINE_TALLY(hw_rx_tally); 109*4882a593Smuzhiyun DEFINE_TALLY(hw_phy_errors); 110*4882a593Smuzhiyun DEFINE_STAT(hw_wlan_queue); 111*4882a593Smuzhiyun DEFINE_STAT(hw_pta_queue); 112*4882a593Smuzhiyun DEFINE_STAT(hw_ampdu_info); 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun struct carl9170_debug_mem_rbe { 116*4882a593Smuzhiyun u32 reg; 117*4882a593Smuzhiyun u32 value; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #define CARL9170_DEBUG_RING_SIZE 64 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun struct carl9170_debug { 123*4882a593Smuzhiyun struct ath_stats stats; 124*4882a593Smuzhiyun struct carl9170_debug_mem_rbe ring[CARL9170_DEBUG_RING_SIZE]; 125*4882a593Smuzhiyun struct mutex ring_lock; 126*4882a593Smuzhiyun unsigned int ring_head, ring_tail; 127*4882a593Smuzhiyun struct delayed_work update_tally; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun struct ar9170; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun void carl9170_debugfs_register(struct ar9170 *ar); 133*4882a593Smuzhiyun void carl9170_debugfs_unregister(struct ar9170 *ar); 134*4882a593Smuzhiyun #endif /* __DEBUG_H */ 135