1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2015 Qualcomm Atheros Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission to use, copy, modify, and/or distribute this software for any 5*4882a593Smuzhiyun * purpose with or without fee is hereby granted, provided that the above 6*4882a593Smuzhiyun * copyright notice and this permission notice appear in all copies. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*4882a593Smuzhiyun * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*4882a593Smuzhiyun * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*4882a593Smuzhiyun * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*4882a593Smuzhiyun * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*4882a593Smuzhiyun * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*4882a593Smuzhiyun * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef REG_AIC_H 18*4882a593Smuzhiyun #define REG_AIC_H 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define AR_SM_BASE 0xa200 21*4882a593Smuzhiyun #define AR_SM1_BASE 0xb200 22*4882a593Smuzhiyun #define AR_AGC_BASE 0x9e00 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define AR_PHY_AIC_CTRL_0_B0 (AR_SM_BASE + 0x4b0) 25*4882a593Smuzhiyun #define AR_PHY_AIC_CTRL_1_B0 (AR_SM_BASE + 0x4b4) 26*4882a593Smuzhiyun #define AR_PHY_AIC_CTRL_2_B0 (AR_SM_BASE + 0x4b8) 27*4882a593Smuzhiyun #define AR_PHY_AIC_CTRL_3_B0 (AR_SM_BASE + 0x4bc) 28*4882a593Smuzhiyun #define AR_PHY_AIC_CTRL_4_B0 (AR_SM_BASE + 0x4c0) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define AR_PHY_AIC_STAT_0_B0 (AR_SM_BASE + 0x4c4) 31*4882a593Smuzhiyun #define AR_PHY_AIC_STAT_1_B0 (AR_SM_BASE + 0x4c8) 32*4882a593Smuzhiyun #define AR_PHY_AIC_STAT_2_B0 (AR_SM_BASE + 0x4cc) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define AR_PHY_AIC_CTRL_0_B1 (AR_SM1_BASE + 0x4b0) 35*4882a593Smuzhiyun #define AR_PHY_AIC_CTRL_1_B1 (AR_SM1_BASE + 0x4b4) 36*4882a593Smuzhiyun #define AR_PHY_AIC_CTRL_4_B1 (AR_SM1_BASE + 0x4c0) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define AR_PHY_AIC_STAT_0_B1 (AR_SM1_BASE + 0x4c4) 39*4882a593Smuzhiyun #define AR_PHY_AIC_STAT_1_B1 (AR_SM1_BASE + 0x4c8) 40*4882a593Smuzhiyun #define AR_PHY_AIC_STAT_2_B1 (AR_SM1_BASE + 0x4cc) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define AR_PHY_AIC_SRAM_ADDR_B0 (AR_SM_BASE + 0x5f0) 43*4882a593Smuzhiyun #define AR_PHY_AIC_SRAM_DATA_B0 (AR_SM_BASE + 0x5f4) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define AR_PHY_AIC_SRAM_ADDR_B1 (AR_SM1_BASE + 0x5f0) 46*4882a593Smuzhiyun #define AR_PHY_AIC_SRAM_DATA_B1 (AR_SM1_BASE + 0x5f4) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define AR_PHY_BT_COEX_4 (AR_AGC_BASE + 0x60) 49*4882a593Smuzhiyun #define AR_PHY_BT_COEX_5 (AR_AGC_BASE + 0x64) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* AIC fields */ 52*4882a593Smuzhiyun #define AR_PHY_AIC_MON_ENABLE 0x80000000 53*4882a593Smuzhiyun #define AR_PHY_AIC_MON_ENABLE_S 31 54*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_MAX_HOP_COUNT 0x7F000000 55*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_MAX_HOP_COUNT_S 24 56*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_MIN_VALID_COUNT 0x00FE0000 57*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_MIN_VALID_COUNT_S 17 58*4882a593Smuzhiyun #define AR_PHY_AIC_F_WLAN 0x0001FC00 59*4882a593Smuzhiyun #define AR_PHY_AIC_F_WLAN_S 10 60*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_CH_VALID_RESET 0x00000200 61*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_CH_VALID_RESET_S 9 62*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_ENABLE 0x00000100 63*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_ENABLE_S 8 64*4882a593Smuzhiyun #define AR_PHY_AIC_BTTX_PWR_THR 0x000000FE 65*4882a593Smuzhiyun #define AR_PHY_AIC_BTTX_PWR_THR_S 1 66*4882a593Smuzhiyun #define AR_PHY_AIC_ENABLE 0x00000001 67*4882a593Smuzhiyun #define AR_PHY_AIC_ENABLE_S 0 68*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_BT_REF_DELAY 0x00F00000 69*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_BT_REF_DELAY_S 20 70*4882a593Smuzhiyun #define AR_PHY_AIC_BT_IDLE_CFG 0x00080000 71*4882a593Smuzhiyun #define AR_PHY_AIC_BT_IDLE_CFG_S 19 72*4882a593Smuzhiyun #define AR_PHY_AIC_STDBY_COND 0x00060000 73*4882a593Smuzhiyun #define AR_PHY_AIC_STDBY_COND_S 17 74*4882a593Smuzhiyun #define AR_PHY_AIC_STDBY_ROT_ATT_DB 0x0001F800 75*4882a593Smuzhiyun #define AR_PHY_AIC_STDBY_ROT_ATT_DB_S 11 76*4882a593Smuzhiyun #define AR_PHY_AIC_STDBY_COM_ATT_DB 0x00000700 77*4882a593Smuzhiyun #define AR_PHY_AIC_STDBY_COM_ATT_DB_S 8 78*4882a593Smuzhiyun #define AR_PHY_AIC_RSSI_MAX 0x000000F0 79*4882a593Smuzhiyun #define AR_PHY_AIC_RSSI_MAX_S 4 80*4882a593Smuzhiyun #define AR_PHY_AIC_RSSI_MIN 0x0000000F 81*4882a593Smuzhiyun #define AR_PHY_AIC_RSSI_MIN_S 0 82*4882a593Smuzhiyun #define AR_PHY_AIC_RADIO_DELAY 0x7F000000 83*4882a593Smuzhiyun #define AR_PHY_AIC_RADIO_DELAY_S 24 84*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_STEP_SIZE_CORR 0x00F00000 85*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_STEP_SIZE_CORR_S 20 86*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_ROT_IDX_CORR 0x000F8000 87*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_ROT_IDX_CORR_S 15 88*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_CONV_CHECK_FACTOR 0x00006000 89*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_CONV_CHECK_FACTOR_S 13 90*4882a593Smuzhiyun #define AR_PHY_AIC_ROT_IDX_COUNT_MAX 0x00001C00 91*4882a593Smuzhiyun #define AR_PHY_AIC_ROT_IDX_COUNT_MAX_S 10 92*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_SYNTH_TOGGLE 0x00000200 93*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_SYNTH_TOGGLE_S 9 94*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_SYNTH_AFTER_BTRX 0x00000100 95*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_SYNTH_AFTER_BTRX_S 8 96*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_SYNTH_SETTLING 0x000000FF 97*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_SYNTH_SETTLING_S 0 98*4882a593Smuzhiyun #define AR_PHY_AIC_MON_MAX_HOP_COUNT 0x07F00000 99*4882a593Smuzhiyun #define AR_PHY_AIC_MON_MAX_HOP_COUNT_S 20 100*4882a593Smuzhiyun #define AR_PHY_AIC_MON_MIN_STALE_COUNT 0x000FE000 101*4882a593Smuzhiyun #define AR_PHY_AIC_MON_MIN_STALE_COUNT_S 13 102*4882a593Smuzhiyun #define AR_PHY_AIC_MON_PWR_EST_LONG 0x00001000 103*4882a593Smuzhiyun #define AR_PHY_AIC_MON_PWR_EST_LONG_S 12 104*4882a593Smuzhiyun #define AR_PHY_AIC_MON_PD_TALLY_SCALING 0x00000C00 105*4882a593Smuzhiyun #define AR_PHY_AIC_MON_PD_TALLY_SCALING_S 10 106*4882a593Smuzhiyun #define AR_PHY_AIC_MON_PERF_THR 0x000003E0 107*4882a593Smuzhiyun #define AR_PHY_AIC_MON_PERF_THR_S 5 108*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_TARGET_MAG_SETTING 0x00000018 109*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_TARGET_MAG_SETTING_S 3 110*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_PERF_CHECK_FACTOR 0x00000006 111*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_PERF_CHECK_FACTOR_S 1 112*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_PWR_EST_LONG 0x00000001 113*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_PWR_EST_LONG_S 0 114*4882a593Smuzhiyun #define AR_PHY_AIC_MON_DONE 0x80000000 115*4882a593Smuzhiyun #define AR_PHY_AIC_MON_DONE_S 31 116*4882a593Smuzhiyun #define AR_PHY_AIC_MON_ACTIVE 0x40000000 117*4882a593Smuzhiyun #define AR_PHY_AIC_MON_ACTIVE_S 30 118*4882a593Smuzhiyun #define AR_PHY_AIC_MEAS_COUNT 0x3F000000 119*4882a593Smuzhiyun #define AR_PHY_AIC_MEAS_COUNT_S 24 120*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_ANT_ISO_EST 0x00FC0000 121*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_ANT_ISO_EST_S 18 122*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_HOP_COUNT 0x0003F800 123*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_HOP_COUNT_S 11 124*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_VALID_COUNT 0x000007F0 125*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_VALID_COUNT_S 4 126*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_BT_TOO_WEAK_ERR 0x00000008 127*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_BT_TOO_WEAK_ERR_S 3 128*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_BT_TOO_STRONG_ERR 0x00000004 129*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_BT_TOO_STRONG_ERR_S 2 130*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_DONE 0x00000002 131*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_DONE_S 1 132*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_ACTIVE 0x00000001 133*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_ACTIVE_S 0 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #define AR_PHY_AIC_MEAS_MAG_MIN 0xFFC00000 136*4882a593Smuzhiyun #define AR_PHY_AIC_MEAS_MAG_MIN_S 22 137*4882a593Smuzhiyun #define AR_PHY_AIC_MON_STALE_COUNT 0x003F8000 138*4882a593Smuzhiyun #define AR_PHY_AIC_MON_STALE_COUNT_S 15 139*4882a593Smuzhiyun #define AR_PHY_AIC_MON_HOP_COUNT 0x00007F00 140*4882a593Smuzhiyun #define AR_PHY_AIC_MON_HOP_COUNT_S 8 141*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_AIC_SM 0x000000F8 142*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_AIC_SM_S 3 143*4882a593Smuzhiyun #define AR_PHY_AIC_SM 0x00000007 144*4882a593Smuzhiyun #define AR_PHY_AIC_SM_S 0 145*4882a593Smuzhiyun #define AR_PHY_AIC_SRAM_VALID 0x00000001 146*4882a593Smuzhiyun #define AR_PHY_AIC_SRAM_VALID_S 0 147*4882a593Smuzhiyun #define AR_PHY_AIC_SRAM_ROT_QUAD_ATT_DB 0x0000007E 148*4882a593Smuzhiyun #define AR_PHY_AIC_SRAM_ROT_QUAD_ATT_DB_S 1 149*4882a593Smuzhiyun #define AR_PHY_AIC_SRAM_VGA_QUAD_SIGN 0x00000080 150*4882a593Smuzhiyun #define AR_PHY_AIC_SRAM_VGA_QUAD_SIGN_S 7 151*4882a593Smuzhiyun #define AR_PHY_AIC_SRAM_ROT_DIR_ATT_DB 0x00003F00 152*4882a593Smuzhiyun #define AR_PHY_AIC_SRAM_ROT_DIR_ATT_DB_S 8 153*4882a593Smuzhiyun #define AR_PHY_AIC_SRAM_VGA_DIR_SIGN 0x00004000 154*4882a593Smuzhiyun #define AR_PHY_AIC_SRAM_VGA_DIR_SIGN_S 14 155*4882a593Smuzhiyun #define AR_PHY_AIC_SRAM_COM_ATT_6DB 0x00038000 156*4882a593Smuzhiyun #define AR_PHY_AIC_SRAM_COM_ATT_6DB_S 15 157*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_ROT_ATT_DB_EST_ISO 0x0000E000 158*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_ROT_ATT_DB_EST_ISO_S 13 159*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_COM_ATT_DB_EST_ISO 0x00001E00 160*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_COM_ATT_DB_EST_ISO_S 9 161*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_ISO_EST_INIT_SETTING 0x000001F8 162*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_ISO_EST_INIT_SETTING_S 3 163*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_COM_ATT_DB_BACKOFF 0x00000006 164*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_COM_ATT_DB_BACKOFF_S 1 165*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_COM_ATT_DB_FIXED 0x00000001 166*4882a593Smuzhiyun #define AR_PHY_AIC_CAL_COM_ATT_DB_FIXED_S 0 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun #endif /* REG_AIC_H */ 169