1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2008-2011 Atheros Communications Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission to use, copy, modify, and/or distribute this software for any 5*4882a593Smuzhiyun * purpose with or without fee is hereby granted, provided that the above 6*4882a593Smuzhiyun * copyright notice and this permission notice appear in all copies. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*4882a593Smuzhiyun * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*4882a593Smuzhiyun * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*4882a593Smuzhiyun * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*4882a593Smuzhiyun * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*4882a593Smuzhiyun * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*4882a593Smuzhiyun * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef PHY_H 18*4882a593Smuzhiyun #define PHY_H 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define CHANSEL_DIV 15 21*4882a593Smuzhiyun #define CHANSEL_2G(_freq) (((_freq) * 0x10000) / CHANSEL_DIV) 22*4882a593Smuzhiyun #define CHANSEL_5G(_freq) (((_freq) * 0x8000) / CHANSEL_DIV) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define AR_PHY_BASE 0x9800 25*4882a593Smuzhiyun #define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2)) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX 0x0007E000 28*4882a593Smuzhiyun #define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_S 13 29*4882a593Smuzhiyun #define AR_PHY_TX_GAIN_CLC 0x0000001E 30*4882a593Smuzhiyun #define AR_PHY_TX_GAIN_CLC_S 1 31*4882a593Smuzhiyun #define AR_PHY_TX_GAIN 0x0007F000 32*4882a593Smuzhiyun #define AR_PHY_TX_GAIN_S 12 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define AR_PHY_CLC_TBL1 0xa35c 35*4882a593Smuzhiyun #define AR_PHY_CLC_I0 0x07ff0000 36*4882a593Smuzhiyun #define AR_PHY_CLC_I0_S 16 37*4882a593Smuzhiyun #define AR_PHY_CLC_Q0 0x0000ffd0 38*4882a593Smuzhiyun #define AR_PHY_CLC_Q0_S 5 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define ANTSWAP_AB 0x0001 41*4882a593Smuzhiyun #define REDUCE_CHAIN_0 0x00000050 42*4882a593Smuzhiyun #define REDUCE_CHAIN_1 0x00000051 43*4882a593Smuzhiyun #define AR_PHY_CHIP_ID 0x9818 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000 46*4882a593Smuzhiyun #define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define AR_PHY_PLL_CONTROL 0x16180 49*4882a593Smuzhiyun #define AR_PHY_PLL_MODE 0x16184 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun enum ath9k_ant_div_comb_lna_conf { 52*4882a593Smuzhiyun ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2, 53*4882a593Smuzhiyun ATH_ANT_DIV_COMB_LNA2, 54*4882a593Smuzhiyun ATH_ANT_DIV_COMB_LNA1, 55*4882a593Smuzhiyun ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2, 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #endif 59