xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/ath/ath9k/common-init.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (c) 2008-2011 Atheros Communications Inc.
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Permission to use, copy, modify, and/or distribute this software for any
5*4882a593Smuzhiyun  * purpose with or without fee is hereby granted, provided that the above
6*4882a593Smuzhiyun  * copyright notice and this permission notice appear in all copies.
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9*4882a593Smuzhiyun  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10*4882a593Smuzhiyun  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11*4882a593Smuzhiyun  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12*4882a593Smuzhiyun  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13*4882a593Smuzhiyun  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14*4882a593Smuzhiyun  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15*4882a593Smuzhiyun  */
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun /* We use the hw_value as an index into our private channel structure */
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #include "common.h"
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #define CHAN2G(_freq, _idx)  { \
22*4882a593Smuzhiyun 	.band = NL80211_BAND_2GHZ, \
23*4882a593Smuzhiyun 	.center_freq = (_freq), \
24*4882a593Smuzhiyun 	.hw_value = (_idx), \
25*4882a593Smuzhiyun 	.max_power = 20, \
26*4882a593Smuzhiyun }
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #define CHAN5G(_freq, _idx) { \
29*4882a593Smuzhiyun 	.band = NL80211_BAND_5GHZ, \
30*4882a593Smuzhiyun 	.center_freq = (_freq), \
31*4882a593Smuzhiyun 	.hw_value = (_idx), \
32*4882a593Smuzhiyun 	.max_power = 20, \
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun /* Some 2 GHz radios are actually tunable on 2312-2732
36*4882a593Smuzhiyun  * on 5 MHz steps, we support the channels which we know
37*4882a593Smuzhiyun  * we have calibration data for all cards though to make
38*4882a593Smuzhiyun  * this static */
39*4882a593Smuzhiyun static const struct ieee80211_channel ath9k_2ghz_chantable[] = {
40*4882a593Smuzhiyun 	CHAN2G(2412, 0), /* Channel 1 */
41*4882a593Smuzhiyun 	CHAN2G(2417, 1), /* Channel 2 */
42*4882a593Smuzhiyun 	CHAN2G(2422, 2), /* Channel 3 */
43*4882a593Smuzhiyun 	CHAN2G(2427, 3), /* Channel 4 */
44*4882a593Smuzhiyun 	CHAN2G(2432, 4), /* Channel 5 */
45*4882a593Smuzhiyun 	CHAN2G(2437, 5), /* Channel 6 */
46*4882a593Smuzhiyun 	CHAN2G(2442, 6), /* Channel 7 */
47*4882a593Smuzhiyun 	CHAN2G(2447, 7), /* Channel 8 */
48*4882a593Smuzhiyun 	CHAN2G(2452, 8), /* Channel 9 */
49*4882a593Smuzhiyun 	CHAN2G(2457, 9), /* Channel 10 */
50*4882a593Smuzhiyun 	CHAN2G(2462, 10), /* Channel 11 */
51*4882a593Smuzhiyun 	CHAN2G(2467, 11), /* Channel 12 */
52*4882a593Smuzhiyun 	CHAN2G(2472, 12), /* Channel 13 */
53*4882a593Smuzhiyun 	CHAN2G(2484, 13), /* Channel 14 */
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun /* Some 5 GHz radios are actually tunable on XXXX-YYYY
57*4882a593Smuzhiyun  * on 5 MHz steps, we support the channels which we know
58*4882a593Smuzhiyun  * we have calibration data for all cards though to make
59*4882a593Smuzhiyun  * this static */
60*4882a593Smuzhiyun static const struct ieee80211_channel ath9k_5ghz_chantable[] = {
61*4882a593Smuzhiyun 	/* _We_ call this UNII 1 */
62*4882a593Smuzhiyun 	CHAN5G(5180, 14), /* Channel 36 */
63*4882a593Smuzhiyun 	CHAN5G(5200, 15), /* Channel 40 */
64*4882a593Smuzhiyun 	CHAN5G(5220, 16), /* Channel 44 */
65*4882a593Smuzhiyun 	CHAN5G(5240, 17), /* Channel 48 */
66*4882a593Smuzhiyun 	/* _We_ call this UNII 2 */
67*4882a593Smuzhiyun 	CHAN5G(5260, 18), /* Channel 52 */
68*4882a593Smuzhiyun 	CHAN5G(5280, 19), /* Channel 56 */
69*4882a593Smuzhiyun 	CHAN5G(5300, 20), /* Channel 60 */
70*4882a593Smuzhiyun 	CHAN5G(5320, 21), /* Channel 64 */
71*4882a593Smuzhiyun 	/* _We_ call this "Middle band" */
72*4882a593Smuzhiyun 	CHAN5G(5500, 22), /* Channel 100 */
73*4882a593Smuzhiyun 	CHAN5G(5520, 23), /* Channel 104 */
74*4882a593Smuzhiyun 	CHAN5G(5540, 24), /* Channel 108 */
75*4882a593Smuzhiyun 	CHAN5G(5560, 25), /* Channel 112 */
76*4882a593Smuzhiyun 	CHAN5G(5580, 26), /* Channel 116 */
77*4882a593Smuzhiyun 	CHAN5G(5600, 27), /* Channel 120 */
78*4882a593Smuzhiyun 	CHAN5G(5620, 28), /* Channel 124 */
79*4882a593Smuzhiyun 	CHAN5G(5640, 29), /* Channel 128 */
80*4882a593Smuzhiyun 	CHAN5G(5660, 30), /* Channel 132 */
81*4882a593Smuzhiyun 	CHAN5G(5680, 31), /* Channel 136 */
82*4882a593Smuzhiyun 	CHAN5G(5700, 32), /* Channel 140 */
83*4882a593Smuzhiyun 	/* _We_ call this UNII 3 */
84*4882a593Smuzhiyun 	CHAN5G(5745, 33), /* Channel 149 */
85*4882a593Smuzhiyun 	CHAN5G(5765, 34), /* Channel 153 */
86*4882a593Smuzhiyun 	CHAN5G(5785, 35), /* Channel 157 */
87*4882a593Smuzhiyun 	CHAN5G(5805, 36), /* Channel 161 */
88*4882a593Smuzhiyun 	CHAN5G(5825, 37), /* Channel 165 */
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun /* Atheros hardware rate code addition for short preamble */
92*4882a593Smuzhiyun #define SHPCHECK(__hw_rate, __flags) \
93*4882a593Smuzhiyun 	((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0)
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun #define RATE(_bitrate, _hw_rate, _flags) {              \
96*4882a593Smuzhiyun 	.bitrate        = (_bitrate),                   \
97*4882a593Smuzhiyun 	.flags          = (_flags),                     \
98*4882a593Smuzhiyun 	.hw_value       = (_hw_rate),                   \
99*4882a593Smuzhiyun 	.hw_value_short = (SHPCHECK(_hw_rate, _flags))  \
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun static struct ieee80211_rate ath9k_legacy_rates[] = {
103*4882a593Smuzhiyun 	RATE(10, 0x1b, 0),
104*4882a593Smuzhiyun 	RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE),
105*4882a593Smuzhiyun 	RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE),
106*4882a593Smuzhiyun 	RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE),
107*4882a593Smuzhiyun 	RATE(60, 0x0b, (IEEE80211_RATE_SUPPORTS_5MHZ |
108*4882a593Smuzhiyun 			IEEE80211_RATE_SUPPORTS_10MHZ)),
109*4882a593Smuzhiyun 	RATE(90, 0x0f, (IEEE80211_RATE_SUPPORTS_5MHZ |
110*4882a593Smuzhiyun 			IEEE80211_RATE_SUPPORTS_10MHZ)),
111*4882a593Smuzhiyun 	RATE(120, 0x0a, (IEEE80211_RATE_SUPPORTS_5MHZ |
112*4882a593Smuzhiyun 			 IEEE80211_RATE_SUPPORTS_10MHZ)),
113*4882a593Smuzhiyun 	RATE(180, 0x0e, (IEEE80211_RATE_SUPPORTS_5MHZ |
114*4882a593Smuzhiyun 			 IEEE80211_RATE_SUPPORTS_10MHZ)),
115*4882a593Smuzhiyun 	RATE(240, 0x09, (IEEE80211_RATE_SUPPORTS_5MHZ |
116*4882a593Smuzhiyun 			 IEEE80211_RATE_SUPPORTS_10MHZ)),
117*4882a593Smuzhiyun 	RATE(360, 0x0d, (IEEE80211_RATE_SUPPORTS_5MHZ |
118*4882a593Smuzhiyun 			 IEEE80211_RATE_SUPPORTS_10MHZ)),
119*4882a593Smuzhiyun 	RATE(480, 0x08, (IEEE80211_RATE_SUPPORTS_5MHZ |
120*4882a593Smuzhiyun 			 IEEE80211_RATE_SUPPORTS_10MHZ)),
121*4882a593Smuzhiyun 	RATE(540, 0x0c, (IEEE80211_RATE_SUPPORTS_5MHZ |
122*4882a593Smuzhiyun 			 IEEE80211_RATE_SUPPORTS_10MHZ)),
123*4882a593Smuzhiyun };
124*4882a593Smuzhiyun 
ath9k_cmn_init_channels_rates(struct ath_common * common)125*4882a593Smuzhiyun int ath9k_cmn_init_channels_rates(struct ath_common *common)
126*4882a593Smuzhiyun {
127*4882a593Smuzhiyun 	struct ath_hw *ah = (struct ath_hw *)common->ah;
128*4882a593Smuzhiyun 	void *channels;
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) +
131*4882a593Smuzhiyun 		     ARRAY_SIZE(ath9k_5ghz_chantable) !=
132*4882a593Smuzhiyun 		     ATH9K_NUM_CHANNELS);
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
135*4882a593Smuzhiyun 		channels = devm_kzalloc(ah->dev,
136*4882a593Smuzhiyun 			sizeof(ath9k_2ghz_chantable), GFP_KERNEL);
137*4882a593Smuzhiyun 		if (!channels)
138*4882a593Smuzhiyun 		    return -ENOMEM;
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 		memcpy(channels, ath9k_2ghz_chantable,
141*4882a593Smuzhiyun 		       sizeof(ath9k_2ghz_chantable));
142*4882a593Smuzhiyun 		common->sbands[NL80211_BAND_2GHZ].channels = channels;
143*4882a593Smuzhiyun 		common->sbands[NL80211_BAND_2GHZ].band = NL80211_BAND_2GHZ;
144*4882a593Smuzhiyun 		common->sbands[NL80211_BAND_2GHZ].n_channels =
145*4882a593Smuzhiyun 			ARRAY_SIZE(ath9k_2ghz_chantable);
146*4882a593Smuzhiyun 		common->sbands[NL80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
147*4882a593Smuzhiyun 		common->sbands[NL80211_BAND_2GHZ].n_bitrates =
148*4882a593Smuzhiyun 			ARRAY_SIZE(ath9k_legacy_rates);
149*4882a593Smuzhiyun 	}
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
152*4882a593Smuzhiyun 		channels = devm_kzalloc(ah->dev,
153*4882a593Smuzhiyun 			sizeof(ath9k_5ghz_chantable), GFP_KERNEL);
154*4882a593Smuzhiyun 		if (!channels)
155*4882a593Smuzhiyun 			return -ENOMEM;
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 		memcpy(channels, ath9k_5ghz_chantable,
158*4882a593Smuzhiyun 		       sizeof(ath9k_5ghz_chantable));
159*4882a593Smuzhiyun 		common->sbands[NL80211_BAND_5GHZ].channels = channels;
160*4882a593Smuzhiyun 		common->sbands[NL80211_BAND_5GHZ].band = NL80211_BAND_5GHZ;
161*4882a593Smuzhiyun 		common->sbands[NL80211_BAND_5GHZ].n_channels =
162*4882a593Smuzhiyun 			ARRAY_SIZE(ath9k_5ghz_chantable);
163*4882a593Smuzhiyun 		common->sbands[NL80211_BAND_5GHZ].bitrates =
164*4882a593Smuzhiyun 			ath9k_legacy_rates + 4;
165*4882a593Smuzhiyun 		common->sbands[NL80211_BAND_5GHZ].n_bitrates =
166*4882a593Smuzhiyun 			ARRAY_SIZE(ath9k_legacy_rates) - 4;
167*4882a593Smuzhiyun 	}
168*4882a593Smuzhiyun 	return 0;
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun EXPORT_SYMBOL(ath9k_cmn_init_channels_rates);
171*4882a593Smuzhiyun 
ath9k_cmn_setup_ht_cap(struct ath_hw * ah,struct ieee80211_sta_ht_cap * ht_info)172*4882a593Smuzhiyun void ath9k_cmn_setup_ht_cap(struct ath_hw *ah,
173*4882a593Smuzhiyun 			    struct ieee80211_sta_ht_cap *ht_info)
174*4882a593Smuzhiyun {
175*4882a593Smuzhiyun 	struct ath_common *common = ath9k_hw_common(ah);
176*4882a593Smuzhiyun 	u8 tx_streams, rx_streams;
177*4882a593Smuzhiyun 	int i, max_streams;
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 	ht_info->ht_supported = true;
180*4882a593Smuzhiyun 	ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
181*4882a593Smuzhiyun 		       IEEE80211_HT_CAP_SM_PS |
182*4882a593Smuzhiyun 		       IEEE80211_HT_CAP_SGI_40 |
183*4882a593Smuzhiyun 		       IEEE80211_HT_CAP_DSSSCCK40;
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	if (ah->caps.hw_caps & ATH9K_HW_CAP_LDPC)
186*4882a593Smuzhiyun 		ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING;
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 	if (ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
189*4882a593Smuzhiyun 		ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
192*4882a593Smuzhiyun 	ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 	if (AR_SREV_9271(ah) || AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah))
195*4882a593Smuzhiyun 		max_streams = 1;
196*4882a593Smuzhiyun 	else if (AR_SREV_9462(ah))
197*4882a593Smuzhiyun 		max_streams = 2;
198*4882a593Smuzhiyun 	else if (AR_SREV_9300_20_OR_LATER(ah))
199*4882a593Smuzhiyun 		max_streams = 3;
200*4882a593Smuzhiyun 	else
201*4882a593Smuzhiyun 		max_streams = 2;
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	if (AR_SREV_9280_20_OR_LATER(ah)) {
204*4882a593Smuzhiyun 		if (max_streams >= 2)
205*4882a593Smuzhiyun 			ht_info->cap |= IEEE80211_HT_CAP_TX_STBC;
206*4882a593Smuzhiyun 		ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
207*4882a593Smuzhiyun 	}
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun 	/* set up supported mcs set */
210*4882a593Smuzhiyun 	memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
211*4882a593Smuzhiyun 	tx_streams = ath9k_cmn_count_streams(ah->txchainmask, max_streams);
212*4882a593Smuzhiyun 	rx_streams = ath9k_cmn_count_streams(ah->rxchainmask, max_streams);
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 	ath_dbg(common, CONFIG, "TX streams %d, RX streams: %d\n",
215*4882a593Smuzhiyun 		tx_streams, rx_streams);
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun 	if (tx_streams != rx_streams) {
218*4882a593Smuzhiyun 		ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
219*4882a593Smuzhiyun 		ht_info->mcs.tx_params |= ((tx_streams - 1) <<
220*4882a593Smuzhiyun 				IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
221*4882a593Smuzhiyun 	}
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	for (i = 0; i < rx_streams; i++)
224*4882a593Smuzhiyun 		ht_info->mcs.rx_mask[i] = 0xff;
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 	ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
227*4882a593Smuzhiyun }
228*4882a593Smuzhiyun EXPORT_SYMBOL(ath9k_cmn_setup_ht_cap);
229*4882a593Smuzhiyun 
ath9k_cmn_reload_chainmask(struct ath_hw * ah)230*4882a593Smuzhiyun void ath9k_cmn_reload_chainmask(struct ath_hw *ah)
231*4882a593Smuzhiyun {
232*4882a593Smuzhiyun 	struct ath_common *common = ath9k_hw_common(ah);
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 	if (!(ah->caps.hw_caps & ATH9K_HW_CAP_HT))
235*4882a593Smuzhiyun 		return;
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun 	if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
238*4882a593Smuzhiyun 		ath9k_cmn_setup_ht_cap(ah,
239*4882a593Smuzhiyun 			&common->sbands[NL80211_BAND_2GHZ].ht_cap);
240*4882a593Smuzhiyun 	if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
241*4882a593Smuzhiyun 		ath9k_cmn_setup_ht_cap(ah,
242*4882a593Smuzhiyun 			&common->sbands[NL80211_BAND_5GHZ].ht_cap);
243*4882a593Smuzhiyun }
244*4882a593Smuzhiyun EXPORT_SYMBOL(ath9k_cmn_reload_chainmask);
245