1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2009-2011 Atheros Communications Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Permission to use, copy, modify, and/or distribute this software for any
5*4882a593Smuzhiyun * purpose with or without fee is hereby granted, provided that the above
6*4882a593Smuzhiyun * copyright notice and this permission notice appear in all copies.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9*4882a593Smuzhiyun * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10*4882a593Smuzhiyun * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11*4882a593Smuzhiyun * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12*4882a593Smuzhiyun * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13*4882a593Smuzhiyun * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14*4882a593Smuzhiyun * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15*4882a593Smuzhiyun */
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <linux/export.h>
18*4882a593Smuzhiyun #include <linux/types.h>
19*4882a593Smuzhiyun #include <linux/ath9k_platform.h>
20*4882a593Smuzhiyun #include "hw.h"
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun enum ath_bt_mode {
23*4882a593Smuzhiyun ATH_BT_COEX_MODE_LEGACY, /* legacy rx_clear mode */
24*4882a593Smuzhiyun ATH_BT_COEX_MODE_UNSLOTTED, /* untimed/unslotted mode */
25*4882a593Smuzhiyun ATH_BT_COEX_MODE_SLOTTED, /* slotted mode */
26*4882a593Smuzhiyun ATH_BT_COEX_MODE_DISABLED, /* coexistence disabled */
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun struct ath_btcoex_config {
30*4882a593Smuzhiyun u8 bt_time_extend;
31*4882a593Smuzhiyun bool bt_txstate_extend;
32*4882a593Smuzhiyun bool bt_txframe_extend;
33*4882a593Smuzhiyun enum ath_bt_mode bt_mode; /* coexistence mode */
34*4882a593Smuzhiyun bool bt_quiet_collision;
35*4882a593Smuzhiyun bool bt_rxclear_polarity; /* invert rx_clear as WLAN_ACTIVE*/
36*4882a593Smuzhiyun u8 bt_priority_time;
37*4882a593Smuzhiyun u8 bt_first_slot_time;
38*4882a593Smuzhiyun bool bt_hold_rx_clear;
39*4882a593Smuzhiyun u8 wl_active_time;
40*4882a593Smuzhiyun u8 wl_qc_time;
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun static const u32 ar9003_wlan_weights[ATH_BTCOEX_STOMP_MAX]
44*4882a593Smuzhiyun [AR9300_NUM_WLAN_WEIGHTS] = {
45*4882a593Smuzhiyun { 0xfffffff0, 0xfffffff0, 0xfffffff0, 0xfffffff0 }, /* STOMP_ALL */
46*4882a593Smuzhiyun { 0x88888880, 0x88888880, 0x88888880, 0x88888880 }, /* STOMP_LOW */
47*4882a593Smuzhiyun { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* STOMP_NONE */
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun static const u32 mci_wlan_weights[ATH_BTCOEX_STOMP_MAX]
51*4882a593Smuzhiyun [AR9300_NUM_WLAN_WEIGHTS] = {
52*4882a593Smuzhiyun { 0x01017d01, 0x41414101, 0x41414101, 0x41414141 }, /* STOMP_ALL */
53*4882a593Smuzhiyun { 0x01017d01, 0x3b3b3b01, 0x3b3b3b01, 0x3b3b3b3b }, /* STOMP_LOW */
54*4882a593Smuzhiyun { 0x01017d01, 0x01010101, 0x01010101, 0x01010101 }, /* STOMP_NONE */
55*4882a593Smuzhiyun { 0x01017d01, 0x013b0101, 0x3b3b0101, 0x3b3b013b }, /* STOMP_LOW_FTP */
56*4882a593Smuzhiyun { 0xffffff01, 0xffffffff, 0xffffff01, 0xffffffff }, /* STOMP_AUDIO */
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun
ath9k_hw_init_btcoex_hw(struct ath_hw * ah,int qnum)59*4882a593Smuzhiyun void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
62*4882a593Smuzhiyun const struct ath_btcoex_config ath_bt_config = {
63*4882a593Smuzhiyun .bt_time_extend = 0,
64*4882a593Smuzhiyun .bt_txstate_extend = true,
65*4882a593Smuzhiyun .bt_txframe_extend = true,
66*4882a593Smuzhiyun .bt_mode = ATH_BT_COEX_MODE_SLOTTED,
67*4882a593Smuzhiyun .bt_quiet_collision = true,
68*4882a593Smuzhiyun .bt_rxclear_polarity = true,
69*4882a593Smuzhiyun .bt_priority_time = 2,
70*4882a593Smuzhiyun .bt_first_slot_time = 5,
71*4882a593Smuzhiyun .bt_hold_rx_clear = true,
72*4882a593Smuzhiyun .wl_active_time = 0x20,
73*4882a593Smuzhiyun .wl_qc_time = 0x20,
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun bool rxclear_polarity = ath_bt_config.bt_rxclear_polarity;
76*4882a593Smuzhiyun u8 time_extend = ath_bt_config.bt_time_extend;
77*4882a593Smuzhiyun u8 first_slot_time = ath_bt_config.bt_first_slot_time;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun if (AR_SREV_9300_20_OR_LATER(ah))
80*4882a593Smuzhiyun rxclear_polarity = !ath_bt_config.bt_rxclear_polarity;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun if (AR_SREV_SOC(ah)) {
83*4882a593Smuzhiyun first_slot_time = 0x1d;
84*4882a593Smuzhiyun time_extend = 0xa;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun btcoex_hw->bt_coex_mode3 =
87*4882a593Smuzhiyun SM(ath_bt_config.wl_active_time, AR_BT_WL_ACTIVE_TIME) |
88*4882a593Smuzhiyun SM(ath_bt_config.wl_qc_time, AR_BT_WL_QC_TIME);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun btcoex_hw->bt_coex_mode2 =
91*4882a593Smuzhiyun AR_BT_PROTECT_BT_AFTER_WAKEUP |
92*4882a593Smuzhiyun AR_BT_PHY_ERR_BT_COLL_ENABLE;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun btcoex_hw->bt_coex_mode =
96*4882a593Smuzhiyun (btcoex_hw->bt_coex_mode & AR_BT_QCU_THRESH) |
97*4882a593Smuzhiyun SM(time_extend, AR_BT_TIME_EXTEND) |
98*4882a593Smuzhiyun SM(ath_bt_config.bt_txstate_extend, AR_BT_TXSTATE_EXTEND) |
99*4882a593Smuzhiyun SM(ath_bt_config.bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) |
100*4882a593Smuzhiyun SM(ath_bt_config.bt_mode, AR_BT_MODE) |
101*4882a593Smuzhiyun SM(ath_bt_config.bt_quiet_collision, AR_BT_QUIET) |
102*4882a593Smuzhiyun SM(rxclear_polarity, AR_BT_RX_CLEAR_POLARITY) |
103*4882a593Smuzhiyun SM(ath_bt_config.bt_priority_time, AR_BT_PRIORITY_TIME) |
104*4882a593Smuzhiyun SM(first_slot_time, AR_BT_FIRST_SLOT_TIME) |
105*4882a593Smuzhiyun SM(qnum, AR_BT_QCU_THRESH);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun btcoex_hw->bt_coex_mode2 |=
108*4882a593Smuzhiyun SM(ath_bt_config.bt_hold_rx_clear, AR_BT_HOLD_RX_CLEAR) |
109*4882a593Smuzhiyun SM(ATH_BTCOEX_BMISS_THRESH, AR_BT_BCN_MISS_THRESH) |
110*4882a593Smuzhiyun AR_BT_DISABLE_BT_ANT;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun EXPORT_SYMBOL(ath9k_hw_init_btcoex_hw);
113*4882a593Smuzhiyun
ath9k_hw_btcoex_pin_init(struct ath_hw * ah,u8 wlanactive_gpio,u8 btactive_gpio,u8 btpriority_gpio)114*4882a593Smuzhiyun static void ath9k_hw_btcoex_pin_init(struct ath_hw *ah, u8 wlanactive_gpio,
115*4882a593Smuzhiyun u8 btactive_gpio, u8 btpriority_gpio)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
118*4882a593Smuzhiyun struct ath9k_platform_data *pdata = ah->dev->platform_data;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun if (btcoex_hw->scheme != ATH_BTCOEX_CFG_2WIRE &&
121*4882a593Smuzhiyun btcoex_hw->scheme != ATH_BTCOEX_CFG_3WIRE)
122*4882a593Smuzhiyun return;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun /* bt priority GPIO will be ignored by 2 wire scheme */
125*4882a593Smuzhiyun if (pdata && (pdata->bt_active_pin || pdata->bt_priority_pin ||
126*4882a593Smuzhiyun pdata->wlan_active_pin)) {
127*4882a593Smuzhiyun btcoex_hw->btactive_gpio = pdata->bt_active_pin;
128*4882a593Smuzhiyun btcoex_hw->wlanactive_gpio = pdata->wlan_active_pin;
129*4882a593Smuzhiyun btcoex_hw->btpriority_gpio = pdata->bt_priority_pin;
130*4882a593Smuzhiyun } else {
131*4882a593Smuzhiyun btcoex_hw->btactive_gpio = btactive_gpio;
132*4882a593Smuzhiyun btcoex_hw->wlanactive_gpio = wlanactive_gpio;
133*4882a593Smuzhiyun btcoex_hw->btpriority_gpio = btpriority_gpio;
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun
ath9k_hw_btcoex_init_scheme(struct ath_hw * ah)137*4882a593Smuzhiyun void ath9k_hw_btcoex_init_scheme(struct ath_hw *ah)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun struct ath_common *common = ath9k_hw_common(ah);
140*4882a593Smuzhiyun struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun /*
143*4882a593Smuzhiyun * Check if BTCOEX is globally disabled.
144*4882a593Smuzhiyun */
145*4882a593Smuzhiyun if (!common->btcoex_enabled) {
146*4882a593Smuzhiyun btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
147*4882a593Smuzhiyun return;
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) {
151*4882a593Smuzhiyun btcoex_hw->scheme = ATH_BTCOEX_CFG_MCI;
152*4882a593Smuzhiyun } else if (AR_SREV_9300_20_OR_LATER(ah)) {
153*4882a593Smuzhiyun btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun ath9k_hw_btcoex_pin_init(ah, ATH_WLANACTIVE_GPIO_9300,
156*4882a593Smuzhiyun ATH_BTACTIVE_GPIO_9300,
157*4882a593Smuzhiyun ATH_BTPRIORITY_GPIO_9300);
158*4882a593Smuzhiyun } else if (AR_SREV_9280_20_OR_LATER(ah)) {
159*4882a593Smuzhiyun if (AR_SREV_9285(ah))
160*4882a593Smuzhiyun btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
161*4882a593Smuzhiyun else
162*4882a593Smuzhiyun btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun ath9k_hw_btcoex_pin_init(ah, ATH_WLANACTIVE_GPIO_9280,
165*4882a593Smuzhiyun ATH_BTACTIVE_GPIO_9280,
166*4882a593Smuzhiyun ATH_BTPRIORITY_GPIO_9285);
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun EXPORT_SYMBOL(ath9k_hw_btcoex_init_scheme);
170*4882a593Smuzhiyun
ath9k_hw_btcoex_init_2wire(struct ath_hw * ah)171*4882a593Smuzhiyun void ath9k_hw_btcoex_init_2wire(struct ath_hw *ah)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun /* connect bt_active to baseband */
176*4882a593Smuzhiyun REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
177*4882a593Smuzhiyun (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
178*4882a593Smuzhiyun AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
181*4882a593Smuzhiyun AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun /* Set input mux for bt_active to gpio pin */
184*4882a593Smuzhiyun if (!AR_SREV_SOC(ah))
185*4882a593Smuzhiyun REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
186*4882a593Smuzhiyun AR_GPIO_INPUT_MUX1_BT_ACTIVE,
187*4882a593Smuzhiyun btcoex_hw->btactive_gpio);
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun /* Configure the desired gpio port for input */
190*4882a593Smuzhiyun ath9k_hw_gpio_request_in(ah, btcoex_hw->btactive_gpio,
191*4882a593Smuzhiyun "ath9k-btactive");
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun EXPORT_SYMBOL(ath9k_hw_btcoex_init_2wire);
194*4882a593Smuzhiyun
ath9k_hw_btcoex_init_3wire(struct ath_hw * ah)195*4882a593Smuzhiyun void ath9k_hw_btcoex_init_3wire(struct ath_hw *ah)
196*4882a593Smuzhiyun {
197*4882a593Smuzhiyun struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun /* btcoex 3-wire */
200*4882a593Smuzhiyun REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
201*4882a593Smuzhiyun (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB |
202*4882a593Smuzhiyun AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB));
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun /* Set input mux for bt_prority_async and
205*4882a593Smuzhiyun * bt_active_async to GPIO pins */
206*4882a593Smuzhiyun if (!AR_SREV_SOC(ah)) {
207*4882a593Smuzhiyun REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
208*4882a593Smuzhiyun AR_GPIO_INPUT_MUX1_BT_ACTIVE,
209*4882a593Smuzhiyun btcoex_hw->btactive_gpio);
210*4882a593Smuzhiyun REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
211*4882a593Smuzhiyun AR_GPIO_INPUT_MUX1_BT_PRIORITY,
212*4882a593Smuzhiyun btcoex_hw->btpriority_gpio);
213*4882a593Smuzhiyun }
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun /* Configure the desired GPIO ports for input */
216*4882a593Smuzhiyun ath9k_hw_gpio_request_in(ah, btcoex_hw->btactive_gpio,
217*4882a593Smuzhiyun "ath9k-btactive");
218*4882a593Smuzhiyun ath9k_hw_gpio_request_in(ah, btcoex_hw->btpriority_gpio,
219*4882a593Smuzhiyun "ath9k-btpriority");
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun EXPORT_SYMBOL(ath9k_hw_btcoex_init_3wire);
222*4882a593Smuzhiyun
ath9k_hw_btcoex_deinit(struct ath_hw * ah)223*4882a593Smuzhiyun void ath9k_hw_btcoex_deinit(struct ath_hw *ah)
224*4882a593Smuzhiyun {
225*4882a593Smuzhiyun struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun ath9k_hw_gpio_free(ah, btcoex_hw->btactive_gpio);
228*4882a593Smuzhiyun ath9k_hw_gpio_free(ah, btcoex_hw->btpriority_gpio);
229*4882a593Smuzhiyun ath9k_hw_gpio_free(ah, btcoex_hw->wlanactive_gpio);
230*4882a593Smuzhiyun }
231*4882a593Smuzhiyun EXPORT_SYMBOL(ath9k_hw_btcoex_deinit);
232*4882a593Smuzhiyun
ath9k_hw_btcoex_init_mci(struct ath_hw * ah)233*4882a593Smuzhiyun void ath9k_hw_btcoex_init_mci(struct ath_hw *ah)
234*4882a593Smuzhiyun {
235*4882a593Smuzhiyun ah->btcoex_hw.mci.ready = false;
236*4882a593Smuzhiyun ah->btcoex_hw.mci.bt_state = 0;
237*4882a593Smuzhiyun ah->btcoex_hw.mci.bt_ver_major = 3;
238*4882a593Smuzhiyun ah->btcoex_hw.mci.bt_ver_minor = 0;
239*4882a593Smuzhiyun ah->btcoex_hw.mci.bt_version_known = false;
240*4882a593Smuzhiyun ah->btcoex_hw.mci.update_2g5g = true;
241*4882a593Smuzhiyun ah->btcoex_hw.mci.is_2g = true;
242*4882a593Smuzhiyun ah->btcoex_hw.mci.wlan_channels_update = false;
243*4882a593Smuzhiyun ah->btcoex_hw.mci.wlan_channels[0] = 0x00000000;
244*4882a593Smuzhiyun ah->btcoex_hw.mci.wlan_channels[1] = 0xffffffff;
245*4882a593Smuzhiyun ah->btcoex_hw.mci.wlan_channels[2] = 0xffffffff;
246*4882a593Smuzhiyun ah->btcoex_hw.mci.wlan_channels[3] = 0x7fffffff;
247*4882a593Smuzhiyun ah->btcoex_hw.mci.query_bt = true;
248*4882a593Smuzhiyun ah->btcoex_hw.mci.unhalt_bt_gpm = true;
249*4882a593Smuzhiyun ah->btcoex_hw.mci.halted_bt_gpm = false;
250*4882a593Smuzhiyun ah->btcoex_hw.mci.need_flush_btinfo = false;
251*4882a593Smuzhiyun ah->btcoex_hw.mci.wlan_cal_seq = 0;
252*4882a593Smuzhiyun ah->btcoex_hw.mci.wlan_cal_done = 0;
253*4882a593Smuzhiyun ah->btcoex_hw.mci.config = (AR_SREV_9462(ah)) ? 0x2201 : 0xa4c1;
254*4882a593Smuzhiyun }
255*4882a593Smuzhiyun EXPORT_SYMBOL(ath9k_hw_btcoex_init_mci);
256*4882a593Smuzhiyun
ath9k_hw_btcoex_enable_2wire(struct ath_hw * ah)257*4882a593Smuzhiyun static void ath9k_hw_btcoex_enable_2wire(struct ath_hw *ah)
258*4882a593Smuzhiyun {
259*4882a593Smuzhiyun struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun /* Configure the desired GPIO port for TX_FRAME output */
262*4882a593Smuzhiyun ath9k_hw_gpio_request_out(ah, btcoex_hw->wlanactive_gpio,
263*4882a593Smuzhiyun "ath9k-wlanactive",
264*4882a593Smuzhiyun AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun /*
268*4882a593Smuzhiyun * For AR9002, bt_weight/wlan_weight are used.
269*4882a593Smuzhiyun * For AR9003 and above, stomp_type is used.
270*4882a593Smuzhiyun */
ath9k_hw_btcoex_set_weight(struct ath_hw * ah,u32 bt_weight,u32 wlan_weight,enum ath_stomp_type stomp_type)271*4882a593Smuzhiyun void ath9k_hw_btcoex_set_weight(struct ath_hw *ah,
272*4882a593Smuzhiyun u32 bt_weight,
273*4882a593Smuzhiyun u32 wlan_weight,
274*4882a593Smuzhiyun enum ath_stomp_type stomp_type)
275*4882a593Smuzhiyun {
276*4882a593Smuzhiyun struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
277*4882a593Smuzhiyun struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
278*4882a593Smuzhiyun u8 txprio_shift[] = { 24, 16, 16, 0 }; /* tx priority weight */
279*4882a593Smuzhiyun bool concur_tx = (mci_hw->concur_tx && btcoex_hw->tx_prio[stomp_type]);
280*4882a593Smuzhiyun const u32 *weight = ar9003_wlan_weights[stomp_type];
281*4882a593Smuzhiyun int i;
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun if (!AR_SREV_9300_20_OR_LATER(ah)) {
284*4882a593Smuzhiyun btcoex_hw->bt_coex_weights =
285*4882a593Smuzhiyun SM(bt_weight, AR_BTCOEX_BT_WGHT) |
286*4882a593Smuzhiyun SM(wlan_weight, AR_BTCOEX_WL_WGHT);
287*4882a593Smuzhiyun return;
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
291*4882a593Smuzhiyun enum ath_stomp_type stype =
292*4882a593Smuzhiyun ((stomp_type == ATH_BTCOEX_STOMP_LOW) &&
293*4882a593Smuzhiyun btcoex_hw->mci.stomp_ftp) ?
294*4882a593Smuzhiyun ATH_BTCOEX_STOMP_LOW_FTP : stomp_type;
295*4882a593Smuzhiyun weight = mci_wlan_weights[stype];
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun for (i = 0; i < AR9300_NUM_WLAN_WEIGHTS; i++) {
299*4882a593Smuzhiyun btcoex_hw->bt_weight[i] = AR9300_BT_WGHT;
300*4882a593Smuzhiyun btcoex_hw->wlan_weight[i] = weight[i];
301*4882a593Smuzhiyun if (concur_tx && i) {
302*4882a593Smuzhiyun btcoex_hw->wlan_weight[i] &=
303*4882a593Smuzhiyun ~(0xff << txprio_shift[i-1]);
304*4882a593Smuzhiyun btcoex_hw->wlan_weight[i] |=
305*4882a593Smuzhiyun (btcoex_hw->tx_prio[stomp_type] <<
306*4882a593Smuzhiyun txprio_shift[i-1]);
307*4882a593Smuzhiyun }
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun /* Last WLAN weight has to be adjusted wrt tx priority */
311*4882a593Smuzhiyun if (concur_tx) {
312*4882a593Smuzhiyun btcoex_hw->wlan_weight[i-1] &= ~(0xff << txprio_shift[i-1]);
313*4882a593Smuzhiyun btcoex_hw->wlan_weight[i-1] |= (btcoex_hw->tx_prio[stomp_type]
314*4882a593Smuzhiyun << txprio_shift[i-1]);
315*4882a593Smuzhiyun }
316*4882a593Smuzhiyun }
317*4882a593Smuzhiyun EXPORT_SYMBOL(ath9k_hw_btcoex_set_weight);
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun
ath9k_hw_btcoex_enable_3wire(struct ath_hw * ah)320*4882a593Smuzhiyun static void ath9k_hw_btcoex_enable_3wire(struct ath_hw *ah)
321*4882a593Smuzhiyun {
322*4882a593Smuzhiyun struct ath_btcoex_hw *btcoex = &ah->btcoex_hw;
323*4882a593Smuzhiyun u32 val;
324*4882a593Smuzhiyun int i;
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun /*
327*4882a593Smuzhiyun * Program coex mode and weight registers to
328*4882a593Smuzhiyun * enable coex 3-wire
329*4882a593Smuzhiyun */
330*4882a593Smuzhiyun if (AR_SREV_SOC(ah))
331*4882a593Smuzhiyun REG_CLR_BIT(ah, AR_BT_COEX_MODE2, AR_BT_PHY_ERR_BT_COLL_ENABLE);
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun REG_WRITE(ah, AR_BT_COEX_MODE, btcoex->bt_coex_mode);
334*4882a593Smuzhiyun REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2);
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun if (AR_SREV_SOC(ah))
337*4882a593Smuzhiyun REG_WRITE(ah, AR_BT_COEX_MODE3, btcoex->bt_coex_mode3);
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun if (AR_SREV_9300_20_OR_LATER(ah)) {
340*4882a593Smuzhiyun REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, btcoex->wlan_weight[0]);
341*4882a593Smuzhiyun REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, btcoex->wlan_weight[1]);
342*4882a593Smuzhiyun for (i = 0; i < AR9300_NUM_BT_WEIGHTS; i++)
343*4882a593Smuzhiyun REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS(i),
344*4882a593Smuzhiyun btcoex->bt_weight[i]);
345*4882a593Smuzhiyun } else
346*4882a593Smuzhiyun REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex->bt_coex_weights);
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun if (AR_SREV_9271(ah)) {
349*4882a593Smuzhiyun val = REG_READ(ah, 0x50040);
350*4882a593Smuzhiyun val &= 0xFFFFFEFF;
351*4882a593Smuzhiyun REG_WRITE(ah, 0x50040, val);
352*4882a593Smuzhiyun }
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
355*4882a593Smuzhiyun REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun ath9k_hw_gpio_request_out(ah, btcoex->wlanactive_gpio,
358*4882a593Smuzhiyun "ath9k-wlanactive",
359*4882a593Smuzhiyun AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL);
360*4882a593Smuzhiyun }
361*4882a593Smuzhiyun
ath9k_hw_btcoex_enable_mci(struct ath_hw * ah)362*4882a593Smuzhiyun static void ath9k_hw_btcoex_enable_mci(struct ath_hw *ah)
363*4882a593Smuzhiyun {
364*4882a593Smuzhiyun struct ath_btcoex_hw *btcoex = &ah->btcoex_hw;
365*4882a593Smuzhiyun int i;
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun for (i = 0; i < AR9300_NUM_BT_WEIGHTS; i++)
368*4882a593Smuzhiyun REG_WRITE(ah, AR_MCI_COEX_WL_WEIGHTS(i),
369*4882a593Smuzhiyun btcoex->wlan_weight[i]);
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
372*4882a593Smuzhiyun btcoex->enabled = true;
373*4882a593Smuzhiyun }
374*4882a593Smuzhiyun
ath9k_hw_btcoex_disable_mci(struct ath_hw * ah)375*4882a593Smuzhiyun static void ath9k_hw_btcoex_disable_mci(struct ath_hw *ah)
376*4882a593Smuzhiyun {
377*4882a593Smuzhiyun struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
378*4882a593Smuzhiyun int i;
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_NONE);
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun for (i = 0; i < AR9300_NUM_BT_WEIGHTS; i++)
383*4882a593Smuzhiyun REG_WRITE(ah, AR_MCI_COEX_WL_WEIGHTS(i),
384*4882a593Smuzhiyun btcoex_hw->wlan_weight[i]);
385*4882a593Smuzhiyun }
386*4882a593Smuzhiyun
ath9k_hw_btcoex_enable(struct ath_hw * ah)387*4882a593Smuzhiyun void ath9k_hw_btcoex_enable(struct ath_hw *ah)
388*4882a593Smuzhiyun {
389*4882a593Smuzhiyun struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun switch (ath9k_hw_get_btcoex_scheme(ah)) {
392*4882a593Smuzhiyun case ATH_BTCOEX_CFG_NONE:
393*4882a593Smuzhiyun return;
394*4882a593Smuzhiyun case ATH_BTCOEX_CFG_2WIRE:
395*4882a593Smuzhiyun ath9k_hw_btcoex_enable_2wire(ah);
396*4882a593Smuzhiyun break;
397*4882a593Smuzhiyun case ATH_BTCOEX_CFG_3WIRE:
398*4882a593Smuzhiyun ath9k_hw_btcoex_enable_3wire(ah);
399*4882a593Smuzhiyun break;
400*4882a593Smuzhiyun case ATH_BTCOEX_CFG_MCI:
401*4882a593Smuzhiyun ath9k_hw_btcoex_enable_mci(ah);
402*4882a593Smuzhiyun break;
403*4882a593Smuzhiyun }
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun if (ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_MCI &&
406*4882a593Smuzhiyun !AR_SREV_SOC(ah)) {
407*4882a593Smuzhiyun REG_RMW(ah, AR_GPIO_PDPU,
408*4882a593Smuzhiyun (0x2 << (btcoex_hw->btactive_gpio * 2)),
409*4882a593Smuzhiyun (0x3 << (btcoex_hw->btactive_gpio * 2)));
410*4882a593Smuzhiyun }
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun ah->btcoex_hw.enabled = true;
413*4882a593Smuzhiyun }
414*4882a593Smuzhiyun EXPORT_SYMBOL(ath9k_hw_btcoex_enable);
415*4882a593Smuzhiyun
ath9k_hw_btcoex_disable(struct ath_hw * ah)416*4882a593Smuzhiyun void ath9k_hw_btcoex_disable(struct ath_hw *ah)
417*4882a593Smuzhiyun {
418*4882a593Smuzhiyun struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
419*4882a593Smuzhiyun int i;
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun btcoex_hw->enabled = false;
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun if (ath9k_hw_get_btcoex_scheme(ah) == ATH_BTCOEX_CFG_MCI) {
424*4882a593Smuzhiyun ath9k_hw_btcoex_disable_mci(ah);
425*4882a593Smuzhiyun return;
426*4882a593Smuzhiyun }
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun if (!AR_SREV_9300_20_OR_LATER(ah))
429*4882a593Smuzhiyun ath9k_hw_set_gpio(ah, btcoex_hw->wlanactive_gpio, 0);
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun ath9k_hw_gpio_request_out(ah, btcoex_hw->wlanactive_gpio,
432*4882a593Smuzhiyun NULL, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun if (btcoex_hw->scheme == ATH_BTCOEX_CFG_3WIRE) {
435*4882a593Smuzhiyun REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE);
436*4882a593Smuzhiyun REG_WRITE(ah, AR_BT_COEX_MODE2, 0);
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun if (AR_SREV_9300_20_OR_LATER(ah)) {
439*4882a593Smuzhiyun REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, 0);
440*4882a593Smuzhiyun REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, 0);
441*4882a593Smuzhiyun for (i = 0; i < AR9300_NUM_BT_WEIGHTS; i++)
442*4882a593Smuzhiyun REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS(i), 0);
443*4882a593Smuzhiyun } else
444*4882a593Smuzhiyun REG_WRITE(ah, AR_BT_COEX_WEIGHT, 0);
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun }
447*4882a593Smuzhiyun }
448*4882a593Smuzhiyun EXPORT_SYMBOL(ath9k_hw_btcoex_disable);
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun /*
451*4882a593Smuzhiyun * Configures appropriate weight based on stomp type.
452*4882a593Smuzhiyun */
ath9k_hw_btcoex_bt_stomp(struct ath_hw * ah,enum ath_stomp_type stomp_type)453*4882a593Smuzhiyun void ath9k_hw_btcoex_bt_stomp(struct ath_hw *ah,
454*4882a593Smuzhiyun enum ath_stomp_type stomp_type)
455*4882a593Smuzhiyun {
456*4882a593Smuzhiyun if (AR_SREV_9300_20_OR_LATER(ah)) {
457*4882a593Smuzhiyun ath9k_hw_btcoex_set_weight(ah, 0, 0, stomp_type);
458*4882a593Smuzhiyun return;
459*4882a593Smuzhiyun }
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun switch (stomp_type) {
462*4882a593Smuzhiyun case ATH_BTCOEX_STOMP_ALL:
463*4882a593Smuzhiyun ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
464*4882a593Smuzhiyun AR_STOMP_ALL_WLAN_WGHT, 0);
465*4882a593Smuzhiyun break;
466*4882a593Smuzhiyun case ATH_BTCOEX_STOMP_LOW:
467*4882a593Smuzhiyun ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
468*4882a593Smuzhiyun AR_STOMP_LOW_WLAN_WGHT, 0);
469*4882a593Smuzhiyun break;
470*4882a593Smuzhiyun case ATH_BTCOEX_STOMP_NONE:
471*4882a593Smuzhiyun ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
472*4882a593Smuzhiyun AR_STOMP_NONE_WLAN_WGHT, 0);
473*4882a593Smuzhiyun break;
474*4882a593Smuzhiyun default:
475*4882a593Smuzhiyun ath_dbg(ath9k_hw_common(ah), BTCOEX, "Invalid Stomptype\n");
476*4882a593Smuzhiyun break;
477*4882a593Smuzhiyun }
478*4882a593Smuzhiyun }
479*4882a593Smuzhiyun EXPORT_SYMBOL(ath9k_hw_btcoex_bt_stomp);
480*4882a593Smuzhiyun
ath9k_hw_btcoex_set_concur_txprio(struct ath_hw * ah,u8 * stomp_txprio)481*4882a593Smuzhiyun void ath9k_hw_btcoex_set_concur_txprio(struct ath_hw *ah, u8 *stomp_txprio)
482*4882a593Smuzhiyun {
483*4882a593Smuzhiyun struct ath_btcoex_hw *btcoex = &ah->btcoex_hw;
484*4882a593Smuzhiyun int i;
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun for (i = 0; i < ATH_BTCOEX_STOMP_MAX; i++)
487*4882a593Smuzhiyun btcoex->tx_prio[i] = stomp_txprio[i];
488*4882a593Smuzhiyun }
489*4882a593Smuzhiyun EXPORT_SYMBOL(ath9k_hw_btcoex_set_concur_txprio);
490