1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2010-2011 Atheros Communications Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission to use, copy, modify, and/or distribute this software for any 5*4882a593Smuzhiyun * purpose with or without fee is hereby granted, provided that the above 6*4882a593Smuzhiyun * copyright notice and this permission notice appear in all copies. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*4882a593Smuzhiyun * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*4882a593Smuzhiyun * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*4882a593Smuzhiyun * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*4882a593Smuzhiyun * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*4882a593Smuzhiyun * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*4882a593Smuzhiyun * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef AR9003_MAC_H 18*4882a593Smuzhiyun #define AR9003_MAC_H 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define AR_DescId 0xffff0000 21*4882a593Smuzhiyun #define AR_DescId_S 16 22*4882a593Smuzhiyun #define AR_CtrlStat 0x00004000 23*4882a593Smuzhiyun #define AR_CtrlStat_S 14 24*4882a593Smuzhiyun #define AR_TxRxDesc 0x00008000 25*4882a593Smuzhiyun #define AR_TxRxDesc_S 15 26*4882a593Smuzhiyun #define AR_TxQcuNum 0x00000f00 27*4882a593Smuzhiyun #define AR_TxQcuNum_S 8 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define AR_BufLen 0x0fff0000 30*4882a593Smuzhiyun #define AR_BufLen_S 16 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define AR_TxDescId 0xffff0000 33*4882a593Smuzhiyun #define AR_TxDescId_S 16 34*4882a593Smuzhiyun #define AR_TxPtrChkSum 0x0000ffff 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define AR_LowRxChain 0x00004000 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define AR_Not_Sounding 0x20000000 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* ctl 12 */ 41*4882a593Smuzhiyun #define AR_PAPRDChainMask 0x00000e00 42*4882a593Smuzhiyun #define AR_PAPRDChainMask_S 9 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define MAP_ISR_S2_CST 6 45*4882a593Smuzhiyun #define MAP_ISR_S2_GTT 6 46*4882a593Smuzhiyun #define MAP_ISR_S2_TIM 3 47*4882a593Smuzhiyun #define MAP_ISR_S2_CABEND 0 48*4882a593Smuzhiyun #define MAP_ISR_S2_DTIMSYNC 7 49*4882a593Smuzhiyun #define MAP_ISR_S2_DTIM 7 50*4882a593Smuzhiyun #define MAP_ISR_S2_TSFOOR 4 51*4882a593Smuzhiyun #define MAP_ISR_S2_BB_WATCHDOG 6 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define AR9003TXC_CONST(_ds) ((const struct ar9003_txc *) _ds) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun struct ar9003_rxs { 56*4882a593Smuzhiyun u32 ds_info; 57*4882a593Smuzhiyun u32 status1; 58*4882a593Smuzhiyun u32 status2; 59*4882a593Smuzhiyun u32 status3; 60*4882a593Smuzhiyun u32 status4; 61*4882a593Smuzhiyun u32 status5; 62*4882a593Smuzhiyun u32 status6; 63*4882a593Smuzhiyun u32 status7; 64*4882a593Smuzhiyun u32 status8; 65*4882a593Smuzhiyun u32 status9; 66*4882a593Smuzhiyun u32 status10; 67*4882a593Smuzhiyun u32 status11; 68*4882a593Smuzhiyun } __packed __aligned(4); 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* Transmit Control Descriptor */ 71*4882a593Smuzhiyun struct ar9003_txc { 72*4882a593Smuzhiyun u32 info; /* descriptor information */ 73*4882a593Smuzhiyun u32 link; /* link pointer */ 74*4882a593Smuzhiyun u32 data0; /* data pointer to 1st buffer */ 75*4882a593Smuzhiyun u32 ctl3; /* DMA control 3 */ 76*4882a593Smuzhiyun u32 data1; /* data pointer to 2nd buffer */ 77*4882a593Smuzhiyun u32 ctl5; /* DMA control 5 */ 78*4882a593Smuzhiyun u32 data2; /* data pointer to 3rd buffer */ 79*4882a593Smuzhiyun u32 ctl7; /* DMA control 7 */ 80*4882a593Smuzhiyun u32 data3; /* data pointer to 4th buffer */ 81*4882a593Smuzhiyun u32 ctl9; /* DMA control 9 */ 82*4882a593Smuzhiyun u32 ctl10; /* DMA control 10 */ 83*4882a593Smuzhiyun u32 ctl11; /* DMA control 11 */ 84*4882a593Smuzhiyun u32 ctl12; /* DMA control 12 */ 85*4882a593Smuzhiyun u32 ctl13; /* DMA control 13 */ 86*4882a593Smuzhiyun u32 ctl14; /* DMA control 14 */ 87*4882a593Smuzhiyun u32 ctl15; /* DMA control 15 */ 88*4882a593Smuzhiyun u32 ctl16; /* DMA control 16 */ 89*4882a593Smuzhiyun u32 ctl17; /* DMA control 17 */ 90*4882a593Smuzhiyun u32 ctl18; /* DMA control 18 */ 91*4882a593Smuzhiyun u32 ctl19; /* DMA control 19 */ 92*4882a593Smuzhiyun u32 ctl20; /* DMA control 20 */ 93*4882a593Smuzhiyun u32 ctl21; /* DMA control 21 */ 94*4882a593Smuzhiyun u32 ctl22; /* DMA control 22 */ 95*4882a593Smuzhiyun u32 ctl23; /* DMA control 23 */ 96*4882a593Smuzhiyun u32 pad[8]; /* pad to cache line (128 bytes/32 dwords) */ 97*4882a593Smuzhiyun } __packed __aligned(4); 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun struct ar9003_txs { 100*4882a593Smuzhiyun u32 ds_info; 101*4882a593Smuzhiyun u32 status1; 102*4882a593Smuzhiyun u32 status2; 103*4882a593Smuzhiyun u32 status3; 104*4882a593Smuzhiyun u32 status4; 105*4882a593Smuzhiyun u32 status5; 106*4882a593Smuzhiyun u32 status6; 107*4882a593Smuzhiyun u32 status7; 108*4882a593Smuzhiyun u32 status8; 109*4882a593Smuzhiyun } __packed __aligned(4); 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun void ar9003_hw_attach_mac_ops(struct ath_hw *hw); 112*4882a593Smuzhiyun void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size); 113*4882a593Smuzhiyun void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp, 114*4882a593Smuzhiyun enum ath9k_rx_qtype qtype); 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, 117*4882a593Smuzhiyun struct ath_rx_status *rxs, 118*4882a593Smuzhiyun void *buf_addr); 119*4882a593Smuzhiyun void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah); 120*4882a593Smuzhiyun void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start, 121*4882a593Smuzhiyun u32 ts_paddr_start, 122*4882a593Smuzhiyun u16 size); 123*4882a593Smuzhiyun #endif 124