1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2015 Qualcomm Atheros Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission to use, copy, modify, and/or distribute this software for any 5*4882a593Smuzhiyun * purpose with or without fee is hereby granted, provided that the above 6*4882a593Smuzhiyun * copyright notice and this permission notice appear in all copies. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*4882a593Smuzhiyun * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*4882a593Smuzhiyun * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*4882a593Smuzhiyun * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*4882a593Smuzhiyun * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*4882a593Smuzhiyun * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*4882a593Smuzhiyun * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef AR9003_AIC_H 18*4882a593Smuzhiyun #define AR9003_AIC_H 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define ATH_AIC_MAX_COM_ATT_DB_TABLE 6 21*4882a593Smuzhiyun #define ATH_AIC_MAX_AIC_LIN_TABLE 69 22*4882a593Smuzhiyun #define ATH_AIC_MIN_ROT_DIR_ATT_DB 0 23*4882a593Smuzhiyun #define ATH_AIC_MIN_ROT_QUAD_ATT_DB 0 24*4882a593Smuzhiyun #define ATH_AIC_MAX_ROT_DIR_ATT_DB 37 25*4882a593Smuzhiyun #define ATH_AIC_MAX_ROT_QUAD_ATT_DB 37 26*4882a593Smuzhiyun #define ATH_AIC_SRAM_AUTO_INCREMENT 0x80000000 27*4882a593Smuzhiyun #define ATH_AIC_SRAM_GAIN_TABLE_OFFSET 0x280 28*4882a593Smuzhiyun #define ATH_AIC_SRAM_CAL_OFFSET 0x140 29*4882a593Smuzhiyun #define ATH_AIC_SRAM_OFFSET 0x00 30*4882a593Smuzhiyun #define ATH_AIC_MEAS_MAG_THRESH 20 31*4882a593Smuzhiyun #define ATH_AIC_BT_JUPITER_CTRL 0x66820 32*4882a593Smuzhiyun #define ATH_AIC_BT_AIC_ENABLE 0x02 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun enum aic_cal_state { 35*4882a593Smuzhiyun AIC_CAL_STATE_IDLE = 0, 36*4882a593Smuzhiyun AIC_CAL_STATE_STARTED, 37*4882a593Smuzhiyun AIC_CAL_STATE_DONE, 38*4882a593Smuzhiyun AIC_CAL_STATE_ERROR 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun struct ath_aic_sram_info { 42*4882a593Smuzhiyun bool valid:1; 43*4882a593Smuzhiyun bool vga_quad_sign:1; 44*4882a593Smuzhiyun bool vga_dir_sign:1; 45*4882a593Smuzhiyun u8 rot_quad_att_db; 46*4882a593Smuzhiyun u8 rot_dir_att_db; 47*4882a593Smuzhiyun u8 com_att_6db; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun struct ath_aic_out_info { 51*4882a593Smuzhiyun int16_t dir_path_gain_lin; 52*4882a593Smuzhiyun int16_t quad_path_gain_lin; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun u8 ar9003_aic_calibration(struct ath_hw *ah); 56*4882a593Smuzhiyun u8 ar9003_aic_start_normal(struct ath_hw *ah); 57*4882a593Smuzhiyun u8 ar9003_aic_cal_reset(struct ath_hw *ah); 58*4882a593Smuzhiyun u8 ar9003_aic_calibration_single(struct ath_hw *ah); 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #endif /* AR9003_AIC_H */ 61