1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2008-2011 Atheros Communications Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission to use, copy, modify, and/or distribute this software for any 5*4882a593Smuzhiyun * purpose with or without fee is hereby granted, provided that the above 6*4882a593Smuzhiyun * copyright notice and this permission notice appear in all copies. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*4882a593Smuzhiyun * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*4882a593Smuzhiyun * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*4882a593Smuzhiyun * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*4882a593Smuzhiyun * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*4882a593Smuzhiyun * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*4882a593Smuzhiyun * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef ANI_H 18*4882a593Smuzhiyun #define ANI_H 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define BEACON_RSSI(ahp) (ahp->stats.avgbrssi) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* units are errors per second */ 23*4882a593Smuzhiyun #define ATH9K_ANI_OFDM_TRIG_HIGH 3500 24*4882a593Smuzhiyun #define ATH9K_ANI_OFDM_TRIG_HIGH_BELOW_INI 1000 25*4882a593Smuzhiyun #define ATH9K_ANI_OFDM_TRIG_HIGH_OLD 500 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define ATH9K_ANI_OFDM_TRIG_LOW 400 28*4882a593Smuzhiyun #define ATH9K_ANI_OFDM_TRIG_LOW_ABOVE_INI 900 29*4882a593Smuzhiyun #define ATH9K_ANI_OFDM_TRIG_LOW_OLD 200 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define ATH9K_ANI_CCK_TRIG_HIGH 600 32*4882a593Smuzhiyun #define ATH9K_ANI_CCK_TRIG_HIGH_OLD 200 33*4882a593Smuzhiyun #define ATH9K_ANI_CCK_TRIG_LOW 300 34*4882a593Smuzhiyun #define ATH9K_ANI_CCK_TRIG_LOW_OLD 100 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define ATH9K_ANI_SPUR_IMMUNE_LVL 3 37*4882a593Smuzhiyun #define ATH9K_ANI_FIRSTEP_LVL 2 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define ATH9K_ANI_RSSI_THR_HIGH 40 40*4882a593Smuzhiyun #define ATH9K_ANI_RSSI_THR_LOW 7 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define ATH9K_ANI_PERIOD 300 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* in ms */ 45*4882a593Smuzhiyun #define ATH9K_ANI_POLLINTERVAL 1000 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define ATH9K_SIG_FIRSTEP_SETTING_MIN 0 48*4882a593Smuzhiyun #define ATH9K_SIG_FIRSTEP_SETTING_MAX 20 49*4882a593Smuzhiyun #define ATH9K_SIG_SPUR_IMM_SETTING_MIN 0 50*4882a593Smuzhiyun #define ATH9K_SIG_SPUR_IMM_SETTING_MAX 22 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* values here are relative to the INI */ 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun enum ath9k_ani_cmd { 55*4882a593Smuzhiyun ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x1, 56*4882a593Smuzhiyun ATH9K_ANI_FIRSTEP_LEVEL = 0x2, 57*4882a593Smuzhiyun ATH9K_ANI_SPUR_IMMUNITY_LEVEL = 0x4, 58*4882a593Smuzhiyun ATH9K_ANI_MRC_CCK = 0x8, 59*4882a593Smuzhiyun ATH9K_ANI_ALL = 0xfff 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun struct ath9k_mib_stats { 63*4882a593Smuzhiyun u32 ackrcv_bad; 64*4882a593Smuzhiyun u32 rts_bad; 65*4882a593Smuzhiyun u32 rts_good; 66*4882a593Smuzhiyun u32 fcs_bad; 67*4882a593Smuzhiyun u32 beacons; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* INI default values for ANI registers */ 71*4882a593Smuzhiyun struct ath9k_ani_default { 72*4882a593Smuzhiyun u16 m1ThreshLow; 73*4882a593Smuzhiyun u16 m2ThreshLow; 74*4882a593Smuzhiyun u16 m1Thresh; 75*4882a593Smuzhiyun u16 m2Thresh; 76*4882a593Smuzhiyun u16 m2CountThr; 77*4882a593Smuzhiyun u16 m2CountThrLow; 78*4882a593Smuzhiyun u16 m1ThreshLowExt; 79*4882a593Smuzhiyun u16 m2ThreshLowExt; 80*4882a593Smuzhiyun u16 m1ThreshExt; 81*4882a593Smuzhiyun u16 m2ThreshExt; 82*4882a593Smuzhiyun u16 firstep; 83*4882a593Smuzhiyun u16 firstepLow; 84*4882a593Smuzhiyun u16 cycpwrThr1; 85*4882a593Smuzhiyun u16 cycpwrThr1Ext; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun struct ar5416AniState { 89*4882a593Smuzhiyun u8 noiseImmunityLevel; 90*4882a593Smuzhiyun u8 ofdmNoiseImmunityLevel; 91*4882a593Smuzhiyun u8 cckNoiseImmunityLevel; 92*4882a593Smuzhiyun bool ofdmsTurn; 93*4882a593Smuzhiyun u8 mrcCCK; 94*4882a593Smuzhiyun u8 spurImmunityLevel; 95*4882a593Smuzhiyun u8 firstepLevel; 96*4882a593Smuzhiyun bool ofdmWeakSigDetect; 97*4882a593Smuzhiyun u32 listenTime; 98*4882a593Smuzhiyun u32 ofdmPhyErrCount; 99*4882a593Smuzhiyun u32 cckPhyErrCount; 100*4882a593Smuzhiyun struct ath9k_ani_default iniDef; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun struct ar5416Stats { 104*4882a593Smuzhiyun u32 ast_ani_spurup; 105*4882a593Smuzhiyun u32 ast_ani_spurdown; 106*4882a593Smuzhiyun u32 ast_ani_ofdmon; 107*4882a593Smuzhiyun u32 ast_ani_ofdmoff; 108*4882a593Smuzhiyun u32 ast_ani_cckhigh; 109*4882a593Smuzhiyun u32 ast_ani_ccklow; 110*4882a593Smuzhiyun u32 ast_ani_stepup; 111*4882a593Smuzhiyun u32 ast_ani_stepdown; 112*4882a593Smuzhiyun u32 ast_ani_ofdmerrs; 113*4882a593Smuzhiyun u32 ast_ani_cckerrs; 114*4882a593Smuzhiyun u32 ast_ani_reset; 115*4882a593Smuzhiyun u32 ast_ani_lneg_or_lzero; 116*4882a593Smuzhiyun u32 avgbrssi; 117*4882a593Smuzhiyun struct ath9k_mib_stats ast_mibstats; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun #define ah_mibStats stats.ast_mibstats 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun void ath9k_enable_mib_counters(struct ath_hw *ah); 122*4882a593Smuzhiyun void ath9k_hw_disable_mib_counters(struct ath_hw *ah); 123*4882a593Smuzhiyun void ath9k_hw_ani_init(struct ath_hw *ah); 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun #endif /* ANI_H */ 126